Integrated circuit (IC) structure having high impedance semiconductor material between substrate and transistors

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure having a high-resistance semiconductor material between a substrate and a transistor. The IC structure can include a substrate, a high-resistance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high-resistance semiconductor material. The transistor includes a semiconductor channel region between a first source / drain (S / D) region and a second S / D region in a horizontal direction. The high-resistance semiconductor material is between the transistor and the substrate in a vertical direction; a first insulator region is on the substrate and adjacent to the first S / D region in the horizontal direction; a first doped well is on the substrate and adjacent to the first insulator region in the horizontal direction. A first insulator region is between the first doped well and the transistor in the horizontal direction.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to integrated circuit (IC) structures. More specifically, various embodiments of this disclosure provide IC structures having a high-resistivity semiconductor material between a substrate and a transistor. Background Technology

[0002] In the microelectronics industry, and other industries involving the construction of microstructures, there has always been a desire to reduce the size of structural features and microelectronic devices and / or to provide more circuitry for a given chip size. Miniaturization typically allows for improved performance (more processing per clock cycle and less heat generation) at lower power levels and lower costs. Current technology involves atomically scaling certain microdevices such as logic gates, FETs, and capacitors. Circuit chips with hundreds of millions of such devices are commonplace.

[0003] Circuit manufacturers are currently striving to reduce the two-dimensional area occupied by device components, for example, to reduce 2D area and power consumption. One problem with the miniaturization of radio frequency (RF) devices is the reduction in resistance to the transistor body connections (e.g., back gate terminals), which reduces the voltage gain and / or linearity of the expected input-output voltage function in the circuit component. In conventional circuits, the lower resistance of the transistor can be offset by applying a larger voltage bias to the body to reduce capacitance. However, this may not be feasible in many device or technology settings. Summary of the Invention

[0004] Some aspects of this disclosure provide an integrated circuit (IC) structure comprising: a substrate; a high-impedance semiconductor material located on a portion of the substrate; a transistor located on a top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in a horizontal direction between a first source / drain (S / D) region and a second S / D region, wherein the high-impedance semiconductor material is located in a vertical direction between the transistor and the substrate; a first insulating region located on the substrate and horizontally adjacent to the first S / D region; and a first doped well located on the substrate and horizontally adjacent to the first insulating region, wherein the first insulating region is located in a horizontal direction between the first doped well and the transistor.

[0005] Other aspects of this disclosure provide an integrated circuit (IC) structure, comprising: a substrate having a top surface; a high-impedance semiconductor material located within the substrate, wherein the top surface of the high-impedance semiconductor material is coplanar with the top surface of the substrate; a transistor located on the top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in a horizontal direction between a first source / drain (S / D) region and a second S / D region, wherein the high-impedance semiconductor material is located in a vertical direction between the transistor and the substrate; a first insulating region located on the top surface of the substrate and adjacent in a horizontal direction to the first S / D region; and a second... A doped well located within the substrate and horizontally adjacent to the first insulating region, wherein the first insulating region is horizontally located between the first doped well and the first S / D region of the transistor; a first body terminal located on the first doped well; a second insulating region located on the top surface of the substrate and horizontally adjacent to the second S / D region; a second doped well located within the substrate and horizontally adjacent to the second insulating region, wherein the second insulating region is horizontally located between the second doped well and the second S / D region of the transistor; and a second body terminal located on the second doped well.

[0006] Another aspect of this disclosure provides an integrated circuit (IC) structure, comprising: a substrate having a top surface; a high-impedance semiconductor material located within the substrate, wherein the top surface of the high-impedance semiconductor material is coplanar with the top surface of the substrate; a transistor located on the top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in a horizontal direction between a first source / drain (S / D) region and a second S / D region, wherein the high-impedance semiconductor material is located in a vertical direction between the transistor and the substrate; a first insulator region located on the top surface of the substrate and the top surface of the high-impedance semiconductor material, and adjacent in a horizontal direction to the first S / D region; and a second insulator region. The first S / D region is located on the top surface of the substrate and the top surface of the high-impedance semiconductor material, and is horizontally adjacent to the second S / D region; a first doped well is located on the top surface of the substrate and is horizontally adjacent to the first insulating region and the substrate, wherein the first insulating region is horizontally located between the first doped well and the transistor; a first body terminal is located within the first doped well; a second doped well is located on the top surface of the substrate and is horizontally adjacent to the first insulating region and the substrate, wherein the second insulating region is horizontally located between the second doped well and the transistor; and a second body terminal is located within the second doped well. Attached Figure Description

[0007] These and other features of this disclosure will be more readily understood through a detailed description of various aspects thereof, taken in conjunction with the accompanying drawings, which illustrate various embodiments of this disclosure, wherein:

[0008] Figure 1 A cross-sectional view of an integrated circuit (IC) structure having a high-impedance semiconductor material between a substrate and a transistor, according to an embodiment of the present disclosure, is provided.

[0009] Figure 2 Another cross-sectional view of the IC structure and active device according to embodiments of the present disclosure is provided.

[0010] Figure 3 A cross-sectional view of an IC structure having a high-impedance semiconductor material between a substrate and a transistor, according to another embodiment of the present disclosure, is provided.

[0011] Figure 4 Another cross-sectional view of the IC structure and active device according to another embodiment of the present disclosure is provided.

[0012] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0013] In this description, reference is made to the accompanying drawings, which form part of the specification and are illustrated by way of specific exemplary embodiments in which the teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the teachings, and it should be understood that other embodiments may be used and changes may be made within the scope of the teachings. Therefore, the description herein is merely illustrative.

[0014] Embodiments of this disclosure provide an integrated circuit (IC) structure having a high-impedance semiconductor material between a substrate and a transistor. The IC structure can be formed on a substrate, such as a bulk region of the semiconductor material. The structure may also include a layer of high-impedance semiconductor material on a portion of the substrate, which may be embedded within the semiconductor material. The IC structure may include a transistor located on top of the high-impedance semiconductor material. The transistor includes a semiconductor channel region located horizontally between a first source / drain (S / D) region and a second S / D region. In this configuration, the high-impedance semiconductor material electrically insulates the active region of the transistor from the underlying substrate at RF frequencies, while allowing a DC bias to be applied to the substrate from other contacts. One or more insulator regions may be located on the substrate and horizontally adjacent to the first or second S / D region. One or more doped wells on the substrate may be horizontally adjacent to a corresponding insulator region. The insulator regions horizontally separate the transistor from the doped wells. By being located near the transistor, the doped wells can achieve electrical biasing of the substrate beneath the high-impedance semiconductor material.

[0015] refer to Figure 1 This diagram shows a cross-sectional view of an integrated circuit (IC) structure 100 according to an embodiment of the present disclosure. The IC structure 100 can be formed from a substrate 102 comprising, for example, one or more semiconductor materials. The substrate 102 can include any semiconductor material now known or hereafter developed, including but not limited to silicon, germanium, silicon carbide, and materials substantially composed of one or more III-V compound semiconductors having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition is defined, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions that are each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The substrate 102 is a II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). The entire substrate 102 or a portion thereof may be subjected to strain. The substrate 102 may include a bulk silicon layer, but in other embodiments, it may take the form of a semiconductor-on-insulator (SOI) substrate, semiconductor fins, and / or other types of substrates.

[0016] To provide a bias element for a transistor, substrate 102 may include one or more doped regions taking the form of a first doped well 104a having a first doping type. Substrate 102 may also include a second doped well 104b, which also has the same (i.e., first) doping type. The first doped well 104a and the second doped well 104b may be located at different locations in substrate 102 and are horizontally distant from each other. According to one example, the first doping type may be P-type doping. When referring to dopants, P-type dopants are elements introduced into a semiconductor material to generate free holes by “accepting” electrons from semiconductor atoms and thus “releasing” holes. The acceptor atom must have one less valence electron than the matrix semiconductor. P-type dopants suitable for substrate 102 may include, but are not limited to, boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives include In and Ga. Ga has a high diffusivity in silicon dioxide (SiO2), so the oxide cannot be used as a mask during Ga diffusion.

[0017] The undoped portion of substrate 102 can separate the first doped well 104a from the second doped well 104b. The first doped well 104a and the second doped well 104b can be formed within substrate 102, for example, by vertical ion implantation. In some cases, substrate 102 may also include a dopant. In this case, doped wells 104a and 104b may have the same doping type as substrate 102, but have a higher dopant concentration of the first doping type (e.g., p-type doping) than substrate 102. Therefore, doped wells 104a and 104b can be distinguished from substrate 102 at least in part based on their doping concentration, dopant material, etc., even if doped wells 104a and 104b and substrate 102 have the same doping type. Substrate 102 may include other doped wells having the same or different doping types, and for clarity only, these wells are... Figure 1 Omitted in .

[0018] IC structure 100 may include a high-resistivity semiconductor material 106 located on a portion of substrate 102. The high-resistivity semiconductor material 106 may be formed of silicon (Si) and / or any other semiconductor material capable of exhibiting a high resistivity (i.e., significantly higher than the resistivity of substrate 102). As used herein, the term "high impedance" may refer to a material having an impedance of at least about ten megaohms (MΩ). To form the high-resistivity semiconductor material 106, a crystalline semiconductor material may be formed on or derived from other portions of substrate 102. The crystalline semiconductor material may be converted to polycrystalline silicon (poly-Si) by any process now known or developed hereafter to form the high-resistivity material, for example, by intentionally damaging the crystalline semiconductor material through implantation, annealing, and / or other operations. A polycrystalline semiconductor material refers to any polycrystalline thin-film semiconductor that does not have a long-range crystal order. The polycrystalline thin-film semiconductor material may be converted from amorphous silicon (α-Si), in which case some portions of the amorphous material may remain inside or near the high-resistivity semiconductor material 106. Since the resulting material can contain a variety of components, the high-impedance semiconductor material 106 can typically comprise any semiconductor material or combination of semiconductor-based materials (e.g., polycrystalline silicon, one or more polycrystalline films of semiconductor materials) exhibiting an impedance of at least about 10 MΩ, as described herein. Polycrystalline semiconductor materials provide electrical insulation in particular compared to single crystals (e.g., the material within substrate 102 and doped wells 104a, 104b).

[0019] A high-resistivity semiconductor material 106 may be formed on a portion of the substrate 102 between the doped wells 104a and 104b, while being physically separated from the doped wells 104a and 104b. In this location, the high-resistivity semiconductor material 106 can electrically isolate the substrate 102 from other materials and / or structures formed thereon. The top surface J of the high-resistivity semiconductor material 106 may be substantially coplanar with the adjacent upper surface of the substrate 102.

[0020] IC structure 100 may include a transistor 110 located on the top surface J of a high-resistivity semiconductor material 106. Transistor 110 may include a channel region 112 (e.g., a crystalline semiconductor having the same doping type as doped wells 104a, 104b), and thus may be referred to in some cases as a “shallow well.” The channel region 112 may be located horizontally between a first source / drain (S / D) region 114a and a second S / D region 114b. S / D regions 114a, 114b may have a second doping type (e.g., N-type doping) opposite to the doping type of the first doped well 104a and the second doped well 104b. S / D regions 114a, 114b may be formed by introducing an N-type dopant into the substrate 102 and / or the precursor semiconductor material using any now-known or later-developed technique (e.g., ion implantation). An N-type dopant is an element introduced into a semiconductor material to generate free electrons, for example, by “donating” electrons to the semiconductor. An N-type dopant must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb).

[0021] Transistor 110 may include a gate dielectric material 116 located above channel region 112. The gate dielectric material 116 may include a high-k dielectric, such as, but not limited to: metal oxides, such as tantalum oxide (Ta₂O₅), barium titanium oxide (BaTiO₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and aluminum oxide (Al₂O₃); or metal silicates, such as hafnium silicate (HfO₂). A1 Si A2 O A3 ) or hafnium oxynitride silicate (Hf A1 Si A2 O A3 N A4), where A1, A2, A3 and A4 represent relative proportions, which are greater than or equal to zero and A1+A2+A3+A4 (1 is the total relative molar amount). The gate dielectric layer 134 may include any conceivable insulating material, such as, but not limited to: silicon nitride (Si3N4); silicon oxide (SiO2); fluorinated SiO2 (FSG); hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; borosilicate glass (BPSG); silsesquioxane; carbon (C) doped oxides (i.e., organosilicones) comprising atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H); thermosetting polyarylene ethers; SiLK (polyarylene ethers available from Dow Chemical Corporation); spin-coated silicon-carbon-containing polymer materials available from JSR Corporation; hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; porous methylsilsesquioxane (MSQ); porous hydrogen silsesquioxane (HSQ); octamethylcyclotetrasiloxane (OMCTS)[(CH3)2SiO]4 available from Air Liquide. 2.7, or other low dielectric constant (k<3.9) materials, or combinations thereof. The gate dielectric layer 116 may also include high-k dielectric materials, such as, but not limited to, hafnium silicate (HfSiO), zirconium silicate (ZrSiOx), silicon oxynitride (SiON), or any combination thereof.

[0022] Transistor 110 may include a gate structure 118 located above the gate dielectric layer 116 and between the S / D regions 114a, 114b. During operation, the gate structure 118 may be used to apply a voltage across the gate dielectric 116 to the channel region 114, thereby putting transistor 110 into an operational state (e.g., allowing charge carriers to flow from the first S / D region 114a to the second S / D region 114b or from the second S / D region 114b to the first S / D region 114a). Those skilled in the art will understand that the gate structure 118 may include one or more layers, potentially forming a gate stack. According to one example, the gate structure 118 may be formed of doped or undoped polysilicon (poly-Si). In another example, the gate structure 118 may include materials such as, but not limited to, aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and / or combinations thereof. Various insulating materials (e.g., spacers) may be included within and / or formed on the sidewalls of the gate structure 118, but for clarity only, such materials are excluded. Figure 1 Omitted in .

[0023] A set of insulating regions, identified as a first insulating region 120a and a second insulating region 120b, respectively, separates the transistor 110 from the first doped well 104a and the second doped well 104b. The insulating regions 120a and 120b can be identified and referred to as "trench isolation," and therefore can be provided in the form of shallow trench isolation or deep trench isolation. In this case, the insulating regions 120a and 120b can be provided by forming trenches within selected portions of the substrate 102 and filling the trenches with an insulating material (e.g., oxide) to isolate one region of the substrate from an adjacent region of the substrate. With two insulating regions 120a and 120b provided, a high-resistivity semiconductor material 106 can continuously extend from a first end E1 located below the first insulating region 120a to a second end E2 located below the second insulating region 120b. The separation distance L between the first doped well 104a or the second doped well 104b and the high-resistivity semiconductor material 106 can be less than the horizontal width of the overlying insulating regions 120a, 120b. In this configuration, the high-resistivity semiconductor material 106, together with the insulating regions 120a, 120b, physically isolates the substrate 102 from the transistor 110. The transistor 110 and / or other suitable devices can be disposed within the region isolated by the insulating regions 120a, 120b. Each insulating region 120a, 120b may be formed of any material now known or later developed for providing electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or multilayers thereof.

[0024] Transistor 110 is capable of operating under predetermined conditions, for example, by controlling the flow of current between S / D regions 114a, 114b by a voltage applied via gate structure 118. Embodiments of IC structure 100 may include additional components for electrically biasing transistor 110 itself, for example, via a host voltage. Among other things, the bias voltage applied to substrate 102 may affect the gate structure 118 voltage required for current to flow between S / D regions 114a, 114b, or the current flow between S / D regions 114a, 114b during the application of such a voltage. Conventional transistors may include host contacts for electrically biasing the substrate material beneath the transistor. Such transistors may include one or more layers of insulating and / or alternately doped material to physically and electrically isolate the biased substrate material from the active regions of the device. However, embodiments of this disclosure avoid the use of additional insulating material by including the high-impedance semiconductor material 106 discussed herein.

[0025] IC structure 100 may include body terminals in the form of, for example, a first body contact 122a on a first doped well 104a and / or a second body contact 122b on a second doped well 104b. The body contacts 122a, 122b may be formed of a doped semiconductor material and may initially form part of the substrate 102 before being doped. Regardless of the configuration, the body contacts 122a and 122b are of a first doping type (e.g., P+ doping). According to an example, the body contacts 122a and 122b may be directly adjacent in the horizontal direction to the upper portion of the insulating regions 120a, 122b and may be directly located on the doped wells 104a, 104b. A vertical interface between each pair of doped wells 104a, 104b and body contacts 122a, 122b may divide the sidewalls of the insulating regions 120a, 120b in two, such as... Figure 1 As shown.

[0026] IC structure 100 may include an interlayer dielectric (ILD) 130 formed over body contacts 122a, 122b, insulating regions 120a, 120b, and transistor 110, for example by deposition or other techniques of forming insulating material on the structure. ILD 130 may include the same insulating material as insulating regions 120a, 120b, or may include different electrically insulating materials. Nevertheless, ILD 130 and insulating regions 120a, 120b constitute different components, for example, because insulating regions 120a, 120b are formed from a portion of substrate 102 rather than on the substrate. Additional metallization layers (not shown) may be formed on ILD 130 during mid-process and / or back-processing. To electrically couple the various portions of IC structure 100 to such metallization layers, a set of S / D contacts 132a, 132b may be formed on S / D regions 114a, 114b, within ILD 130. Similarly, a gate contact 134 may be formed on the gate structure 118 and within the ILD 130. In addition, one or more body contacts 134a, 134b may be formed on the body terminals 122a, 122b and within the ILD 130.

[0027] One or more of contacts 130a, 130b, 132, 134a, 134b can be formed within a predetermined portion of the ILD 130 to overlying circuit elements by vertical etching to form openings to one or more contact locations, followed by filling these openings with a conductor. Each contact 130a, 130b, 132, 134a, 134b may include any known or later-developed conductive material configured for electrical contact, such as copper (Cu), aluminum (Al), gold (Au), etc. Contacts 132a, 132b, 134, 136a, 136b may additionally include a refractory metal liner (not shown) positioned transversely to the ILD 130 to prevent electromigration degradation, short circuits to other components, etc. In addition, selected portions of the S / D regions 114a, 114b, the gate structure 118, and / or the body terminals 122a, 122b may include silicide regions (i.e., semiconductor portions annealed in the presence of an overlying conductor to increase the conductivity of the semiconductor region) to increase the conductivity from the contacts 132a, 132b, 134, 136a, 136b.

[0028] Applying a voltage to the body contacts 122a, 122b during device operation can electrically bias the adjacent portions of the doped wells 104a, 104b and the substrate 102 beneath them. However, the high-impedance semiconductor material 106 prevents this bias from forming a low-resistance electrical path from the body contacts 122a, 122b to the channel region 112 of the transistor 110. The formation of the high-impedance semiconductor material 106 prevents any noise coupled from the substrate or from adjacent devices (which may be another MOSFET, diode, BJT, etc.). Applying a bias voltage to the body contacts 122a, 122b can affect, for example, the threshold voltage required for the gate structure 118 to form a conductive path through the channel region 112 of the transistor 110 and through the high-impedance semiconductor material 106. The electrical bias of the substrate 102 can be provided simultaneously through each of the body terminals 122a, 122b, or it can be provided solely through one of the body terminals 122a, 122b. In this configuration, portions of the substrate 102 located beneath the amorphous semiconductor material 106 may not require additional doping, provided they are very close to the doped wells 104a and 104b (e.g., approximately five micrometers (µm) apart). The minimum distance may vary for a specific application and is typically governed by rules defined in the Design Rule Check (DRC) for a given technology. To provide and / or enhance these electrical properties, the substrate 102, doped wells 104a and 104b, transistor 110, and / or other components of the IC structure 100 may be free of amorphous semiconductor material.

[0029] refer to Figure 2 Since no additional insulating material other than the high-impedance semiconductor material 106 and the insulating regions 120a and 120b is required to be formed in the substrate 102, embodiments of the IC structure 100 can allow the electrical bias of the transistor 110. Figure 2 An embodiment of IC structure 100 is shown, wherein a substrate 102 spans an indeterminate horizontal length from transistor 110 to an active device 140 also formed on or within substrate 102. Active device 140 may include any conceivable electroactive element formed within substrate 102 and operating differently from transistor 110. Active device 140 is shown, for example, as a doped region within substrate 102 (e.g., part of a diode junction extending into or out of the page plane), but in other examples, active device 140 may include one or more of transistors, capacitors, resistors, and / or other electrical components formed on or within substrate 102.

[0030] The portion of substrate 102 located between transistor 110 and active device 140 may define a partition region D of substrate 102. Partially shown with dashed lines to indicate an indefinite length. According to one example, partition region D may have a horizontal width of at least about thirty micrometers (µm), and in various embodiments, it may be fifty micrometers, one hundred micrometers, five hundred micrometers, etc. Regardless of the implementation, partition region D may be defined to include all portions of substrate 102 located between substrate 102 and active device 104, excluding other electrically active devices and / or insulating materials formed on or within substrate 102. Furthermore, the size of partition region D may prevent any current within active device 140 from electrically biasing substrate 102 below channel region 112, although no additional insulating material is present within partition region D. The presence of body contacts 122a, 122b provides strong local control, which makes the electrical behavior of transistor 110 independent of any other active or passive devices on IC 100.

[0031] Turn now Figure 3 Other embodiments of the IC structure 100 may include different configurations of components adjacent to the transistor 110. Similar to other configurations discussed herein, the IC structure 100 may include a substrate 102, a high-resistivity semiconductor material 106 formed on a portion of the substrate 102, and a transistor 110 located on the high-resistivity semiconductor material 106. The high-resistivity semiconductor material 106 vertically separates the substrate 102 from the channel region 112 of the transistor 110 above it. The transistor 110 may be located horizontally between the first and second insulating regions 120a, 120b. However, in Figure 3 In this configuration, the top surface J of the high-resistivity semiconductor material 106 can be coplanar with the top surface K of the substrate 102. Here, the substrate 102 may not have doped well regions, where the high-resistivity semiconductor material 106 defines a uniquely distinct material region within the substrate 102. The first doped well 104a and / or the second doped well 104b can be maintained within the IC structure 100 by being formed on the upper surface K of the substrate 102 and adjacent to the insulating regions 120a, 120b. In this configuration, the body terminals 122a, 122b can be formed by introducing dopants into the respective doped wells 104a, 104b and forming contacts 136a, 136b to the body terminals 122a, 122b, respectively.

[0032] exist Figure 3In this configuration, the main terminals 122a and 122b maintain the ability to electrically bias the substrate 102 below the channel region 112 and adjacent portions of the substrate 102. Although the doped wells 104a and 104b do not extend below the top surface K of the substrate 102, the horizontal separation distance M between each end E1 and E2 of the high-resistivity semiconductor material 106 and the corresponding doped wells 104a and 104b can be, for example, up to about five micrometers. The formation of the high-resistivity semiconductor material 106 prevents any noise coupled from the substrate or from adjacent devices (which could be another MOSFET, diode, BJT, etc.). In such a configuration, applying a voltage to the main terminals 122a and 122b can affect the threshold voltage of the transistor 110 and thus affect the ability of the transistor 110 to form a conductive path through the channel region 112. Furthermore, the separation distance M can be smaller than the horizontal width of the insulating regions 120a and 120b to prevent the formation of a current path between the doped wells 104a and 104b and the channel region 112 of the transistor 110.

[0033] refer to Figure 3 and 4 Similarly, embodiments of IC structure 100 can be used for active devices 140 formed on substrate 102 without requiring additional insulating material to be formed on or within substrate 102. Figure 4 As shown, substrate 102 may span an indeterminate horizontal length from transistor 110 to active device 140. As discussed elsewhere herein, active device 140 may include any conceivable electroactive element (e.g., transistor, capacitor, resistor, and / or other electroactive element) formed within substrate 102 and operationally distinct from transistor 110. Separator D is partially shown in dashed lines to indicate an indeterminate length and may have a horizontal width of at least about thirty micrometers, as discussed elsewhere herein. Separator D may include all portions of substrate 102 located between substrate 102 and active device 140, excluding other electroactive devices and / or insulating material formed on or within substrate 102. Although no additional insulating material is present within separator D, separator D may be large enough to prevent current within active device 140 from electrically biasing substrate 102 below channel region 112. Similarly, the size and scale of the separation region D can prevent the electrical bias of the doped wells 104a and 104b from significantly affecting the active device 140.

[0034] The embodiments of this disclosure can provide several technical and commercial advantages, some of which are discussed herein by way of example. By providing a high-impedance semiconductor material 106 between the substrate 102 and the transistor 110, while other portions of the substrate 100 within the first region 102 are free of other insulating and / or other high-impedance materials, the body terminals 122a, 122b can be effectively biased against the channel region 112 with strong local control. Compared to insulating regions of material formed on or within the substrate 102 (e.g., in conventional structures), embodiments of the IC structure 100 provide a significantly reduced junction capacitance between the substrate 102 and the channel region 112 when a bias voltage is applied to the substrate 102. These technical features can be achieved with a high-impedance semiconductor material that is relatively thin compared to insulating materials and / or layers typically formed to a portion of the body terminals of the transistor channel region, due to the inherent properties of the high-impedance semiconductor material. During operation, these features of the IC structure 100 can prevent significant deviations between the expected and actual values ​​of the voltage gain across the body terminals of the transistor 110. As discussed herein, embodiments of IC structure 100 prevent electrical bias interference from the substrate 102 beneath the high-impedance semiconductor material 106 from forming active devices 140 at other locations on the substrate 102.

[0035] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art within the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, and / or technical improvements to technologies found in the market, and / or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit (IC) structure, comprising: Substrate; A high-impedance semiconductor material is located on a portion of the substrate; A transistor located on the top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in the horizontal direction between a first source / drain (S / D) region and a second source / drain region, wherein the high-impedance semiconductor material is located in the vertical direction between the transistor and the substrate; A first insulating region is located on the substrate and is adjacent to the first source / drain region in the horizontal direction; as well as A first doped well is located on the substrate and is horizontally adjacent to the first insulating region, wherein the first insulating region is horizontally located between the first doped well and the transistor. A portion of the substrate located below the first insulator region lies horizontally between the high-impedance semiconductor material and the first doped well.

2. The IC structure according to claim 1 further includes: The second insulating region is located on the substrate and is adjacent to the second source / drain region in the horizontal direction; as well as A second doped well is located on the substrate and is horizontally adjacent to the second insulating region, wherein the second insulating region is horizontally located between the second doped well and the transistor.

3. The IC structure according to claim 2, wherein the high-impedance semiconductor material extends continuously from a first end located below the first insulator region to a second end located below the second insulator region.

4. The IC structure according to claim 1, wherein the high-impedance semiconductor material comprises polysilicon, and wherein the substrate, the first doped well, and the transistor do not contain polysilicon.

5. The IC structure according to claim 1, wherein the first doped well and the semiconductor channel region of the transistor have a first doping type, and wherein the first source / drain region and the second source / drain region have a second doping type opposite to the first doping type.

6. The IC structure according to claim 1, wherein the horizontal separation between the high-impedance semiconductor material and the first doped well is less than the horizontal width of the first insulator region.

7. The IC structure of claim 1, further comprising a body terminal to the first doped well, wherein the body terminal is configured to electrically bias a portion of the substrate beneath the high-impedance semiconductor material.

8. The IC structure of claim 1 further includes an active device located within the substrate, wherein the substrate includes a partition region located in a horizontal direction between the active device and the first doped well.

9. The IC structure of claim 8, wherein the horizontal width of the partition region of the substrate prevents the active device from electrically biasing a portion of the substrate located beneath the high-impedance semiconductor material.

10. An integrated circuit (IC) structure, comprising: Substrate having a top surface; A high-resistivity semiconductor material is located within the substrate, wherein the top surface of the high-resistivity semiconductor material is coplanar with the top surface of the substrate; A transistor located on the top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in the horizontal direction between a first source / drain (S / D) region and a second source / drain region, wherein the high-impedance semiconductor material is located in the vertical direction between the transistor and the substrate; A first insulating region is located on the top surface of the substrate and is adjacent to the first source / drain region in the horizontal direction; A first doped well is located within the substrate and is horizontally adjacent to the first insulating region, wherein the first insulating region is horizontally located between the first doped well and the first source / drain region of the transistor. The first main terminal is located on the first doped well; The second insulating region is located on the top surface of the substrate and is adjacent to the second source / drain region in the horizontal direction; A second doped well is located within the substrate and is horizontally adjacent to the second insulating region, wherein the second insulating region is horizontally located between the second doped well and the second source / drain region of the transistor; as well as The second main terminal is located on the second doped well.

11. The IC structure of claim 10, wherein the high-impedance semiconductor material extends continuously from a first end located below the first insulator region to a second end located below the second insulator region.

12. The IC structure of claim 10, wherein the bottom surface of the first insulating region is lower than the top surface of the first doped well, and wherein the bottom surface of the second insulating region is lower than the top surface of the second doped well.

13. The IC structure of claim 10 further includes an active device located within the substrate, wherein the substrate includes a partition region located in a horizontal direction between the active device and the first doped well or the second doped well.

14. The IC structure of claim 13, wherein the horizontal width of the partition region of the substrate prevents the active device from electrically biasing a portion of the substrate located beneath the high-impedance semiconductor material.

15. An integrated circuit (IC) structure, comprising: Substrate having a top surface; A high-resistivity semiconductor material is located within the substrate, wherein the top surface of the high-resistivity semiconductor material is coplanar with the top surface of the substrate; A transistor located on the top surface of the high-impedance semiconductor material, the transistor including a semiconductor channel region located in the horizontal direction between a first source / drain (S / D) region and a second source / drain region, wherein the high-impedance semiconductor material is located in the vertical direction between the transistor and the substrate; A first insulating region is located on the top surface of the substrate and the top surface of the high-resistivity semiconductor material, and is adjacent to the first source / drain region in the horizontal direction. The second insulating region is located on the top surface of the substrate and the top surface of the high-impedance semiconductor material, and is adjacent to the second source / drain region in the horizontal direction. A first doped well is located on the top surface of the substrate and is horizontally adjacent to the first insulating region and the substrate, wherein the first insulating region is horizontally located between the first doped well and the transistor; The first main terminal is located within the first doped well; A second doped well is located on the top surface of the substrate and is horizontally adjacent to the first insulating region and the substrate, wherein the second insulating region is horizontally located between the second doped well and the transistor; as well as The second main terminal is located within the second doped well.

16. The IC structure of claim 15, wherein the high-impedance semiconductor material extends continuously horizontally from a first end located below the first insulator region to a second end located below the second insulator region.

17. The IC structure of claim 15, wherein the bottom surface of the first insulating region is coplanar with the bottom surface of the first doped well, and wherein the bottom surface of the second insulating region is coplanar with the bottom surface of the second doped well.

18. The IC structure of claim 15, further comprising an active device located within the substrate, wherein the substrate includes a partition region located in a horizontal direction between the active device and the first doped well or the second doped well.

19. The IC structure of claim 18, wherein the horizontal width of the partition region of the substrate prevents the active device from electrically biasing a portion of the substrate located beneath the high-impedance semiconductor material.

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