Low-cost low-voltage antifuse array

Abstract

The present invention relates to a low-cost low-voltage anti-fuse array, which includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistors of all anti-fuse memory cells have anti-fuse gates shared with other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit lines, and the anti-fuse memory cells in the same row are connected to different bit lines, while all anti-fuse memory cells are connected to the same selection line and are respectively connected to different word lines. The present invention utilizes a configuration method of sharing source contacts to achieve a stable source architecture and reduce the overall layout area. At the same time, the least control voltage types can be used to reduce leakage current.

Description

Technical Field

[0001] The invention relates to an anti-fuse transistor, in particular to a low-cost and low-voltage anti-fuse array. Background Art

[0002] Anti-fuse transistors mainly add a dielectric layer between two conductors in a capacitive manner. When writing, a bias is applied to each of the two end conductors to cause the dielectric layer to collapse and break down. After writing, the resistance value of the anti-fuse will decrease. With the rapid development of integrated circuits, the size of components is shrinking. In recent years, the use of MOS components to make anti-fuse transistors has been developed, and its writing method is mainly based on the gate dielectric layer collapse mechanism. Since anti-fuse transistors are based on the rupture of the gate dielectric layer to form a permanent conductive path, their limitation is that a voltage sufficient to collapse the gate dielectric layer must be applied. However, in traditional anti-fuse transistors, the junction of the anti-fuse gate and the gate dielectric layer is mostly a flat surface, and its charge density will be evenly distributed. In order to achieve the purpose of breaking through the gate dielectric layer, a high voltage is required, which also requires a relatively high current, and the component area is larger.

[0003] Please refer to Figure 1 , describing a low voltage anti-fuse element and array known to the applicant of this case. The anti-fuse gate 2 of each anti-fuse memory cell 1 is designed to be shared by four gate dielectric layers 3, so that a sharp corner is formed at the junction of the anti-fuse gate 2 and the gate dielectric layer 3, thereby utilizing the tip discharge principle to reduce the breakdown voltage, reduce current consumption, and reduce the device area. When performing a write operation, the selection line SL1 or SL2 is grounded to select the anti-fuse memory cell 1 in the upper or lower row of the array, and a low voltage is applied to the bit line BL1, and a low voltage is provided to the word line WL1 or WL2 to select a specific anti-fuse memory cell 1 in a row of the array to break through the gate dielectric layer 3. However, when the anti-fuse array selects anti-fuse memory cell 1 for writing, other unselected anti-fuse memory cells are easily affected by the selection bias, which may cause leakage current to flow to the unselected anti-fuse memory cells through the bit line BL1. Moreover, such a source structure is not stable enough, thereby increasing cost requirements. Summary of the invention

[0004] In view of the above problems, the main purpose of the present invention is to provide a low-cost low-voltage anti-fuse array, which utilizes a source contact sharing configuration to reduce the cell area, stabilize the source architecture, and thus reduce costs; at the same time, the present invention can also reduce the types of control voltages and avoid the occurrence of leakage current.

[0005] Therefore, in order to achieve the above-mentioned purpose, the present invention provides a low-cost low-voltage anti-fuse transistor, which includes: a plurality of parallel bit lines, word lines and selection lines; these bit lines include adjacent first bit lines and second bit lines, and the word lines are perpendicular to the bit lines and include a first word line, a second word line, a third word line and a fourth word line, and the selection lines are parallel to the word lines and include a first selection line.

[0006] There are a plurality of sub-memory arrays, each of which includes a first anti-fuse memory cell, a second anti-fuse memory cell, a third anti-fuse memory cell and a fourth anti-fuse memory cell.

[0007] The first anti-fuse memory cell is connected to the first word line, the first selection line and the first bit line;

[0008] The second anti-fuse memory cell is connected to the second word line, the first selection line and the second bit line, and the first anti-fuse memory cell and the second anti-fuse memory cell are adjacent to each other in the horizontal direction;

[0009] The third anti-fuse memory cell is connected to the third word line, the first selection line and the first bit line, and the third anti-fuse memory cell and the first anti-fuse memory cell are adjacent to each other in a vertical direction;

[0010] The fourth anti-fuse memory cell is connected to the fourth word line, the first selection line and the second bit line. The fourth anti-fuse memory cell is located at the intersection of the horizontal direction of the third anti-fuse memory cell and the vertical direction of the second anti-fuse memory cell, and the first anti-fuse memory cell, the second anti-fuse memory cell, the third anti-fuse memory cell and the fourth anti-fuse memory cell are located between the first bit line and the second bit line.

[0011] The first anti-fuse memory cell, the second anti-fuse memory cell, the third anti-fuse memory cell and the fourth anti-fuse memory cell all have an anti-fuse transistor, and only one corner of the first gate dielectric layer of the anti-fuse transistor overlaps with the anti-fuse gate.

[0012] Optionally, four corners of the anti-fuse gate of the anti-fuse transistor overlap with a corner of different first gate dielectric layers respectively, so that the anti-fuse gate is shared by the four first gate dielectric layers.

[0013] Optionally, the overlapping corners of the anti-fuse gate and each first gate dielectric layer form a sharp corner. During operation, the density of charges at the sharp corner is higher to reduce the breakdown voltage, thereby reducing the current requirement of the programmed anti-fuse memory cell and reducing the device area.

[0014] The present invention utilizes a configuration method of sharing source contacts to reduce the cell area, stabilize the source architecture, and thus reduce costs; at the same time, the present invention can also reduce the types of control voltages and avoid the occurrence of leakage current.

[0015] The following is a detailed description of specific embodiments with reference to the accompanying drawings to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 The present invention is a planar layout of an anti-fuse array in the prior art.

[0018] Figure 2 FIG. 4 is a planar layout of a low-cost low-voltage antifuse array according to an embodiment of the present invention.

[0019] Figure 3 FIG. 4 is a planar layout of a sub-memory array according to an embodiment of the present invention.

[0020] Figure 4 It is a structural cross-sectional view of an anti-fuse memory cell according to an embodiment of the present invention.

[0021] Figure 5 This is another embodiment of the anti-fuse gate of the present invention.

[0022] Explanation of symbols:

[0023] 1… anti-fuse memory cell, 2… anti-fuse gate, 3… gate dielectric layer, 10… bit line, 12… first bit line, 14… second bit line, 20… word line, 22… first word line, 24… second word line, 26… third word line, 28… fourth word line, 30… selection line, 32… first selection line, 40… sub-memory array, 42… first anti-fuse memory cell, 44… second anti-fuse memory cell, 46… third anti-fuse memory cell, 48… fourth anti-fuse memory cell,

[0024] 100, 100', 100", 100"'... anti-fuse transistor, 102... substrate, 104, 104', 104", 104"'... first gate dielectric layer, 106, 106', 106", 106"'... anti-fuse gate, 108... sharp corner, 110... sidewall spacer, 112... first ion doping region, 114... channel region, 116... LDD region, 120... extension portion, 124... well region,

[0025] 200, 200', 200", 200''...select transistor, 204...second gate dielectric layer, 206, 206', 206", 206'''...select gate, 210...sidewall spacer, 212...second ion doping region, 214...channel region, 216...LDD region,

[0026] θ…angle, BL1~BL3…bit lines, WL1~WL8…word lines, SL1~SL2…select lines. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] The purpose of the present invention is to provide a low-cost low-voltage anti-fuse array, which utilizes a source contact sharing configuration to reduce the cell area, stabilize the source architecture, and thus reduce costs; at the same time, the present invention can also reduce the types of control voltages and avoid the occurrence of leakage current.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] like Figure 2 As shown, the low-cost low-voltage antifuse array provided by the embodiment of the present invention includes a plurality of parallel bit lines 10, and these bit lines 10 include bit lines BL1 to BL3, wherein bit line BL1 is defined as a first bit line 12, and bit line BL2 is defined as a second bit line 14. There are also a plurality of parallel word lines 20 perpendicular to the bit lines 10, which include word lines WL1 to WL8, wherein word lines WL1, WL2, WL3, and WL4 are respectively defined as a first word line 22, a second word line 24, a third word line 26, and a fourth word line 28. There are a plurality of parallel selection lines 30 parallel to the word lines 20, which include selection lines SL1 and SL2, wherein selection line SL1 is defined as a first selection line 32. The above-mentioned bit lines 10, word lines 20, and selection lines 30 are connected to a plurality of sub-memory arrays 40, as shown in FIG. Figure 2 The figure shows four sub-memory arrays 40 arranged in a 2*2 matrix, each sub-memory array 40 is connected to four word lines 20, one selection line 30 and two bit lines 10. Since the connection relationship between each sub-memory array 40 and the word line 20, the selection line 30 and the bit line 10 is very similar, the following description will focus on the similarities.

[0031] like Figure 3 As shown, each sub-memory array 40 includes a first anti-fuse memory cell 42, a second anti-fuse memory cell 44, a third anti-fuse memory cell 46, and a fourth anti-fuse memory cell 48, and is located between the first bit line 12 and the second bit line 14. The first anti-fuse memory cell 42 is connected to the first word line 22, the first selection line 32, and the first bit line 12. The second anti-fuse memory cell 44 is connected to the second word line 24, the first selection line 32, and the second bit line 14. The first anti-fuse memory cell 42 and the second anti-fuse memory cell 44 are adjacent to each other in the horizontal direction, that is, they are located in the same row. The third anti-fuse memory cell 46 is connected to the third word line 26, the first selection line 32, and the first bit line 12. The third anti-fuse memory cell 46 and the first anti-fuse memory cell 42 are adjacent to each other in the vertical direction, that is, they are located in the same column. The fourth anti-fuse memory cell 48 is connected to the fourth word line 28, the first selection line 32 and the second bit line 14, and the fourth anti-fuse memory cell 48 is located at the intersection of the horizontal direction of the third anti-fuse memory cell 46 and the vertical direction of the second anti-fuse memory cell 44, that is, the fourth anti-fuse memory cell 48 is located in the same row as the third anti-fuse memory cell 46, and in the same column as the second anti-fuse memory cell 44.

[0032] Since the first anti-fuse memory cell 42, the second anti-fuse memory cell 44, the third anti-fuse memory cell 46, and the fourth anti-fuse memory cell 48 are symmetrically arranged along the first selection line 32 and are all connected to the first selection line 32, they can share a source contact on the first selection line 32 and be connected to each other. Compared with the configuration method of connecting different selection lines separately, a stable source structure can be achieved and the overall layout area can be reduced.

[0033] To further illustrate, the first anti-fuse memory cell 42 includes an anti-fuse transistor 100 and a selection transistor 200 connected in series outside the anti-fuse transistor 100. The anti-fuse transistor 100 has a first gate dielectric layer 104, which is disposed on a substrate 102 and shares an anti-fuse gate 106 with other first gate dielectric layers 104, so that only one corner of the first gate dielectric layer 104 overlaps with the anti-fuse gate 106. The anti-fuse gate 106 is connected to the first bit line 12. The first ion doped region (not shown) is connected to the first selection line 32. The selection gate 206 of the selection transistor 200 is connected to the first word line 22, and the second ion doped region (not shown) is connected to the first selection line 32.

[0034] The second anti-fuse memory cell 44 includes an anti-fuse transistor 100' and a selection transistor 200' connected in series outside the anti-fuse transistor 100'. The anti-fuse transistor 100' has a first gate dielectric layer 104', which is disposed on the substrate 102 and shares an anti-fuse gate with other first gate dielectric layers, so that only one corner of the first gate dielectric layer 104' overlaps with the anti-fuse gate 106'. The anti-fuse gate 106' is connected to the second bit line 14. The first ion doped region (not shown) is connected to the first selection line 32. The selection gate 206' of the selection transistor 200' is connected to the second word line 24, and the second ion doped region (not shown) is connected to the first selection line 32.

[0035] The third anti-fuse memory cell 46 includes an anti-fuse transistor 100" and a selection transistor 200" connected in series on the outside of the anti-fuse transistor 100". The anti-fuse transistor 100" has a first gate dielectric layer 104", and the first gate dielectric layer 104" is arranged on the substrate 102 and shares an anti-fuse gate 106" with other first gate dielectric layers, so that only one corner of the first gate dielectric layer 104" overlaps with the anti-fuse gate 106". The anti-fuse gate 106" is connected to the first bit line 12. The first ion doped region (not shown in the figure) is connected to the first selection line 32. The selection gate 206" of the selection transistor 200" is connected to the third word line 26, and the second ion doped region (not shown in the figure) is connected to the first selection line 32.

[0036] The fourth anti-fuse memory cell 48 includes an anti-fuse transistor 100"' and a selection transistor 200"' connected in series to the outside of the anti-fuse transistor 100"'. The anti-fuse transistor 100"' has a first gate dielectric layer 104"', which is disposed on the substrate 102 and shares an anti-fuse gate 106"' with other first gate dielectric layers, so that only one corner of the first gate dielectric layer 104"' overlaps with the anti-fuse gate 106"'. The anti-fuse gate 106"' is connected to the second bit line 14. The first ion-doped region (not shown in the figure) is connected to the first selection line 32. The selection gate 206"' of the selection transistor 200"' is connected to the fourth word line 28, and the second ion-doped region (not shown in the figure) is connected to the first selection line 32.

[0037] In the present invention, the first anti-fuse memory cell 42 , the second anti-fuse memory cell 44 , the third anti-fuse memory cell 46 , and the fourth anti-fuse memory cell 48 respectively have anti-fuse gates 106 , 106 ′, 106 ″, and 106 ′″ shared with other anti-fuse memory cells.

[0038] like Figure 2As shown, the four corners of the anti-fuse gate 106'" overlap with a corner of four different first gate dielectric layers respectively, that is, four anti-fuse memory cells adjacent in rows and columns (in the definition of the present invention, the four anti-fuse memory cells belong to different sub-memory arrays 40 respectively) share one anti-fuse gate 106'".

[0039] Furthermore, the four corners of the anti-fuse gates 106, 106', 106" and 106'" of the present embodiment are respectively formed with a sharp corner 108 on different first gate dielectric layers. The angle θ of the sharp corner 108 (see Figure 3 ) is preferably less than or equal to 90 degrees; in practice, the number of sharp corners 108 formed at each corner is at least one, preferably one, and can also be designed as multiple sharp corners 108, and the size of the sharp corner 108 is not limited and can be appropriately selected according to the preset write voltage and the thickness of the first gate dielectric layer.

[0040] like Figure 5 As shown, another embodiment of the anti-fuse gate 106'' is shown. The four corners of the anti-fuse gate 106'' are respectively formed with extensions 120 protruding outward. The extensions 120 have two sharp corners 108, and the angle θ of each sharp corner 108 is preferably less than or equal to 90 degrees. The present invention utilizes the configuration of a shared anti-fuse gate to reduce the anti-fuse gate area and achieve the effect of reducing the size of the component.

[0041] Next, the detailed structures of the first anti-fuse memory cell 42, the second anti-fuse memory cell 44, the third anti-fuse memory cell 46, and the fourth anti-fuse memory cell 48 are described. Since the cross-sectional structures of each anti-fuse memory cell are substantially the same, only the first anti-fuse memory cell 42 is used as a representative. Figure 4As shown, the anti-fuse transistor 100 and the selection transistor 200 connected in series therewith have a well region 124 disposed on the substrate 102. The anti-fuse transistor 100 includes a first gate dielectric layer 104, a shared anti-fuse gate 106, a sidewall spacer 110, a first ion doped region 112, and a channel region 114. The first gate dielectric layer 104 is formed on the well region 124, the anti-fuse gate 106 is disposed on a corner of the first gate dielectric layer 104, the sidewall spacer 110 is formed on the outer side of the anti-fuse gate 106, the first ion doped region 112 is formed in the well region 124 on one side of the first gate dielectric layer 104, and may have a lightly doped (LDD) region 116 adjacent to the vertical edge of the first gate dielectric layer 104. The selection transistor 200 includes a second gate dielectric layer 204, a selection gate 206, a sidewall spacer 210, a second ion doped region 212, and a channel region 214. The second gate dielectric layer 204 is disposed on the well region 124, and the second gate dielectric layer 204 is connected to the first gate dielectric layer 104. The selection gate 206 covers the second gate dielectric layer 204, and has sidewall spacers 210 on both sides. The first ion doped region 112 is formed on one side of the second gate dielectric layer 204, and the second ion doped region 212 is formed on the other side of the second gate dielectric layer 204, that is, in the well region 124 on the side of the second gate dielectric layer 204 away from the first ion doped region 112. The second ion doped region 212 may have a lightly doped (LDD) region 216 adjacent to the vertical edge of the second gate dielectric layer 204. The first ion-doped region 112 and the second ion-doped region 212 may be doped with the same type of ions, and the first ion-doped region 112 and the well region 124 may be doped with different types of ions and may have different doping concentrations depending on the desired operating voltage.

[0042] In this embodiment, the substrate 102 can be a P-type semiconductor substrate or an N-type semiconductor substrate; when the substrate 102 is a P-type semiconductor substrate, the first ion doping region 112 and the second ion doping region 212 are N-type doping regions, and the well region 124 is a P-type doping region; when the substrate 102 is an N-type semiconductor substrate, the first ion doping region 112 and the second ion doping region 212 are P-type doping regions, and the well region 124 is an N-type doping region. The first gate dielectric layer 104 is a gate oxide with a relatively thin and substantially uniform thickness under the anti-fuse gate 106, and its material can be selected from an oxide layer, a nitride layer, an oxynitride layer, a metal oxide layer, and a combination thereof. Each anti-fuse memory cell of the above-mentioned embodiment can be manufactured by any standard CMOS process, such as the formation of sidewall spacers, light doping (LDD) and gate silicide. The second gate dielectric layer 204 is formed at the same time as the first gate dielectric layer 104 is formed. Therefore, the second gate dielectric layer 204 and the first gate dielectric layer 104 have substantially the same composition and may have the same or different thicknesses.

[0043] When performing a write operation, the first selection line 32 is grounded, and a low voltage is applied to the first bit line 12 or the second bit line 14 to select the second anti-fuse memory cell 44 and the fourth anti-fuse memory cell 48 in the right column or the first anti-fuse memory cell 42 and the third anti-fuse memory cell 46 in the left column in the sub-memory array 40, and a low voltage is provided to the first word line 22, the second word line 24, the third word line 26 or the fourth word line 28 to select a specific anti-fuse memory cell in a column of the sub-memory array 40 to break through the first gate dielectric layer 104. For example, the first selection line 32 is grounded, a low voltage is applied to the second bit line 14, and a low voltage is applied to the second word line 24, so that the second anti-fuse memory cell 44 is used as the selected memory cell to be written.

[0044] The present invention uses a word line to replace a selection line to select an anti-fuse memory cell to be written, so that other anti-fuse memory cells are not affected by the selection bias voltage, thereby reducing the occurrence of leakage current. At the same time, the present invention uses the principle of tip discharge, and each corner of the anti-fuse gate has a sharp corner. Since a large amount of charge is concentrated at the sharp corner, the electric field is strong, so that a part of the first gate dielectric layer corresponding to the sharp corner collapses, the required writing voltage is reduced, it is easier to be broken down, and the writing time can be shortened.

[0045] In summary, according to the low-cost low-voltage anti-fuse array provided by the present invention, based on the architecture of sharing the anti-fuse gate, multiple anti-fuse memory cells in the array are connected to the same selection line and connected to different word lines, so as to utilize the source contact sharing method to realize a stable source architecture and reduce the overall layout area. At the same time, the minimum control voltage can be used to reduce the occurrence of leakage current, thereby reducing the manufacturing cost.

[0046] The above description is to illustrate the features of the present invention by way of embodiments, and its purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly, rather than to limit the patent scope of the present invention. Therefore, any other equivalent modifications or amendments that do not depart from the spirit disclosed by the present invention should still be included in the scope of the patent application described below.

[0047] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A low-cost, low-voltage antifuse array, characterized in that: The low-cost, low-voltage antifuse array includes: A plurality of parallel bit lines, including a first bit line and a second bit line adjacent to each other; A plurality of parallel word lines are perpendicular to the bit lines and include a first word line, a second word line, a third word line and a fourth word line; A plurality of parallel selection lines are parallel to the word lines and include a first selection line; A plurality of sub-memory arrays, each of the sub-memory arrays comprising: a first anti-fuse memory cell, connecting the first word line, the first selection line and the first bit line; a second anti-fuse memory cell, connecting the second word line, the first selection line and the second bit line; the first anti-fuse memory cell and the second anti-fuse memory cell are adjacent to each other in a horizontal direction; a third anti-fuse memory cell, connecting the third word line, the first selection line and the first bit line, the third anti-fuse memory cell and the first anti-fuse memory cell being adjacent to each other in a vertical direction; and a fourth anti-fuse memory cell, connecting the fourth word line, the first selection line and the second bit line, the fourth anti-fuse memory cell being located at an intersection of a horizontal direction of the third anti-fuse memory cell and a vertical direction of the second anti-fuse memory cell, and the first anti-fuse memory cell, the second anti-fuse memory cell, the third anti-fuse memory cell and the fourth anti-fuse memory cell being located between the first bit line and the second bit line; The first anti-fuse memory cell, the second anti-fuse memory cell, the third anti-fuse memory cell and the fourth anti-fuse memory cell all have an anti-fuse transistor, and only one corner of a first gate dielectric layer of the anti-fuse transistor overlaps with an anti-fuse gate.

2. The low-cost low-voltage antifuse array according to claim 1, characterized in that: Four corners of the anti-fuse gate overlap with a corner of a different first gate dielectric layer respectively.

3. The low-cost low-voltage antifuse array according to claim 2, characterized in that: The four corners of the anti-fuse gate each form at least one sharp angle, and the sharp angle is less than or equal to 90 degrees.

4. The low-cost low-voltage antifuse array according to claim 3, characterized in that: The four corners of the anti-fuse gate each form an extension portion, and the extension portion has two sharp corners.

5. The low-cost low-voltage antifuse array according to claim 1, characterized in that: The first anti-fuse memory cell has the anti-fuse transistor and a selection transistor, and the anti-fuse transistor includes: The anti-fuse gate is disposed on a substrate and connected to the first bit line; The first gate dielectric layer is disposed between the anti-fuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The select transistor comprises: a selection gate disposed on the substrate and connected to the first word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate at a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region and the first ion doping region are doped with the same type of ions.

6. The low-cost low-voltage antifuse array according to claim 1, characterized in that: The second anti-fuse memory cell has the anti-fuse transistor and a selection transistor, and the anti-fuse transistor includes: The anti-fuse gate is disposed on a substrate and connected to the second bit line; The first gate dielectric layer is disposed between the anti-fuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The select transistor comprises: a selection gate disposed on the substrate and connected to the second word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate at a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region is doped with the same type of ions as the first ion doping region.

7. The low-cost low-voltage antifuse array according to claim 1, characterized in that: The third anti-fuse memory cell has the anti-fuse transistor and a selection transistor, and the anti-fuse transistor includes: The anti-fuse gate is disposed on a substrate and connected to the first bit line; The first gate dielectric layer is disposed between the anti-fuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The select transistor comprises: a selection gate disposed on the substrate and connected to the third word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate at a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region and the first ion doping region are doped with the same type of ions.

8. The low-cost low-voltage antifuse array according to claim 1, characterized in that: The fourth anti-fuse memory cell has the anti-fuse transistor and a selection transistor, and the anti-fuse transistor includes: The anti-fuse gate is disposed on a substrate and connected to the second bit line; The first gate dielectric layer is disposed between the anti-fuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The select transistor comprises: a selection gate disposed on the substrate and connected to the fourth word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate at a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region is doped with the same type of ions as the first ion doping region.

9. The low-cost low-voltage antifuse array according to any one of claims 5 to 8, characterized in that: The substrate is a P-type semiconductor substrate, and the first ion-doped region and the second ion-doped region are N-type doped regions.

10. The low-cost low-voltage antifuse array according to any one of claims 5 to 8, characterized in that: The substrate is an N-type semiconductor substrate, and the first ion-doped region and the second ion-doped region are P-type doped regions.

11. The low-cost low-voltage antifuse array according to any one of claims 5 to 8, characterized in that: The low-cost low-voltage anti-fuse array further comprises a well region, which is arranged in the substrate and located below the first ion doping regions. The well region and the first ion doping regions are doped with ions of different types.

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