Conjugate symmetric matrix data access method, device and terminal

Abstract

A method and device for accessing conjugate symmetric matrix data, and a terminal, the method comprising: using a preset number of parallel memories to store N conjugate symmetric matrices of N order 2 data, among which, for the N 2 The data is divided, and the divided data is stored in different memories. The amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number after storage are consistent among the memories. The present invention can effectively save wiring area, reduce the area overhead occupied by the storage device, alleviate the layout and wiring congestion of the back end, and reduce the storage cost.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for accessing conjugate symmetric matrix data, and a terminal. Background Art

[0002] The terminal estimates the channel state and other related information according to the downlink channel state information reference signal (CSI-RS) sent by the base station, and calculates the downlink channel state information (CSI) information that is suitable for its own receiving capability and demodulation capability, and then sends this information to the base station. The base station can adjust the data transmission method according to the content of the CSI information, thereby promoting the effective transmission of data interaction between the base station and the terminal and improving the communication quality.

[0003] In a single CSI reporting cycle, several CSI-RS can be configured at the same time. For each CSI-RS, data operation will be started and extracted according to predefined rules for codebook calculation. Since the data processing rate of data operation is different from the extraction rate, the data obtained after the operation needs to be cached.

[0004] In the prior art, data caching is performed in the form of registers, so that each data can be directly obtained and different data extraction in different combinations can be easily realized. However, when the amount of data is large, using registers to directly store data will cause problems such as large area overhead of storage devices and congestion of back-end layout and wiring, thereby increasing storage costs.

[0005] There is an urgent need for a conjugate symmetric matrix data access method that can reduce the area overhead of storage devices, alleviate back-end layout and routing congestion, and reduce storage costs. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a conjugate symmetric matrix data access method, device and terminal, which can effectively improve the extraction efficiency, save wiring area, reduce the area overhead occupied by the storage device, alleviate the layout and wiring congestion of the back end, and reduce the storage cost.

[0007] In order to solve the above technical problems, an embodiment of the present invention provides a method for accessing conjugate symmetric matrix data, comprising: using a preset number of parallel memories to store N in an N-order conjugate symmetric matrix 2 data, among which, for the N 2The data is divided, and each part of the divided data is stored in a different memory, and the amount of data stored in each memory is equal. Moreover, among the memories, the logical addresses of the data with the same row number and column number after storage are kept consistent.

[0008] Optionally, in the N-th order conjugate symmetric matrix N is stored 2 Before the data, the access method of the conjugate symmetric matrix data also includes: determining the upper triangular data of the N-order conjugate symmetric matrix; calculating the N contained in the N-order conjugate symmetric matrix according to the complex conjugate symmetric property of the conjugate symmetric matrix and the upper triangular data of the N-order conjugate symmetric matrix; 2 The remaining data in the data.

[0009] Optionally, determining the first column data or the first row data of the N-order conjugate symmetric matrix includes: determining the channel estimation results and noise estimation results of the CSI-RS obtained based on the N transmitting antenna ports and M receiving antennas of the CSI-RS signal, and determining the relevant data of each transmitting antenna port with itself and subsequent transmitting antenna ports as the upper triangular data of the N-order conjugate symmetric matrix.

[0010] Optionally, the N 2 The data are obtained by dividing the row data into N / k columns and dividing the column data into N / m rows; wherein k and m are both divisors of N, and 1<k<N, 1<m<N.

[0011] Optionally, the divided data is stored in groups, and adjacent groups are stored in the same or different memories; wherein each group of data contains an equal amount of data, and the amount of data in each group of data is less than or equal to the amount of data in a single area after division.

[0012] Optionally, the N 2 The data is divided by using the N / 2th row and column data and the N / 2th column and row data to obtain 4 groups of data and store them in four memories respectively.

[0013] Optionally, the N 2 The data are divided into groups with P rows and P columns of data each, so as to obtain group data of N / P rows and N / P columns; wherein the group data of odd rows and odd columns are stored in a first memory, the group data of odd rows and even columns are stored in a second memory, the group data of even rows and odd columns are stored in a third memory, and the group data of even rows and even columns are stored in a fourth memory; P is a divisor of N, and 1<P<N.

[0014] Optionally, the method further comprises: extracting at least a portion of the data in the memory, wherein each time a logical address is used to extract all the data pointed to by the logical address.

[0015] Optionally, extracting at least a portion of the data in the memory includes: extracting in groups, and extracting the data in the memory using the logical addresses of all data in a single group each time.

[0016] Optionally, the method for accessing conjugate symmetric matrix data further includes: merging the extracted data.

[0017] Optionally, the number of memories is 4, and the merging rule of the merging process is to equally divide the data into 4 blocks and then perform matrix extraction and merging; the merging process of the extracted data includes: merging the 4 data pointed to by each logical address to obtain N 2 / 4 data.

[0018] Optionally, the number of memories is 4, and the merging rule of the merging process is to equally divide the data into 16 blocks and then perform matrix extraction and merging; the merging process of the extracted data is selected from: merging the 4 data pointed to by each logical address to obtain N 2 / 4 data; or, for the N 2 The data are extracted and merged to obtain N 2 / 16 data.

[0019] Optionally, for the N 2 Extracting and merging the N data includes: 2 The data are divided into 16 parts with N / 4 columns and N / 4 rows as intervals; the data with the same row number and column number in the 16 parts are extracted and merged.

[0020] Optionally, the memory is selected from: random access memory RAM and flash memory.

[0021] In order to solve the above technical problems, an embodiment of the present invention provides a conjugate symmetric matrix data access device, comprising: a storage module, which is used to use a preset number of parallel memories to store N in the N-order conjugate symmetric matrix 2 data, among which, for the N 2 The data are divided, and the divided parts of the data are stored in different memories. The amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number stored in each memory remain consistent.

[0022] In order to solve the above technical problem, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above conjugate symmetric matrix data access method are executed.

[0023] To solve the above technical problems, an embodiment of the present invention provides a terminal, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of the above-mentioned conjugate symmetric matrix data access method when running the computer program.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the embodiment of the present invention, by dividing the conjugate symmetric matrix data, multiple data can be extracted each time when extracting data, and the logical addresses of the data with the same row number and column number after division in each memory are consistent, so that it is easy to extract the conjugate symmetric data in the same round of extraction. Compared with the use of registers in the prior art, which requires N2 registers and related wiring, the solution of the embodiment of the present invention significantly reduces the number of memories, can effectively save wiring area, reduce the area overhead occupied by storage devices, alleviate the layout and wiring congestion of the back end, and reduce storage costs.

[0026] Furthermore, at least a portion of the data in the memory is extracted, wherein each time a logical address is used to extract all the data pointed to by the logical address. Compared with the prior art that uses registers and needs to extract data in registers one by one, the solution of the embodiment of the present invention can obtain all the data pointed to by the logical address in a single extraction, thereby effectively improving the extraction efficiency.

[0027] Further, according to the channel estimation results and noise estimation results of the CSI-RS measured by the N transmitting antenna ports and M receiving antennas of the CSI-RS signal, the relevant data of each transmitting antenna port and itself and the subsequent transmitting antenna ports are determined as the upper triangular data of the N-order conjugate symmetric matrix, and the N contained in the N-order conjugate symmetric matrix can be calculated according to the complex conjugate symmetry property of the conjugate symmetric matrix and the upper triangular data of the N-order conjugate symmetric matrix. 2 The remaining data in the data is used to improve the operation efficiency according to the characteristics of large data volume and complex operation of CSI-RS data processing.

[0028] Furthermore, the divided data is stored in groups, and adjacent groups are stored in the same or different memories; wherein the amount of data contained in each group of data is equal, and the amount of data in each group of data is less than or equal to the amount of data in a single area after division. By adopting the scheme of the embodiment of the present invention, after dividing the row data with N / k columns as intervals and dividing the column data with N / m rows as intervals, multiple groups of data can be formed, and then stored in groups, so that adjacent data with strong correlation are stored in the same memory and the logical addresses are consistent, which can improve the accuracy during subsequent extraction.

[0029] Further, in a specific implementation of the embodiment of the present invention, the N 2 The data is divided by the N / 2th row and column data and the N / 2th column and row data to obtain 4 groups of data and store them in four memories respectively, so that more adjacent data can be stored in the same memory and the logical address remains consistent, thereby further improving the accuracy of subsequent extraction.

[0030] Further, in another specific implementation of the embodiment of the present invention, the N 2 The data are divided into a group with P rows and P columns of data to obtain group data of N / P rows and N / P columns, wherein the group data of odd rows and odd columns are stored in a first memory, the group data of odd rows and even columns are stored in a second memory, the group data of even rows and odd columns are stored in a third memory, and the group data of even rows and even columns are stored in a fourth memory, so that more non-adjacent data can be stored in the same memory, thereby further improving the storage flexibility and the flexibility of subsequent extraction.

[0031] Furthermore, by extracting in groups, the data in the memory is extracted using the logical addresses of all the data in a single group each time, so that adjacent data with strong correlation can be extracted at the same time during extraction, thereby improving accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a flow chart of a CSI-RS data calculation process in the prior art;

[0033] Figure 2 is a flow chart of a method for accessing conjugate symmetric matrix data in an embodiment of the present invention;

[0034] Figure 3 It is a schematic diagram of a working scenario of a method for accessing conjugate symmetric matrix data in an embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of a working scenario of another method for accessing conjugate symmetric matrix data in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of a working scenario of a merging processing method in an embodiment of the present invention;

[0037] Figure 6 is a schematic diagram of a working scenario of another merging processing method in an embodiment of the present invention;

[0038] Figure 7 1 is a flow chart of a CSI-RS data calculation process in an embodiment of the present invention;

[0039] Figure 8It is a structural schematic diagram of a conjugate symmetric matrix data access device in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] As mentioned above, in a single CSI reporting period, several CSI-RSs can be configured simultaneously. For each CSI-RS, data operation is started and extracted according to predefined rules to perform codebook calculation.

[0041] In the CSI-RS data calculation process, information such as channel quality indication (Channel-Quality Indicator, CQI), precoding matrix indication (Precoder-Matrix Indicator, PMI), rank indication (Rank Indicator, RI), reference signal resource indicator (CSI-RS resource Indicator, CRI), and layer indication (Layer Indicator, LI) can be determined.

[0042] Specifically, during the operation, the noise coefficient matrix obtained by the previous noise estimation module can be decomposed and inverted, multiplied with the channel estimation matrix calculated by the channel estimation for whitening, the conjugate symmetric matrix is ​​calculated and smoothed, and then the codebook is calculated. After being processed by many algorithm processes such as subband filtering and broadband filtering, the calculated CQI, PMI, CRI, LI, RI, subband value, broadband value and other information are finally reported to the software.

[0043] The reporting time of CSI reporting information is clearly specified in the relevant protocols of the New Radio (NR) (for example, 38.214). Therefore, for the design of the operation module, it is necessary to consider not only resource consumption and allocation, system power consumption, but also the improvement of data processing time.

[0044] Reference Figure 1 , Figure 1 The CSI-RS data calculation process may include steps S11 to S18, and each step is described below.

[0045] In step S11, a channel estimation matrix is ​​determined.

[0046] In step S12, a noise coefficient matrix is ​​determined.

[0047] Specifically, the corresponding channel estimation matrix (such as H matrix) and noise estimation matrix (such as RN matrix) can be obtained through CSI-RS.

[0048] In step S13, whitening processing is performed.

[0049] Specifically, a whitening process may be performed on the channel.

[0050] In step S14, the RHH matrix is ​​calculated and smoothing is performed.

[0051] Specifically, an autocorrelation operation may be performed to obtain an autocorrelation matrix (such as an RHH matrix).

[0052] In step S15, the control logic is written.

[0053] Specifically, data may be written through write control logic.

[0054] In step S16, the register storage unit may be written or read.

[0055] In step S17, the control logic is read.

[0056] Specifically, data may be read through the read control logic.

[0057] In step S18, the codebook is calculated.

[0058] Specifically, after the codebook is calculated, the calculated information such as CQI, PMI, CRI, LI, RI, subband value, broadband value, etc. can be reported to the software.

[0059] The inventors of the present invention have found through research that when the amount of data is large, using registers to directly store data will cause problems such as large area overhead of the storage device and congestion of the back-end layout and routing, thereby increasing storage costs.

[0060] Specifically, taking the CSI-RS with 32 transmit antenna ports (Port) in the maximum CSI-RS reporting as an example, 32×32=1024 related data need to be stored, and the bit width of each data may reach 32 bits (bit) or wider according to performance requirements. According to the protocol, the calculation of the codebook needs to group the beams according to the number of horizontal and vertical antennas and the codebook mode, and perform beam selection, and calculate the polarization direction phase and amplitude. In this process, it is necessary to merge different pattern data according to the configuration, and traverse the matrix rank, beam number, number of layers (rank), number of antennas in the horizontal / vertical direction, etc. Therefore, all the data will be used in the subsequent data processing process, and the 1024 data will be extracted in various combinations.

[0061] As can be seen from the above, using registers for direct storage requires storing up to 1024 data, resulting in large device area overhead. Parallel processing of too many extraction combinations and a large amount of data will generate a large number of combinational logic operations (such as selectors) and wiring overhead, leading to back-end layout and routing congestion, increased power supply flip noise and crosstalk, increased difficulty in timing convergence, and increased manufacturing costs.

[0062] In the embodiment of the present invention, by dividing the conjugate symmetric matrix data, multiple data can be extracted each time when extracting data, and the logical addresses of the data with the same row number and column number after division in each memory are consistent, so that the conjugate symmetric data can be easily extracted in the same round of extraction. 2 The registers and their related wiring adopt the solution of the embodiment of the present invention, which can effectively improve the extraction efficiency, save the wiring area, reduce the area overhead occupied by the storage device, alleviate the back-end layout and wiring congestion, and reduce the storage cost.

[0063] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0064] Reference Figure 2 , Figure 2 1 is a flow chart of a method for accessing conjugate symmetric matrix data in an embodiment of the present invention. The method for accessing conjugate symmetric matrix data may include step S21, and may also include steps S21 to S22:

[0065] Step S21: Using a preset number of parallel memories to store N in the N-order conjugate symmetric matrix 2 data, among which, for the N 2 The data is divided, and each part of the divided data is stored in a different memory and the amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number after storage are consistent among the various memories;

[0066] Step S22: extract at least a portion of the data in the memory, wherein each time a logical address is used to extract all the data pointed to by the logical address.

[0067] It is understandable that, in a specific implementation, the method can be implemented in the form of a software program, and the software program runs in a processor integrated inside a chip or a chip module.

[0068] In the specific implementation of step S21, a preset number of memories are used in parallel to cache data.

[0069] Compared with the use of registers in the prior art, N 2 By adopting the solution of the embodiment of the present invention, a single memory can be used to store multiple data, thereby saving wiring area and reducing the area overhead occupied by the storage device.

[0070] The logical address may be regarded as a logical address area, which is used to indicate the logical addresses of multiple data.

[0071] Furthermore, the memory may be selected from: a random access memory (RAM) and a flash memory.

[0072] In the embodiment of the present invention, RAM or flash memory is used for access, which can further reduce the cost of layout and wiring.

[0073] Furthermore, in storing the N-order conjugate symmetric matrix N 2 Before accessing the conjugate symmetric matrix data, the method for accessing the conjugate symmetric matrix data may also include: determining the upper triangular data of the N-order conjugate symmetric matrix; calculating the remaining data among the N2 data contained in the N-order conjugate symmetric matrix according to the complex conjugate symmetric characteristics of the conjugate symmetric matrix and the upper triangular data of the N-order conjugate symmetric matrix.

[0074] In an embodiment of the present invention, according to the complex conjugate symmetric property of the conjugate symmetric matrix, and according to the upper triangle of the N-order conjugate symmetric matrix, the N-order conjugate symmetric matrix is ​​calculated. 2 The remaining data in the data can utilize the data characteristics of the conjugate symmetric matrix to effectively reduce the computational complexity.

[0075] Furthermore, the step of determining the first column and row data or the first row and column data of the N-order conjugate symmetric matrix may include: determining the relevant data of each transmitting antenna port and itself and subsequent transmitting antenna ports based on the channel estimation results and noise estimation results of the CSI-RS measured by the N transmitting antenna ports and M receiving antennas of the CSI-RS signal, as the upper triangular data of the N-order conjugate symmetric matrix.

[0076] Specifically, the amount of data to be stored can be determined according to the number of transmit antenna ports. Taking the CSI-RS of 32 transmit antenna ports as an example, 32×32=1024 related data need to be stored, and the bit width of each data may reach 32 bits or wider according to performance requirements.

[0077] Referring to Table 1, Table 1 is a 4th-order conjugate symmetric matrix in an embodiment of the present invention.

[0078] Table 1

[0079] <![CDATA[a0]]> <![CDATA[a1+b1j]]> <![CDATA[a2+b2j]]> <![CDATA[a3+b3j]]> <![CDATA[a1-b1j]]> <![CDATA[a4]]> <![CDATA[a5+b5j]]> <![CDATA[a6+b6j]]> <![CDATA[a2-b2j]]> <![CDATA[a5-b5j]]> <![CDATA[a7]]> <![CDATA[a8+b8j]]> <![CDATA[a3-b3j]]> <![CDATA[a6-b6j]]> <![CDATA[a8-b8j]]> <![CDATA[a9]]>

[0080] As shown in Table 1, in the upper triangular data of the N-order conjugate symmetric matrix, each data can be the related data between the corresponding transmitting antenna port and itself and the subsequent transmitting antenna ports, such as a4 can be the autocorrelation data between the second transmitting antenna port data and itself, a5+b5j can be the related data between the second transmitting antenna port data and the third transmitting antenna port data, a6+b6j can be the related data between the second transmitting antenna port data and the fourth transmitting antenna port data; a7 can be the autocorrelation data between the third transmitting antenna port data and itself, a8+b8j can be the related data between the third transmitting antenna port data and the fourth transmitting antenna port data, and so on.

[0081] After determining the upper triangular data, the N-order conjugate symmetric matrix can be determined according to the complex conjugate symmetric property of the conjugate symmetric matrix. 2 The remaining data in the data.

[0082] In an embodiment of the present invention, according to the channel estimation results and noise estimation results of the CSI-RS measured by the N transmitting antenna ports and M receiving antennas of the CSI-RS signal, the relevant data of each transmitting antenna port and itself and the subsequent transmitting antenna ports are determined as the upper triangular data of the N-order conjugate symmetric matrix, and the N contained in the N-order conjugate symmetric matrix can be calculated according to the complex conjugate symmetric property of the conjugate symmetric matrix and the upper triangular data of the N-order conjugate symmetric matrix. 2 The remaining data in the data is used to improve the operation efficiency according to the characteristics of large data volume and complex operation of CSI-RS data processing.

[0083] Furthermore, the N 2 The data can be obtained by dividing the row data into N / k columns and dividing the column data into N / m rows; wherein k and m are both divisors of N, and 1<k<N, 1<m<N.

[0084] Specifically, by using N / k columns as intervals to divide row data and using N / m rows as intervals to divide column data, N 2 The data is evenly divided, and the amount of data in each group after division is consistent.

[0085] In the embodiment of the present invention, N / k columns are used to divide row data and N / m rows are used to divide column data. 2 The data can be effectively divided.

[0086] Furthermore, the divided data is stored in groups, and adjacent groups are stored in the same or different memories; wherein each group of data contains an equal amount of data, and the amount of data in each group of data is less than or equal to the amount of data in a single area after division.

[0087] In an embodiment of the present invention, the divided data is stored in groups, and adjacent groups are stored in the same or different memories; wherein the amount of data contained in each group of data is equal, and the amount of data in each group of data is less than or equal to the amount of data in a single area after the division. By adopting the scheme of the embodiment of the present invention, after dividing the row data with N / k columns as intervals and dividing the column data with N / m rows as intervals, multiple groups of group data can be formed, and then stored in groups, so that the adjacent data with strong correlation are stored in the same memory and the logical addresses are consistent, which can improve the accuracy during subsequent extraction.

[0088] Furthermore, the N 2 The data may be divided by using the N / 2th row and column data and the N / 2th column and row data to obtain 4 groups of data and store them in four memories respectively.

[0089] Reference Figure 3 , Figure 3 It is a schematic diagram of a working scenario of a method for accessing conjugate symmetric matrix data in an embodiment of the present invention.

[0090] As shown in the figure, the N / 2th row and column data and the N / 2th column and row data are used to divide the N 2 data and store them in the first memory, the second memory, the third memory and the fourth memory respectively.

[0091] The data circled by the dotted ellipse may be single data or group data, for example, N / k×N / m data.

[0092] After being stored in each memory, the logical addresses of the reordered data with the same row number and column number are consistent, so as to be applied to subsequent extraction and merging steps.

[0093] In a specific implementation of the embodiment of the present invention, the N 2 The data is divided by the N / 2th row and column data and the N / 2th column and row data to obtain 4 groups of data and store them in four memories respectively, so that more adjacent data can be stored in the same memory and the logical address remains consistent, thereby further improving the accuracy of subsequent extraction.

[0094] Furthermore, the N 2 The data are divided into groups with P rows and P columns of data each, so as to obtain group data of N / P rows and N / P columns; wherein the group data of odd rows and odd columns are stored in a first memory, the group data of odd rows and even columns are stored in a second memory, the group data of even rows and odd columns are stored in a third memory, and the group data of even rows and even columns are stored in a fourth memory; P is a divisor of N, and 1<P<N.

[0095] It should be pointed out that although Figure 3 In the illustrated embodiment, the number of each group of data is 4×4 as an example for description, however, the number of rows and columns in each group of data may be different, for example, may be N / k×N / m.

[0096] Reference Figure 4 , Figure 4 It is a schematic diagram of a working scenario of another method for accessing conjugate symmetric matrix data in an embodiment of the present invention.

[0097] As shown in the figure, data of every P rows and P columns are divided into a group, so as to obtain group data of N / P rows and N / P columns, which can be stored in the first memory, the second memory, the third memory and the fourth memory respectively.

[0098] The portion circled by the dotted ellipse may contain P×P data.

[0099] After being stored in each memory, the logical addresses of the reordered data with the same row number and column number are consistent, so as to be applied to subsequent extraction and merging steps.

[0100] In another specific implementation of the embodiment of the present invention, the N 2 The data are divided into a group with P rows and P columns of data to obtain group data of N / P rows and N / P columns, wherein the group data of odd rows and odd columns are stored in a first memory, the group data of odd rows and even columns are stored in a second memory, the group data of even rows and odd columns are stored in a third memory, and the group data of even rows and even columns are stored in a fourth memory, so that more non-adjacent data can be stored in the same memory, thereby further improving the storage flexibility and the flexibility of subsequent extraction.

[0101] In the embodiment of the present invention, by dividing the conjugate symmetric matrix data, multiple data can be extracted each time when extracting data, and the logical addresses of the data with the same row number and column number after division in each memory are consistent, so that it is easy to extract the conjugate symmetric data in the same round of extraction. Compared with the use of registers in the prior art, which requires N2 registers and related wiring, the solution of the embodiment of the present invention significantly reduces the number of memories, can effectively save wiring area, reduce the area overhead occupied by storage devices, alleviate the layout and wiring congestion of the back end, and reduce storage costs.

[0102] Continue to refer to Figure 2 In the specific implementation of step S12, at least a portion of the data in the memory is extracted, wherein all the data pointed to by the logical address are extracted each time using the logical address.

[0103] Specifically, since the logical addresses of data with the same row number and column number after storage remain consistent between various memories, and each logical address points to multiple data, multiple data can be extracted based on a single logical address. Compared with the use of registers in the prior art, which can only extract single data based on a single logical address, the extraction efficiency can be effectively improved by using the memory in the embodiment of the present invention.

[0104] In an embodiment of the present invention, at least a portion of the data in the memory is extracted, wherein each time a logical address is used to extract all the data pointed to by the logical address. Compared with the use of registers in the prior art, which requires extracting data in registers one by one, the solution of the embodiment of the present invention can obtain all the data pointed to by the logical address in a single extraction, thereby effectively improving the extraction efficiency.

[0105] Furthermore, the step of extracting at least a portion of the data in the memory may include: extracting in groups, each time using the logical addresses of all the data in a single group to extract the data in the memory.

[0106] In the embodiment of the present invention, by extracting in groups, the data in the memory is extracted using the logical addresses of all the data in a single group each time, so that when extracting, adjacent data with strong correlation can be extracted at the same time, thereby improving accuracy.

[0107] Furthermore, the method for accessing conjugate symmetric matrix data may also include: merging the extracted data.

[0108] In a specific implementation, all the data extracted each time may be merged according to a predefined method (eg, protocol provisions), or part of the data extracted each time may be merged, or multiple rounds of extraction and merging may be performed.

[0109] In a specific implementation of the embodiment of the present invention, the number of the memories is 4, and the merging rule of the merging process is to equally divide the 4 blocks and then perform matrix extraction and merging; the step of merging the extracted data may include: merging the 4 data pointed to by each logical address to obtain N 2 / 4 data.

[0110] Reference Figure 5 , Figure 5 It is a schematic diagram of a working scenario of a merging processing method in an embodiment of the present invention.

[0111] As shown in the figure, the four data belong to different memories. The row numbers and column numbers in each memory are consistent, and the logical addresses are also consistent, so they can be merged. Similarly, in other data, the data with the same row numbers and column numbers can also be merged. After the merging process, we can get N 2 / 4 data.

[0112] It should be pointed out that the dotted ellipse may also be circled with group data, and four group data may be combined into one group data.

[0113] In the embodiment of the present invention, by setting the 4 data pointed to by each logical address to be merged, N 2 / 4 data to achieve effective merging and processing.

[0114] In another specific implementation of the embodiment of the present invention, the number of the memories is 4, and the merging rule of the merging process is to equally divide the 16 blocks and then perform matrix extraction and merging; the merging process of the extracted data is selected from: merging the 4 data pointed to by each logical address to obtain N 2 / 4 data; or, for the N 2 The data are extracted and merged to obtain N 2 / 16 data.

[0115] Furthermore, for the N 2 The step of extracting and merging the N data may include: 2 The data are divided into 16 parts with N / 4 columns and N / 4 rows as intervals; the data with the same row number and column number in the 16 parts are extracted and merged.

[0116] Reference Figure 6 , Figure 6 It is a schematic diagram of a working scenario of another merging processing method in an embodiment of the present invention.

[0117] As shown in the figure, the N / 4 columns and N / 4 rows shown by the dashed lines can be used to 2 The data is divided into 16 parts, each part contains 4 data.

[0118] The 16 data points enclosed by the dotted ellipse are merged. Similarly, in the other data points, every 16 corresponding data points can also be merged. After the merging process, we can get N 2 / 16 data.

[0119] It should be pointed out that the dotted ellipse may also be group data, and 16 group data may be combined into one group data.

[0120] In the embodiment of the present invention, by setting the 16 data pointed to by each logical address to be merged, N 2 / 16 data to achieve effective merging and processing.

[0121] Reference Figure 7 , Figure 7 1 is a flow chart of a CSI-RS data calculation process in an embodiment of the present invention. The CSI-RS data calculation process may include steps S71 to S78, and each step is described below.

[0122] In step S71, a channel estimation matrix is ​​determined.

[0123] In step S72, a noise coefficient matrix is ​​determined.

[0124] Specifically, the corresponding channel estimation matrix (such as H matrix) and noise estimation matrix (such as RN matrix) can be obtained through CSI-RS.

[0125] In step S73, whitening processing is performed.

[0126] Specifically, a whitening process may be performed on the channel.

[0127] In step S74, the RHH matrix is ​​calculated and smoothing is performed.

[0128] Specifically, an autocorrelation operation may be performed to obtain an autocorrelation matrix (such as an RHH matrix).

[0129] In step S75, the control logic is written.

[0130] Specifically, data may be written through write control logic.

[0131] In step S76, the data may be stored in each memory or read from each memory respectively.

[0132] Specifically, a first memory, a second memory, a third memory, ... an Nth memory, etc. may be provided to implement access to cache data.

[0133] It should be pointed out that, compared with using registers, in the embodiment of the present invention, multiple memories are used for reading, and the back-end layout and wiring are significantly reduced.

[0134] In step S77, the control logic is read.

[0135] Specifically, data may be read through the read control logic.

[0136] In step S78, the codebook is calculated.

[0137] Specifically, after the codebook is calculated, the calculated information such as CQI, PMI, CRI, LI, RI, subband value, broadband value, etc. can be reported to the software.

[0138] In the embodiment of the present invention, multiple memories are used to read data, which requires N memory cells compared to the prior art that uses registers. 2 The registers and their related wiring adopt the solution of the embodiment of the present invention, which can effectively improve the extraction efficiency, save the wiring area, reduce the area overhead occupied by the storage device, alleviate the back-end layout and wiring congestion, and reduce the storage cost.

[0139] Reference Figure 8 , Figure 8 8 is a schematic diagram of a conjugate symmetric matrix data access device according to an embodiment of the present invention. The conjugate symmetric matrix data access device may include a storage module 81, and may also include the storage module 81 and an extraction module 82:

[0140] The storage module 81 is used to use a preset number of parallel memories to store N in the N-order conjugate symmetric matrix. 2 data, among which, for the N 2 The data is divided, and each part of the divided data is stored in a different memory and the amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number stored in each memory are consistent;

[0141] The extraction module 82 is used to extract at least a portion of the data in the memory, wherein each time a logical address is used to extract all the data pointed to by the logical address.

[0142] In a specific implementation, the above-mentioned conjugate symmetric matrix data access device may correspond to a chip with an access function; or correspond to a chip module with an access function in a terminal, or correspond to a terminal.

[0143] about Figure 8 For more information on the working principle, working method and beneficial effects of the conjugate symmetric matrix data access device shown in FIG. Figures 1 to 7 The relevant description will not be repeated here.

[0144] In a specific application of an embodiment of the present invention, in the data path part, compared with the use of registers, the use of memories can optimize the wiring area by about 56%; in the control path part, compared with the use of registers and their complex storage logic in the prior art, the use of memories in the embodiments of the present invention and their extraction control logic can also optimize the wiring area by nearly 40%, thereby achieving an overall area optimization of about 43%.

[0145] The embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned conjugate symmetric matrix data access method are executed. The storage medium may include ROM, RAM, a magnetic disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.

[0146] The embodiment of the present invention further provides a terminal, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of the above-mentioned conjugate symmetric matrix data access method when running the computer program. The terminal includes but is not limited to terminal devices such as mobile phones, computers, tablet computers, servers, and cloud platforms.

[0147] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0148] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0149] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer program may be stored in a computer-readable storage medium, or may be transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means.

[0150] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0151] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units. For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least part of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least part of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0152] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0153] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0154] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for accessing conjugate symmetric matrix data, characterized in that: include: A preset number of parallel memories are used to store N of the N-order conjugate symmetric matrix. 2 data, among which, for the N 2 The data is divided, and each part of the divided data is stored in a different memory and the amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number after storage are consistent among the memories; extracting at least a portion of the data in the memory; Among them, the N 2 The data is obtained by dividing the row data into N / k columns and dividing the column data into N / m rows. The divided data is stored in groups, and adjacent groups are stored in the same or different memories. Wherein, k and m are both divisors of N, and 1<k<N, 1<m<N.

2. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: In storing N-order conjugate symmetric matrices, N 2 Before the data, it also includes: Determine the upper triangular data of the N-order conjugate symmetric matrix; According to the complex conjugate symmetric property of the conjugate symmetric matrix, and according to the upper triangle of the N-order conjugate symmetric matrix, the N-order conjugate symmetric matrix is ​​calculated. 2 The remaining data in the data.

3. The method for accessing conjugate symmetric matrix data according to claim 2, characterized in that: Determining the first column and row data or the first row and column data of an N-order conjugate symmetric matrix includes: According to the channel estimation results and noise estimation results of the CSI-RS obtained by measuring the N transmitting antenna ports and M receiving antennas of the CSI-RS signal, the relevant data of each transmitting antenna port and itself and subsequent transmitting antenna ports are determined as the upper triangular data of the N-order conjugate symmetric matrix.

4. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: in, The amount of data contained in each group of data is equal, and the amount of data in each group of data is less than or equal to the amount of data in a single area after division.

5. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: The N 2 The data is divided by using the N / 2th row and column data and the N / 2th column and row data to obtain 4 groups of data and store them in four memories respectively.

6. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: The N 2 The data is divided into groups of P rows and P columns to obtain group data of N / P rows and N / P columns; The group data of odd rows and odd columns are stored in the first memory, the group data of odd rows and even columns are stored in the second memory, the group data of even rows and odd columns are stored in the third memory, and the group data of even rows and even columns are stored in the fourth memory; P is a divisor of N, and 1<P<N.

7. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: in, Each time a logical address is used, all data pointed to by the logical address are extracted.

8. The method for accessing conjugate symmetric matrix data according to claim 7, characterized in that: Extracting at least a portion of the data in the memory includes: Extraction is performed in groups, and the data in the memory is extracted each time using the logical addresses of all the data in a single group.

9. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: Also includes: Merge the extracted data.

10. The method for accessing conjugate symmetric matrix data according to claim 9, characterized in that: The number of the memories is 4, and the merging rule of the merging process is to equally divide the blocks into 4 blocks and then perform matrix extraction and merging; The merging process of the extracted data includes: Merge the 4 data pointed to by each logical address to get N 2 / 4 data.

11. The method for accessing conjugate symmetric matrix data according to claim 9, characterized in that: The number of the memories is 4, and the merging rule of the merging process is to equally divide into 16 blocks and then perform matrix extraction and merging; The merging process of the extracted data is selected from: Merge the 4 data pointed to by each logical address to get N 2 / 4 data; or, For the N 2 The data are extracted and merged to obtain N 2 / 16 data.

12. The method for accessing conjugate symmetric matrix data according to claim 11, characterized in that: For the N 2 The data extraction and merging process includes: For the N 2 The data is divided into 16 parts using N / 4 columns and N / 4 rows as intervals; The data with the same row number and column number in the 16 parts are extracted and merged.

13. The method for accessing conjugate symmetric matrix data according to claim 1, characterized in that: The memory is selected from: random access memory RAM or flash memory.

14. A device for accessing conjugate symmetric matrix data, characterized in that: include: A storage module is used to use a preset number of parallel memories to store N in the N-order conjugate symmetric matrix. 2 data, among which, for the N 2 The data is divided, and each part of the divided data is stored in a different memory and the amount of data stored in each memory is equal, and the logical addresses of the data with the same row number and column number stored in each memory are consistent; The device is further configured to perform: extracting at least a portion of the data in the memory; Among them, the N 2 The data is obtained by dividing the row data into N / k columns and dividing the column data into N / m rows. The divided data is stored in groups, and adjacent groups are stored in the same or different memories. Wherein, k and m are both divisors of N, and 1<k<N, 1<m<N.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for accessing conjugate symmetric matrix data according to any one of claims 1 to 13 are executed.

16. A terminal comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor runs the computer program, the processor performs the steps of the method for accessing conjugate symmetric matrix data according to any one of claims 1 to 13.

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