Operational amplifier and startup circuit of operational amplifier

Abstract

The present application provides an operational amplifier and a startup circuit for the operational amplifier, which have the advantages of simple structure and low power consumption. The operational amplifier includes: a multi-stage series amplifier and a startup circuit, the startup circuit includes a first startup transistor M16 and a second startup transistor M17, the source of the first startup transistor M16 and the source of the second startup transistor M17 are connected to the tail bias node of the first stage amplifier in the multi-stage series amplifier, and the gate of the first startup transistor M16 and the gate of the second startup transistor M17 are used to connect a first bias voltage V b The drain of the first start-up transistor M16 and the drain of the second start-up transistor M17 are connected to the input end of the second stage or the amplifier above the second stage.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an operational amplifier and a startup circuit of the operational amplifier. Background Art

[0002] Operational amplifiers (OPAs), one of the most fundamental building blocks in analog integrated circuits, are widely used in various analog and mixed-signal circuits. Taking RF transceiver systems as an example, op amps are typically used in key modules such as trans-impedance amplifiers (TIAs), low-pass filters (LPFs), variable gain amplifiers (VGAs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). In a cascaded link system, if the upstream or downstream circuitry of these key modules fails to provide a valid startup signal, the op amp may not be able to start up smoothly and operate normally. Therefore, op amps typically require a startup circuit to ensure self-startup. This circuit provides startup current during the op amp's startup process, ensuring that each transistor in the op amp operates normally. While various startup circuit topologies exist in existing circuit designs, the industry is continuously researching startup circuits with lower power consumption and simpler designs. Summary of the Invention

[0003] The present application provides an operational amplifier and a startup circuit for the operational amplifier, which have the advantages of simple structure and low power consumption.

[0004] In a first aspect, an operational amplifier is provided, comprising: a multi-stage series amplifier; and a startup circuit. The startup circuit comprises: a first startup transistor M16 and a second startup transistor M17, wherein the source of the first startup transistor M16 and the source of the second startup transistor M17 are connected to the tail bias node of the first stage amplifier in the multi-stage series amplifier, and the gate of the first startup transistor M16 and the gate of the second startup transistor M17 are connected to a first bias voltage V b The drain of the first start-up transistor M16 and the drain of the second start-up transistor M17 are connected to the input end of the second stage or the amplifier above the second stage.

[0005] An embodiment of the present application provides an operational amplifier including a startup circuit capable of quickly starting the operational amplifier. The startup circuit has a simple structure and does not introduce additional zeros and poles, eliminating the need for bandwidth compensation in the operational amplifier, facilitating high-speed, high-gain designs. Furthermore, the startup circuit draws low operating current after the operational amplifier starts, resulting in low power consumption.

[0006] In combination with the first aspect, in some possible implementations of the first aspect, the first bias voltage V b The setting is such that: when the input transistor pair of the first stage amplifier is not turned on, |V GS |>|V th |; and, after the operational amplifier is started, |V GS |<|V th |, where V GS represents the gate-source voltage of the first startup transistor M16 and the second startup transistor M17, V th represents the threshold voltage of the first start-up transistor M16 and the second start-up transistor M17.

[0007] In the embodiment of the present application, the first bias voltage V b , so that after the operational amplifier startup circuit is started, |V GS |<|V th |, so the operating current of the startup circuit is zero in an ideal state, which will not introduce additional DC offset, improve the performance of the operational amplifier, and reduce power consumption.

[0008] In combination with the first aspect, in some possible implementations of the first aspect, the tail bias node is the drain of the tail bias transistor M5 of the first-stage amplifier.

[0009] In combination with the first aspect, in some possible implementations of the first aspect, the tail bias node is one end of a bias resistor of the first-stage amplifier.

[0010] In combination with the first aspect, in some possible implementations of the first aspect, the operational amplifier includes a three-stage series amplifier, the drain of the first start transistor M16 is connected to the gate of the third input transistor M7 of the second-stage amplifier, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second-stage amplifier.

[0011] In combination with the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes: a stability compensation circuit, including a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2, wherein the first end of the first capacitor C1 is connected to the drain of the third input transistor M7 of the second-stage amplifier, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the drain of the first input transistor M1 of the first-stage amplifier; the first end of the second capacitor C2 is connected to the drain of the fourth input transistor M9 of the second-stage amplifier, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the drain of the second input transistor M2 of the first-stage amplifier.

[0012] In combination with the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a common-mode detection circuit, wherein the common-mode detection circuit includes: a first input terminal for receiving a first differential output voltage Voutp output by the operational amplifier; a second input terminal for receiving a second differential output voltage Voutn output by the operational amplifier; and an output terminal for outputting a common-mode output voltage V CM , the common-mode output voltage V CM is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn.

[0013] In combination with the first aspect, in some possible implementations of the first aspect, the common-mode detection circuit includes: a third resistor R3 and a fourth resistor R4, the first end of the third resistor R3 is connected to the first differential output end of the operational amplifier, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the second differential output end of the operational amplifier, and the second end of the third resistor R3 is the output end of the common-mode detection circuit.

[0014] In combination with the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes: a common-mode loop compensation circuit, including a third capacitor C3 and a fourth capacitor C4, wherein a first end of the third capacitor C3 is connected to the first differential output terminal of the operational amplifier, a second end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and a second end of the fourth capacitor C4 is connected to the second differential output terminal of the operational amplifier.

[0015] In combination with the first aspect, in some possible implementations of the first aspect, the operational amplifier further includes a common-mode negative feedback circuit, the common-mode negative feedback circuit includes an error amplifier, and the first input terminal of the error amplifier is used to receive the common-mode reference voltage V CMREFThe second input terminal of the error amplifier is used to receive the common-mode output voltage V output by the common-mode detection circuit. CM The output end of the error amplifier is connected to the bias circuit of the operational amplifier.

[0016] In a second aspect, a startup circuit of an operational amplifier is provided, wherein the operational amplifier includes a multi-stage series amplifier, and the startup circuit includes: a first startup transistor M16 and a second startup transistor M17, wherein the source of the first startup transistor M16 and the source of the second startup transistor M17 are connected to the tail bias node of the first stage amplifier in the multi-stage series amplifier, and the gate of the first startup transistor M16 and the gate of the second startup transistor M17 are used to connect a first bias voltage V b The drain of the first start-up transistor M16 and the drain of the second start-up transistor M17 are connected to the input end of the second stage or the amplifier above the second stage.

[0017] Embodiments of the present application provide a startup circuit capable of quickly starting an operational amplifier. This startup circuit has a simple structure and does not introduce additional zeros and poles, eliminating the need for bandwidth compensation in the operational amplifier, facilitating high-speed, high-gain designs. Furthermore, the operational current after the operational amplifier is started is low, resulting in low power consumption.

[0018] In conjunction with the second aspect, in some possible implementations of the second aspect, the first bias voltage V b The setting is such that: when the input transistor pair of the first-stage amplifier is not conducting, |V GS |>|V th |; and,

[0019] After the operational amplifier starts up, |V GS |<|V th |, where V GS represents the gate-source voltage of the first startup transistor M16 and the second startup transistor M17, V th represents the threshold voltage of the first start-up transistor M16 and the second start-up transistor M17.

[0020] In combination with the second aspect, in some possible implementations of the second aspect, the tail bias node is the drain of the tail bias transistor M5 of the first-stage amplifier.

[0021] In combination with the second aspect, in some possible implementations of the second aspect, the tail bias node is one end of a bias resistor of the first-stage amplifier.

[0022] In combination with the second aspect, in some possible implementations of the second aspect, the operational amplifier includes a three-stage series amplifier, the drain of the first start transistor M16 is connected to the gate of the third input transistor M7 of the second-stage amplifier, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second-stage amplifier.

[0023] In conjunction with the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes:

[0024] A stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The first end of the first capacitor C1 is connected to the drain of the third input transistor M7 of the second-stage amplifier, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the drain of the first input transistor M1 of the first-stage amplifier; the first end of the second capacitor C2 is connected to the drain of the fourth input transistor M9 of the second-stage amplifier, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the drain of the second input transistor M2 of the first-stage amplifier.

[0025] In combination with the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes a common-mode detection circuit, wherein the common-mode detection circuit includes: a first input terminal for receiving a first differential output voltage Voutp output by the operational amplifier; a second input terminal for receiving a second differential output voltage Voutn output by the operational amplifier; and an output terminal for outputting a common-mode output voltage V CM , the common-mode output voltage V CM is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn.

[0026] In combination with the second aspect, in some possible implementations of the second aspect, the common-mode detection circuit includes: a third resistor R3 and a fourth resistor R4, the first end of the third resistor R3 is connected to the first differential output end of the operational amplifier, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the second differential output end of the operational amplifier, and the second end of the third resistor R3 is the output end of the common-mode detection circuit.

[0027] In combination with the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes: a common-mode loop compensation circuit, including a third capacitor C3 and a fourth capacitor C4, wherein the first end of the third capacitor C3 is connected to the first differential output terminal of the operational amplifier, the second end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the second differential output terminal of the operational amplifier.

[0028] In combination with the second aspect, in some possible implementations of the second aspect, the operational amplifier further includes: a common-mode negative feedback circuit, the common-mode negative feedback circuit including an error amplifier, the first input terminal of the error amplifier being used to receive a common-mode reference voltage V CMREF The second input terminal of the error amplifier is used to receive the common-mode output voltage V output by the common-mode detection circuit. CM The output end of the error amplifier is connected to the bias circuit of the operational amplifier.

[0029] In a third aspect, a chip is provided, comprising the operational amplifier described in the first aspect or any possible implementation manner of the first aspect.

[0030] In a fourth aspect, an electronic device is provided, comprising the operational amplifier described in the first aspect or any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of an application environment of an embodiment of the present application.

[0032] Figure 2 2 is a schematic structural diagram of an operational amplifier according to an embodiment of the present application.

[0033] Figure 3 2 is a schematic structural diagram of an operational amplifier according to another embodiment of the present application.

[0034] Figure 4 2 is a schematic structural diagram of an operational amplifier according to another embodiment of the present application.

[0035] Figure 5 FIG. 1 is a schematic diagram of the circuit structure of an operational amplifier according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solution in this application will be described below with reference to the accompanying drawings.

[0037] An embodiment of the present application provides an operational amplifier and a startup circuit for the operational amplifier. The startup circuit has the advantages of a simple circuit structure and low power consumption, and can achieve rapid startup of the operational amplifier.

[0038] Figure 1 It is a schematic diagram of an application environment of an embodiment of the present application. Figure 1 The figure shows a schematic diagram of a link cascade in a radio frequency system, which is a receiver system, including a low noise amplifier (LNA), a mixer, a trans-impedance amplifier (TIA), a low-pass filter (LPF) and an analog to digital converter (ADC). The operational amplifier in the embodiment of the present application can be set to Figure 1 In the TIA, LPF, VGA, ADC and other modules. It should be noted that, Figure 1 The operational amplifiers of the embodiments of the present application are merely used as examples to illustrate the application environment. The operational amplifiers can be widely used in various analog integrated circuits or digital-to-analog integrated circuits, such as filter circuits, amplifier circuits, operational circuits, signal generation circuits, signal conversion circuits, or power supplies.

[0039] After startup, an operational amplifier typically exists in two stable states: a normal amplification state and an abnormal amplification state. The abnormal amplification state can refer to an input voltage outside the normal input voltage range of the operational amplifier. These abnormal amplification states include low input bias and high input bias. Low input bias refers to an input voltage below the lower limit of the operational amplifier's normal input voltage range, while high input bias refers to an input voltage above the upper limit of the normal input voltage range. When an operational amplifier is in an abnormal operating state, the performance of the circuit module or circuit system in which it resides will be affected. For example, in an abnormal amplification state, the input transistor pair of the operational amplifier may be in the subthreshold region, with the operating current far below the expected value, thus affecting various characteristic parameters of the circuit and causing it to deviate from the design specifications.

[0040] If the upstream or downstream stages of the module housing the operational amplifier (OPA) fail to provide a valid startup signal, the OPA will not operate in its normal amplification state, but instead in an abnormal amplification state. To ensure that the OPA operates in its normal amplification state after startup, the OPA typically requires a startup circuit to ensure self-startup. This circuit provides startup current during the OPA startup process, ensuring that each transistor in the OPA operates in its normal amplification state.

[0041] Various startup circuits with different principles and topologies exist in the prior art, but these circuits have drawbacks. For example, the startup circuits go through numerous startup loop stages during startup, requiring additional stability compensation design. Alternatively, the startup circuits continue to operate after startup, consuming additional power. Furthermore, the startup circuit design is complex, occupying a significant amount of chip area.

[0042] Therefore, the embodiment of the present application provides a startup circuit that can quickly start the operational amplifier. The startup circuit has a simple structure and does not affect the performance of the main signal path. In addition, the operating current after starting the operational amplifier is small, which has the advantage of low power consumption. Figure 2-Figure 5 , a detailed introduction to the operational amplifier and the startup circuit of the operational amplifier provided in the embodiments of the present application.

[0043] Figure 2 2 is a schematic diagram of the structure of an operational amplifier 200 according to an embodiment of the present application. The operational amplifier 200 may include a multi-stage series amplifier. For example, the operational amplifier 200 may be a two-stage amplifier, a three-stage amplifier, or an amplifier with more than three stages. Figure 2 The operational amplifier 200 is taken as an example to be a two-stage amplifier.

[0044] like Figure 2 As shown, operational amplifier 200 includes a first-stage amplifier, a second-stage amplifier, and a startup circuit. The input terminal of operational amplifier 200 can be a differential input terminal. The output terminal of operational amplifier 200 can be a differential output terminal or a single output terminal, which is not limited in this embodiment of the present application. If operational amplifier 200 has a differential output terminal, the differential input terminal can be referred to as a first differential input terminal Vinp and a second differential input terminal Vinn, respectively. The differential output terminals of the above operational amplifier can be referred to as a first differential output terminal Voutp and a second differential output terminal Voutn, respectively.

[0045] The first-stage amplifier includes a bias circuit, a tail bias circuit, and an input transistor pair (M1, M2). For ease of explanation, transistor M1 and transistor M2 may be referred to as the first input transistor M1 and the second input transistor M2, or collectively referred to as the input transistor pair of the first-stage amplifier. The gates (g) of the input transistor pair (M1, M2) are the differential input terminals (Vinp, Vinn) of the operational amplifier 200, respectively. The source (s) of the input transistor pair (M1, M2) is connected to the tail bias circuit, and the drain (d) of the input transistor pair (M1, M2) is connected to the bias circuit. The drain (d) of the input transistor pair (M1, M2) is the output terminal of the first-stage amplifier, which is connected to the input terminal of the second-stage amplifier. The tail bias circuit and the bias circuit are used to provide bias current for the input transistor pair (M1, M2).

[0046] Continue to see Figure 2 The startup circuit includes a first startup transistor M16 and a second startup transistor M17, wherein the first startup transistor M16 and the second startup transistor M17 form a differential transistor pair. For ease of explanation, the transistors M16 and M17 can be collectively referred to as a startup transistor pair. The source (s) of the startup transistor pair (M16, M17) is connected to the tail bias node P of the first stage amplifier, and the gate (g) of the startup transistor pair (M16, M17) is used to connect to the first bias voltage V b , the drain (d) of the start transistor pair (M16, M17) can be connected to the input terminal of the second or higher-stage amplifier. Figure 2 The drains (d) of the shown enabling transistor pair (M16, M17) are connected to the input of the second stage amplifier.

[0047] The tail bias node P of the first stage amplifier may refer to a node where the tail bias circuit of the first stage amplifier is connected to the source (s) of the input transistor pair (M1, M2). For example, the tail bias circuit may include a tail bias transistor, and the tail bias node P may be the drain of the tail bias transistor of the first stage amplifier. Alternatively, the tail bias circuit may include a bias resistor, and the tail bias node P is one end of the bias resistor of the first stage amplifier. Alternatively, the tail bias node P may be the source (s) of the input transistor pair (M1, M2). In an embodiment of the present application, the voltage at the tail bias node P may be represented by V p express.

[0048] The input terminals of the second-stage or higher-stage amplifiers may be differential input terminals. For example, the differential input terminals of the second-stage amplifier may include a first differential input terminal Vinp2 and a second differential input terminal Vinn2. In some examples, the drains (d) of the start-up transistors M16 and M17 may be connected to the two differential input terminals of the second-stage or higher-stage amplifiers, respectively. Figure 2 As shown, the drain (d) of the first start-up transistor M16 is connected to the first differential input terminal Vinp2 of the second stage amplifier, and the drain (d) of the second start-up transistor M17 is connected to the second differential input terminal Vinn2 of the second stage amplifier.

[0049] In some examples, the source (s) and drain (d) of the startup transistor pair (M16, M17) are connected in the same manner as the source (s) and drain (d) of the input transistor pair (M1, M2) of the first-stage amplifier. That is, the source (s) of the startup transistor pair (M16, M17) and the source (s) of the input transistor pair (M1, M2) are connected to the same node, and the drain (d) of the startup transistor pair (M16, M17) and the drain (d) of the input transistor pair (M1, M2) are connected to the same node.

[0050] After the operational amplifier 200 is powered on, the bias voltages in the circuit are first established. For example, the first bias voltage V b , the tail bias circuit, and the bias voltage in the bias circuit. After the bias voltage is established, the startup transistors (M16, M17) are first turned on, generating an operating current and driving the second-stage amplifier of the operational amplifier to operate. After the second-stage amplifier is started, the external loop feedback drives the input transistor pair (M1, M2) to operate, causing operational amplifier 200 to enter normal operation, thereby completing the startup of operational amplifier 200.

[0051] In some examples, in order to enable the start-up transistors (M16, M17) to be turned on smoothly after the operational amplifier 200 is powered on, the first bias voltage V b The setting is such that: before the operational amplifier 200 starts, |V GS |>|V th |, where V GS represents the gate-source voltage of the startup transistor pair (M16, M17), V th represents the threshold voltage of the start-up transistor pair (M16, M17). GS |>|V th |, the start-up transistor pair (M16, M17) is in the on state. Therefore, after the operational amplifier 200 is powered on, the start-up transistor pair (M16, M17) is first turned on and generates an operating current to start the operational amplifier. The gate-source voltage V GS It can be expressed as V GS =V b -V p , where V p Represents the voltage at the tail bias node P. After the startup circuit is started, the first stage differential amplifier works normally, and the tail bias circuit provides bias current for the input transistor pair (M1, M2). At this time, the voltage V p increases, and the bias voltage V b The gate-source voltage V of the start-up transistor pair (M16, M17) remains unchanged. GS =V b -V p decreases, so that the operating current of the startup transistor pair (M16, M17) begins to decrease, and the power consumption of the startup circuit is also reduced.

[0052] In some examples, in order to reduce the operating current of the transistors (M16, M17) after the operational amplifier 200 is started, the first bias voltage V b The setting is such that: after the operational amplifier 200 is started, |V GS|<|V th If the first bias voltage V is set properly b , it can make the operational amplifier 200 start up (ie in the normal amplification state), |V GS |<|V th In this case, the startup transistor pair (M16, M17) is in the off state. Ideally, the operating current of the startup transistor pair (M16, M17) is zero, thereby reducing the power consumption of the startup circuit.

[0053] The startup circuit structure of the operational amplifier in the embodiment of the present application is simple and can be realized with only two transistors. After the operational amplifier 200 is started, the gate-source voltage V GS Therefore, the operating current I D Small, which is conducive to the realization of low power consumption circuit. For the convenience of explanation, formula (1) shows the working current formula of the transistor when it works in the saturation region,

[0054]

[0055] Among them, I D Indicates the operating current, μ represents the carrier mobility, C ox Indicates the capacitance per unit area of the gate oxide layer of the transistor, W represents the channel width of the transistor, L represents the channel length of the transistor, V GS Represents the gate-source voltage of the transistor, V th Represents the threshold voltage of the transistor.

[0056] From formula (1), we can see that as V GS The reduction of the working current I D Also decreases accordingly. If V GS Less than V th , the working state of the MOS tube enters the cut-off region. Under ideal conditions, the working current I D is zero.

[0057] In some examples, the first bias voltage V b It can be set to the common mode reference voltage V CMREF are equal in size.

[0058] The startup circuit in the embodiment of the present application has a simple loop and does not introduce additional zeros and poles, so there is no need for bandwidth compensation of an operational amplifier, which is conducive to high-speed and high-gain design.

[0059] The startup circuit of the present embodiment adopts a differential structure, which has good differential characteristics. In addition, after the operational amplifier is started, the operating current of the startup circuit is reduced, or even zero, thereby eliminating the introduction of additional direct current offset (DC offset), which is beneficial for advanced process low-voltage design.

[0060] Optionally, the startup transistor pair (M16, M17) can be an N-type metal oxide semiconductor (NMOS) transistor or a P-type metal oxide semiconductor (PMOS) transistor. For example, the startup transistor pair (M16, M17) can be the same type as the input transistor pair (M1, M2) of the first-stage amplifier. If the input transistor pair (M1, M2) is an NMOS transistor, the startup transistors (M16, M17) are NMOS transistors. If the input transistor pair (M1, M2) is a PMOS transistor, the startup transistor pair (M16, M17) is a PMOS transistor.

[0061] Optionally, the operational amplifier in the embodiments of the present application may use a complementary metal oxide semiconductor (CMOS) process or other integrated circuit processes, such as a bipolar junction transistor (BJT) process or a silicon-on-insulator (SOI) process.

[0062] Figure 3 FIG. 3 is a structural diagram of an operational amplifier 300 according to another embodiment of the present application. Figure 3 The operational amplifier 300 with Figure 2 The operational amplifier 200 in FIG. 1 has a similar structure, except that the drains of the pair of enable transistors (M16, M17) are connected to the two differential input terminals of the third-stage amplifier. Specifically, the drain of the first enable transistor M16 is connected to the first differential input terminal of the third-stage amplifier, and the drain (d) of the second enable transistor M17 is connected to the second differential input terminal of the third-stage amplifier.

[0063] Optionally, the startup transistor pair (M16, M17) in the embodiment of the present application can also be replaced by a single transistor. For example, Figure 4 FIG. 4 is a structural diagram of an operational amplifier 400 according to another embodiment of the present application. Figure 4As shown, the startup circuit may only include a first startup transistor M16, the source of the first startup transistor M16 is used to connect to the tail bias node P, and the gate of the first startup transistor M16 is used to connect to the first bias voltage V b The drain of the first start-up transistor M16 is used to connect to the input end of the second-stage or higher-stage amplifier. Figure 4 The drain of the first enabling transistor M16 is used to connect to any one of the two differential input terminals of the second-stage amplifier. In some examples, the drain of the first enabling transistor M16 can also be used to connect to any one of the two differential input terminals of the second-stage amplifier or higher.

[0064] Figure 5 FIG. 5 is a circuit structure diagram of an operational amplifier 500 according to another embodiment of the present application. Figure 5 The operational amplifier 500 in the figure is a two-stage amplifier. It should be understood that, with limited modification, the structure of the operational amplifier 500 is also applicable to a three-stage amplifier or an amplifier with more than three stages. Figure 5 As shown, the first stage amplifier circuit of the operational amplifier includes transistors M1, M2, M3, M4, and M5. Figure 2-Figure 4 The bias circuit of the first stage amplifier may include Figure 5 Transistors M3 and M4 in. Figure 2-Figure 4 The tail bias circuit of the first stage amplifier in the Figure 5 For ease of explanation, transistors M3 and M4 may be referred to as bias transistors, and transistor M5 may be referred to as a tail bias transistor. The second-stage amplifier circuit of the operational amplifier includes transistors M6, M7, M8, and M9.

[0065] In the first stage amplifier circuit, the sources of bias transistors M3 and M4 are connected to the power supply V DD The drains of bias transistors M3 and M4 are connected to the drains of the input transistor pair (M1, M2). Transistor M7 and transistor M9 form the input transistor pair of the second-stage amplifier. For ease of explanation, transistor M7 and transistor M9 can be referred to as the third input transistor M7 and fourth input transistor M9 of the second-stage amplifier. The gate of the third input transistor M7 serves as the first differential input terminal of the second-stage amplifier, and the gate of the fourth input transistor M9 serves as the second differential input terminal of the second-stage amplifier. The drain of the third input transistor M7 serves as the first differential output terminal of the second-stage amplifier, and the drain of the fourth input transistor M9 serves as the second differential output terminal of the second-stage amplifier. The drains of the third input transistor M7 and the fourth input transistor M9 also serve as the differential output terminals of the operational amplifier.

[0066] like Figure 5As shown, the startup circuit includes a first startup transistor M16 and a second startup transistor M17. The gates of the first startup transistor M16 and the second startup transistor M17 are used to connect to the first bias voltage V b The source of the first start-up transistor M16 and the second start-up transistor M17 are connected to each other and are also connected to the drain of the tail bias transistor M5. The drain of the first start-up transistor M16 is connected to the gate of the third input transistor M7 of the second stage amplifier, and the drain of the second start-up transistor M17 is connected to the gate of the fourth input transistor M9 of the second stage amplifier. The drain of the third input transistor M7 is the differential output terminal V outp The drain of the fourth input transistor M9 is the differential output terminal V outn .

[0067] Optionally, the operational amplifier further includes a stability compensation circuit, which can be used for frequency compensation of the fully differential amplifier. Figure 5 As shown, as an example, the stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The drain of the third input transistor M7 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the drain of the first input transistor M1 of the first-stage amplifier. The drain of the fourth input transistor M9 is connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the drain of the second input transistor M2 of the first-stage amplifier. Transistor M15 is a current mirror bias circuit for the operational amplifier, used to receive bias current and generate a bias voltage for the operational amplifier. Transistors M12 and M13 are diode-connected, forming the load of the error amplifier in the common-mode negative feedback circuit.

[0068] Optionally, the operational amplifier further includes a common-mode detection circuit, which is used to generate a common-mode output voltage V CM The common mode detection circuit includes: a first input terminal for receiving the first differential output voltage Voutp output by the operational amplifier; a second input terminal for receiving the second differential output voltage Voutn output by the operational amplifier; an output terminal for outputting the common mode output voltage V CM , the common-mode output voltage V CM is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn, that is, V CM =(Voutp+Voutn) / 2.

[0069] like Figure 5As shown, as an example, the common-mode detection circuit includes a third resistor R3 and a fourth resistor R4, wherein the first end of the third resistor R3 is connected to the first differential output terminal Voutp of the operational amplifier, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the second differential output terminal Voutn of the operational amplifier, and the second end of the third resistor R3 is the output end of the common-mode detection circuit.

[0070] Optionally, the operational amplifier further includes a common-mode loop compensation circuit, which is used for frequency compensation of the common-mode loop. Figure 5 As shown, as an example, the common-mode loop compensation circuit includes a third capacitor C3 and a fourth capacitor C4. The first end of the third capacitor C3 is connected to the first differential output terminal Voutp of the operational amplifier, the second end of the third capacitor C3 is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the second differential output terminal Voutn of the operational amplifier. The second end of the third capacitor C3 is connected to the output terminal of the common-mode detection circuit, that is, the second end of the third capacitor C3 is connected to the second end of the third resistor R3.

[0071] Optionally, the operational amplifier further includes a common-mode negative feedback circuit, which is used to compare the common-mode output voltage V CM and the common-mode reference voltage V CMREF , and adjust the bias circuit of the operational amplifier according to the comparison result so that the common-mode output voltage V CM and the common-mode reference voltage V CMREF Equal. Figure 5 As shown, the common-mode negative feedback circuit includes an error amplifier, wherein the first input terminal of the error amplifier is used to be connected to the common-mode reference voltage V of the operational amplifier. CMREF The second input of the error amplifier is connected to the common-mode output voltage V CM , that is, connected to the second end of the third resistor R3. The output end of the error amplifier is connected to the bias circuit of the operational amplifier to facilitate adjustment of the bias circuit of the operational amplifier.

[0072] like Figure 5As shown, as an example, the error amplifier includes transistors M10, M11, M12, M13, and M14. Among them, transistor M10 and transistor M11 are amplifier tubes, and transistors M12, M13, and M14 are bias transistors. The gates of transistors M10 and transistor M11 are differential input terminals of the error amplifier, and the drain of transistor M10 is the output terminal of the error amplifier. The gate of transistor M10 in the common-mode negative feedback circuit is connected to the second end of the third resistor R3 in the common-mode detection circuit. The gate of transistor M11 in the common-mode feedback circuit is used to be connected to the common-mode reference voltage V CMREF connected.

[0073] It should be understood that Figure 5 The specific circuit structure of the operational amplifier in the embodiment of the present application is only an example and not a limitation. For example, Figure 5 The stability compensation circuit, common-mode detection circuit, common-mode loop compensation circuit or common-mode negative feedback circuit may also be implemented in other ways, which is not limited in the embodiments of the present application.

[0074] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0075] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An operational amplifier, characterized in that: include: Multi-stage series amplifier; The startup circuit includes: a first startup transistor M16 and a second startup transistor M17, wherein the source of the first startup transistor M16 and the source of the second startup transistor M17 are connected to the tail bias node of the first stage amplifier in the multi-stage series amplifier, and the gate of the first startup transistor M16 and the gate of the second startup transistor M17 are used to connect to the first bias voltage V b The drain of the first startup transistor M16 and the drain of the second startup transistor M17 are connected to the input end of the second-stage or higher-stage amplifier; the startup circuit provides a startup current during the startup process of the operational amplifier.

2. The operational amplifier according to claim 1, wherein The first bias voltage V b The settings make: When the input transistor pair of the first-stage amplifier is not conducting, |V GS |>|V th |; and, After the operational amplifier starts up, |V GS |<|V th |, where V GS represents the gate-source voltage of the first startup transistor M16 and the second startup transistor M17, V th represents the threshold voltage of the first start-up transistor M16 and the second start-up transistor M17.

3. The operational amplifier according to claim 1 or 2, wherein: The tail bias node is the drain of the tail bias transistor M5 of the first stage amplifier.

4. The operational amplifier according to claim 1 or 2, wherein: The tail bias node is one end of a bias resistor of the first-stage amplifier.

5. The operational amplifier according to claim 1 or 2, wherein: The operational amplifier includes three stages of series amplifiers, the drain of the first start transistor M16 is connected to the gate of the third input transistor M7 of the second stage amplifier, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second stage amplifier.

6. The operational amplifier according to claim 1 or 2, wherein: The operational amplifier further includes: a stability compensation circuit, comprising a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2, wherein a first end of the first capacitor C1 is connected to a drain of the third input transistor M7 of the second-stage amplifier, a second end of the first capacitor C1 is connected to a first end of the first resistor R1, and a second end of the first resistor R1 is connected to a drain of the first input transistor M1 of the first-stage amplifier; The first end of the second capacitor C2 is connected to the drain of the fourth input transistor M9 of the second stage amplifier, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the drain of the second input transistor M2 of the first stage amplifier.

7. The operational amplifier according to claim 6, wherein: The operational amplifier further includes a common mode detection circuit, and the common mode detection circuit includes: A first input terminal, configured to receive a first differential output voltage Voutp output by the operational amplifier; A second input terminal, configured to receive a second differential output voltage Voutn output by the operational amplifier; Output terminal, used to output common mode output voltage V CM , the common-mode output voltage V CM is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn.

8. The operational amplifier according to claim 7, wherein: The common-mode detection circuit includes: a third resistor R3 and a fourth resistor R4, wherein the first end of the third resistor R3 is connected to the first differential output end of the operational amplifier, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the second differential output end of the operational amplifier, and the second end of the third resistor R3 is the output end of the common-mode detection circuit.

9. The operational amplifier according to claim 7 or 8, wherein: The operational amplifier further includes: The common-mode loop compensation circuit includes a third capacitor C3 and a fourth capacitor C4, wherein a first end of the third capacitor C3 is connected to the first differential output terminal of the operational amplifier, a second end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and a second end of the fourth capacitor C4 is connected to the second differential output terminal of the operational amplifier.

10. The operational amplifier according to claim 7 or 8, wherein: The operational amplifier further includes a common-mode negative feedback circuit, which includes an error amplifier. The first input terminal of the error amplifier is used to receive the common-mode reference voltage V CMREF The second input terminal of the error amplifier is used to receive the common-mode output voltage V output by the common-mode detection circuit. CM The output end of the error amplifier is connected to the bias circuit of the operational amplifier.

11. A chip, characterized in that: The chip includes the operational amplifier according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device comprises the operational amplifier according to any one of claims 1 to 10.

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