MEMS Actuation Device Using Sparse Pulses

Abstract

A MEMS actuation device utilizing sparse pulses is disclosed. A method of operating a MEMS device includes: generating a MEMS drive signal; and generating and modifying the MEMS drive signal based on a control signal to produce a modified drive signal. The method further includes generating the control signal by determining when a feedback signal from the MEMS device is at its peak, comparing the peak to an expected value when the feedback signal is at its peak, and generating the control signal based on whether the peak is at least equal to the expected value. Modifying the MEMS drive signal based on the control signal to generate a modified drive signal includes skipping the generation of the next pulse of the modified drive signal when the control signal indicates that the peak is at least equal to the expected value.

Description

Technical Field

[0001] The present disclosure relates to the field of actuation of microelectromechanical system (MEMS) devices, which modify individual drive pulses on a pulse-by-pulse basis to achieve a desired oscillation amplitude with a faster start-up time. Background Art

[0002] Microfabrication techniques enable the fabrication of microelectromechanical structures and systems (MEMS) within layers of semiconductor materials, which are deposited or grown on top of sacrificial layers, and the sacrificial layers are removed by chemical etching. Oscillating micromirrors fabricated using this technique are widely used in laser beam scanning (LBS) modules, which can be used in different small portable electronic devices to perform, for example, 3D sensing, LIDAR-based sensing, or projection. For example, a scanning projector or "pico projector" is a small portable electronic device that utilizes such an LBS module. A pico projector is typically paired with or incorporated into a user device such as smart glasses, a smartphone, a tablet, a laptop, or a digital camera, and is used to project virtual and augmented reality, documents, images, or videos stored on these user devices onto a projection surface, such as a waveguide, a wall, a light field, a holographic surface, or an internal display surface of virtual or augmented reality glasses.

[0003] More specifically, a typical LBS module includes a laser source and one or more MEMS micromirrors to scan a laser beam generated by the laser source on a projection surface in a projection mode. As an example, in the case of using an LBS in a pico projector, an image stream is displayed by modulating the laser beam according to the position of the laser beam on the projection surface while scanning the laser beam in the projection mode. Typically, although optical modules of other designs can be used, at least one lens focuses the beam before or after the beam is reflected by one or more MEMS micromirrors and before the laser beam irradiates the projection surface.

[0004] The projection subsystem controls the driving of the laser source and the driving of the movement of one or more MEMS micromirrors, and the synchronization of the movement of one or more MEMS micromirrors with the modulation of the laser source. Typically, driving the movement of one of the MEMS micromirrors causes it to oscillate at or near its natural resonance frequency, and driving the movement of another MEMS micromirror causes it to move along a predetermined trajectory.

[0005] Resonantly driven MEMS micromirrors are typically driven with a square wave, as Figure 1 shown, where the wave oscillates between voltage 0 and Vin_max over time. Such MEMS micromirrors are typically equipped with a mirror position sensor, such as a tilt sensor, so as to be able to sense the movement of the MEMS micromirror itself to provide feedback. A typical mirror position sensor provides a sinusoidal output, as Figure 2As shown, the sine wave indicates the mirror position. As shown in the figure, when operating normally, such a MEMS mirror oscillates between a maximum angle θmax and a minimum angle θmin to define an amplitude, which can be referred to as the opening angle of the MEMS mirror.

[0006] To reduce power consumption and improve the suppression of vibration noise, the MEMS mirror can be formed as a mirror with a high quality factor (Q factor). However, a high Q factor MEMS mirror takes a long time to reach the desired amplitude when starting up, and the resonant frequency bandwidth is narrow, as Figure 3 shown. To operate correctly when this narrow resonant frequency bandwidth moves over time, a drive signal (e.g., a square wave) is generated with high resolution. Although this does allow correct operation, such a drive signal generation circuit is complex and consumes an undesired amount of area, and does not solve the problem that the startup time is longer than desired. Figure 4 is a graph of the amplitude of a high Q factor MEMS mirror (Q = 10,000) driven using known techniques when starting up, where F 0 is the natural resonant frequency of the MEMS mirror, and F D is the drive frequency of the MEMS mirror. It can be observed that to bring the amplitude to a steady state, the elapsed time is close to 0.5 seconds, which is much longer than what is desired in some applications, such as virtual reality, augmented reality, and mixed reality. In fact, in some cases, the time for the amplitude to reach a steady state can even exceed 0.5 seconds.

[0007] Therefore, further development of the drive for high Q factor MEMS mirrors is needed. SUMMARY OF THE INVENTION

[0008] Described herein is a control circuit for a microelectromechanical system (MEMS) device, the control circuit including: an input logic circuit configured to receive at least one MEMS drive signal and a control signal and cause at least one modified drive signal to be generated based thereon, the at least one modified drive signal being used to drive the MEMS device; and logic circuitry. The logic circuitry is configured to: receive a feedback signal from the MEMS device and indicate when the feedback signal is at its peak, the feedback signal indicating the movement of the MEMS device; and generate a control signal based on the indication of when the feedback signal is at its peak, based on whether the peak is at least equal to a desired peak, the desired peak indicating that the movement of the MEMS device has reached a desired amplitude. The input logic circuit is configured to modify at least one MEMS drive signal to generate at least one modified drive signal when the feedback signal is at least equal to the desired peak, the modification of the at least one MEMS drive signal causing the at least one modified drive signal to have a variable frequency and / or duty cycle that depends on the control signal.

[0009] The logic circuit device may include an analog-to-digital converter that digitizes a feedback signal when the logic circuit device indicates that the feedback signal is at its peak; and a comparator that compares the digitized feedback signal with a desired peak to generate a control signal.

[0010] When the digitized feedback signal is less than the desired peak, the comparator may assert its output; otherwise, it may de-assert its output. The input logic circuit may include at least one AND gate that receives the control signal and at least one MEMS drive signal as inputs, and the AND gate generates at least one modified drive signal as a result of performing a logical AND operation on the control signal and the at least one MEMS drive signal.

[0011] A buffer may be coupled between the output of the at least one AND gate and the MEMS device.

[0012] When the digitized feedback signal is less than the desired peak, the comparator may assert its output; otherwise, it may de-assert its output. The at least one MEMS drive signal may include a first MEMS drive signal and a second MEMS drive signal with opposite phases to each other. The at least one modified drive signal may include a first modified drive signal and a second modified drive signal for driving the MEMS device. The input logic circuit may include: a first AND gate that receives the control signal and the first MEMS drive signal as inputs, and as a result of performing a logical AND operation on the control signal and the first MEMS drive signal, the first AND gate generates the first modified drive signal; and a second AND gate that receives the control signal and the second MEMS drive signal as inputs, and as a result of performing a logical AND operation on the control signal and the second MEMS drive signal, the second AND gate generates the second modified drive signal.

[0013] A first buffer may be coupled between the output of the first AND gate and the MEMS device, and a second buffer may be coupled between the output of the second AND gate and the MEMS device.

[0014] The drive clock generator may be configured to generate a drive frequency signal, and the drive clock generator may be configured to generate at least one MEMS drive signal based on the drive frequency signal.

[0015] The phase delay circuit can be configured to receive a feedback signal and apply a phase delay to the feedback signal. The phase estimation circuit can be configured to receive the feedback signal after the phase delay circuit has applied a phase delay to the feedback signal, receive at least one MEMS drive signal, and generate a phase estimation signal indicating whether the feedback signal leads or lags the at least one MEMS drive signal. The group delay estimation circuit can be configured to receive the phase estimation signal, determine whether the MEMS device is operating at resonance considering the system phase delay, and generate an output signal based on that determination. The resonant proportional-integral-derivative loop can be configured to operate based on the output signal from the group delay estimation circuit to generate a drive frequency input. The drive clock generator can be configured to generate a drive frequency signal based on the drive frequency input.

[0016] When the feedback signal is at least equal to the desired peak, the input logic circuit can modify at least one MEMS drive signal by preventing the generation of at least one modified drive signal until the feedback signal is less than the desired peak.

[0017] When the feedback signal is at least equal to the desired peak, the input logic circuit can modify at least one MEMS drive signal by shortening the pulse width of at least one modified drive signal until the feedback signal is less than the desired peak.

[0018] The MEMS device can include a MEMS micromirror driven by at least one modified drive signal, and a position sensor associated with the MEMS micromirror and generating a feedback signal.

[0019] When the feedback signal is at least equal to the desired peak, the input logic circuit can modify at least one modified drive signal by inverting the modified drive signal.

[0020] The logic circuitry can include: a peak estimation circuit configured to receive the feedback signal from the MEMS device and indicate when the feedback signal is at its peak, the feedback signal indicating the movement of the MEMS device; and a logic core configured to receive an indication from the peak estimation circuit of when the feedback signal is at its peak and generate a control signal based on whether the peak is at least equal to the desired peak, the desired peak indicating that the movement of the MEMS device has reached a desired amplitude.

[0021] Also disclosed herein is a method of operating a MEMS device. The method includes: generating at least one MEMS drive signal; generating and modifying at least one MEMS drive signal based on a control signal to generate at least one modified drive signal; and generating the control signal by: determining when a feedback signal from the MEMS device is at its peak, comparing the peak with an expected value when the feedback signal is at its peak, and generating the control signal based on whether the peak is at least equal to the expected value. Modifying at least one MEMS drive signal based on the control signal to generate at least one modified drive signal can be performed by skipping the generation of the next pulse of at least one modified drive signal when the control signal indicates that the peak is at least equal to the expected value.

[0022] When the peak is at least equal to the expected value, the control signal can be asserted, and modifying at least one MEMS drive signal can be accomplished by performing a logical AND operation between the control signal and at least one MEMS drive signal.

[0023] When the feedback signal is at least equal to the expected value, at least one modified drive signal is generated by inverting the modified drive signal at least some of the time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a graph of a prior art drive signal for a MEMS mirror.

[0025] Figure 2 is a graph of the opening angle of a MEMS mirror when operated with a prior art drive signal.

[0026] Figure 3 is a graph showing the narrow bandwidth of the resonant frequency of a high Q-factor prior art MEMS mirror.

[0027] Figure 4 is a graph of the opening angle of a prior art high Q-factor MEMS mirror at startup when driven with prior art.

[0028] Figure 5 is a block diagram of a drive circuit including a drive signal modification core disclosed herein.

[0029] Figure 5A is Figure 5 a block diagram of the logic core of

[0030] Figure 6 is a graph of different signals when the drive circuit is operating.

[0031] Figure 7 is Figure 5 a block diagram of the drive logic circuit of

[0032] Figure 8It is a graph of different signals of the drive circuit during operation when the drive logic circuit generates a half-width modified drive signal.

[0033] Figures 9 to 10 It is a comparison of the opening angle and start-up time of the same MEMS micromirror without using and using Figure 5 the drive signal modification core.

[0034] Figures 11 to 12 It is a graph showing the error in the opening angle of the MEMS micromirror during driving without the control of the amplitude-based drive signal modification core described herein compared to when driving with the amplitude-based drive signal modification core.

[0035] Figure 13 It is a block diagram of another embodiment of a drive circuit including a drive signal modification core disclosed herein.

[0036] Figure 14 It is a block diagram of another embodiment of a drive circuit disclosed herein, the drive circuit including a drive signal modification core with a locked resonance embedded within the drive signal modification core. Detailed Description

[0037] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. Without departing from the spirit and scope of the present disclosure, the general principles described herein can be applied to embodiments and applications other than those described in detail above. The present disclosure is not intended to be limited to the embodiments shown, but rather to the broadest scope consistent with the principles and features disclosed or suggested herein.

[0038] Now refer to Figure 5 Describe the drive circuit 10 for the MEMS micromirror 11. The drive circuit 10 includes a drive clock generator 13 that receives a drive frequency control signal FREQ from a drive frequency control signal generator 27 and thereby generates a first drive signal DRV1 and a second drive signal DRV2, the second drive signal DRV2 being opposite in phase to the first drive signal DRV1.

[0039] The drive signal modification core 30 receives the drive signals DRV1 and DRV2 as inputs, thereby generating modified drive signals D1 and D2 for driving the MEMS micromirror 11 and generating a feedback signal FBK representing the movement of the MEMS micromirror 11 as an output. The drive signal modification core 30 will be described in detail below, but first the remainder of the drive circuit 10 will be described.

[0040] The phase delay circuit 19 adds a delay to the feedback signal FBK to generate a delayed feedback signal FBK_DLY. The phase estimation circuit 23 (e.g., a phase frequency detector) compares the phase of the delayed feedback signal FBK_DLY with the phase of the first drive signal DRV1 and outputs the comparison result to the group delay estimation circuit 24. The group delay estimation circuit 24 not only estimates the phase delay between the phase of the delayed feedback signal FBK_DLY and the phase of the first drive signal DRV1, but also takes into account the additional phase delay added within the system in order to generate an output indicating whether the MEMS mirror 11 is in a resonant state. This output is used by the resonance lock proportional-integral-differential (PID) loop 25 to generate an output that is combined with the drive frequency control signal FREQ as feedback for causing the drive frequency control signal generator 27 to generate a drive frequency control signal FREQ such that ultimately the MEMS mirror 11 moves while in resonance. This is achieved by controlling the phase of the drive frequency control signal FREQ.

[0041] The drive signal modification core 30 includes AND gates 14 and 15, and buffers 16 and 17 powered by a voltage generator 18. The first drive signal DRV1 and the logic signal LGK are logically ANDed together by the AND gate 14 and buffered by the buffer 16 (powered by the voltage generator 18) to generate a first modified drive signal D1. Similarly, the second drive signal DRV2 and the logic signal LGK are logically ANDed together by the AND gate 15 and buffered by the buffer 17 (also powered by the voltage generator 18) to generate a second modified drive signal D2. The MEMS mirror 11 is driven by the first modified drive signal D1 and the second modified drive signal D2. The position sensor 12 (exemplarily a piezoresistive position sensor, but any suitable position sensor may be used) generates a feedback signal FBK indicating the movement of the MEMS mirror 11.

[0042] The peak estimation circuit 20 determines when the peak amplitude value of the delayed feedback signal FBK_DLY is reached (e.g., determines the opening angle of the MEMS mirror 11) and passes it to the logic core 21. Note that the purpose of the peak estimation circuit 20 is to prevent the logic core 21 operating at high frequency from continuously analyzing the delayed feedback signal FBK_DLY, but rather to allow the logic core 21 to analyze the peak of the delayed feedback signal FBK_DLY at other times instead of analyzing the delayed feedback signal FBK_DLY continuously. As Figure 5AAs shown, the logic core 21 includes an analog-to-digital converter 21a that digitizes the peak value (e.g., the opening angle of the MEMS mirror 11), and a comparison circuit 21b that compares it with a reference signal REF generated by the target opening angle circuit 22. The reference signal REF is a digital voltage representing the voltage at which the delayed feedback signal FBK_DLY will be when the MEMS mirror 11 is at its target opening angle.

[0043] Therefore, if the digitized peak amplitude value of the delayed feedback signal FBK_DLY is less than the reference signal REF, indicating that the MEMS mirror 11 has not reached the target opening angle, the logic core 21 asserts its output LGK to logic high, thereby allowing the drive signals DRV1 and DRV2 to pass through the AND gates 14 and 15. On the other hand, if the digitized peak amplitude value of the delayed feedback signal FBK_DLY is equal to the reference signal REF, indicating that the MEMS mirror 11 has reached its target opening angle, the logic core 21 deasserts its output LGK (e.g., pulls it to logic low), blocking the drive signals DRV1 and DRV2 from passing through the AND gates 14 and 15, having the effect of cutting off the first modified drive signal D1 and the second modified drive signal D2, where the mirror continues to oscillate, but its opening angle decays over time.

[0044] This repeats the comparison of the delayed feedback signal FBK_DLY on a cycle-by-cycle basis such that when the peak of the delayed feedback signal FBK_DLY is at or above the desired peak, the drive signals DRV1 and DRV2 are blocked, and such that when the peak of the delayed feedback signal FBK_DLY is below the desired peak, the drive signals DRV1 and DRV2 are passed to generate the modified drive signals D1 and D2. Note that since the drive signals DRV1 and DRV2 are opposite in phase to each other, in some cases, by comparing the delayed feedback signal FBK_FLY with the reference signal REF, pulses from one of them will be allowed to pass. As an alternative, the comparison of the delayed feedback signal FBK_DLY can be repeated on a half-cycle basis such that when the peak of the delayed feedback signal FBK_DLY is at or above the desired positive peak, the drive signals DRV1 and DRV2 are blocked, and such that when the peak of the delayed feedback signal FBK_DLY is at or below the desired negative peak, the drive signals DRV1 and DRV2 are blocked, otherwise the drive signals DRV1 and DR2 are passed to generate the modified signals D1 and D2.

[0045] Therefore, the actual driving of the MEMS mirror 11 is performed by drive signals D1 and D2 that contain "sparse" pulses. By "sparse" it is meant that, unlike in the case of traditional drive signals where the pulses of the signal have the same width and occur periodically, the pulses of drive signals D1 and D2 are generated only when the peak of the delayed feedback signal FBK_DLY is lower than the desired peak. This means that different pulses can have different pulse widths and any number of pulses can be skipped altogether.

[0046] Figure 6 is a graph showing this operation over time. Note that the time T0 of the first marked time point is a period of time after startup at which the opening angle of the MEMS mirror 11 begins to approach the desired opening angle. Keep in mind that between time T0 and T1, the output LGK of the logic core 21 is at logic high. Therefore, the modified drive signals D1 and D2 follow the drive signals DRV1 and DRV2, and each pulse is reproduced. However, at time T1, the peak of the delayed feedback signal FBK_DLY has reached its desired peak (FBK_DLY = REF), so the logic core 21 de-asserts its output LGK. Since at time T1, a D1 pulse is currently being generated, the change of LGK to logic low causes the AND gate 14 to block DRV1 (e.g., output logic zero), which means that D1 is immediately pulled to logic zero. The fact that LGK is at logic low also causes the AND gate 15 to block DRV2, and as a result, no D2 pulses are generated between time T1 and T2, as can be observed. At time T2, the peak of the delayed feedback signal FBK_DLY has dropped below its desired peak (FBK_DLY < REF), so the logic core 21 asserts its output LGK. Therefore, at time T2, the AND gate 14 passes DRV1, and as a result, a D1 pulse is generated. However, by time T3, the delayed feedback signal FBK_DLY has reached its desired peak (FBK_DLY = REF) and remains there until T4, causing the logic core 21 to de-assert its output LGK, pulling D1 low and preventing the generation of D2 pulses. At time T4, the delayed feedback signal FBK_DLY has dropped below its desired peak (FBK_DLY < REF) and remains there until T5, which means that the logic core 21 asserts its output LGK, allowing the generation of D2 pulses. However, since at T5, the delayed feedback signal FBK_DLY has reached its desired peak (FBK_DLY = REF) and remains there until T6, the logic core 21 de-asserts its output LGK again, preventing the generation of D1 and D2 pulses. Until D6, as described above, the delayed feedback signal FBK_DLY has dropped below its desired peak (FBK_DLY = REF), causing the logic core 21 to assert its output LGK again, allowing the generation of D2 pulses.

[0047] Therefore, in Figure 6 it can be observed that the operation of the drive circuit 30 can cause either or both of the modified drive signals D1 and D2 to be blocked. Note that although not shown in Figure 6 in some cases, the output LGK of the logic core 21 can be arranged to change the pulse widths of the drive signals D1 and D2 according to whether the delayed feedback signal FBK_DLY reaches its desired peak (FBK_DLY = REF) rather than simply blocking the pulses. It should be understood that naturally, when fewer pulses of the modified drive signals D1 and D2 are generated, the power consumption is reduced.

[0048] In this instance, the AND gates 14 and 15 are replaced by logic circuits 14' and 15' that generate full-width pulses of D1 and D2 or half-width pulses of D1 and D2. These logic circuits 14' and 15' can be seen in Figure 7 where it can be observed that they include drive edge counters 14a' and 15a' that receive the output LGK and count the number of drive signal edges between the two edges of LGK. Thus, the drive edge counter 14a' counts the number of drive signal DRV1 edges between the two edges of LGK, and if the number of edges is greater than a given number N, the modified drive signal D1 is generated with a half-width pulse, otherwise it is generated with a full-width pulse. Similarly, the drive edge counter 15a' counts the number of drive signal DRV2 edges between the two edges of LGK, and if the number of edges is greater than the given number N, a modified drive signal D2 with a half-width pulse is generated, otherwise a clipped full-width pulse is generated. The half-width pulses thus generated can be observed in Figure 8 and in Figure 8 it can be seen that the pulse widths of these pulses are not half of the mirror movement period but one quarter of the mirror movement period.

[0049] A comparison of the amplitude and start-up time of the same MEMS mirror 11 when only using the phase-based control of the drive circuit 10 without using the amplitude-based control of the drive signal modification core 30 ( Figure 9 ) and when using the amplitude-based control of the drive signal modification core 30 ( Figure 10 ) helps to illustrate the advantages provided by the drive signal modification core 30. In this example, the target amplitude of the movement of the MEMS mirror 11 is 30° (e.g., oscillating between ±15°), the target frequency is 28 kHz, and the Q factor is 10,000. Note that without the drive signal modification core 30, the start-up time is greater than 200 ms, as shown in Figure 9 , but with the drive signal modification core 30, the start-up time is less than 50 ms, as shown in Figure 10As shown. Note that when modifying the core 30 using the drive signals, the amplitudes of the drive signals D1 and D2 are higher, for example, shown as 5V in this text, while when not using the drive signals to modify the core 30, the amplitudes of the drive signals D1 and D2 are lower, shown as 1.7V in this text. The drive signals in both examples are at 27.999 kHz (~28 kHz). Note that the start-up time can be reduced by increasing the drive voltage. For example, to reduce the start-up time from approximately 50 ms to 10 ms, the drive voltage can be increased from 5V to 20V.

[0050] The fast start-up time provided by modifying the core 30 with the drive signals is particularly desirable for applications where the MEMS mirror 11 does not operate frequently but starts and stops multiple times during operation. One such example is mixed reality glasses, where at certain times, the MEMS mirror 11 is started to display information to the user, but in other cases, it is stopped to provide an uninterrupted view to the user through the glasses.

[0051] It should be understood that the drive signal modification core 30 is independent of the mechanical parameters of the MEMS mirror 11, eliminating or substantially reducing the need to carefully and specifically match the drive signals DRV1 and DRV2 to the specific properties of the MEMS mirror 11. For prior art designs, calibration or trimming performed on the drive circuit 10 may be necessary for each unit product to account for process variations between batches of MEMS mirrors. However, this is eliminated when the drive signal modification core 30 reaches the desired amplitude or opening angle, regardless of whether the drive signals DRV1 and DRV2 and the drive circuit 10 precisely match the specific properties of the MEMS mirror 11. Additionally, due to the drive signal modification core 30, there is also no need to particularly carefully control the amplitudes and frequencies of the drive signals DRV1 and DRV2.

[0052] Figures 11 to 12 is a graph showing the opening angle error of the MEMS mirror 11 when driven using only the phase-based control of the drive circuit 10 without using the amplitude-based control of the drive signal modification core 30 ( Figure 11 ) compared to when driven using the amplitude-based control of the drive signal modification core 30 ( Figure 12 ). It shows that using the amplitude-based control of the drive signal modification core 30, although amplitude errors do occur, the trajectory of the MEMS mirror 11 is not affected. However, such amplitude errors can be easily eliminated through compensation. Therefore, using the amplitude-based control of the drive signal modification core does not reduce the accuracy.

[0053] A variant of the drive signal modification core 30' is as Figure 13As shown. Note here that, instead of an AND gate, the drive logic circuits 14' and 15' receive drive signals DRV1 and DRV2 from the drive clock generator 13 respectively. In addition, the drive logic circuits 14' and 15' also receive a first logic signal LGK1 and a second logic signal LGK2 from the logic core 21. If needed, the variant 30' can operate exactly as Figure 5 the drive signal modifies the core 30. However, according to the peak of the delayed feedback signal FBK_DLY, the variant 30' can also generate phase-inverted modified drive signals D1 and D2, thereby providing a pulse train that quickly stops the movement of the MEMS mirror 11 or quickly pulls the amplitude of the MEMS mirror 11 back below the desired threshold.

[0054] In some instances, using the drive signal modification core 30 or 30' can eliminate the part in the drive circuitry 10 for providing phase-based control. Figure 14 Such an example of the drive circuitry 10″ is shown, where it can be observed that the drive frequency generation circuit 27 does not receive feedback. Instead, the desired opening angle (e.g., amplitude) can be achieved only through the amplitude-based modification provided by the drive signal modification core 30″.

[0055] Note that although the above has been described with respect to the operation of the MEMS mirror, the drive signal modification cores 30, 30' and 30″ described herein can be used with any MEMS device, such as a gyroscope or a lens operating at resonance using MEMS technology.

[0056] Although the present disclosure has been described for a limited number of embodiments, those skilled in the art who benefit from the present disclosure will understand that other embodiments can be envisioned without departing from the scope of the present disclosure as disclosed herein. Therefore, the disclosed scope is limited only by the appended claims.

Claims

1. A control circuit for a microelectromechanical system (MEMS) device, the control circuit comprising: An input logic circuit configured to receive a control signal and at least one MEMS drive signal and, based thereon, cause generation of at least one modified drive signal for driving the MEMS device; Logic circuitry configured to: Receive a feedback signal from the MEMS device and indicate when the feedback signal is at its peak, the feedback signal indicating movement of the MEMS device; and Based on the indication of when the feedback signal is at its peak, generate the control signal based on whether the peak is at least equal to a desired peak, the desired peak indicating that the movement of the MEMS device has reached a desired amplitude; wherein the input logic circuit is configured to: when the feedback signal is at least equal to the desired peak, modify the at least one MEMS drive signal to generate the at least one modified drive signal, the modification of the at least one MEMS drive signal causing the at least one modified drive signal to have a variable frequency and / or duty cycle dependent on the control signal.

2. The control circuit according to claim 1, wherein the logic circuitry comprises: An analog-to-digital converter that digitizes the feedback signal when the logic circuitry indicates that the feedback signal is at its peak; and a comparator that compares the digitized feedback signal with the desired peak to generate the control signal.

3. The control circuit according to claim 2, wherein the comparator asserts the output of the comparator when the digitized feedback signal is less than the desired peak and de-asserts the output of the comparator otherwise; and wherein the input logic circuit includes at least one AND gate that receives the control signal and the at least one MEMS drive signal as inputs and, as a result of performing a logical AND operation on the control signal and the at least one MEMS drive signal, generates the at least one modified drive signal.

4. The control circuit according to claim 3, further comprising a buffer coupled between the output of the at least one AND gate and the MEMS device.

5. The control circuit according to claim 2, wherein the comparator asserts the output of the comparator when the digitized feedback signal is less than the desired peak and de-asserts the output of the comparator otherwise; wherein the at least one MEMS drive signal includes a first MEMS drive signal and a second MEMS drive signal having opposite phases ； wherein the at least one modified drive signal includes a first modified drive signal and a second modified drive signal for driving the MEMS device; and wherein the input logic circuit includes: A first AND gate receives the control signal and the first MEMS drive signal as inputs, and as a result of performing a logical AND operation on the control signal and the first MEMS drive signal, the first AND gate generates the first modified drive signal; and A second AND gate receives the control signal and the second MEMS drive signal as inputs, and as a result of performing a logical AND operation on the control signal and the second MEMS drive signal, the second AND gate generates the second modified drive signal.

6. The control circuit according to claim 5, further comprising a first buffer and a second buffer, the first buffer being coupled between the output of the first AND gate and the MEMS device, and the second buffer being coupled between the output of the second AND gate and the MEMS device.

7. The control circuit according to claim 1, further comprising a drive frequency generator and a drive clock generator, the drive frequency generator being configured to generate a drive frequency signal, and the drive clock generator being configured to generate the at least one MEMS drive signal based on the drive frequency signal.

8. The control circuit according to claim 7, further comprising: A phase delay circuit configured to receive the feedback signal and apply a phase delay to the feedback signal; A phase estimation circuit configured to receive the feedback signal after the phase delay circuit applies the phase delay to the feedback signal, receive the at least one MEMS drive signal, and generate a phase estimation signal that indicates whether the feedback signal leads or lags the at least one MEMS drive signal; A group delay estimation circuit configured to receive the phase estimation signal to determine whether the MEMS device is operating in a resonant state considering system phase delay, and generate an output signal based on the determination; and A resonant proportional-integral-derivative loop configured to operate based on the output signal from the group delay estimation circuit to generate a drive frequency input; wherein the drive clock generator is configured to generate the drive frequency signal based on the drive frequency input.

9. The control circuit according to claim 1, wherein when the feedback signal is at least equal to the desired peak, the input logic circuit modifies the at least one MEMS drive signal by preventing generation of the at least one modified drive signal until the feedback signal is less than the desired peak.

10. The control circuit according to claim 1, wherein when the feedback signal is at least equal to the desired peak, the input logic circuit modifies the at least one MEMS drive signal by shortening the pulse width of the at least one modified drive signal until the feedback signal is less than the desired peak.

11. The control circuit according to claim 1, wherein the MEMS device includes a MEMS micromirror and a position sensor, the MEMS micromirror is driven by the at least one modified drive signal, the position sensor is associated with the MEMS micromirror, and generates the feedback signal.

12. The control circuit according to claim 1, wherein when the feedback signal is at least equal to the desired peak value, the input logic circuit modifies the at least one drive signal by inverting the at least one drive signal.

13. The control circuit according to claim 1, wherein the logic circuit means comprises: a peak estimation circuit configured to receive the feedback signal from the MEMS device and indicate when the feedback signal is at its peak, the feedback signal indicating the movement of the MEMS device; and a logic core configured to receive the indication from the peak estimation circuit, the indication indicating when the feedback signal is at its peak, and generate the control signal based on whether the peak is at least equal to a desired peak value, the desired peak value indicating that the movement of the MEMS device reaches a desired amplitude.

14. A method of operating a MEMS device, comprising: generating at least one MEMS drive signal; modifying the at least one MEMS drive signal based on a control signal to generate at least one modified drive signal; and generating the control signal by: determining when a feedback signal from the MEMS device is at its peak, comparing the peak with a desired value when the feedback signal is at its peak, and generating the control signal based on whether the peak is at least equal to the desired value; wherein modifying the at least one MEMS drive signal based on the control signal to generate the at least one modified drive signal includes: when the control signal indicates that the peak is at least equal to the desired value, skipping the generation of the next pulse of the at least one modified drive signal.

15. The method according to claim 14, wherein when the peak is at least equal to the desired value, the control signal is asserted; and wherein the modification of the at least one MEMS drive signal is accomplished by performing a logical AND operation between the control signal and the at least one MEMS drive signal.

16. The method according to claim 14, wherein the at least one modified drive signal is generated by inverting the at least one drive signal for at least some time when the feedback signal is at least equal to the desired value.

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