Apparatus and method for generating bias voltage in nonvolatile memory

Abstract

Embodiments provide an apparatus and method for generating bias voltages in non-volatile memory. The present disclosure relates to an integrated circuit including a non-volatile memory (NVM). The integrated circuit includes a bias generator that generates stable word line voltages and bit line voltages for reliable read operations of the NVM. The present disclosure relates to low voltage memory operations for memory read, erase verification, and program verification. The present disclosure relates to a non-volatile memory circuit that can also operate at a low power supply voltage within a digital voltage supply range.

Description

Technical Field

[0001] The present disclosure relates to a memory circuit including a non-volatile memory array. Background Art

[0002] A non-volatile memory circuit generates word line voltages for memory read operations, erase verification operations, and program verification operations, and bit line voltages for avoiding read interference situations. The non-volatile memory circuit is vulnerable to process variations and temperature variations. Current solutions that seek to address the undesired variations in word line voltages and bit line voltages due to temperature and process changes can be resource-intensive and may affect the performance of the non-volatile memory circuit.

[0003] Some of the current solutions require temperature signals from a temperature sensor external to the non-volatile memory circuit. Some other solutions monitor any changes in the voltage on an external pin due to factors such as temperature and process, and use that information to change circuit parameters until the correct voltage is obtained on the monitored pin. Also, current word line generation circuits operate only using a high analog supply voltage. Summary of the Invention

[0004] The present disclosure relates to an integrated circuit including a non-volatile memory (NVM). The integrated circuit includes a bias generator that generates stable word line voltages and bit line voltages for reliable read operations of the NVM. The present disclosure relates to low voltage memory operations for memory read, erase verification, and program verification. The present disclosure relates to a non-volatile memory circuit that can also operate at a low supply voltage within a digital voltage supply range.

[0005] The bias generator includes both a bias replication circuit for generating a word line bias voltage and a cascode voltage generation circuit for generating a bit line bias voltage. The bias voltages generated by the bias generator compensate for any temperature and process variations.

[0006] The cascode voltage generation circuit is coupled to a current mirror, which is in turn coupled to a current comparator, an oscillator, a phase generator, and a switched capacitor charge pump. The charge pump generates a word line bias (V GATE ) for the main memory array, and generates a floating gate voltage (VFG) for a reference memory array in the bias replication circuit.

[0007] When a memory read operation begins, VFG can be zero, the supply voltage (VDD) can be stable, the oscillator is enabled and propagating a clock. The word line bias V GATEBegin to approach the power supply voltage (VDD), the floating gate voltage (VFG) begins to increase, and current begins to accumulate in the bias replication circuit. This current is mirrored and compared with a reference current (I REF ), and this reference current (I REF ) is the same reference current as the reference current of the sense amplifier in the main memory array. If the mirrored current is less than the reference current I REF , then the oscillator propagates the clock. The inverter and AND gate can be coupled to the oscillator and can indicate that the charge pump maintains increasing the word line bias (V GATE ) and the floating gate (VFG) until the mirrored current equals the reference current I REF .

[0008] The bias replication circuit is coupled to the main memory array for which the bias voltage is being generated. The bias replication circuit has a smaller proportion of all the elements of the main memory array to mimic or replicate the characteristics and behavior of the main memory array. The bias replication circuit includes a column decoding block, a replicated memory array, and a source line path block.

[0009] The cascode voltage generation circuit is coupled to a plurality of sense amplifiers of the main memory array. In one embodiment, the cascode voltage generation circuit includes an operational amplifier and an n-mos transistor, wherein the source of the n-mos transistor is coupled to the operational amplifier in a feedback arrangement such that the voltage output (V CASC ) of the operational amplifier changes to maintain a stable voltage at the source of this n-mos transistor. Brief Description of the Drawings

[0010] Figure 1 is a non-volatile memory system, the non-volatile memory system includes a memory array having memory cells and circuitry for generating memory read voltages including word line voltages and bit line voltages;

[0011] Figure 2A is a graph of current versus gate voltage for memory read, erase verification, and program verification;

[0012] Figure 2B is a representation of the parasitic capacitance associated with the gate of a transistor;

[0013] Figure 3 is one embodiment of a circuit in a non-volatile memory for generating word line voltages for different read operations and verification operations and bit line voltages for avoiding read interference phenomena;

[0014] Figure 4 is another embodiment of a circuit in a non-volatile memory for generating word line voltages for different read operations and verification operations and bit line voltages for avoiding read interference phenomena, the circuit having a voltage controlled oscillator;

[0015] Figure 5 is an embodiment of a replicated memory array having memory cells coupled in series and parallel configurations;

[0016] Figure 6 is an alternative embodiment of a replicated memory array having memory cells coupled in parallel configurations;

[0017] Figure 7 is a time-versus-voltage graph of a plurality of gate voltages required to obtain a fixed current in a memory array for a non-volatile memory in response to process and temperature variations; and

[0018] Figure 8 is another embodiment of a circuit without an oscillator that generates word line voltages for different read and verify operations and bit line voltages for avoiding read disturb phenomena in a non-volatile memory. DETAILED DESCRIPTION

[0019] Figure 1 is an embodiment of a circuit 100 of a non-volatile memory system according to the present disclosure, the non-volatile memory system adapted to process and temperature variations that may occur during use. The circuit illustrates how word line voltages and bit line voltages are generated and used by memory cells of a memory array to perform memory read operations, program verify operations, and erase verify operations in a non-volatile memory. A memory read operation of the circuit is described in detail below.

[0020] Figure 1 is an embodiment of a circuit 100 of a non-volatile memory system including a non-volatile memory array 106 having a plurality of memory cells 102 that are coupled in series to form a plurality of rows 103 of memory cells 102. Word line voltages and bit line voltages are used to read non-volatile memory cells 102, the word line voltages and bit line voltages being applied to a word line 124 in a plurality of word lines 104 and a bit line 105 in a plurality of bit lines 107, respectively. The plurality of bit lines 107 are coupled to a column multiplexer 112. The column multiplexer 112 is coupled to a plurality of sense amplifiers 108. Each bit line 105 is coupled to a corresponding sense amplifier 110. A read voltage generator 116 generates a gate voltage V GATE 120 and a cascode voltage V CASC 114. The gate voltage 120 is coupled to a plurality of word line drivers 121. A word line driver 122 in the plurality of word line drivers 121 is coupled to the read voltage generator 116 through the gate voltage V GATE 120. The plurality of sense amplifiers 108 are coupled to the read voltage generator 116 through the cascode voltage V CASC114 is coupled to a read voltage generator 116. A row decoder 118 among a plurality of row decoders 119 is coupled to a word line driver 122 among a plurality of word line drivers 121.

[0021] During operation, when a memory cell 102 is selected for reading, a word line voltage is applied to the gate of the memory cell 102 and current discharges on the bit line 105, and the bit line 105 is sensed by a sense amplifier 110. The sense amplifier 110 is activated by a cascode voltage V CASC 114. The word line voltage is obtained by boosting the gate voltage 120 via the word line driver 122.

[0022] Figure 2A is a graph of the current versus the gate voltage for a memory cell 102 during operation for memory read operations, erase verification operations, and program verification operations. In the non-volatile memory 100, the threshold voltage is defined as the gate voltage that provides a selected reference current I REF for the memory cell. The threshold voltage of the memory cell 102 is different for different memory operations (such as memory read, erase verification, and program verification), see Vth_ERASE and Vth_PROG. The memory row to which the memory cell to be read belongs receives a fixed gate voltage equal to the threshold voltage (V GATE ) for that operation from the read voltage generator 116.

[0023] As a result of aging and repeated operations, the threshold voltages for different operations may start to shift. The voltage for the read operation lies with a voltage margin between the voltage for the erase verification operation and the voltage for the program verification operation, such that these operations remain error-free and the shifts (if any) of the threshold voltages do not overlap with each other.

[0024] Figure 2B is an equivalent circuit representation of the memory cell to be read, and the memory cell to be read can be represented as two capacitors C1, C2 coupled in series. The floating gate voltage Vfg is represented by the following equation:

[0025]

[0026] The ratio of the memory cell capacitances is given by the following equation:

[0027]

[0028] This ratio is used to determine the floating gate voltage Vfg coupled to the gate of the memory cell of the replica memory array, which is described in more detail below.

[0029] The floating gate voltage can be represented by the following formula:

[0030] Vfg = αV GATE , where

[0031] Figure 3 is an embodiment of a non - volatile memory (NVM) circuit 300 according to the present disclosure. The non - volatile memory (NVM) circuit 300 generates word - line voltages for temperature and process compensation for memory read operations, erase verification operations, and program verification operations, and generates bit - line voltages for temperature and process compensation to avoid read interference. When the high supply voltage VDD is not available, this embodiment can be utilized. The absence of the high supply voltage VDD results in the use of a charge pump to generate a word - line voltage and a cascode voltage (V CASC ) higher than the input supply voltage VDD.

[0032] The circuit 300 includes a main memory array circuit 339, which is coupled to a bias replication circuit 301 to generate stable word - line voltages and bit - line voltages for reliable read operations of the NVM. The main memory array circuit 339 includes a main memory array 341, which is coupled to a source - line path block 343, and the source - line path block 343 is coupled to ground. The main memory array 341 is coupled to a column decoding block 345, and the column decoding block 345 is coupled to a plurality of sense amplifiers 333. In Figure 3 , a plurality of cascode transistors 335 are located between the plurality of sense amplifiers 333 and the column decoding block 345. In some embodiments, the cascode transistors 335 are located within the sense amplifiers 333.

[0033] The bias replication circuit 301 includes a replicated source - line path block 302, which is coupled to ground and a replicated memory array block 303, and the replicated memory array block 303 is further coupled to a replicated column decoding block 305. The bias replication circuit 301 is a representation of the components of the main memory array circuit 339, which include the column decoding block 345, the main memory array 341, and the source - line path block 343. The bias replication circuit 301 is formed simultaneously with the main memory array circuit 339 during chip fabrication, such that the components of the bias replication circuit will have the same or similar physical characteristics and will have performance very similar to that of the main memory array. This allows the bias replication circuit 301 to minimize voltage fluctuations caused by different temperature and process variations during use.

[0034] The offset copy circuit is coupled to a cascode voltage generation circuit 307, which is coupled to the main memory array circuit 339 through a cascode transistor 335. The cascode voltage generation circuit 307 includes an operational amplifier 309, which is coupled to a transistor 311 in a feedback arrangement. The output of the operational amplifier 309 is coupled to the gate of the transistor 311. The source terminal of the transistor 311 is coupled to the negative input of the operational amplifier 309. The positive terminal of the operational amplifier 309 is coupled to a voltage supply (reference voltage) V REF . In some embodiments, the transistor 311 may be an N-MOS transistor.

[0035] The cascode voltage generation circuit 307 is coupled to a current mirror 313, which has two transistors 315 and 317, and these two transistors 315 and 317 may be P-MOS transistors. The gates of the transistors 315 and 317 are shorted and coupled to a terminal of the transistor 315, and this terminal of the transistor 315 is further coupled to a terminal of the transistor 311 in the cascode voltage generation circuit 307. A terminal of the current mirror transistor 317 of the current mirror 313 is coupled to a current source 319, which generates a reference current I that is the same as the reference current applied to each of the plurality of sense amplifiers 334 in the plurality of sense amplifiers 333 REF . A terminal of the current mirror transistor 317 is also coupled to an inverter 323. The output of the inverter 323 is coupled to one of the inputs of an AND gate 325. The other input of the AND gate 325 is coupled to an oscillator 321.

[0036] The output of the AND gate 325 is a clock, which triggers the phase generator 327 to generate a plurality of clock phases (CK and CKN) at its output. In the illustrated embodiment, the phase generator 327 generates two clock phases. However, the phase generator may generate 4 clock phases. The number of clock phases is a multiple of 2.

[0037] The phase generator 327 is coupled to a switched capacitor charge pump (CP) 329. The two clock phases at the output of the phase generator 327 are the inputs of the charge pump 329. The charge pump 329 generates an output voltage V GATE , and this output voltage V GATE controls the gates of a plurality of transistors in the main memory array block 341 to generate word line voltages. The charge pump 329 is coupled to a resistor ladder 331, which generates a floating gate voltage VFG.

[0038] Different V GATE voltages are used for memory read operations, program verification operations, or erase verification operations, and these voltages are obtained from the resistor ladder 331 by changing the resistances of the resistors R1 and R2. The floating gate voltage VFG is the gate voltage VGATE The function, which is given by:

[0039] VFG = alpha × V GATE ,

[0040] where C1 and C2 are the capacitances of transistors 308 and 306 respectively.

[0041] The floating gate voltage VFG controls the floating gates of multiple field programmable (FTP) memory cells in the replicated memory array block 303. For illustrative purposes, one FTP memory cell in the FTP memory cells is shown in block 303, and this FTP memory cell includes three transistors 304, 306, 308, where the gates of transistor 306 and transistor 308 are short-circuited and coupled to the floating gate voltage VFG. The gate of the third transistor 304 is coupled to the power supply voltage VDD. The terminals of transistor 304 are coupled to the source line path block 302. The terminals of transistor 306 are coupled to the column decoding block 305. The terminals of transistor 308 can be floating or short-circuited with the terminals of transistor 308. As beneficial for the overall circuit design, this arrangement of FTP memory cells is repeated with multiple FTP memory cells.

[0042] The source line path block 302 includes multiple transistors. The number of transistors in the source line path block 302 is proportional to the size of the source line path 343. In the illustrated embodiment, three transistors 353, 354, and 355 are connected in series, and the gates of these three transistors 353, 354, and 355 are coupled to the power supply voltage VDD. The terminals of transistor 353 are coupled to the replicated array block 303. The terminals of transistor 355 are coupled to ground.

[0043] The column decoding block 305 includes multiple transistors. The number of transistors in the column decoding block 305 is proportional to the size of the column decoding block 345. In the illustrated embodiment, two transistors 351 and 352 are connected in series, and the gates of these two transistors 351 and 352 are coupled to the power supply voltage VDD. The terminals of transistor 351 are coupled to the terminals of the cascode transistor 311. The terminals of transistor 352 are coupled to the replicated array.

[0044] When the circuit is turned on and the power supply VDD is stable or otherwise not fluctuating, the floating gate voltage VFG is zero and the oscillator 321 is enabled. The clock at the output of the oscillator 321 starts to propagate, V GATE starts to approach VDD and VFG starts to increase. Current starts to accumulate in the bias replication circuit 301, which is mirrored by the current mirror 313 and is compared with the reference current (I used in the current source 319 REF) are compared. The current source and transistor 317 together form a current comparator. If the mirrored current is greater than I REF , a stop signal (logic high) is triggered at node 312, which is formed by shorting the terminals of current mirror transistor 317, current source 319, and the input of inverter 323. The stop signal generates a logic low signal at the output of inverter 323, which stops the clock at the output of AND gate 325.

[0045] The V GATE voltage at the output of charge pump 329 and the VFG voltage hold their values in response to the stopped clock at the output of AND gate 325. At this time, the current in bias replica circuit 301 starts to decrease, such that the I REF current is greater than the current in bias replica circuit 301. This generates a stop signal (logic low) at the input of inverter 323, thereby generating a logic high signal at the output of inverter 323, which starts the clock at the output of AND gate 325. Thus, the V GATE voltage at the output of CP 329 and the VFG voltage start to increase. As a result, the current in bias replica circuit 301 starts to increase again until the I REF current is equal to the current in bias replica circuit 301. This feedback loop generates a stable voltage for the main memory array.

[0046] The transconductances of the cascode transistors 311, the memory cells of replica memory array 303, and the memory cells of main memory array 341 may change with process and temperature, which may change the currents flowing in bias replica circuit 301 and main memory circuit 339. Such a change in current causes the bit line voltages VBL at nodes 350 and 362 of bias replica circuit 301 to change. The change in the bit line voltage VBL at node 362 causes the cascode voltage output of operational amplifier 309 to change, such that the current flowing in the bias replica circuit changes to maintain the earlier bit line voltage level that existed before the process and temperature changes had an effect. Since the cascode voltage output of operational amplifier 309 is also coupled to the cascode transistors 335 of multiple sense amplifiers 333 in the main memory circuit, the bit line voltages in the main memory circuit are protected from process and temperature variations in the same manner as the bit line voltages of the replica memory array.

[0047] As temperature and process changes cause the current flowing in main memory array circuit 339 to vary, since the cells of the main memory array and the replica memory array are formed in the same manufacturing process and have similar responses to process and temperature variations, the same current variations are mimicked by the current flowing in bias replica circuit 301. By changing voltage V GATEWith VFG, circuit operation ensures that the currents in the bias copy circuit 301 and the main memory array circuit 339 remain stable regardless of any temperature and process variations.

[0048] Figure 4 FIG. 4 is an alternative embodiment of the non-volatile memory circuit 400 according to the present disclosure. The non-volatile memory circuit 400 generates word line voltages for temperature and process compensation for memory read operations, erase verification operations, and program verification operations, and generates bit line voltages for temperature and process compensation to avoid read interference. This embodiment can be utilized when the high power supply voltage VDD is not available. The absence of the high power supply voltage VDD results in the use of a charge pump to increase the power supply voltage VDD to a level higher than the available VDD to generate the word line voltage and the bit line voltage.

[0049] The circuit 400 includes a main memory array circuit 439 that is coupled to a bias copy circuit 401. The main memory array circuit 439 includes a main memory array 441 that is coupled to a source line path block 443 that is coupled to ground. The main memory array 441 is coupled to a column decoding block 445 that is coupled to a plurality of sense amplifiers 433. In Figure 4 FIG. 9, a plurality of cascode transistors 435 are located between the plurality of sense amplifiers 433 and the column decoding block 445. In some embodiments, the cascode transistors 435 are located within the sense amplifiers 433.

[0050] The bias copy circuit 401 includes a copy source line path block 402 that is coupled to ground and a copy memory array block 403 that is further coupled to a copy column decoding block 405. The bias copy circuit 401 is a representation of the components of the main memory array circuit 439 that include the column decoding block 445, the main memory array 441, and the source line path block 443. The bias copy circuit 401 is formed simultaneously with the main memory array circuit 439 such that the components of the bias copy circuit will have the same or similar physical characteristics and will have performance very similar to that of the main memory array. This allows the bias copy circuit 401 to minimize voltage fluctuations caused by different temperature and process variations during use.

[0051] The bias copy circuit is coupled to the cascode voltage generation circuit 407, which is coupled to the main memory array circuit 439 through the cascode transistor 435. The cascode voltage generation circuit 407 includes an operational amplifier 409, which is coupled to the transistor 411 in a feedback arrangement. The output of the operational amplifier 409 is coupled to the gate of the transistor 411. The terminals of the transistor 411 are coupled to the negative input of the operational amplifier 409. The positive terminal of the operational amplifier 409 is coupled to a voltage supply (which is a reference voltage) V REF . In some embodiments, the transistor 411 may be an N-MOS transistor.

[0052] The cascode voltage generation circuit 407 is coupled to a current mirror 413, which has two transistors 415 and 417, and these two transistors 415 and 417 may be P-MOS transistors. The gates of the transistors 415 and 417 are shorted and coupled to the terminal of the transistor 415, and this terminal of the transistor 415 is further coupled to the other terminal of the transistor 411 of the cascode voltage generation circuit 407.

[0053] The terminal of the current mirror transistor 417 of the current mirror 413 is coupled to a current source 419, which uses a reference current I REF , and this reference current I REF is the same as the reference current applied to each of the plurality of sense amplifiers 434 in the sense amplifiers 433. This terminal of the current mirror transistor 417 is also coupled to a voltage-controlled oscillator 421.

[0054] The output of the oscillator 421 is a clock, which triggers the phase generator 427 to generate a plurality of clock phases (CK, CKN). The phase generator 427 is coupled to a switched-capacitor charge pump (CP) 429. The two clock phases at the output of the phase generator 427 are the inputs of the charge pump 429. The charge pump 429 generates an output voltage V GATE , and this output voltage V GATE controls the gates of a plurality of transistors in the main memory array block 441 to generate a word line voltage. The charge pump 429 is coupled to a resistor ladder 431, which generates a floating gate voltage VFG. VFG controls the gates of a plurality of transistors in the replicated memory array block 403.

[0055] When the circuit is turned on and the power supply VDD is stable or otherwise not fluctuating, the floating gate voltage VFG is zero and the oscillator 421 is enabled. The clock at the output of the oscillator 421 starts to propagate, V GATE starts to approach VDD and VFG starts to increase. Current starts to accumulate in the bias copy circuit 401, which is mirrored by the current mirror 413 and is the same as the reference current (I) used by the current source 419REF ) is compared. If the mirror current is greater than I REF , a signal is triggered at node 412, which is formed by shorting the terminals of current mirror transistor 417, current source 419, and the input of VCO 421. This signal causes the clock frequency at the output of oscillator 421 to slow down. Current source 419 and transistor 417 form a current comparator.

[0056] In response to the slow clock at the output of oscillator 421, the V GATE voltage at the output of charge pump 429 and the VFG voltage hold their values. At this time, the current in bias replication circuit 401 starts to decrease, such that I REF is greater than the current in bias replication circuit 401. The signal at node 412 changes such that the clock frequency at the output of oscillator 421 starts to increase. Thus, the V GATE voltage at the output of charge pump 429 and the VFG voltage start to increase. As a result, the current in bias replication circuit 401 starts to increase again until the I REF current equals the current in bias replication circuit 401. This feedback loop generates a stable voltage for the main memory array.

[0057] The transconductances of the cascode transistors 411, the memory cells of replicated memory array 403, and the memory cells of main memory array 441 may change with process and temperature, which may change the currents flowing in bias replication circuit 401 and main memory circuit 439. This change in current causes the bit line voltages VBL at nodes 450 and 452 of bias replication circuit 401 to change. The change in the bit line voltage VBL at node 452 causes the cascode voltage output of operational amplifier 409 to change, such that the current flowing in the bias replication circuit changes to maintain an earlier bit line voltage level, which existed before the process and temperature changes had an effect. Since the cascode voltage output of operational amplifier 409 is also coupled to the cascode transistors 435 of a plurality of sense amplifiers 433 in the main memory circuit, the bit line voltages in the main memory circuit are protected from process and temperature variations in the same manner as the bit line voltages of the replicated memory array.

[0058] As temperature and process changes cause the current flowing in main memory array circuit 439 to vary, since the cells of the main memory array and the replicated memory array are formed in the same manufacturing process and have similar responses to process and temperature variations, the same current variations are mimicked by the current flowing in bias replication circuit 401. By changing voltages V GATE and VFG, the circuit operation ensures that the currents in bias replication circuit 401 and main memory array circuit 439 remain stable regardless of any temperature and process changes.

[0059] Figure 5 is an embodiment of a replicated memory array of a bias replication circuit. The replicated memory array includes memory cells coupled in series and parallel combinations such that the aspect ratio of the memory array is the aspect ratio that determines the mirror ratio of a current mirror, which is equivalent to a single memory cell. If the ratio is an integer multiple ratio, the mirror ratio will be adjusted accordingly. In this embodiment, the replicated memory array includes sixteen memory cells arranged in a 4×4 matrix such that they are arranged in four rows and four columns. All the memory cells in each of the four rows are coupled in series, and all the memory cells in each of the four columns are coupled in parallel. The source line terminals SL of transistor 2 of the memory cells are shorted and coupled to the source line, and the bit line terminals of transistor 1 of each memory cell are shorted and coupled to the bit line. The gates of transistor 1, the gates of transistor 3, and the terminals of transistor 3 of all the memory cells of the replicated memory array are shorted and coupled to the floating gate voltage VFG. The gates of transistor 2 of all the memory cells of the replicated memory array are also shorted and coupled to the power supply voltage VDD.

[0060] In this example, connecting the memory cells in parallel increases the width of the memory cells to be equal to 4*W. Similarly, connecting the memory cells in series makes the length of the memory cells equivalent to 4*L. This makes the width-to-length ratio (W / L) equivalent to that of a single memory cell. If the series-parallel ratio is different, the current mirror ratio in the bias replication branch can be adjusted.

[0061] Figure 6 is an embodiment of a replicated memory array of a bias replication circuit. In this embodiment, the replicated memory array includes sixteen memory cells arranged in a 4×4 matrix such that they are arranged in four rows and four columns. Four memory cells 4, 5, 6, and 7 of the replicated memory array are joined in parallel, and all the remaining twelve memory cells of the replicated memory array are coupled to ground by shorting the gates of transistors 1, 2, and 3 of each memory cell and coupling them to ground. The terminal of transistor 3 is also coupled to the shorted ground of the three transistors 1, 2, and 3. This results in an aspect ratio of 1:4 in the replicated memory array, which determines the mirror ratio of the current mirror.

[0062] The source line terminals SL of transistor 2 of the four memory cells 4, 5, 6, and 7 are shorted and coupled to the source line, and the bit line terminals of transistor 1 of the four memory cells 4, 5, 6, and 7 in the replicated memory array are shorted and coupled to the bit line. The gates of transistor 1, the gates of transistor 3, and the source of transistor 3 of all these four memory cells of the replicated memory array are shorted and coupled to the floating gate voltage VFG / V GATEThe gates of the transistors 2 that copy all the memory cells of the memory array are also shorted and coupled to the power supply voltage VDD.

[0063] Figure 7 Shows different gate voltages corresponding to temperature and process variations required to obtain a fixed current in the memory array. The different gate voltages shown in the graph are achieved using the proposed solution, Figure 3 、 Figure 4 and Figure 8 shows several embodiments of the solution.

[0064] Figure 8 is an embodiment of a non-volatile memory (NVM) circuit 800 according to the present disclosure. The non-volatile memory (NVM) circuit 800 generates word line voltages for temperature and process compensation for memory read operations, erase verification operations, and program verification operations, and generates bit line voltages for temperature and process compensation to avoid read interference. When a high power supply voltage VDD is available, this embodiment can be utilized. The availability of the high power supply voltage VDD allows the circuit to operate without a charge pump to increase the voltage levels of the word line voltage and the bit line voltage.

[0065] The circuit 800 includes a main memory array circuit 839 that is coupled to a bias copy circuit 801 to generate stable word line voltages and bit line voltages for reliable read operations of the NVM. The main memory array circuit 839 includes a main memory array 841 that is coupled to a source line path block 843 that is coupled to ground. The main memory array 841 is coupled to a column decoding block 845 that is coupled to a plurality of sense amplifiers 833. In Figure 8 a plurality of cascode transistors 835 are located between the plurality of sense amplifiers 833 and the column decoding block 845. In some embodiments, the cascode transistors 835 are located within the sense amplifiers 833.

[0066] The bias copy circuit 801 includes a copy source line path block 802 that is coupled to ground and a copy memory array block 803 that is in turn coupled to a copy column decoding block 805. The bias copy circuit 801 is a representation of the components of the main memory array circuit 839, which include the column decoding block 845, the main memory array 841, and the source line path block 843. The bias copy circuit 801 is formed simultaneously with the main memory array circuit 839 during chip fabrication such that the components of the bias copy circuit will have the same or similar physical characteristics and will have performance very similar to that of the main memory array. This allows the bias copy circuit 801 to minimize voltage fluctuations caused by different temperature and process variations during use.

[0067] The cascode voltage generation circuit 807 is coupled to a bias copy circuit, and the cascode voltage generation circuit 807 is coupled to the main memory array circuit 839 through a cascode transistor 835. The cascode voltage generation circuit 807 includes an operational amplifier 809, and the operational amplifier 809 is coupled to a transistor 811 in a feedback arrangement. The output of the operational amplifier 809 is coupled to the gate of the transistor 811. The source terminal of the transistor 811 is coupled to the negative input of the operational amplifier 809. The positive terminal of the operational amplifier 809 is coupled to a voltage supply (reference voltage) Vref. In some embodiments, the transistor 811 may be an N-MOS transistor.

[0068] The cascode voltage generation circuit 807 is coupled to a current mirror 813, and the current mirror 813 has two transistors 815 and 817, and the two transistors 815 and 817 may be P-MOS transistors. The gates of the transistors 815 and 817 are short-circuited and coupled to a terminal of the transistor 815, and this terminal of the transistor 815 is further coupled to a terminal of the transistor 811 of the cascode voltage generation circuit 807.

[0069] A terminal of the current mirror transistor 817 of the current mirror 813 is coupled to a current source 819, and the current source 819 uses a reference current I REF , and the reference current I REF is the same as the reference current applied to each sense amplifier 834 among a plurality of sense amplifiers 833. This terminal of the current mirror transistor 817 is further coupled to an inverter 830, and the inverter 830 is coupled to a switch S1 832. The switch 832 is coupled to the power supply voltage VDD when enabled. The switch 832 is also coupled to a capacitor 829 through a current source 834. The switch S2 831 is coupled to ground and the copy array 803 when enabled. One terminal of the capacitor 829 is coupled to ground, and the other terminal is coupled to an operational amplifier-based feedback circuit 821 through VFG. The operational amplifier feedback circuit 821 includes an operational amplifier 825, and the output of the operational amplifier 825 is coupled to the gate of a transistor 827. The terminal of the transistor 827 is coupled to the power supply voltage VDD, and the other terminal is coupled to a resistor ladder 823.

[0070] When the NVM circuit is in an inactive state and VDD is not available, switch S2 831 is enabled and switch S1 832 is disabled. The floating gate voltage VFG is clamped to ground through switch S2. When the NVM circuit is activated and the power supply VDD is stable or otherwise not fluctuating, switch S2 is turned off and switch S1 is turned on. With VFG being at ground, no current flows through the replica memory array, and node COMP1 is low. This pulls up another node STOPN to the power supply voltage VDD, thus enabling switch S1. With switch S1 enabled, capacitor C 829 starts charging with a fixed current. Then, the voltage VFG starts to rise, and the current in the replica memory array also starts to increase. Once the current from the replica memory array increases and becomes equal to current I REF , the state of node COMP1 changes from low to high.

[0071] As COMP1 goes high and STOPN goes low, switch S1 is turned off to stop the charging of capacitor C. Consequently, VFG also stops increasing. VFG stabilizes at a value such that the current from the replica memory array is equal to I REF current. When VFG is input into operational amplifier 825, VFG is also converted to V GATE through the feedback circuit 821. This feedback loop generates a stable voltage for the main memory array.

[0072] The transconductances of the cascode transistors 811, the memory cells of the replica memory array 803, and the memory cells of the main memory array 841 may change with process and temperature, which may change the currents flowing in the bias replica circuit 801 and the main memory circuit 839. This change in current causes the bit line voltages VBL at nodes 850 and 852 of the bias replica circuit 801 to change. The change in the bit line voltage VBL at node 852 causes the cascode voltage output of operational amplifier 809 to change, such that the current flowing in the bias replica circuit changes to maintain the earlier bit line voltage level that existed before the process and temperature changes had an effect. Since the cascode voltage output of operational amplifier 809 is also coupled to the cascode transistors 835 of multiple sense amplifiers 833 in the main memory circuit, the bit line voltages in the main memory circuit are protected from process and temperature variations in the same manner as the bit line voltages of the replica memory array.

[0073] As temperature and process changes cause the current flowing in the main memory array circuit 839 to vary, since the cells of the main memory array and the replica memory array are formed in the same manufacturing process and have similar responses to process and temperature changes, the same current variations are mimicked by the current flowing in the bias replica circuit 801. By changing voltage V GATEWith VFG, circuit operation ensures that the currents in the bias replication circuit 801 and the main memory array circuit 839 remain stable regardless of any temperature and process variations.

[0074] Embodiments of the present disclosure also include a non - volatile memory circuit that includes a main memory array having a plurality of sense amplifiers coupled to the main memory array. A bias replication circuit is coupled to the main memory array. A cascode voltage generation circuit is coupled to the plurality of sense amplifiers and the bias replication circuit. The non - volatile memory circuit further includes: a current mirror; a current comparator coupled to the current mirror; an oscillator coupled to the current comparator; a phase generator coupled to the oscillator; and a charge pump coupled to the phase generator and the bias replication circuit.

[0075] The non - volatile memory circuit includes a resistor divider coupled to the charge pump, the bias replication circuit, and the main memory array. The bias replication circuit includes: a replicated memory array; a replicated column decoding block coupled to the replicated memory array; and a source line path block coupled to the replicated memory array and ground.

[0076] The bias replication circuit is configured to maintain stable bit - line voltages and stable currents across processes and temperature variations in the main memory array, the current comparator is configured to compare the current from the bias replication circuit with a reference current, the oscillator is configured to generate a clock based on a signal from the current comparator, the phase generator is configured to generate a plurality of clock phases based on the clock, and the charge pump is configured to maintain an output voltage in response to the plurality of clock phases being generated. The cascode voltage generation circuit includes: an operational amplifier coupled to the bias replication circuit; and a transistor coupled to the operational amplifier and the plurality of sense amplifiers.

[0077] The operational amplifier includes: a first input coupled to a reference voltage; a second input coupled to the bias replication circuit; and an output coupled to the gate of the transistor. A first terminal of the transistor is coupled to the second input of the operational amplifier, and a second terminal of the transistor is coupled to the current mirror. The current mirror includes: a first transistor coupled between the second terminal of the transistor in the cascode voltage generation circuit and the supply voltage; and a second transistor coupled between the supply voltage and the current comparator, with the gate of the first transistor coupled to the gate of the second transistor. The current mirror further includes a transistor pair coupled to the cascode voltage generation circuit, the supply voltage, and the current comparator.

[0078] The replica memory array includes a plurality of replica memory cells coupled in a series-parallel configuration. The replica memory array may also include a plurality of active and inactive memory cells such that the active memory cells are coupled in parallel. The oscillator may be a resistor-capacitor oscillator, or may be a voltage-controlled oscillator, or may be any type of oscillator that can provide a stable clock frequency.

[0079] Embodiments of the present disclosure also include a method for generating a read voltage in a non-volatile memory circuit having a main memory array by: reading a stable current from a plurality of main memory cells in the main memory array, the reading including providing a word line voltage to the plurality of main memory cells, the providing including doubling a supply voltage using a charge pump, providing a floating gate voltage to a plurality of replica memory cells in a bias replica circuit using a resistor ladder; and generating a stable bit line voltage from a cascode voltage generation circuit coupled to the bias replica circuit.

[0080] The method for generating a stable bit line voltage includes: generating a cascode voltage in a cascode voltage generation circuit, activating a transistor, coupling a feedback voltage from the transistor to an operational amplifier, and comparing the feedback voltage with a reference voltage in the operational amplifier.

[0081] The method for generating a stable bit line voltage further includes: transmitting the stable bit line voltage to a plurality of sense amplifiers in the main memory array, and comparing a current from the bias replica circuit with a reference current in a current comparator coupled to the cascode voltage generation circuit. The method further includes: mirroring the current from the bias replica circuit in a current mirror, wherein the current mirror is coupled to the current comparator. The method further includes: generating a clock in an oscillator based on a signal from the current comparator, generating a plurality of clock phases in a phase generator in response to the clock from the oscillator, and maintaining an output voltage in a charge pump in response to the plurality of clock phases.

[0082] Embodiments of the present disclosure also include a method for generating a read voltage in a non-volatile memory having a main memory array by generating a stable bit line voltage from a cascode voltage generation circuit coupled to a bias replica circuit, generating the stable bit line includes: generating a cascode voltage in a cascode voltage generation circuit, activating a transistor, coupling a feedback voltage from the transistor to an operational amplifier, and comparing the feedback voltage with a reference voltage in the operational amplifier.

[0083] A method of generating a read voltage includes: reading a stable current from a plurality of main memory cells in a main memory array, the reading including providing a word line voltage to the plurality of main memory cells, the providing including: doubling a power supply voltage using a charge pump, and providing a floating gate voltage to a plurality of replica memory cells in a bias replica circuit using a resistor ladder. The method further includes: transmitting a cascode voltage to a plurality of sense amplifiers in the main memory array, and increasing or decreasing the cascode voltage in response to a current through a transistor.

[0084] Embodiments of the present disclosure also include a non-volatile memory circuit, the non-volatile memory circuit including: a main memory array, a plurality of sense amplifiers coupled to the main memory array, a bias replica circuit coupled to the main memory array, a cascode voltage generation circuit coupled to the plurality of sense amplifiers and the bias replica circuit, a current mirror, and a current comparator coupled to the current mirror. A capacitor is coupled to the current comparator and the bias replica circuit, and a feedback circuit is coupled to the capacitor and the main memory array. The bias replica circuit further includes a replica memory array, a replica column decoding block coupled to the replica memory array, and a source line path block coupled between the replica memory array and ground.

[0085] The cascode voltage generation circuit includes: an operational amplifier coupled to the bias replica circuit; and a transistor coupled to the operational amplifier and the plurality of sense amplifiers. The operational amplifier includes: a first input coupled to a reference voltage; a second input coupled to the bias replica circuit; and an output coupled to the gate of the transistor, wherein a first terminal of the transistor is coupled to the second input of the operational amplifier, and a second terminal of the transistor is coupled to the current mirror. The current mirror includes: a first transistor coupled between the second terminal of the transistor in the cascode voltage generation circuit and the power supply voltage; a second transistor coupled between the power supply voltage and a current source, and the gate of the first transistor is coupled to the gate of the second transistor. The current mirror includes a transistor pair coupled to the cascode voltage generation circuit, the power supply voltage, and the current source.

[0086] The bias replica circuit is configured to maintain a stable bit line voltage and a stable current across process and temperature variations in the main memory array, the current comparator is configured to compare a current from the bias replica circuit with a reference current, the capacitor is coupled to the replica memory array and is configured to maintain a floating gate voltage in response to a signal from the current comparator, and the feedback circuit is configured to maintain an output voltage in response to the floating gate voltage.

[0087] The feedback circuit includes: a resistor divider; a transistor coupled to a supply voltage; and an operational amplifier having a first input coupled to a floating gate voltage, a second input coupled to the resistor divider, and an output coupled to the transistor.

[0088] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned and / or listed in the application data sheet in this specification are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified if concepts from various patents, applications, and publications are required to provide yet further other embodiments.

[0089] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and equivalents of the full scope to which such claims are entitled. Thus, the claims are not limited by the disclosure.

Claims

1. A non-volatile memory circuit, comprising: a main memory array; a plurality of sense amplifiers coupled to the main memory array; a bias replica circuit coupled to the main memory array, wherein the bias replica circuit includes representations of components of the main memory array to replicate characteristics of the main memory array; a cascode voltage generating circuit coupled to the plurality of sense amplifiers and the bias replica circuit, wherein the cascode voltage generating circuit is coupled to the plurality of sense amplifiers via a cascode voltage generated by the cascode voltage generating circuit; a current mirror configured to mirror a current from the bias replica circuit; a current comparator configured to compare the mirrored current with a reference current; an oscillator coupled to the current comparator; a phase generator coupled to the oscillator; as well as A charge pump is coupled to the phase generator and the bias replica circuit.

2. The nonvolatile memory circuit of claim 1 further comprising a resistor divider coupled to the charge pump, the bias replica circuit, and the main memory array.

3. The nonvolatile memory circuit of claim 2 , wherein the bias replica circuit comprises: replicating a memory array; a replica column decoding block coupled to the replica memory array; as well as A source line routing block is coupled to the replica memory array and to ground.

4. The non-volatile memory circuit according to claim 3, wherein: The bias replica circuit is configured to maintain a stable bit line voltage and a stable current across process and temperature variations in the main memory array; The oscillator is configured to generate a clock based on a signal from the current comparator; The phase generator is configured to generate a plurality of clock phases based on the clock; as well as The charge pump is coupled to the replica memory array, the charge pump being configured to maintain an output voltage in response to the plurality of clock phases being generated.

5. The nonvolatile memory circuit according to claim 2, wherein the cascode voltage generating circuit comprises: an operational amplifier coupled to the bias replica circuit; as well as A transistor is coupled to the operational amplifier and the plurality of sense amplifiers.

6. The nonvolatile memory circuit of claim 5 , wherein the operational amplifier comprises: a first input coupled to a reference voltage; and a second input coupled to the bias replica circuit; and an output coupled to a gate of the transistor.

7. The non-volatile memory circuit of claim 6, wherein a first terminal of the transistor is coupled to the second input of the operational amplifier and a second terminal of the transistor is coupled to the current mirror.

8. The nonvolatile memory circuit of claim 7 , wherein the current mirror comprises: a first transistor coupled between the second terminal of the transistor of the cascode voltage generating circuit and a power supply voltage; as well as A second transistor is coupled between the power supply voltage and the oscillator, and a gate of the first transistor is coupled to a gate of the second transistor.

9. The nonvolatile memory circuit of claim 2, wherein the current mirror comprises a transistor pair coupled to the cascode voltage generating circuit, a supply voltage, and the oscillator.

10. The nonvolatile memory circuit of claim 3, wherein the replica memory array comprises a plurality of replica memory cells coupled in series and parallel combinations.

11. The nonvolatile memory circuit of claim 3, wherein the replica memory array comprises a plurality of active memory cells and inactive memory cells, the active memory cells being coupled in parallel.

12. The non-volatile memory circuit of claim 1, wherein the oscillator is a resistor-capacitor oscillator.

13. The non-volatile memory circuit of claim 1, wherein the oscillator is a voltage controlled oscillator.

14. A method of generating a voltage, comprising: A read voltage is generated in a nonvolatile memory having a main memory array by: Reading a stabilization current from a plurality of main memory cells in the main memory array, the reading comprising: Providing a word line voltage to the plurality of main memory cells, the providing comprising: multiplying a power supply voltage using a charge pump to generate the word line voltage; providing a floating gate voltage to a plurality of replica memory cells in a bias replica circuit using a resistor ladder coupled to the charge pump, wherein the plurality of replica memory cells replicate characteristics of the plurality of master memory cells; comparing a current from the bias replica circuit with a reference current in a current comparator; maintaining an output voltage in the charge pump based on a signal from the current comparator; and A stable bit line voltage is generated from a cascode voltage generating circuit coupled to the bias replica circuit.

15. The method of claim 14, wherein said generating said stable bit line voltage comprises: generating a cascode voltage in the cascode voltage generating circuit; Activate the transistor; coupling a feedback voltage from the transistor to an operational amplifier; as well as The feedback voltage is compared with a reference voltage in the operational amplifier.

16. The method according to claim 15, further comprising: transmitting the stable bit line voltage to a plurality of sense amplifiers in the main memory array; as well as The current comparator is coupled to the cascode voltage generating circuit.

17. The method according to claim 14, further comprising: The current from the bias replica circuit is mirrored in a current mirror, the current mirror coupled to a current source.

18. The method according to claim 14, further comprising: generating a clock in an oscillator based on the signal from the current comparator; generating a plurality of clock phases in a phase generator in response to the clock from the oscillator; as well as The output voltage in the charge pump is maintained in response to the plurality of clock phases.

19. A method of generating a voltage, comprising: A read voltage is generated in a nonvolatile memory having a main memory array by: Generating a stable bit line voltage from a cascode voltage generating circuit coupled to a bias replica circuit, wherein the bias replica circuit includes a representation of a component of the main memory array to replicate characteristics of the main memory array, the generating the stable bit line comprising: generating a cascode voltage in the cascode voltage generating circuit; activating a transistor by the cascode voltage, the transistor being coupled to the bias replica circuit; coupling a feedback voltage from the transistor to an operational amplifier; and The feedback voltage is compared with a reference voltage in the operational amplifier to generate the cascode voltage.

20. The method of claim 19, wherein generating the read voltage comprises: Reading a stabilization current from a plurality of main memory cells in the main memory array, the reading comprising: Providing a word line voltage to the plurality of main memory cells, the providing comprising: Using a charge pump to multiply the supply voltage; and A resistor ladder is used to provide floating gate voltages to a plurality of replica memory cells in a bias replica circuit.

21. The method of claim 19, further comprising: transmitting the cascode voltage to a plurality of sense amplifiers in the main memory array; as well as The cascode voltage is increased or decreased in response to current through the transistor.

22. A non-volatile memory circuit comprising: a main memory array; a plurality of sense amplifiers coupled to the main memory array; a bias replica circuit coupled to the main memory array, wherein the bias replica circuit includes representations of components of the main memory array to replicate characteristics of the main memory array; a cascode voltage generating circuit coupled to the plurality of sense amplifiers and the bias replica circuit, wherein the cascode voltage generating circuit is coupled to the plurality of sense amplifiers via a cascode voltage generated by the cascode voltage generating circuit; a current mirror configured to mirror a current from the bias replica circuit; a current comparator configured to compare the mirrored current with a reference current; a capacitor coupled to the current comparator and the bias replica circuit; as well as A feedback circuit is coupled to the capacitor and the main memory array.

23. The non-volatile memory circuit of claim 22, wherein the bias replica circuit comprises: replicating a memory array; a replica column decoding block coupled to the replica memory array; as well as A source line routing block is coupled between the replica memory array and ground.

24. The nonvolatile memory circuit of claim 22, wherein the cascode voltage generating circuit comprises: an operational amplifier coupled to the bias replica circuit; as well as A transistor is coupled to the operational amplifier and the plurality of sense amplifiers.

25. The non-volatile memory circuit of claim 24, wherein the operational amplifier comprises: a first input coupled to a reference voltage; and a second input coupled to the bias replica circuit; and an output coupled to a gate of the transistor.

26. The non-volatile memory circuit of claim 25, wherein a first terminal of the transistor is coupled to the second input of the operational amplifier and a second terminal of the transistor is coupled to the current mirror; and A current source is coupled to the current mirror.

27. The non-volatile memory circuit of claim 26, wherein the current mirror comprises: a first transistor coupled between the second terminal of the transistor of the cascode voltage generating circuit and a power supply voltage; as well as A second transistor is coupled between the power supply voltage and the current source, and a gate of the first transistor is coupled to a gate of the second transistor.

28. The non-volatile memory circuit of claim 22, wherein the current mirror comprises a transistor pair coupled to the cascode voltage generation circuit, a supply voltage, and the current comparator.

29. The non-volatile memory circuit of claim 23, wherein: The bias replica circuit is configured to maintain a stable bit line voltage and a stable current across process and temperature variations in a main memory array; the capacitor coupled to the replica memory array, the capacitor configured to maintain a floating gate voltage in response to a signal from the current comparator; as well as The feedback circuit is configured to maintain an output voltage in response to the floating gate voltage.

30. The non-volatile memory circuit of claim 29, wherein the feedback circuit comprises: Resistor voltage divider; a transistor, coupled to a supply voltage; as well as An operational amplifier has a first input coupled to the floating gate voltage, a second input coupled to the resistor divider, and an output coupled to the transistor.

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