A method for manufacturing a CMOS image sensor

Abstract

The application discloses a CMOS image sensor manufacturing method, which comprises the following steps: manufacturing a first hard mask layer on a substrate with a first conductive type, and opening a window on the first hard mask layer to form a trench with a first width; manufacturing a second hard mask layer with a second width in the trench, the first width is larger than the second width, and the second hard mask layer is completely located in the trench; doping the second hard mask layer with impurities with a second conductive type and then performing an etching process, so that the width of the second hard mask layer, i.e. the second width, is reduced; repeating the steps of doping the second hard mask layer with impurities and then performing an etching process until the second hard mask layer is completely etched, and a plurality of sub-photosensitive areas with the second conductive type and different doping concentrations and gradients are formed. The manufacturing of the multi-concentration gradient photosensitive area of the photodiode costs at most two mask plates, the manufacturing cost is greatly saved, the process flow is simple, and the method is suitable for industrial mass production.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and specifically relates to a method for fabricating a CMOS image sensor. Background Technology

[0002] With the continuous development of semiconductor technology and industry, the mainstream image sensor technology currently is CMOS image sensor technology, which is compatible with CMOS processes. Based on the characteristics of their pixel array reset and exposure control signals, CMOS image sensors are broadly classified into global shutter type and rolling shutter type. Global shutter type CMOS image sensors typically have control signals for simultaneous exposure and reset of all pixels in the pixel array; rolling shutter type CMOS image sensors intelligently perform unified exposure and reset control on pixels in the same row.

[0003] In recent years, the advantage of imaging high-speed moving objects has spurred the rapid development of global shutter CMOS image sensor technology. Currently, this technology mostly utilizes small pixel units, primarily because it allows for relatively complete transfer of photogenerated carriers, such as electrons, from the photodiode (PD) region to the storage region (SD) and reset region. Larger pixel units can achieve greater dynamic range and full-well capacity, capturing more image details; however, existing structures can only transport photogenerated carriers in the PD in one direction, while the transport speed in the other direction is slower, resulting in poor overall performance of large-pixel-unit global shutter CMOS image sensors.

[0004] Existing technologies have proposed a scheme to set different doping concentrations and depths in different regions within the photosensitive doped region of a photodiode, which can effectively solve the above-mentioned problems. However, the different doping concentration gradients formed in different regions complicate the fabrication process and increase the cost accordingly.

[0005] Therefore, it is necessary to provide a CMOS image sensor fabrication method that is simplified in manufacturing process, low in cost, and easy to implement. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the present invention proposes a method for manufacturing a CMOS image sensor, which has the advantages of simplified manufacturing process, low cost and easy implementation.

[0007] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0008] A method for fabricating a CMOS image sensor, comprising:

[0009] A first hard mask layer is fabricated on a substrate having a first conductivity type, and a window is made in the first hard mask layer to form a trench with a width of a first width t1.

[0010] A second hard mask layer with a width of the second width t2 is fabricated in the trench, the first width t1 is greater than the second width t2, and the second hard mask layer is completely located in the trench; in a preferred case, the distance between the first sidewall of the second hard mask layer and the first sidewall of the trench and the distance between the second sidewall of the second hard mask layer and the second sidewall of the trench are equal, that is, the centerline of the second hard mask layer coincides with the center of the trench;

[0011] The second hard mask layer is first doped with impurities of a second conductivity type and then etched to reduce the width of the second hard mask layer, i.e., the second width. The process of doping the second hard mask layer and then etching is repeated until the second hard mask layer is completely etched, forming multiple sub-photosensitive areas with different doping concentrations and gradients and of the second conductivity type. In a more preferred embodiment, the centerline of the second hard mask layer still coincides with the center of the trench during repeated etching processes. In some embodiments, the second hard mask layer is reduced by the same step size in each etching process.

[0012] A pinning layer with a first conductivity type is fabricated, and the first hard mask layer is removed to complete the fabrication of the photosensitive area of ​​the photodiode.

[0013] The present invention also relates to a CMOS image sensor, wherein the photodiode photosensitive area is fabricated by the above method.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] The CMOS image sensor manufacturing method provided by this invention requires a maximum of two photomasks to fabricate multi-concentration, gradient photosensitive areas of a photodiode, which greatly saves manufacturing costs and has a simple process that is suitable for mass production in industry. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 Cross-sectional views are shown after the first hard mask layer is etched and after the second hard mask layer is fabricated.

[0018] Figure 2 Figures (a)-(d) show cross-sectional views of one embodiment of the photosensitive area fabrication process;

[0019] Figure 3 A cross-sectional view of a completed CMOS image sensor (partial structure) is shown.

[0020] Reference numerals: 101-substrate; 103-photodiode photosensitive area; 103a-first sub-photosensitive area; 103b-second sub-photosensitive area; 103c-third sub-photosensitive area; 103d-fourth sub-photosensitive area; 104-pinning layer; 112-first hard mask layer; 113-second hard mask layer. Detailed Implementation

[0021] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Embodiments of the present invention relate to a method for fabricating a CMOS image sensor. More specifically, it relates to a method for fabricating a photosensitive area of ​​a photodiode in a CMOS image sensor. The photosensitive area has multiple sub-photosensitive areas with multiple concentration gradients. For example, the photosensitive area has multiple sub-photosensitive areas. In one embodiment, a first hard mask layer is first fabricated on a substrate having a first conductivity type, and then a second hard mask layer is fabricated in a trench formed by opening a window in the first hard mask layer. After the second hard mask layer is formed, the second hard mask layer is subjected to multiple doping etchings to form multiple sub-photosensitive areas with multiple concentration gradients. In one embodiment, the multiple doping etchings include repeatedly performing the step of first doping with an impurity having a second conductivity type and then etching. The doping concentration of the multiple dopings decreases from high to low, and the doping depth increases from shallow to deep.

[0023] Reference Figure 1 A cross-sectional view is shown after the formation of the first and second hard mask layers, wherein, Figure 1 (a) shows a cross-sectional view after the first hard mask layer has been fabricated. Figure 1 (b) shows a cross-sectional view after the second hard mask layer has been fabricated.

[0024] like Figure 1 As shown in (a), the fabrication process begins with providing a substrate 101. In one embodiment, the substrate may have a first conductivity type, for example, the substrate is a P-type silicon substrate. Other types of substrates may also be used. The substrate has an upper surface and a lower surface. For example, the upper surface refers to an active surface, and the lower surface refers to a passive surface.

[0025] In one embodiment, a first hard mask layer 112 is formed over a substrate. The first hard mask layer may be, for example, a SiN layer. Other types of first hard mask layers are also possible. The first hard mask layer can be formed by chemical vapor deposition or other methods. The first hard mask layer can be a single-layer structure or a multilayer structure composed of the same or different materials.

[0026] The trenches in the first hard mask layer can be formed using the first mask through photolithography, dry etching processes such as plasma etching, etc. Of course, other etching processes are also possible.

[0027] In one embodiment, a window is made in the first hard mask layer to form a trench with a width of a first width t1. The windowing process, for example, includes an etching process using an etching mask. The etching process includes laser etching, RIE etching, or other etching techniques. For example, the etching may use the upper surface of the substrate as the etching stop surface. The etching uses an etching mask to pattern the first hard mask layer to form an opening and then etches away the first hard mask layer, thereby forming a trench with a width of the first width t1 within the first hard mask layer. The trench sidewall profile is preferably vertical or substantially vertical. The width t1 of the trench can be determined according to the size of the photosensitive area of ​​the photodiode.

[0028] like Figure 1 As shown in (b), after the first hard mask layer is windowed, a second hard mask layer 113 is fabricated within the trench formed by the window. The second hard mask layer is located above the substrate 101. The second hard mask layer is made of a different material and / or has a different structure than the first hard mask layer. A different material is chosen to ensure that the first hard mask layer is not correspondingly etched when the second hard mask layer is etched. The structure of the second hard mask layer may be the same as or different from the structure of the first hard mask layer. The second hard mask layer is formed sequentially by methods including, but not limited to, deposition, photolithography, and etching.

[0029] The thickness of the second hard mask layer is determined by actual process requirements. It can be the same as or greater than the thickness of the first hard mask layer, but the thicknesses of both the first and second hard mask layers must be sufficient to block doping. The second width t2 of the second hard mask layer can be determined based on the size of the photosensitive area of ​​the photodiode. The second hard mask layer can be formed, for example, by dry etching using a second mask, such as plasma etching. Other etching processes are also possible. The etching is preferably perpendicular or substantially perpendicular to the sidewall contour of the second hard mask layer.

[0030] In one embodiment, the distances between the plurality of sidewalls of the second hard mask layer and the plurality of sidewalls of the first hard mask layer are equal, but the distances between the plurality of sidewalls of the second hard mask layer and the plurality of sidewalls of the first hard mask layer may also be different. For example, the first sidewall of the second hard mask layer has a first distance from the first sidewall of the first hard mask layer, and the second sidewall of the second hard mask layer has a second distance from the second sidewall of the first hard mask layer.

[0031] Figure 2 The process of etching the second hard mask layer to form a photosensitive area 103 is illustrated. In one embodiment, the photosensitive area includes a plurality of sub-photosensitive areas. The plurality of sub-photosensitive areas can be formed by etching after multiple doping of the second hard mask layer. In this embodiment, the doping depth of the multiple dopings is from shallow to deep, and the doping concentration is from high to low. In other embodiments, the concentration and depth of each doping can be determined according to actual needs. The schematic diagrams of doping depth and concentration in the accompanying drawings of this application are only for distinguishing between multiple etching and / or doping, and do not represent actual depth and concentration. In one embodiment, the etching first involves doping the substrate with an impurity of a second conductivity type before wet etching. The second conductivity type is different from the first conductivity type. Other etching methods are also possible. The etching forms vertical or substantially vertical sidewalls of the second hard mask layer.

[0032] In one embodiment, the second hard mask layer has a larger etch selectivity ratio than the first hard mask layer to control the loss of the upper surface and sidewalls of the first hard mask layer during the etching of the second hard mask layer, while ensuring that the width of the upper surface and sidewalls of the second hard mask layer gradually decreases. Preferably, the etch selectivity ratio is greater than 100:1. Other etch selectivity ratios that can protect the first hard mask layer while etching the second hard mask layer are also possible. Figure 2 As shown, the photodiode photosensitive area 103 includes a first sub-photosensitive area 103a, a second sub-photosensitive area 103b, a third sub-photosensitive area 103c, and a fourth sub-photosensitive area 103d.

[0033] Reference Figure 2 (a) An impurity of a second conductivity type is doped into a substrate 101 on which a first hard mask layer 112 is formed and a second hard mask layer 113 is spaced a third width from the first hard mask layer 112, thereby forming a first sub-photosensitive region 103a on the substrate surface toward the substrate interior. The second conductivity type is different from the first conductivity type. Other types of doped impurities may also be used. The doping has a first doping depth and a first doping concentration.

[0034] Reference Figure 2(b) Etching the second hard mask layer 113 to a distance of a fourth width from the first hard mask layer 112, and doping it with impurities of a second conductivity type, at which point both the first sub-photosensitive region 103a and the second sub-photosensitive region 103b are doped. The doping has a second doping depth and a second doping concentration. The second doping depth is deeper than the first doping depth, and the second doping concentration is lower than the first doping concentration.

[0035] Reference Figure 2 (c) The second hard mask layer 113 is etched to a distance of five widths from the first hard mask layer 112, and impurities of a second conductivity type are doped into the first sub-photosensitive region 103a, the second sub-photosensitive region 103b, and the third sub-photosensitive region 103c. At this time, the first sub-photosensitive region 103a is doped three times, the second sub-photosensitive region 103b is doped twice, and the third sub-photosensitive region 103c is doped once. The doping has a third doping depth and a third doping concentration. The third doping depth is deeper than the second doping depth, and the third doping concentration is lower than the second doping concentration.

[0036] Reference Figure 2 (d) The second hard mask layer 113 is etched until it is completely etched, and impurities of a second conductivity type are doped into the first sub-photosensitive region 103a, the second sub-photosensitive region 103b, the third sub-photosensitive region 103c, and the fourth sub-photosensitive region 103d. At this time, the first sub-photosensitive region 103a is doped four times, the second sub-photosensitive region 103b is doped three times, the third sub-photosensitive region 103c is doped twice, and the fourth sub-photosensitive region 103d is doped once. The doping has a fourth doping depth and a fourth doping concentration. The fourth doping depth is deeper than the third doping depth, and the fourth doping concentration is lower than the third doping concentration. For ease of explanation, as... Figure 2 As shown, this embodiment uses vertical injection for doping, but it is not limited to this method. The doping method can also be single-angle oblique injection or multi-angle oblique injection, etc.

[0037] Then, the first hard mask layer 112 is removed, and after high-temperature thermal annealing, a first sub-photosensitive area 103a, a second sub-photosensitive area 103b, a third sub-photosensitive area 103c, and a fourth sub-photosensitive area 103d are formed. In one embodiment, as... Figure 3 As shown, a pinning layer 104 with a first conductivity type is fabricated, and the first hard mask layer 112 is removed to complete the fabrication of the photodiode photosensitive area. After the photosensitive area is formed, the image sensor is fabricated using existing semiconductor CMOS technology. The fabrication method is not detailed here.

[0038] The fabrication method of the CMOS image sensor provided by this invention has been described in detail above. Specific examples have been used to illustrate the structure and working principle of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. A method for fabricating a CMOS image sensor, comprising: fabricating a first hard mask layer on a substrate having a first conductivity type, and opening a window in the first hard mask layer to form a trench having a first width; fabricating a second hard mask layer having a second width in the trench, the first width being greater than the second width, and the second hard mask layer being entirely within the trench, a center line of the second hard mask layer coinciding with a center line of the trench; implanting impurities having a second conductivity type in the substrate to form a first sub-photoreceptive region having a first doped depth region in a direction from a surface of the substrate to an interior of the substrate on the substrate having the first hard mask layer and the second hard mask layer spaced apart by a third width; etching the second hard mask layer to be spaced apart from the first hard mask layer by a fourth width, implanting impurities having the second conductivity type to form the first sub-photoreceptive region and a second sub-photoreceptive region having different doped concentrations and depth regions; etching the second hard mask layer to be spaced apart from the first hard mask layer by a fifth width, implanting impurities having the second conductivity type to form the first sub-photoreceptive region, the second sub-photoreceptive region, and a third sub-photoreceptive region having different doped concentrations and depth regions; etching the second hard mask layer to be completely etched, implanting impurities having the second conductivity type to form the first sub-photoreceptive region, the second sub-photoreceptive region, the third sub-photoreceptive region, and a fourth sub-photoreceptive region having different doped concentrations and depth regions, at this time the first sub-photoreceptive region being doped four times, the second sub-photoreceptive region being doped three times, the third sub-photoreceptive region being doped twice, and the fourth sub-photoreceptive region being doped once; fabricating a pinning layer having the first conductivity type, and removing the first hard mask layer to complete fabrication of a photodiode photoreceptive region.

2. The method of manufacturing a CMOS image sensor according to claim 1, wherein The first conductivity type and the second conductivity type are different.

3. The method for fabricating a CMOS image sensor according to any one of claims 1-2, the second hard mask layer being reduced by the same step in the etching process.

4. The method for fabricating a CMOS image sensor according to claim 1, the first hard mask layer being a single layer structure.

5. The method for fabricating a CMOS image sensor according to claim 1, the first hard mask layer being a multi-layer structure composed of the same material or different materials.

6. The method for fabricating a CMOS image sensor according to claim 4 or 5, the second hard mask layer being different from the first hard mask layer in material and / or structure.

7. The method for fabricating a CMOS image sensor according to claim 1, the second hard mask layer having a large etching selectivity ratio with the first hard mask layer to control loss of the first hard mask layer while etching the second hard mask layer.

8. The method for fabricating a CMOS image sensor according to claim 6, the etching selectivity ratio of the second hard mask layer to the first hard mask layer being 100:

1.

9. The method for fabricating a CMOS image sensor according to claim 1, the thickness of the second hard mask layer and the first hard mask layer being sufficient to form a doped barrier layer.

10. A CMOS image sensor, characterized by comprising: A photodiode photoreceptive region fabricated by any one of the methods of claims 1-9.

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