Graphene infrared detector based on back-illuminated CMOS process and preparation method

Abstract

The present invention discloses a method for preparing a graphene infrared detector based on a back-illuminated CMOS process, comprising: 1) forming a Si substrate using a back-illuminated CMOS process; 2) obtaining a single or multi-layer graphene; and 3) transferring the single-layer graphene to the Si substrate of step 1). The back-illuminated CMOS preparation process of the graphene infrared detector of the present invention separates the electrical components from the light, avoiding the absorption and reflection of light by the metal wiring layer, thereby achieving higher quantum efficiency and realizing higher-quality imaging. Graphene is used as a light-absorbing material. Due to its extremely high carrier mobility and wide-spectrum absorption in the infrared band, the graphene infrared light detector of the present invention has an extremely fast response speed and a full-band response bandwidth.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detection technology, and in particular to a graphene infrared detector based on a back-illuminated CMOS process and a preparation method thereof. Background Art

[0002] CMOS, a low-cost photosensitive element technology, has emerged as a key component in the digital imaging field. Currently, the majority of digital products on the market use CMOS as their photosensitive element. The CMOS manufacturing process, used in the production of photosensitive elements in digital imaging devices, transforms purely logical operations into receiving external light, converting it into electrical energy. The resulting image signal is then converted into a digital output via an internal analog-to-digital converter (A / D) on the chip. The photosensitive element was initially designed using the front-illuminated CMOS (FSI) process, which follows the semiconductor manufacturing process. For each pixel, light enters through the metal wiring on the front of the chip before being focused onto the photodiode in the photosensitive area. FSI offers sufficient performance for larger pixels. Because the ratio of the optical stack height to the pixel area is small, the photosensitive area is relatively large. Furthermore, FSI manufacturing is simple, resulting in low costs and high yields.

[0003] However, the inventors discovered that the prior art has at least the following technical problems:

[0004] As pixel size continues to shrink, small fill factors, long optical paths, and multi-layer metal wiring can partially block and reflect incident light, reducing the amount absorbed by the photodiode to 70% or less of the total incident light. Furthermore, this reflection can interfere with adjacent pixels, causing image distortion and further limiting sensor performance. Therefore, further adjustments and improvements to the CMOS process are needed.

[0005] Graphene has excellent optical, electrical, and mechanical properties and has important application prospects in materials science, micro-nano processing, energy, biomedicine, and drug delivery. Its carrier mobility at room temperature is approximately 15,000 cm 2 / (V•s), and possesses zero bandgap properties and excellent optical properties, with an absorptivity of approximately 2.3% over a wide wavelength range, making it well-suited for infrared detection. When infrared light strikes graphene, it generates high-energy photogenerated carriers. Under bias conditions, these photogenerated carriers, under the influence of an applied electric field, generate a current in the graphene-silicon heterojunction that is correlated with the infrared light intensity, enabling detection of infrared light signals. This infrared photocurrent, generated by the hot carrier effect, makes graphene highly effective in harvesting infrared light energy. Summary of the Invention

[0006] To address the challenges of existing technologies, the present invention proposes a method for fabricating a graphene infrared detector using a silicon substrate from a back-illuminated CMOS process. This method avoids the light absorption effects of the metal wiring layer produced by a front-illuminated CMOS process, enabling higher-quality imaging.

[0007] The present application provides a graphene infrared detector based on a back-illuminated CMOS process, comprising a silicon substrate layer, a supporting substrate, transistors and metal interconnect layers manufactured by a CMOS front-end process, and TSV vias; the transistors and metal interconnect layers manufactured by the CMOS front-end process are arranged between the bonded silicon substrate layer and the supporting substrate;

[0008] The transistor manufactured by the CMOS front-end process includes a silicon well disposed on the bottom surface of a silicon substrate layer, a source region and a drain region disposed on the silicon well, a gate disposed between the source region and the drain region, a buffer isolation layer deposited on the surfaces of the source region, the drain region, and the gate; a borophosphosilicate glass layer deposited on the surface of the buffer isolation layer, a metal insulator material layer deposited below the borophosphosilicate glass layer, and the metal interconnect layer distributed within the borophosphosilicate glass layer and the metal insulator material layer;

[0009] The metal interconnection layer includes several layers of contact holes filled with metal materials, the metal materials in the top two contact holes are connected to the drain region and the source region respectively, and the contact holes between two adjacent layers are connected through a metal aluminum layer;

[0010] The TSV through hole penetrates the silicon substrate layer, silicon well, buffer isolation layer, borophosphosilicate glass layer from top to bottom and reaches the surface of the metal aluminum layer. A second passivation layer is deposited on the surface of the TSV through hole.

[0011] The technical solution of the present invention is further defined as follows: an isolation trench is provided on the silicon substrate layer at the edge of the silicon well.

[0012] Preferably, a first passivation layer is provided between the supporting substrate layer and the metal-insulator material layer.

[0013] Preferably, a graphene layer is provided on top of the silicon substrate layer, and a top electrode is evaporated on the graphene layer.

[0014] The present invention also protects a method for preparing a graphene infrared detector based on a back-illuminated CMOS process, which is characterized by comprising the following steps:

[0015] 1) The silicon substrate is cleaned to remove surface particles and oxide impurities. Isolation trenches are then created using photolithography and inductively coupled plasma etching. A furnace liner oxidation treatment is then performed to prevent deposited ions from entering the transistor area. Finally, the isolation trenches are filled and chemically mechanically polished to remove excess oxide.

[0016] 2) Forming a silicon well on a silicon substrate by photolithography and high-energy ion implantation followed by annealing;

[0017] 3) Thermally grow a 2-10 nm gate oxide layer at 800°C, then deposit polysilicon as the gate. After the deposition is completed, perform gate photolithography, and then use reactive ion etching to etch away the excess polysilicon and gate silicon dioxide.

[0018] 4) Form source and drain regions on the silicon well through photolithography and ion implantation, and then deposit a buffer isolation layer on the drain, source, and gate surfaces using a self-aligned metal silicide process;

[0019] 5) Fabricate a metal interconnect layer on the prepared transistor area. Use CVD to deposit a borophosphosilicate glass layer and a metal insulator material layer. Use photolithography and inductively coupled plasma etching to create contact holes connected to the drain and source regions, respectively. Fill the contact holes with metal and smooth them. Then, deposit aluminum at the ends of the contact holes and etch to form a rectangular aluminum layer connected to the contact holes. Repeat this process to prepare as many metal interconnect layers as needed.

[0020] 6) Depositing silicon nitride and silicon carbide as a first passivation layer between the metal insulator material layer and the supporting substrate layer;

[0021] 7) Aligning and bonding the processed substrate material to the supporting substrate through wafer bonding, and performing back thinning;

[0022] 8) A TSV through-hole structure is formed on the back of the thinned wafer using photolithography and dry etching. A layer of aluminum is then deposited to connect the metal interconnect layer to the top to achieve effective deposition of the top photosensitive device. A second passivation layer is then deposited to complete the substrate package.

[0023] 9) removing the second passivation layer on the surface by inductively coupled plasma etching;

[0024] 10) Spin-coating the graphene grown on the copper mesh with polymethyl methacrylate and then etching the copper mesh in an ammonium persulfate solution. After 2 hours, the transparent graphene with polymethyl methacrylate is transferred to deionized water using a glass slide and rinsed multiple times. The graphene with polymethyl methacrylate is then transferred to the prepared silicon substrate surface and dried naturally in the shade. The graphene pixel units are then isolated using electron beam exposure and reactive ion etching to complete the transfer of the graphene layer.

[0025] 11) Electron beam exposure was used to define the electrode area on the surface of the graphene layer, and then Cr5nm / Au 45nm electrodes were evaporated by electron beam evaporation.

[0026] Preferably, in step 8), the TSV through-hole penetrates the silicon substrate layer, the silicon well, the buffer isolation layer, the borophosphosilicate glass layer and reaches the surface of the metal aluminum layer from top to bottom.

[0027] Preferably, in step 10), the graphene layer is a single layer, a double layer or a multilayer.

[0028] The technical solutions provided in the embodiments of this application have at least the following technical effects:

[0029] (1) The back-illuminated CMOS manufacturing process of the graphene infrared detector of the present invention separates the electrical components from the light, avoiding the absorption and reflection of light by the metal wiring layer, thereby obtaining higher quantum efficiency and achieving higher quality imaging.

[0030] (2) Graphene is used as the light-absorbing material. Due to its extremely high carrier mobility and wide-spectrum absorption in the infrared band, the graphene infrared light detector described in the present invention has an extremely fast response speed and a full-band response bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the structure of the graphene infrared detector according to an embodiment of the present invention, wherein Figure 1 (a) Main sectional view, Figure 1 (b) Figure 1 (a) Top view;

[0032] Figure 2 The figure is a schematic diagram of the process flow for preparing a graphene infrared detector according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present embodiment provides a method for preparing a graphene infrared detector based on a back-illuminated CMOS process, comprising the following steps: 1) forming a Si substrate using a back-illuminated CMOS process; 2) obtaining a single or multi-layer graphene; and 3) transferring the single or multi-layer graphene to the Si substrate of step 1). The process of step 1) is as follows:

[0034] (1) Based on the STI process, trench etching and lining oxidation are performed to produce oxide to prevent the deposited ions from entering the active area. Then, filling and chemical mechanical polishing are performed to remove excess filling.

[0035] (2) A well is formed by photolithography and ion implantation, and an oxide layer is formed thereon, and then a polysilicon gate is formed by photolithography and etching.

[0036] (3) A protective oxide layer is made on both sides of the polysilicon gate, and then a lightly doped source / drain process is performed. After that, a secondary isolation layer is made on both sides of the gate to solve the hot carrier injection problem, and finally ion implantation of the source / drain is performed.

[0037] (4) A nitride layer is formed on the transistor processed by the front-end process and then polished. Then, photolithography and etching are performed to form contact holes and metal contact layers. Finally, conductor metal is injected and passivation treatment is performed.

[0038] (5) After CMOS process, the substrate is aligned and bonded to the support wafer through wafer bonding, and the back is thinned.

[0039] (6) A TSV through-hole structure is formed on the back of the thinned wafer using photolithography and dry etching. A layer of metal aluminum is then deposited to connect the metal interconnect layer to the top to achieve effective deposition of the top photosensitive device. The second passivation layer is then deposited to complete the substrate packaging.

[0040] The light-sensing portion of this graphene infrared detector, built on a back-illuminated CMOS process, consists of a graphene layer and a Si substrate. The detection mechanism is that under bias conditions, infrared light irradiates the graphene, generating high-energy hot carriers. Under the influence of an applied electric field, a current related to the infrared light intensity is generated in the graphene-silicon heterojunction, enabling the detection of infrared light signals.

[0041] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0042] Example 1

[0043] like Figure 1 As shown, the graphene infrared detector structure of this embodiment includes a graphene layer 15, a support substrate 12, transistors and metal interconnect layers fabricated using a CMOS front-end process, and TSV vias 13. The entire structure is designed on a bonded CMOS substrate and support substrate 12. The back of the thinned CMOS substrate is covered with the graphene layer 15 and a top electrode 16 is formed. TSV vias 13 penetrate the entire top silicon layer.

[0044] The transistor manufactured using the CMOS front-end process includes a silicon well 3 disposed on the bottom surface of a silicon substrate layer 2, with a source region 4 and a drain region 5 disposed on the silicon well 3, a gate 6 disposed between the source region 4 and the drain region 5, and a buffer isolation layer 7 deposited on the surfaces of the source region 4, the drain region 5, and the gate 6; a borophosphosilicate glass layer 8 is deposited on the surface of the buffer isolation layer 7, a metal insulator material layer is deposited below the borophosphosilicate glass layer 8, and a metal interconnect layer is distributed between the borophosphosilicate glass layer 8 and the metal insulator material layer;

[0045] The metal interconnect layer includes several layers of contact holes 9 filled with metal material. The metal materials in the top two contact holes 9 are connected to the drain region 4 and the source region 5 respectively. The contact holes 9 between two adjacent layers are connected through the metal aluminum layer 10.

[0046] The TSV through hole 13 penetrates the silicon substrate layer 2 , the silicon well 3 , the buffer isolation layer 7 , the borophosphosilicate glass layer 8 from top to bottom and reaches the surface of the metal aluminum layer 10 . A second passivation layer 14 is deposited on the surface of the TSV through hole 13 .

[0047] An isolation trench 1 is provided on the silicon substrate layer 2 at the edge of the silicon well 3, with a graphene layer 15 on top. A top electrode 16 is evaporated on the graphene layer 15. The isolation trench 1 is used to separate adjacent transistors to prevent signal crosstalk.

[0048] A first passivation layer 11 is provided between the supporting substrate layer 12 and the metal-insulator material layer.

[0049] When the graphene infrared detector of this embodiment is working, a bias is applied to the graphene top electrode 16 and the built-in circuit. When infrared light is incident on the surface of the graphene layer 15, hot carriers with higher energy are generated in the body. Under the action of the external electric field, a current related to the infrared light intensity is generated in the graphene-silicon heterojunction, thereby realizing the detection of infrared light signals.

[0050] Figure 2 The following is a schematic diagram of the preparation process of the graphene infrared detector of this embodiment. The specific steps are:

[0051] (1) Figure 2 As shown in (a), the silicon substrate 2 is cleaned to remove surface particles and impurities such as oxides. An isolation trench 1 is then formed thereon by photolithography and inductively coupled plasma (ICP) etching. A liner oxidation treatment is then performed to prevent deposited ions from entering the transistor area. Finally, the isolation trench 1 is filled and chemically mechanically polished to remove excess oxides.

[0052] (2) Figure 2 As shown in (b), a silicon well 3 is formed on a silicon substrate 2 by photolithography and high-energy ion implantation followed by annealing;

[0053] (3) Figure 2 As shown in (c), a 2-10 nm gate oxide layer is thermally grown at 800°C, and then polysilicon is deposited as the gate 6. After the deposition is completed, the gate is photolithographically processed, and then the excess polysilicon and gate silicon dioxide are etched away using reactive ion etching (RIE).

[0054] (4) Figure 2 As shown in (d), a source region 4 and a drain region 5 are formed by photolithography and ion implantation, and then a buffer isolation layer 7 is deposited by a self-aligned metal silicide process;

[0055] (5) Figure 2 As shown in (e), a metal interconnect layer is formed above the prepared transistor area. Borophosphosilicate glass (BPSG) 8 is deposited by CVD to a thickness of approximately 1 μm. Contact holes 9 are formed by photolithography and inductively coupled plasma (ICP) etching. The photoresist is further cleaned and the polymer is etched. Metal filling and polishing are then performed. After that, aluminum is deposited and etched to form a rectangular aluminum layer 10 connected to the contact holes. This process is repeated to prepare a metal interconnect layer that meets the requirements.

[0056] (6) Figure 2 As shown in (f), a first passivation layer 11 is formed by depositing silicon nitride and silicon carbide for protection;

[0057] (7) Figure 2 As shown in (g), the processed substrate material is aligned and bonded to the supporting substrate 12 through wafer bonding, and the back is thinned;

[0058] (8) Figure 2 As shown in (h), a TSV through-hole 13 structure is formed on the back of the thinned wafer by photolithography and dry etching. Then, a layer of metal is deposited to connect the metal interconnect layer with the top to achieve effective deposition of the top photosensitive device. Then, a second passivation layer 14 is deposited to complete the substrate packaging.

[0059] (9) Figure 2 As shown in (i), the second passivation layer 14 on the surface is removed by inductively coupled plasma etching (ICP);

[0060] (10) Figure 2 As shown in (j), the graphene grown on the copper mesh is spin-coated with polymethyl methacrylate (PMMA) and then placed in an ammonium persulfate solution to etch the copper mesh. After about 2 hours, the transparent graphene with polymethyl methacrylate (PMMA) is transferred to deionized water using a glass slide and washed multiple times. The graphene with polymethyl methacrylate (PMMA) is then transferred to a prepared substrate and naturally dried in the shade. Electron beam exposure (EBL) and reactive ion etching (RIE) are then used to isolate the graphene pixel units, completing the transfer process of the graphene layer 15.

[0061] (11) Figure 2 As shown in (k), the electrode area is first defined by electron beam exposure (EBL), and then the electrode 16 of Cr 5nm / Au 45nm is evaporated by electron beam evaporation (EBE);

[0062] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements can be made without departing from the principles of the present invention. These improvements should also be regarded as the scope of protection of the present invention.

Claims

1. A graphene infrared detector based on a back-illuminated CMOS process, comprising a silicon substrate layer (2), a supporting substrate (12), a transistor and a metal interconnection layer manufactured by a CMOS front-end process, and a TSV through-hole (13); the transistor and the metal interconnection layer manufactured by the CMOS front-end process are arranged between the bonded silicon substrate layer (2) and the supporting substrate (12); The transistor manufactured by the CMOS front-end process includes a silicon well (3) arranged on the bottom surface of a silicon substrate layer (2), a source region (4) and a drain region (5) are arranged on the silicon well (3), a gate (6) is arranged between the source region (4) and the drain region (5), and a buffer isolation layer (7) is deposited on the surfaces of the source region (4), the drain region (5) and the gate (6); a borophosphosilicate glass layer (8) is deposited on the surface of the buffer isolation layer (7), a metal insulator material layer is deposited below the borophosphosilicate glass layer (8), and the metal interconnect layer is distributed within the borophosphosilicate glass layer (8) and the metal insulator material layer; The metal interconnection layer includes several layers of contact holes (9) filled with metal materials, the metal materials in the top two contact holes (9) are connected to the drain region (4) and the source region (5) respectively, and the contact holes (9) of two adjacent layers are connected through a metal aluminum layer (10); The TSV through hole (13) penetrates the silicon substrate layer (2), the silicon well (3), the buffer isolation layer (7), the boron phosphorus silicon glass layer (8) from top to bottom and reaches the surface of the metal aluminum layer (10), and a second passivation layer (14) is deposited on the surface of the TSV through hole (13).

2. The graphene infrared detector based on back-illuminated CMOS process according to claim 1, characterized in that: An isolation trench (1) is provided on the silicon substrate layer (2) at the edge of the silicon well (3).

3. The graphene infrared detector based on back-illuminated CMOS process according to claim 1, characterized in that: A first passivation layer (11) is provided between the supporting substrate layer (12) and the metal insulator material layer.

4. The graphene infrared detector based on back-illuminated CMOS process according to claim 1, characterized in that: A graphene layer (15) is provided on the top of the silicon substrate layer (2), and a top electrode (16) is evaporated on the graphene layer (15).

5. A method for preparing a graphene infrared detector based on a back-illuminated CMOS process, characterized in that: The following steps are involved: 1) The silicon substrate is cleaned to remove surface particles and oxide impurities. Isolation trenches are then created using photolithography and inductively coupled plasma etching. A furnace liner oxidation treatment is then performed to prevent deposited ions from entering the transistor area. Finally, the isolation trenches are filled and chemically mechanically polished to remove excess oxide. 2) Forming a silicon well on a silicon substrate by photolithography and high-energy ion implantation followed by annealing; 3) Thermally grow a 2-10 nm gate oxide layer at 800°C, then deposit polysilicon as the gate. After the deposition is completed, perform gate photolithography, and then use reactive ion etching to etch away the excess polysilicon and gate silicon dioxide. 4) Form source and drain regions on the silicon well through photolithography and ion implantation, and then deposit a buffer isolation layer on the drain, source, and gate surfaces using a self-aligned metal silicide process; 5) Fabricate a metal interconnect layer on the prepared transistor area. Use CVD to deposit a borophosphosilicate glass layer and a metal insulator material layer. Use photolithography and inductively coupled plasma etching to create contact holes connected to the drain and source regions, respectively. Fill the contact holes with metal and smooth them. Then, deposit aluminum at the ends of the contact holes and etch to form a rectangular aluminum layer connected to the contact holes. Repeat this process to prepare as many metal interconnect layers as needed. 6) Depositing silicon nitride and silicon carbide as a first passivation layer between the metal insulator material layer and the supporting substrate layer; 7) Aligning and bonding the processed substrate material to the supporting substrate through wafer bonding, and performing back thinning; 8) A TSV through-hole structure is formed on the back of the thinned wafer using photolithography and dry etching. A layer of aluminum is then deposited to connect the metal interconnect layer to the top to achieve effective deposition of the top photosensitive device. A second passivation layer is then deposited to complete the substrate package. 9) removing the second passivation layer on the surface by inductively coupled plasma etching; 10) Spin-coating the graphene grown on the copper mesh with polymethyl methacrylate and then etching the copper mesh in an ammonium persulfate solution. After 2 hours, the transparent graphene with polymethyl methacrylate is transferred to deionized water using a glass slide and rinsed multiple times. The graphene with polymethyl methacrylate is then transferred to the prepared silicon substrate surface and dried naturally in the shade. The graphene pixel units are then isolated using electron beam exposure and reactive ion etching to complete the transfer of the graphene layer. 11) Electron beam exposure was used to define the electrode area on the surface of the graphene layer, and then Cr5nm / Au 45nm electrodes were evaporated by electron beam evaporation.

6. The method for preparing a graphene infrared detector based on a back-illuminated CMOS process according to claim 5, characterized in that: In step 8), the TSV through hole penetrates the silicon substrate layer, silicon well, buffer isolation layer, borophosphosilicate glass layer and reaches the surface of the metal aluminum layer from top to bottom.

7. The method for preparing a graphene infrared detector based on a back-illuminated CMOS process according to claim 5, characterized in that: In step 10), the graphene layer is a single layer, a double layer or a multilayer.

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