Self-adaptive straight-through prevention double-N-type output driving circuit

Abstract

The invention discloses a self-adaptive direct connection prevention double-N-type output driving circuit which comprises a first control circuit, a second control circuit, an output driving stage upper tube, an output driving stage lower tube, a diode D1, a resistor R1 and a resistor R2. The output driving stage upper tube MN1 and the output driving stage lower tube MN2 are NMOS (N-channel metal oxide semiconductor) tubes; the first control circuit is used for controlling the output driving stage upper tube to be conducted when a first time sequence signal CLK is valid; and the second control circuit is used for controlling the output driving stage lower tube to be switched on in a time delay manner when the first time sequence signal CLK is invalid. In the invention, the switch-on time and the switch-off time of the two channels can be respectively controlled by adjusting the resistor R1 and the resistor R2, and an NMOS tube with higher carrier mobility is used as a pull-up tube, so that the current pull-up capability is stronger; and self-adaptive conduction of the output driving stage upper tube and the output driving stage lower tube is formed, so that the high-speed GaN power tube driver can be suitable for a high-speed GaN power tube driver.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of driving circuit, in particular to a self-adaptive anti-through double N-type output driving circuit. BACKGROUND

[0002] Please refer to Figure 1 In the traditional pull-gate shared output driving circuit (VDD is the power supply, VSS is the ground of the driving chip), the upper tube of the output driving stage is PMOS tube MP, and the lower tube of the output driving stage is NMOS tube MN. The drain of the PMOS tube MP and the drain of the NMOS tube MN are connected. The above-mentioned driving circuit structure adopts a single resistance structure, and the resistance Rg cannot be controlled separately for the turn-on time and the turn-off time. When the same driving resistance is used, the adverse effects on the turn-off channel (usually the driving circuit needs shorter turn-off time) cannot be controlled, and it is not suitable for driving GaN power tubes with lower threshold values (the threshold value of the GaN power tube is usually lower than that of the high-voltage MOS power tube).

[0003] Please refer to Figure 2 In the traditional independent pull-gate output driving circuit, the PMOS tube MP and the NMOS tube MN are respectively connected with the resistance Rg1 and the resistance Rg2 to form an independent pull-gate output driving circuit. Due to the different threshold values of the PMOS tube MP and the NMOS tube MN, the risk of the through connection of the output stage PMOS tube MP and the NMOS tube MN is extremely high, and the carrier mobility of the PMOS tube MP is lower than that of the NMOS tube MN, and the pull-up current capacity is weak. SUMMARY

[0004] In view of the above problems of the prior art, the technical problem to be solved by the present application is to provide a self-adaptive anti-through double N-type output driving circuit.

[0005] To solve the above technical problems, the present application provides the following technical solutions: The adaptive anti-direct connection double N-type output drive circuit comprises a first control circuit, a second control circuit, an output drive stage upper tube MN1, an output drive stage lower tube MN2, a diode D1, a resistor R1 and a resistor R2; the output drive stage upper tube MN1 and the output drive stage lower tube MN2 are both NMOS tubes; the first control circuit is connected with the gate of the output drive stage upper tube MN1, and is used for controlling the output drive stage upper tube MN1 to be turned on when the first timing signal CLK is effective; the second control circuit is connected with the gate of the output drive stage lower tube MN2, and is used for delaying the output drive stage lower tube MN2 to be turned on when the first timing signal CLK is ineffective; the drain of the output drive stage upper tube MN1 is connected with the power supply voltage VS, and the source is respectively connected with the positive terminal of the diode D1 and the first terminal of the resistor R1; the drain of the output drive stage lower tube MN2 is respectively connected with the negative terminal of the diode D1 and the first terminal of the resistor R2, and the source is grounded; the second terminals of the resistor R1 and the resistor R2 are mutually connected and used as the output end of the drive circuit.

[0006] Further, the first control circuit is further used for inhibiting the output drive stage upper tube MN1 to be turned on when the second output drive stage lower tube MN2 is turned on.

[0007] Further, the output drive circuit is used for driving a GaN power tube, and the second terminals of the resistor R1 and the resistor R2 are both connected with the gate of the GaN power tube.

[0008] Further, the first control circuit comprises: a capacitor C BOOST , and the lower plate of the capacitor C BOOST is connected with the positive terminal of the diode D1. a charging control unit, which is used for charging the upper plate of the capacitor C BOOST when the first timing signal CLK is ineffective in an initial state, pulling up the lower plate voltage of the capacitor C BOOST when the first timing signal CLK is converted from ineffective to effective, so that the upper plate voltage of the capacitor C BOOST is correspondingly increased to be higher than the power supply voltage VS, and lowering the lower plate voltage of the capacitor C BOOST when the first timing signal CLK is converted from effective to ineffective, so that the upper plate voltage of the capacitor C BOOST is correspondingly decreased to be less than or equal to the power supply voltage VS. a first switch unit, which is used for transmitting the upper plate voltage of the capacitor C BOOST to the gate of the output drive stage upper tube MN1 when the first timing signal CLK is effective, and disconnecting the path between the upper plate of the capacitor C BOOST and the gate of the output drive stage upper tube MN1 when the first timing signal CLK is ineffective; and The second switch unit is used for lowering the gate voltage of the upper transistor MN1 of the output driving stage to a low level when the first timing signal CLK is invalid.

[0009] Further, the charging control unit comprises a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4 and an NMOS transistor MN3; the source of the PMOS transistor MP1 is connected with a power supply voltage VS, the gate is connected with a second timing signal NCLK, and the drain is respectively connected with the lower plate of a capacitor C BOOST and the source of the NMOS transistor MN3; the second timing signal NCLK is the inverse signal of the first timing signal CLK; The drain of the PMOS transistor MP2 is connected with the power supply voltage VS, the gate is respectively connected with the drain of the NMOS transistor MN3 and the drain of the PMOS transistor MP3, and the source is respectively connected with the upper plate of the capacitor C BOOST , the source of the PMOS transistor MP3, the source of the PMOS transistor MP4 and the first end of the first switch unit; The gate of the PMOS transistor MP3 is respectively connected with the gate of the NMOS transistor MN3, the gate of the PMOS transistor MP4 and the second end of the first switch unit; and the drain of the PMOS transistor MP4 is connected with the gate of the upper transistor MN1 of the output driving stage.

[0010] Further, the first switch unit comprises a PMOS transistor MP5, a PMOS transistor MP6, a PMOS transistor PH3, an NMOS transistor NH1 and an NMOS transistor NH2; the source of the PMOS transistor MP5 and the source of the PMOS transistor MP6 are mutually connected and serve as the first end of the first switch unit; the gate of the PMOS transistor MP5 is respectively connected with the drain of the PMOS transistor MP6 and the drain of the NMOS transistor NH1; the drain of the PMOS transistor MP5 is respectively connected with the gate of the PMOS transistor MP6 and the source of the PMOS transistor PH3 and serves as the second end of the first switch unit; The gate of the NMOS transistor NH1 is connected with the second timing signal NCLK, and the source is grounded; the gate of the PMOS transistor PH3 is connected with the positive terminal of a diode D1, and the source is connected with the source of the NMOS transistor NH2; the gate of the NMOS transistor NH2 is connected with the first timing signal CLK, and the source is grounded.

[0011] Further, the PMOS transistor PH3 is a high-voltage PMOS transistor, and the NMOS transistor NH1 and the NMOS transistor NH2 are high-voltage NMOS transistors.

[0012] Further, the second switch unit is defined as an NMOS transistor NH3, the drain of the NMOS transistor NH3 is connected with the gate of the upper transistor MN1 of the output driving stage, the gate is connected with the second timing signal NCLK, and the source is grounded.

[0013] Further, the NMOS tube NH3 is a high-voltage NMOS tube.

[0014] Further, the second control circuit comprises a NOT gate INV and a delay unit Buffer; an input end of the NOT gate INV is connected with a first timing signal CLK, and an output end is used for outputting a second timing signal NCLK; an input end of the delay unit Buffer is connected with the second timing signal NCLK, and an output end is electrically connected with a gate of the lower tube MN2 of the output driving stage.

[0015] The application provides a self-adaptive anti-direct-through double-N-type independent pull-up and pull-down output driving circuit, compared with a traditional pull-up and pull-down shared output driving circuit, can adjust the driving resistors on respective channels to control the turn-on time and turn-off time respectively, avoid the adverse effects on the turn-off channel when using the same driving resistor, use NMOS tubes with greater carrier mobility as pull-up tubes, and has stronger pull-up current capacity; and through output feedback, the self-adaptive conduction of the pull-up tube and the pull-down tube is formed, while preventing the series connection, the positive feedback of the charge pump is introduced to accelerate, and the dead time of the double-NMOS tube output driving stage is kept extremely low, so that the driver can be applied to the high-speed GaN power tube. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the application without imposing undue limitation thereon. In the drawings: Figure 1 It is a structural schematic diagram of a traditional pull-up and pull-down shared output driving circuit.

[0017] Figure 2 It is a structural schematic diagram of a traditional independent pull-up and pull-down output driving circuit.

[0018] Figure 3 It is a circuit diagram of an embodiment of the self-adaptive anti-direct-through double-N-type output driving circuit.

[0019] Figure 4 It is a working state diagram in an initial state.

[0020] Figure 5 It is a working state diagram in an accelerated charge pump state.

[0021] Figure 6 It is a working state diagram in a signal flip state.

[0022] Figure 7 It is a driving transmission delay simulation diagram of the circuit of the embodiment.

[0023] Figure 8Simulation diagram of dead time and overlapping voltage of the double N-type drive tube at the rising edge of the potential of node ZN.

[0024] Figure 9 Simulation diagram of dead time and overlapping voltage of the double N-type drive tube at the rising edge of the potential of node ZN.

[0025] The description is shown in the following figures: first control circuit-1; second control circuit-2; first switch unit-11; second switch unit-12; charge control unit-13. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described below through specific concrete examples, and the figures provided in the following examples only schematically illustrate the basic concept of the present application, and the following examples and features in the examples can be combined with each other without conflict.

[0027] Please refer to Figure 3 , Figure 3 The figure is a circuit diagram of an adaptive anti-continuous double N-type output drive circuit according to an embodiment of the present application. The adaptive anti-continuous double N-type output drive circuit according to the embodiment includes a first control circuit 1, a second control circuit 2, an output drive stage upper tube MN1, an output drive stage lower tube MN2, a diode D1, a resistor R1 and a resistor R2; the output drive stage upper tube MN1 and the output drive stage lower tube MN2 are both NMOS tubes.

[0028] The first control circuit 1 is connected with the gate of the output drive stage upper tube MN1, and is used to control the output drive stage upper tube MN1 to be turned on when the first timing signal CLK is effective. Of course, in order to avoid the output drive stage upper tube MN1 and the output drive stage lower tube MN2 from being in a continuous state, the first control circuit 1 can also be used to inhibit the output drive stage upper tube MN1 from being turned on when the second output drive stage lower tube MN2 is turned on.

[0029] The second control circuit 2 is connected with the gate of the output drive stage lower tube MN2, and is used to delay the output drive stage lower tube MN2 to be turned on when the first timing signal CLK is not effective, so as to leave the time required for the output drive stage upper tube MN1 to be turned off, and make the output drive stage lower tube MN2 to be turned on after the output drive stage upper tube MN1 is turned off.

[0030] The drain of the upper transistor MN1 in the output driver stage is connected to the supply voltage VS (e.g., 5V), and its source is electrically connected to the positive terminal of diode D1 and the first terminal of resistor R1. The drain of the lower transistor MN2 in the output driver stage is electrically connected to the negative terminal of diode D1 and the first terminal of resistor R2, and its source is grounded. The second terminals of resistors R1 and R2 are electrically connected to each other and serve as the output terminal of the driver circuit. For example, the adaptive shoot-through-protected dual N-type output driver circuit of this embodiment can be used to drive GaN power transistors. In this case, the second terminals of resistors R1 and R2 are both electrically connected to the gate of the GaN power transistor.

[0031] In this embodiment, the first control circuit 1 includes a capacitor C. BOOST The charging control unit 13, the first switching unit 11, and the second switching unit 12. The capacitor C... BOOST The lower plate is electrically connected to the positive terminal of diode D1.

[0032] The charging control unit 13 is used to charge capacitor C when the first timing signal CLK is invalid in the initial state. BOOST The upper plate is charged, for example, to the capacitor C. BOOST The voltage of the upper plate reaches the supply voltage VS. The charging control unit 13 is also used to, when the first timing signal CLK changes from invalid to valid, charge capacitor C. BOOST The voltage across the lower plate is pulled up, thus causing capacitor C to... BOOST The voltage on the upper plate is correspondingly increased to be higher than the supply voltage VS, so as to turn on the upper transistor MN1 of the output driver stage. For example: in capacitor C BOOST When the voltage on the upper plate reaches the supply voltage VS, capacitor C... BOOST If the voltage across the lower plate is pulled up to equal the supply voltage VS, then the capacitor C BOOST The voltage on the upper plate increases accordingly to twice the supply voltage, i.e., 2VS. During this process, The voltage difference between the two plates, ΔV = VS, remains constant.

[0033] The charging control unit 13 is also used to, when the first timing signal CLK changes from valid to invalid, cause the capacitor C to... BOOST The voltage across the lower plate decreases, thus reducing the voltage across capacitor C. BOOST The voltage on the upper plate decreases accordingly to be less than or equal to the supply voltage VS. In this embodiment, when capacitor C... BOOST The lower electrode is pulled down to 0V by the NM2 and D1 pathways, resulting in When the voltage on the upper plate changes to VS, after the capacitor is fully charged to VS in the initial state, the voltage difference between the two plates is ΔV = VS.

[0034] The charging control unit 13 can include a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4 and an NMOS tube MN3; the PMOS tube MP1, the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 can adopt low-voltage PMOS tubes, and the NMOS tube MN3 can adopt a low-voltage NMOS tube.

[0035] The source of the PMOS tube MP1 is connected with a power supply voltage VS, the gate is connected with a second timing signal NCLK, and the drain is respectively connected with the lower plate of the capacitor C BOOST and the source of the NMOS tube MN3; the second timing signal NCLK is the inverse signal of the first timing signal CLK. The drain of the PMOS tube MP2 is connected with the power supply voltage VS, the gate is respectively connected with the drain of the NMOS tube MN3 and the drain of the PMOS tube MP3 to form a node C, and the source is respectively connected with the upper plate of the capacitor C BOOST , the source of the PMOS tube MP3, the source of the PMOS tube MP4 and the first end of the first switch unit 11. The gate of the PMOS tube MP3 is respectively connected with the gate of the NMOS tube MN3, the gate of the PMOS tube MP4 and the second end of the first switch unit 11 to form a node J; the drain of the PMOS tube MP4 is connected with the gate of the output driver stage upper tube MN1 to form a node Z.

[0036] The first switch unit 11 is used for transmitting the upper plate voltage of the capacitor C BOOST to the gate of the output driver stage upper tube MN1 when the first timing signal CLK is valid, so that the output driver stage upper tube MN1 is turned on; and disconnecting the path between the upper plate of the capacitor C BOOST and the gate of the output driver stage upper tube MN1 when the first timing signal CLK is invalid, so as to turn off the output driver stage upper tube MN1. The first switch unit 11 includes a PMOS tube MP5, a PMOS tube MP6, a PMOS tube PH3, an NMOS tube NH1 and an NMOS tube NH2; the PMOS tube PH3 is a high-voltage PMOS tube, and the NMOS tube NH1 and the NMOS tube NH2 are high-voltage NMOS tubes; the PMOS tube MP5 and the PMOS tube MP6 can adopt low-voltage PMOS tubes.

[0037] The source of the PMOS tube MP5 and the source of the PMOS tube MP6 are electrically connected to each other to serve as a first end of the first switch unit 11; the gate of the PMOS tube MP5 is electrically connected to the drain of the PMOS tube MP6 and the drain of the NMOS tube NH1 to form a node A; and the drain of the PMOS tube MP5 is electrically connected to the gate of the PMOS tube MP6 and the source of the PMOS tube PH3 to serve as a second end of the first switch unit 11. The gate of the NMOS tube NH1 is connected to the second timing signal NCLK, and the source is grounded. The gate of the PMOS tube PH3 is electrically connected to the positive terminal of the diode D1, and the source is electrically connected to the source of the NMOS tube NH2. The gate of the NMOS tube NH2 is connected to the first timing signal CLK, and the source is grounded.

[0038] The second switch unit 12 is used to lower the gate voltage of the output driver stage upper tube MN1 to a low level when the first timing signal CLK is invalid, so as to disconnect the output driver stage upper tube MN1. In the embodiment, the second switch unit 12 is defined as an NMOS tube NH3, which is a high-voltage NMOS tube. The drain of the NMOS tube NH3 is electrically connected to the gate of the output driver stage upper tube MN1, the gate is connected to the second timing signal NCLK, and the source is grounded.

[0039] The second control circuit 2 includes a NOT gate INV and a delay unit Buffer. The input end of the NOT gate INV is connected to the first timing signal CLK, and the output end is used to output the second timing signal NCLK. The input end of the delay unit Buffer is connected to the second timing signal NCLK, and the output end is electrically connected to the gate of the output driver stage lower tube MN2 to form a node ZN.

[0040] The embodiment has three working states, which are the initial state (first stage), the accelerated charge pump state (second stage) and the signal flip state (third stage), and the first timing signal CLK is high and valid and low and invalid.

[0041] Please refer to Figure 4 , which is the working state diagram of the initial state. In the initial state, the light-colored MOS tube represents that the MOS tube is in the on state. The specific working principle of the initial state is as follows: After power-on, the first timing signal CLK is low, and the second timing signal NCLK is high. At the node ZN of the second control circuit 2, the output driver stage lower tube MN2 is turned on, and the capacitor C BOOST is charged to the voltage OUT_R of the lower plate of the output driver stage lower tube MN2. Since the C point is initially 0, the MP2 is turned on, and the capacitor C BOOST is charged to the voltage BOOST of the upper plate, which is equal to the supply voltage VS.

[0042] At the same time, the second timing signal NCLK is high, turning on NMOS transistor NH1 and turning off NMOS transistor NH2. The voltage at node A is pulled low by NMOS transistor NH1, turning on PMOS transistor MP5, and the voltage at node J V... J =BOOST=VS (in the GaN drive circuit, "VS" ≈ 5V). Due to the voltage increase at point J, NMOS transistor MN3 turns on, while PMOS transistors MP3 and MP4 turn off. The conduction of MN3 creates positive feedback acceleration, increasing the voltage V at node C. C Further lower the clamp to "0" (i.e., V) C =OUT_R="0"), strengthens the conduction of PMOS transistor MP2 as capacitor C BOOST Charge.

[0043] In addition, NMOS transistor NH3 is turned on, and the voltage V at node Z is... Z =“0”, the upper transistor MN1 of the output driver stage remains off, and there will be no shoot-through. The gate potential of the GaN power transistor in the first stage is “0”.

[0044] Please see Figure 5 The diagram illustrates the operating state of the accelerated charge pump state. Light-colored MOSFETs indicate that they are initially on. The PMOS transistor PH3, with a color between dark and light, is on initially in the accelerated charge pump state and then off. The specific operating principle of the accelerated charge pump state is as follows: When the first timing signal CLK is high, the second timing signal NCLK is low, entering the accelerated charge pump state. At this time, NMOS transistor NH2 is turned on. Due to "OUT_R=0" in the previous stage, PMOS transistor PH3 is initially turned on in the second stage, and the potential of node J is pulled low (i.e., V). J The voltage is slightly below "VS", therefore PMOS transistor MP6 is turned on and PMOS transistor MP5 is turned off.

[0045] At this time, since the second timing signal NCLK is low, PMOS transistor MP1 is turned on, and the potential of the lower plate of the capacitor changes from "0" to "VS". The gate voltage of PMOS transistor PH3 rises accordingly, eventually causing PMOS transistor PH3 to turn off, keeping the potential of node J unchanged, and NMOS transistor NM3 to turn off. Simultaneously, the voltage BOOST on the upper plate of the capacitor changes from "VS" to "2VS", turning on PMOS transistor MP3 and causing PMOS transistor MP2 to turn off.

[0046] Because PMOS transistor MP4 is turned on, the potential of node Z is pulled up to "V" by the upper electrode of the capacitor. Z =BOOST=2VS”, which makes the upper transistor MN1 of the output driver stage fully conduct (i.e., its gate-source voltage V). GS1=VS=5V), further positive feedback to pull up the PH3 gate potential to VS, strengthen the PMOS PH3 off, ensure the potential of node J. Strengthen the conduction of PMOS MP4 at the same time, so that the gate-source voltage V GS4 about equal to "VS", to ensure that the low-voltage PMOS MP4 gate is not broken down. Further, the conduction of the output driver stage MN1, with PMOS MP1 together to charge the lower plate of the capacitor, forming a charge pump acceleration.

[0047] Since the conduction of the output driver stage MN1 is controlled by the charge pump, and the lower plate of the capacitor C BOOST connected to the output driver stage MN2 through the diode D1, if the output driver stage MN2 is on at this time, the lower plate of the capacitor C BOOST will not be pulled up from "0" to "VS" by PMOS MP1, affecting the second stage of the start, so as to restrict the output driver stage MN1 and the output driver stage MN2 at the same time, the structure forms a self-adaptive anti-through output drive.

[0048] The second stage output driver stage MN1 is the gate of the GaN power tube to provide pull-up current, pull up the gate potential of the GaN power tube for "VS" (usually 5V), so that the GaN fully conduct (GaN Vth in 1.2V around).

[0049] Please refer to Figure 6 , the working state diagram of the signal flip state, wherein the light-colored MOS tube indicates that the MOS tube is in the on state in the initial state. The specific working principle of the signal flip state is as follows: When the first timing signal CLK is converted from high level to low level, the second timing signal NCLK is converted from low level to high level, and enters the signal flip state. At this time, the NMOS NH3 is turned on, the potential of node Z is lowered, and the MN1 of the double N-type drive is turned off.

[0050] The NMOS NH1 is turned on, the potential of node A is lowered to make the PMOS MP5 conduct, and the PMOS MP6 is turned off (the PMOS MP6 and the PMOS MP5 are interlocked). Since the upper plate potential of the capacitor C BOOST is "2VS", the potential of node J will be pulled up very briefly at the moment of conduction of PMOS MP5, which will make NMOS MN3 pre-conduct, and PMOS MP3 and PMOS MP4 pre-off.

[0051] At the same time, due to the conduction of the output driver stage MN2, the lower plate potential of the capacitor C BOOST is rapidly lowered from "VS" to "0", which accelerates the conduction of NMOS MN3 and PMOS MP2. The capacitor CBOOST The lower plate potential of C will drop from "VS" to "0", C BOOST The upper plate potential of C will drop from "2VS" to "VS", and the PMOS MP2 is turned on, so the potential of node J will recover to the upper plate potential "VS" of C BOOST The gate-source voltage V GS4 of PMOS MP4 becomes "0", and PMOS MP4 is not turned on.

[0052] Due to the existence of the delay unit Buffer, the turn-on of NMOS NH3 will be earlier than the turn-on of the lower output driver MN2, which ensures that the potential of node Z is pulled down first, and the lower output driver MN2 is turned on only after the upper output driver MN1 is turned off, thereby preventing the double N-type drive-through of the upper output driver MN1 and the lower output driver MN2.

[0053] The third stage output driver MN2 provides a discharge current for the gate of the GaN power tube, and the gate potential of the GaN power tube is "0". Thereafter, the second stage and the third stage will be repeated to complete the next cycle.

[0054] It should be noted that the potentials in the present embodiment are all relative potentials compared with the ground potential. When the ground potential is not 0V, the actual potentials of the nodes are the sum of the relative potentials described in the present embodiment and the ground potential. For example, the structure of the present embodiment can also be used in GaN half-bridge driving. When applied to the upper half-bridge, the floating potential SW (i.e. the potential at the connection between the upper half-bridge and the lower half-bridge of the half-bridge driving. When the lower half-bridge is turned on, the floating potential SW is 0. When the upper half-bridge is turned on, the floating potential SW is the bus voltage) in the present embodiment is the ground potential. At this time, the actual potentials of the nodes are the sum of the potentials described in the present embodiment and the floating potential SW.

[0055] Please refer to Figure 7 , which is the driving transmission delay simulation diagram of the circuit in the present embodiment, from Figure 7 It can be seen that the driving transmission delay of the present embodiment is 1ns. Please refer to Figure 8 and Figure 9 , which are the dead time simulation diagram and the overlap voltage simulation diagram of the double N-type drive tubes, respectively, wherein Figure 8 the rising edge side of the potential of node Z, Figure 9 the rising edge side of the potential of node ZN, it can be seen that the dead time of the NM1 and NM2 drive tubes is very short.

[0056] The advantages of the present embodiment are as follows: (1) The turn-on time and the turn-off time can be controlled respectively by adjusting the driving resistances on the respective channels, thereby avoiding the adverse effects on the turn-off channel caused by using the same driving resistance.

[0057] (2) The NMOS tube with greater carrier mobility is used as the pull-up tube, and the pull-up current capacity is stronger.

[0058] (3) The conduction of the upper and lower driving tubes (i.e. the output driving stage upper tube MN1 and the output driving stage lower tube MN2) is mutually restricted, forming a self-adaptive anti-through output driver, avoiding the risk of driving output stage through, and the dead time of the output driving stage is very small, which is suitable for the driver of high-speed GaN power tube.

[0059] (4) The charging and discharging of the capacitor C BOOST by the output driving stage upper tube MN1 and the output driving stage lower tube MN2 is accelerated, which can effectively reduce the size of the charge pump charging tube (i.e. the PMOS tube MP1 and the PMOS tube MP2).

[0060] (5) In the three stages, the conduction is accelerated by positive feedback, and in the third stage, the conduction is accelerated by pre-conduction, which can realize the high-speed conduction of the output stage driving tube and reduce the dead time of the output stage.

[0061] The above embodiments only express the preferred embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as the limitation of the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An adaptive anti-shoot-through dual N-type output drive circuit, characterized in that: The circuit includes a first control circuit, a second control circuit, an upper output driver transistor MN1, a lower output driver transistor MN2, a diode D1, and resistors R1 and R2. Both the upper and lower output driver transistors MN1 and MN2 are NMOS transistors. The first control circuit is connected to the gate of the upper output driver transistor MN1 and is used to control MN1 to conduct when the first timing signal CLK is valid. The second control circuit is connected to the gate of the lower output driver transistor MN2 and is used to control MN2 to conduct after a delay when the first timing signal CLK is invalid. The drain of the upper output driver transistor MN1 is connected to the power supply voltage VS, and its source is electrically connected to the positive terminal of diode D1 and the first terminal of resistor R1. The drain of the lower output driver transistor MN2 is electrically connected to the negative terminal of diode D1 and the first terminal of resistor R2, and its source is grounded. The second terminals of resistors R1 and R2 are electrically connected to each other and serve as the output terminal of the drive circuit.

2. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 1, characterized in that: The first control circuit is also used to suppress the conduction of the upper transistor MN1 of the output driver stage when the lower transistor MN2 of the second output driver stage is turned on.

3. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 1, characterized in that: The output driving circuit is used to drive the GaN power transistor, and the second ends of resistors R1 and R2 are both electrically connected to the gate of the GaN power transistor.

4. The adaptive anti-shoo-through dual N-type output drive circuit as described in any one of claims 1 to 3, characterized in that, The first control circuit includes: Capacitor C BOOST The capacitor C BOOST The lower plate of the diode is electrically connected to the positive terminal of the diode D1. The charging control unit is used to charge capacitor C when the first timing signal CLK is invalid in the initial state. BOOST The upper plate is charged; when the first timing signal CLK changes from invalid to valid, capacitor C is charged. BOOST The voltage across the lower plate is pulled up, thus causing capacitor C to... BOOST The voltage on the upper plate rises accordingly to a level higher than the supply voltage VS; and when the first timing signal CLK changes from valid to invalid, the capacitor C... BOOST The voltage across the lower plate decreases, thus reducing the voltage across capacitor C. BOOST The voltage on the upper plate is correspondingly reduced to less than or equal to the supply voltage VS; The first switching unit is used to switch capacitor C when the first timing signal CLK is valid. BOOST The voltage of the upper plate is transmitted to the gate of the upper transistor MN1 in the output driver stage, and the capacitor C is disconnected when the first timing signal CLK is invalid. BOOST The path between the upper plate of the transistor and the gate of the upper transistor MN1 in the output drive stage; and The second switching unit is used to reduce the gate voltage of the upper transistor MN1 of the output driver stage to a low level when the first timing signal CLK is invalid.

5. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 4, characterized in that: The charging control unit includes PMOS transistors MP1, MP2, MP3, MP4, and NMOS transistor MN3; the source of PMOS transistor MP1 is connected to the power supply voltage VS, the gate is connected to the second timing signal NCLK, and the drain is connected to capacitor C. BOOST The lower plate of the transistor is electrically connected to the source of the NMOS transistor MN3; the second timing signal NCLK is the inverse of the first timing signal CLK. The drain of PMOS transistor MP2 is connected to the power supply voltage VS, and its gate is electrically connected to the drain of NMOS transistor MN3 and the drain of PMOS transistor MP3, respectively. Its source is connected to capacitor C. BOOST The upper plate, the source of PMOS transistor MP3, the source of PMOS transistor MP4, and the first terminal of the first switching unit are electrically connected. The gate of the PMOS transistor MP3 is electrically connected to the gate of the NMOS transistor MN3, the gate of the PMOS transistor MP4, and the second terminal of the first switching unit, respectively; the drain of the PMOS transistor MP4 is electrically connected to the gate of the upper transistor MN1 of the output driver stage.

6. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 5, characterized in that: The first switching unit includes PMOS transistors MP5, MP6, PH3, NMOS transistors NH1 and NH2; the source of PMOS transistor MP5 and the source of PMOS transistor MP6 are electrically connected to each other to serve as the first terminal of the first switching unit; the gate of PMOS transistor MP5 is electrically connected to the drain of PMOS transistor MP6 and the drain of NMOS transistor NH1; the drain of PMOS transistor MP5 is electrically connected to the gate of PMOS transistor MP6 and the source of PMOS transistor PH3 to serve as the second terminal of the first switching unit. The gate of the NMOS transistor NH1 is connected to the second timing signal NCLK, and its source is grounded; the gate of the PMOS transistor PH3 is electrically connected to the positive terminal of the diode D1, and its source is electrically connected to the source of the NMOS transistor NH2; the gate of the NMOS transistor NH2 is connected to the first timing signal CLK, and its source is grounded.

7. The adaptive anti-shoot-through dual N-type output drive circuit as described in claim 6, characterized in that: The PMOS transistor PH3 is a high-voltage PMOS transistor, and the NMOS transistors NH1 and NH2 are high-voltage NMOS transistors.

8. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 4, characterized in that: The second switching unit is defined as an NMOS transistor NH3. The drain of the NMOS transistor NH3 is electrically connected to the gate of the upper transistor MN1 of the output driver stage. The gate is connected to the second timing signal NCLK, and the source is grounded.

9. The adaptive anti-shoo-through dual N-type output drive circuit as described in claim 8, characterized in that: The NMOS transistor NH3 is a high-voltage NMOS transistor.

10. The adaptive anti-shoo-through dual N-type output drive circuit as described in any one of claims 1 to 3, characterized in that: The second control circuit includes an NOT gate INV and a delay unit Buffer; the input of the NOT gate INV is connected to the first timing signal CLK, and the output is used to output the second timing signal NCLK; the input of the delay unit Buffer is connected to the second timing signal NCLK, and the output is electrically connected to the gate of the lower transistor MN2 of the output driver stage.

Images