Hybrid film scheme for self-aligned contact

Abstract

A hybrid film scheme for self-aligned contact is disclosed. A method of forming a semiconductor device includes forming a fin that protrudes above a substrate; forming a metal gate over the fin, the metal gate being surrounded by a dielectric layer; etching the metal gate to lower a height of the metal gate, wherein, after the etching, a recess is formed over the metal gate and between gate spacers of the metal gate; lining sidewalls and a bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a mask layer over the metal gate, wherein a first opening of the mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source / drain region; and filling the second opening with a conductive material.

Description

Technical Field

[0001] This application relates generally to the field of semiconductor technology, and more specifically to hybrid film sheets for self-aligned contacts. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area.

[0003] FinFET devices are becoming increasingly common in integrated circuits. FinFET devices have a three-dimensional structure comprising semiconductor fins protruding from a substrate. A gate structure, configured to control the flow of charge carriers within the conductive channels of the FinFET device, surrounds the semiconductor fins. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming conductive channels on the three sides of the semiconductor fin. Summary of the Invention

[0004] According to one aspect of this application, a method of forming a semiconductor device is provided, the method comprising: forming a metal gate structure on a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below the upper surface of gate spacers extending along opposite sidewalls of the metal gate structure, wherein, after recessing, recesses are formed between the gate spacers; lining the sidewalls and bottom of the recesses with a semiconductor material; filling the recesses with a dielectric material after lining; forming a patterned etch stop layer stack on the dielectric material, the semiconductor material, and the ILD layer, wherein a first opening in the patterned etch stop layer stack is located directly above a first portion of the dielectric material, the semiconductor material, and the ILD layer adjacent to the gate spacers; forming a second opening in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, wherein the second opening exposes a source / drain region adjacent to the metal gate structure; and filling the second opening with a conductive material.

[0005] According to another aspect of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first metal gate structure over a fin; forming a second metal gate structure over the fin and adjacent to the first metal gate structure, wherein the first metal gate structure and the second metal gate structure are surrounded by an interlayer dielectric (ILD) layer; recessing the first metal gate structure and the second metal gate structure to form a first opening between first gate spacers and a second opening between second gate spacers, wherein the first gate spacers are located on opposite sidewalls of the first metal gate structure and the second gate spacers are located on opposite sidewalls of the second metal gate structure; conformally forming a semiconductor material along the sidewalls and bottom of the first opening and the sidewalls and bottom of the second opening; filling the first opening and the second opening by forming a dielectric material on the semiconductor material; and forming a self-aligned contact between the first metal gate structure and the second metal gate structure, wherein the self-aligned contact is electrically coupled to an underlying source / drain region between the first metal gate structure and the second metal gate structure.

[0006] According to another aspect of this application, a method of forming a semiconductor device is provided, the method comprising: forming a fin protruding above a substrate; forming a metal gate on the fin, wherein the metal gate is surrounded by a dielectric layer; etching the metal gate to reduce the height of the metal gate, wherein, after etching, a recess is formed on the metal gate and between gate spacers of the metal gate; lining the sidewalls and bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material on the semiconductor material; forming a patterned mask layer on the metal gate and the dielectric layer, wherein a first opening of the patterned mask layer is located directly above a portion of the dielectric layer adjacent to the metal gate; removing a portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening exposes an underlying source / drain region; and filling the second opening with a conductive material. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of a FinFET device according to some embodiments is shown.

[0009] Figure 2-6 , Figures 7A-7C and Figure 8-15 Various cross-sectional views of the FinFET device according to an embodiment are shown at various manufacturing stages.

[0010] Figure 16 A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact.

[0012] Furthermore, spatially related terms (e.g., "below," "under," "lower part," "above," "above," "top," "upper part," etc.) may be used herein to readily describe the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials(s) by the same or similar methods.

[0013] Embodiments of the present invention are discussed in the context of forming FinFET devices, and more specifically in the context of forming self-aligned contact plugs for FinFET devices. Although the disclosed embodiments have been discussed using FinFET devices as examples, the disclosed methods can also be used with other types of devices, such as planar devices.

[0014] In some embodiments, when forming self-aligned source / drain contacts, a hybrid film structure is formed over the metal gate structure and between the gate spacers of the metal gate structure to reduce the chopping effect. For example, the metal gate structure surrounded by an interlayer dielectric (ILD) layer is recessed to form recesses between gate spacers extending along the sidewalls of the metal gate structure. A semiconductor liner (e.g., a silicon liner) is conformally formed along the sidewalls and bottom of the recess, and a dielectric material (e.g., silicon nitride) is then formed on the semiconductor liner in the recess to fill the recess. The semiconductor liner and dielectric material in the recess are collectively referred to as the hybrid film structure. A mask layer is then formed over the ILD layer, wherein an opening in the mask layer is located directly above the hybrid film structure and a portion of the ILD layer disposed above the source / drain regions. An etching process is then performed using the mask layer as an etch mask to remove said portion of the ILD layer to form an opening in the ILD layer that exposes the underlying source / drain regions. Next, conductive material is formed within the opening to create self-aligned source / drain contacts. Because the hybrid film structure provides etch selectivity during the etching process that forms the opening, it reduces the subtraction effect, which in turn reduces device defects associated with short circuits caused by the subtraction effect.

[0015] Figure 1 An example of a FinFET 30 is shown in perspective. The FinFET 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on the opposite side of the fin 64, with the fin 64 protruding above the isolation region 62. A gate dielectric 66 runs along the sidewalls of the fin 64 and lies above the top surface of the fin 64, and a gate electrode 68 lies above the gate dielectric 66. A source / drain region 80 is located within the fin 64 and on the opposite side of the gate dielectric 66 and the gate electrode 68. Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section BB extends along the longitudinal axis of the gate electrode 68 of the FinFET 30. Cross section AA is perpendicular to cross section BB and runs along the longitudinal axis of the fin 64 in the direction of current flow, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and passes through the source / drain regions 80. These reference cross sections are referenced in subsequent figures for clarity.

[0016] Figure 2-6 , Figures 7A-7C and Figure 8-15 This is a cross-sectional view of a FinFET device 100 according to one embodiment at various manufacturing stages. The FinFET device 100 is similar to... Figure 1 It is a FinFET 30, but with multiple fins and multiple gate structures. Figure 2-5A cross-sectional view of the FinFET device 100 along section BB is shown. Figure 6 , Figure 7A and Figure 8-15 A cross-sectional view of the FinFET device 100 along section AA is shown. Figure 7B and Figure 7C A cross-sectional view of an embodiment of the FinFET device 100 along section CC is shown.

[0017] Figure 2 A cross-sectional view of substrate 50 is shown. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0018] refer to Figure 3 Using techniques such as photolithography and etching to Figure 2 The substrate 50 shown is patterned. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed on the substrate 50. The pad oxide layer 52 may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer 52 may act as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0019] Photolithography can be used to pattern the mask layer. Typically, photolithography utilizes a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, such as... Figure 3 As shown in the image.

[0020] The patterning mask 58 is then used to pattern the exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, such as... Figure 3 As shown in the figure. In some embodiments, the semiconductor fin 64 is formed by etching trenches in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic. In some embodiments, the trenches 61 can be stripes (viewed from top) that are parallel to each other and spaced apart from each other. In some embodiments, the trenches 61 can be continuous and surround the semiconductor fin 64. The semiconductor fin 64 may also be referred to as fin 64 hereinafter.

[0021] The fin 64 can be patterned using any suitable method. For example, the fin 64 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, a smaller pitch than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fin.

[0022] Figure 4 An insulating material is formed between adjacent semiconductor fins 64 to form an isolation region 62. The insulating material can be an oxide, such as silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials and / or other formation processes can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. A planarization process (e.g., chemical mechanical polishing (CMP)) can remove any excess insulating material and form the top surface of the coplanar (not shown) isolation region 62 and the top surface of the semiconductor fin 64. The patterned mask 58 (see also...) can also be removed by the planarization process. Figure 3 ).

[0023] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), located at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0024] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. Recessing the isolation region 62 causes the upper portion of the semiconductor fin 64 to protrude between adjacent STI regions 62. The top surface of the STI region 62 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish shape), or a combination thereof. The top surface of the STI region 62 can be formed as flat, convex, and / or concave by appropriate etching. An acceptable etching process (e.g., an etching process selective for the material of the isolation region 62) can be used to recess the isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) can be performed to recess the isolation region 62.

[0025] Figures 2 to 4 An embodiment of forming fin 64 is shown, but the fin can be formed in a variety of different processes. For example, the top of substrate 50 can be replaced with a suitable material, such as an epitaxial material suitable for the type of semiconductor device to be formed (e.g., N-type or P-type). The substrate 50 with epitaxial material on top is then patterned to form the semiconductor fin 64 containing the epitaxial material.

[0026] As another example, a dielectric layer can be formed on the top surface of the substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form fins.

[0027] In yet another example, the dielectric layer can be formed on the top surface of the substrate; trenches can be etched through the dielectric layer; the heteroepitaxial structure can be epitaxially grown in the trench using a material different from the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0028] In embodiments where one or more epitaxial materials or structures (e.g., heteroepitaxial or homoepitaxial structures) are grown, the grown material or structure may be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together. Furthermore, it is advantageous that the material epitaxially grown in the NMOS region differs from the material in the PMOS region. In various embodiments, fin 64 may comprise silicon-germanium (Si... x Ge 1-x (where x can be between 0 and 1), silicon carbide, pure germanium or essentially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0029] Figure 5 A dummy gate structure 75 is shown formed on a semiconductor fin 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed on the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, or a multilayer thereof, and may be obtained by deposition or thermal growth.

[0030] A gate layer is formed on top of a dielectric layer, and a mask layer is formed on top of the gate layer. The gate layer may be deposited on top of the dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited on top of the gate layer. The gate layer may be formed of, for example, polysilicon, but other materials may also be used. The mask layer may be formed of, for example, silicon nitride.

[0031] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 70. The pattern of mask 70 can then be transferred to the gate layer and dielectric layer using acceptable etching techniques to form gate electrode 68 and gate dielectric 66, respectively. Gate electrode 68 and gate dielectric 66 cover the corresponding channel regions of semiconductor fin 64. The longitudinal direction of gate electrode 68 can also be substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 64.

[0032] exist Figure 5In the example, the gate dielectric 66 is shown formed over the fin 64 (e.g., over the top surface and sidewalls of the fin 64) and over the STI region 62. In other embodiments, the gate dielectric 66 may be formed by thermal oxidation of, for example, the material of the fin 64, and thus may be formed over the fin 64 but not over the STI region 62. These and other variations are fully intended to be included within the scope of this disclosure.

[0033] Figure 6 , Figure 7A and Figure 8-15 A cross-sectional view of the FinFET device 100 further processed along section AA (along the longitudinal axis of fin 64) is shown. Note that in Figure 6 , Figure 7A and Figure 8 In this embodiment, three dummy gate structures 75 (e.g., 75A, 75B, and 75C) are formed on the fin 64. Those skilled in the art will understand that more or fewer than three gate structures may be formed on the fin 64, and these and other variations are fully intended to be included within the scope of this disclosure.

[0034] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in fin 64. LDD region 65 can be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask (e.g., a photoresist) to cover regions in the FinFET that will be protected from the plasma doping process. The plasma doping process can implant N-type or P-type impurities into fin 64 to form LDD region 65. For example, P-type impurities (e.g., boron) can be implanted into fin 64 to form LDD region 65 for P-type devices. As another example, N-type impurities such as phosphorus can be implanted into fin 64 to form LDD region 65 for N-type devices. In some embodiments, LDD region 65 is adjacent to the channel region of FinFET device 100. A portion of LDD region 65 may extend under gate electrode 68 and into the channel region of FinFET device 100. Figure 6 A non-limiting example of LDD region 65 is shown. Other configurations, shapes, and formation methods of LDD region 65 are also possible and are fully intended to be included within the scope of this disclosure. For example, LDD region 65 may be formed after the gate spacer 87 is formed. In some embodiments, LDD region 65 is omitted. For simplicity, LDD region 65 is not shown in the following figures, but it should be understood that LDD region 65 may be formed in fin 64.

[0035] Still referencing Figure 6After forming the LDD region 65, a gate spacer 87 is formed around the dummy gate structure 75. The gate spacer 87 may include a first gate spacer 72 and a second gate spacer 86. For example, the first gate spacer 72 may be a gate sealing spacer and is formed on the opposite side of the gate electrode 68 and the opposite side of the gate dielectric 66. The second gate spacer 86 is formed on the first gate spacer 72. The first gate spacer 72 may be formed of a nitride (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, etc.) or a combination thereof, and may be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. The second gate spacer 86 may be formed of silicon nitride, silicon carbonitride, or a combination thereof using a suitable deposition method. In one embodiment, the first gate spacer 72 is formed of silicon nitride, and the atomic ratio between silicon and nitrogen (e.g., the ratio between the atomic percentages of silicon and nitrogen) is between about 0.7 and about 1.3.

[0036] In one embodiment, the gate spacer 87 is formed by first conformally depositing a first gate spacer layer over the FinFET device 100, and then conformally depositing a second gate spacer layer over the deposited first gate spacer layer. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the second gate spacer layer disposed on the upper surface of the FinFET device 100 (e.g., the upper surface of the mask 70), while retaining a second portion of the second gate spacer layer disposed along the sidewalls of the gate structure. The remaining second portion of the second gate spacer layer after the anisotropic etching process forms the second gate spacer layer 86. The anisotropic etching process also removes portions of the first gate spacer layer disposed outside the sidewalls of the second gate spacer layer 86, and the remaining portion of the first gate spacer layer forms the first gate spacer layer 72.

[0037] like Figure 6 The shape and formation method of the gate spacer 87 shown are merely non-limiting examples, and other shapes and formation methods are also possible. These and other variations are fully intended to be included within the scope of this disclosure.

[0038] Next, in Figure 7A In the process, a recess is formed in the fin 64 and adjacent to the dummy gate structure 75, for example, between and / or near adjacent dummy gate structures 75. A source / drain region 80 is then formed in the recess. In some embodiments, the recess is formed by an anisotropic etching process, for example, using the dummy gate structure 75 and the gate spacer 87 as an etching mask, but any other suitable etching process may also be used.

[0039] Next, as Figure 7AAs shown, a source / drain region 80 is formed in the recess. The source / drain region 80 is formed by epitaxially growing material in the recess using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof.

[0040] like Figure 7A As shown, the epitaxial source / drain region 80 may have a surface that protrudes relative to the corresponding surface of the fin 64 (e.g., protrudes above the non-recessed upper surface 64U of the fin 64) and may have a facet. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see [reference]). Figure 7B In some embodiments, the source / drain regions 80 of adjacent fins 64 do not merge together, but remain independent source / drain regions 80 (see [link]). Figure 7C In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon-phosphorus (SiP), phosphorus-doped silicon-carbon (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and p-type impurities, such as boron or indium.

[0041] The epitaxial source / drain region 80 can be formed by implanting dopants, followed by an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the region of the FinFET device 100 to be protected from the implantation process. The impurity (e.g., dopant) concentration of the source / drain region 80 can be approximately 1E19 cm⁻¹. -3 Approximately 1E21 cm -3 Within the range. P-type impurities (e.g., boron or indium) can be implanted into the source / drain region 80 of the P-type transistor. N-type impurities (e.g., phosphorus or arsenide) can be implanted into the source / drain region 80 of the N-type transistor. In some embodiments, the epitaxial source / drain region can be doped in situ during growth.

[0042] Next, as Figure 8 As shown, in Figure 7A A contact etch stop layer (CESL) 89 is formed on the structure shown. CESL 89 serves as an etch stop layer in subsequent etch processes and may comprise suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed by suitable formation methods such as CVD, PVD, or combinations thereof.

[0043] Next, a first interlayer dielectric (ILD) 90 is formed over CESL 89 and dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), and can be deposited by any suitable method such as CVD, PECVD, or FCVD. A planarization process such as CMP can be performed to remove the mask 70 and the portion of CESL 89 disposed above the gate electrode 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0044] Next, in Figure 9 In this process, a post-gate process (sometimes called a replacement gate process) is performed to replace the gate electrode 68 and the gate dielectric material 66 with an active gate (also called a replacement gate or metal gate) and (one or more) active gate dielectric materials, respectively. Therefore, in the post-gate process, the gate electrode 68 and the gate dielectric 66 can be referred to as a dummy gate electrode and a dummy gate dielectric, respectively.

[0045] refer to Figure 9 The dummy gate structures 75A, 75B, and 75C were replaced with replacement gate structures 97A, 97B, and 97C, respectively (see [reference]). Figure 8 The replacement gate structure 97 (e.g., 97A, 97B, and 97C) may also be referred to as a metal gate structure. According to some embodiments, to form the replacement gate structure 97 (e.g., 97A, 97B, or 97C), the gate electrode 68 and the gate dielectric 66 located directly below the gate electrode 68 are removed in one or more etching steps, thereby forming recesses (not shown) between the gate spacers 87. Each recess exposes a channel region of a corresponding fin 64. During the removal of the dummy gate, the gate dielectric 66 can be used as an etch stop layer while etching the gate electrode 68. The gate dielectric 66 can then be removed after the removal of the gate electrode 68.

[0046] Next, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99 are formed in the recess for replacing the gate structure 97. The gate dielectric layer 94 is conformally deposited in the recess, for example, on the top surface and sidewalls of the fin 64, on the sidewalls of the gate spacer 87, and on the top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or multiples thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. Methods for forming the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0047] Next, a barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may include a conductive material, such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc., may also be used alternatively. The barrier layer 96 may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering, metal-organic chemical vapor deposition (MOCVD), or ALD may be used instead.

[0048] Next, in some embodiments, a work function layer 98, such as a P-type work function layer or an N-type work function layer, may be formed in the recess and over the barrier layer 96 prior to the formation of the gate 99. Exemplary P-type work function metals that may be included in the gate structure of a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure of an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value to achieve a target threshold voltage Vt in the device to be formed. One or more work function layers may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0049] Next, a seed layer (not shown) is conformally formed on the work function layer 98. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, the seed layer may include a titanium layer and a copper layer situated on top of the titanium layer.

[0050] Next, a gate electrode 99 is deposited on the seed layer and fills the remaining portion of the recess. The gate electrode 99 can be made of a metal-containing material, such as Cu, Al, W, combinations thereof, or multiples thereof, and can be formed by, for example, electroplating, electroless plating, or other suitable methods. After forming the gate electrode 99, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 located on the top surface of the first ILD 90. The resulting remaining portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 thus form the replacement gate structure 97 of the resulting FinFET device 100.

[0051] Next reference Figure 10 An etch stop layer 105 is formed (e.g., selectively) on the upper surface of the first ILD 90. The etch stop layer 105 can be a suitable dielectric material, such as silicon nitride or silicon oxynitride formed on the upper surface of the first ILD 90 by, for example, CVD, ALD, or combinations thereof. For example, a patterned mask layer can be formed to cover the replacement gate structure 97 and the gate spacer 87, thus exposing the first ILD 90, and then the etch stop layer 105 is formed over the exposed first ILD 90. After the etch stop layer 105 is formed, the patterned mask layer is removed. As another example, the upper layer of the first ILD 90 can be converted into the etch stop layer 105, for example, by using a nitriding process with a nitrogen-containing gas or nitrogen-containing plasma.

[0052] Next, the replacement gate structure 97 is recessed to form recesses 103 between the respective gate spacers 87. In some embodiments, a metal gate etch-back process is performed to remove the upper portion of the replacement gate structure 97, and thus, recesses 103 are formed between the gate spacers 87 after the metal gate etch-back process. A suitable etching process (e.g., dry etching, wet etching, or a combination thereof) can be performed as a metal gate etch-back process.

[0053] Still referencing Figure 10 After forming the recess 103, a capping layer 101 is formed on the recessed replacement gate structure 97. In some embodiments, the capping layer 101 is formed from a conductive material (e.g., tungsten) using a suitable deposition method (e.g., ALD, CVD, PVD, etc.). Figure 10In the example of, the cap layer 101 extends continuously along the upper surface of the replacement gate structure 97 from the inner sidewall of one gate spacer 87 to the opposite inner sidewall of the corresponding gate spacer 87. In other words, in the illustrated embodiment, the cap layer 101 completely covers the upper surface of the replacement gate structure 97. In some embodiments, the cap layer 101 is omitted.

[0054] Next, in Figure 11 , the recess 103 is filled with the hybrid film 108. As Figure 11 shown in, the semiconductor material 107 (also referred to as a semiconductor liner) is conformally formed along the sidewalls and bottom of the recess 103 and along the upper surface of the etch stop layer 105. Next, a dielectric material 109 is formed over the semiconductor material 107 to fill the recess 103. The dielectric material 109 may also be formed outside the recess 103, over the portions of the semiconductor material 107 that are between the replacement gate structures 97. The semiconductor material 107 and the dielectric material 109 are collectively referred to as the hybrid film 108.

[0055] In an exemplary embodiment, the semiconductor material 107 is amorphous silicon (a-Si), which is formed by a suitable deposition process (e.g., LPCVD, PECVD, ALD, etc.) using a silicon-containing process gas (e.g., SiH4, Si2H6, SiH2Cl2, combinations thereof, etc.). The flow rate of the process gas can be between about 50 standard cubic centimeters per minute (sccm) and about 1000 sccm. The pressure of the deposition process can be between about 0.1 Torr and about 10 Torr, and the temperature of the deposition process can be between about 300 °C and about 500 °C. In one embodiment, the thickness T of the semiconductor material 107 is between about 0.3 nm and about 5 nm (e.g., 0.3 nm < T < 5 nm). In one embodiment, the atomic percentage (at%) of hydrogen in the semiconductor material 107 is less than about 15 at% (e.g., H < 15 at%). In the discussion herein, the conformal semiconductor material 107 may also be referred to as a silicon liner, but it should be understood that other suitable materials may be used as the semiconductor material 107.

[0056] In an exemplary embodiment, the dielectric material 109 is silicon nitride formed by a suitable formation method such as ALD, PECVD, LPCVD, etc. The atomic ratio of silicon to nitrogen (e.g., Si:N atomic ratio) in the dielectric material 109 is between about 0.7 and about 1.3. Besides silicon nitride (e.g., SiN), other suitable dielectric materials (e.g., silicon carbide nitride (SiCN), silicon oxynitride (SiCON), and silicon oxycarbonate (SiCO)) may also be used as the dielectric material 109. In some embodiments, the dielectric material 109 is selected as one or more materials different from the gate spacer 87 to provide etch selectivity in subsequent etch processes, such as the etch process forming the opening 121 (see [link to relevant documentation]). Figure 13 ).

[0057] The deposited semiconductor material 107 may (or may not) include some crystalline structure, such as a polycrystalline structure, which includes grains. Some grains may be interconnected, while others may be embedded in an amorphous structure. For example, copper in the gate electrode 99 can diffuse upwards along the grain boundaries into the subsequently formed overlay. Therefore, to reduce upward diffusion of copper, a processing step (also known as an amorphization process) is performed after the semiconductor material 107 is deposited to convert the polycrystalline structure (if present) in the semiconductor material 107 into an amorphous structure, making the entire semiconductor material 107 amorphous. Since the amorphous semiconductor material 107 has no grain boundaries, it has a better ability to prevent copper diffusion through. In some embodiments, this processing step is performed after the formation of the semiconductor material 107 and before the formation of the dielectric material 109.

[0058] According to some embodiments, a process gas including NH3, N2, or a combination thereof is used to perform a processing process (e.g., a plasma process) on the deposited semiconductor material 107. Other gases, such as argon, may also be added. During the processing, the semiconductor material 107 is bombarded. The bombardment disrupts the crystal structure. Furthermore, if the process gas (e.g., NH3) contains hydrogen and nitrogen atoms, hydrogen and nitrogen may be added to the semiconductor material 107. Therefore, as a result of the processing, the semiconductor material 107 is doped with hydrogen. According to some embodiments, after the amorphization process, the percentage of hydrogen atoms in the semiconductor material 107 is between about 0.5 at% and about 10 at%.

[0059] According to some embodiments, this process is or includes plasma processing, which may be a direct plasma process, wherein plasma is generated in the same processing chamber as the FinFET device 100. The plasma processing is performed using high-frequency radio frequency (HFRF) power (e.g., approximately 13.56 MHz) and low-frequency radio frequency (LFRF) power (e.g., approximately 350 kHz). The HFRF power is used to ionize and generate plasma, and the LFRF power is used to bombard the semiconductor material 107 for amorphization purposes. According to some embodiments of this disclosure, the HFRF power is in the range of approximately 50 watts to approximately 2000 watts.

[0060] The LFRF power is selected within a suitable range. If the LFRF power is too low (e.g., below about 90 watts), the amorphization process may be ineffective. If the LFRF power is too high (e.g., above about 135 watts), severe plasma-induced damage may occur to the layers / structures beneath the semiconductor material 107. According to some embodiments of this disclosure, the LFRF power is selected in the range of about 90 watts to about 135 watts to avoid the aforementioned problems.

[0061] Next, in Figure 12 In this process, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor material 107 and the dielectric material 109 located on the upper surface of the first ILD 90. Figure 12 As shown, the planarization process also removes the top of the etch stop layer 105 and the gate spacer 87. After the planarization process, the remaining portions of the semiconductor material 107 and the dielectric material 109 (displaced between the respective gate spacers 87) are referred to as the hybrid film structure 108.

[0062] Next, a second ILD 111 is formed over the first ILD 90, the gate spacer 87, and the hybrid film structure 108. The second ILD 111 can be formed from the same or similar materials using the same or similar formation method as the first ILD 90, therefore details are not repeated. The second ILD 111 can be used as an etch stop layer in subsequent etch processes.

[0063] Next, an etch stop layer stack 112 is formed on top of the second ILD 111, and the etch stop layer stack 112 is patterned to have openings 120 in the etch stop layer stack 112. In some embodiments, the etch stop layer stack 112 includes a plurality of layers (also referred to as sublayers), wherein each of the plurality of layers is formed of a different material. Figure 12In the example, the etch stop layer stack 112 includes a first layer 113, a second layer 115, and a third layer 117 sequentially formed over the second ILD 111. The first layer 113 is formed of tungsten-doped carbide (WDC, also known as tungsten-doped silicon carbide), the second layer 115 is formed of oxide (e.g., silicon oxide), and the third layer 117 is formed of silicon (e.g., Si). Different material combinations of the sublayers of the etch stop layer stack 112 are used to provide, for example, the formation of... Figure 13 The target level of etching selectivity for subsequent etching processes of opening 121 in the middle.

[0064] Next, the etch stop layer stack 112 is patterned to form an opening 120 in the etch stop layer stack 112. For example, a patterned mask layer 119 (e.g., a patterned photoresist layer) is formed on the etch stop layer stack 112, and then the patterned mask layer 119 is used as an etch mask to perform an anisotropic etch process to pattern the patterned mask layer 119. Figure 12 The number and location of the openings 120 are merely non-limiting examples. Those skilled in the art will readily understand that other numbers of openings 120 can be formed at other locations. In some embodiments, the anisotropic etching process includes multiple etching steps, each using a different etchant to selectively remove sublayers of the etch stop layer stack 112. The anisotropic etching process can be stopped when the second ILD 111 is exposed. The patterned mask layer 119 (e.g., a patterned photoresist layer) can be removed after the openings 120 are formed (e.g., via an ashing process).

[0065] Next, in Figure 13 In this process, an etching process is performed to remove portions of the second ILD 111 and the first ILD 90 located below the opening 120. Following this etching process, an opening 121 is formed in the first ILD 90, exposing the underlying source / drain region 80. For example, the depth D1 of the opening 121 can be between approximately 20 nm and approximately 80 nm. This etching process can be any suitable etching process, such as dry etching (e.g., plasma etching), wet etching, combinations thereof, etc. The etching process can use an etchant that is selective (e.g., has a higher etch rate) to the materials (e.g., oxides) of the first ILD 90 and the second ILD 111, such that the first ILD 90 and the second ILD 111 are removed without substantially damaging other layers of the FinFET device 100. For example, an etchant using C... x F y, etching processes such as H2, Ar, their combinations, etc. are used to remove the exposed portions of the first ILD 90 and the second ILD 111. In some embodiments, after the etching process for removing the exposed portions of the first ILD 90 and the second ILD 111, another etching process using an etchant selective to the material of the CESL 89 is performed to remove the CESL 89 exposed by the opening 121 and expose the source / drain regions 80. Note that the portions of the first ILD 90 / second ILD 111 located below the opening 120 are completely removed to prepare for the formation of self-aligned contacts (SAC) 123 (see Figure 14 ).

[0066] In some embodiments, the etching process for forming the opening 121 also removes Figure 12 the top of the gate spacer 87 and the top of the hybrid film structure 108 located below the opening 120. However, due to its unique structure, dimensions (e.g., 0.3 nm < T < 5 nm), and material composition (e.g., atomic percentage of H < 15 at%, and atomic ratio of Si:N between 0.7 and 1.3), the hybrid film structure 108 provides good etching selectivity in the etching process for forming the opening 121, such that the hybrid film structure 108 is etched at a slower rate than the gate spacer 87. In other words, the etching process for forming the opening 121 causes the hybrid film structure 108 to be recessed less than the gate spacer 87. In Figure 13 an example, after the etching process is completed, the upper surface 87U of the gate spacer 87 is skewed (e.g., tilted). For example, there is an offset D2 between the uppermost edge of the upper surface 87U (which may be flush with the upper surface of the hybrid film structure 108) and the lowermost edge of the upper surface 87U. The offset D2 may be, for example, 10 nm or less. The unintended removal (e.g., etching) of the hybrid film structure 108 and the gate spacer 87 is referred to as the etchback effect.

[0067] This disclosure significantly reduces the attenuation effect by using a hybrid film structure 108, thereby reducing product defects associated with the attenuation effect. To understand the advantages of this disclosure, consider a reference design in which the hybrid film structure 108 is replaced by a single layer of dielectric material (e.g., silicon nitride). In other words, in the reference design, a single silicon nitride layer is formed over the replacement gate structure 97 and fills the space between the respective gate spacers 87. The attenuation effect removes a significant portion of the single silicon nitride layer and the gate spacers 87. In subsequent processes where the opening 121 is filled with a conductive material to form the self-aligned contact 123, the conductive material can fill the space left by the removal of the single silicon nitride layer and the gate spacers 87, which can lead to short circuits (e.g., unintended electrical connections) between the replacement gate structure 97 and the source / drain regions 80 or between the source / drain regions 80 on the opposite side of the replacement gate structure 97. This disclosure avoids or reduces short-circuit defects caused by the attenuation effect. The currently disclosed structure and method have been implemented and tested in production, and the measurement results have confirmed that the short-circuit defects caused by the reduction effect have been reduced by four orders of magnitude.

[0068] Next, in Figure 14 In the process, a conductive material is formed in the opening 121 to fill it. The conductive material can be copper, cobalt, tungsten, a combination thereof, etc., and can be formed by suitable formation methods such as PVD, CVD, PECVD, ALD, etc. Next, a planarization process such as CMP is performed to remove the etch stop layer stack 112 and the second ILD 111. The remaining portion of the conductive material in the opening 121 forms a self-aligned contact 123. Figure 14 As shown, after the planarization process, the first ILD90, the hybrid film structure 108, the gate spacer 87, and the self-aligned contact 123 have coplanar surfaces.

[0069] Next, in Figure 15 In this embodiment, an interconnect structure 148 is formed on the first ILD 90 to interconnect underlying electrical components (e.g., FinFETs) to form a functional circuit. The interconnect structure 148 includes multiple dielectric layers (e.g., 125, 129, 133) and conductive features (e.g., 141, 143, 145, 147) formed in a plurality of dielectric layers. Note that in this description, unless otherwise specified, conductive features and conductive materials refer to conductive characteristics and conductive materials, respectively.

[0070] The dielectric layers 125 / 129 / 133 can also be referred to as intermetallic dielectric (IMD) layers. IMD layers 125 / 129 / 133 can be formed from one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations of these materials, etc. IMD layers 125 / 129 / 133 can be formed by processes such as chemical vapor deposition (CVD), but any suitable process can be used. Etch stop layers 127 and 131 can be formed between adjacent IMD layers. Etch stop layers 127 and 131 can be formed from silicon nitride using PECVD, but other dielectric materials such as nitrides, carbides, borides, combinations thereof, etc., and alternative techniques for forming etch stop layers, such as LPCVD, PVD, etc., can also be used.

[0071] exist Figure 15 In this configuration, the gate contact 141 is formed to extend through the IMD layer 125, the dielectric material 109, and the semiconductor material 107 to be electrically coupled to the replacement gate structure 97, for example, through the cap layer 101. Figure 15 In the example, the lower surface of the gate contact 141 substantially contacts and extends along the upper surface of the lower cap layer 101. Furthermore, the source / drain contact 143 is formed to extend through the IMD layer 125 to be electrically coupled to the self-aligned contact 123. Figure 15 The conductive lines 145 and vias 147 formed in IMD layers 129 and 133, respectively, are further illustrated. The gate contact 141, source / drain contact 143, conductive lines 145, and vias 147 are formed of one or more conductive materials (e.g., copper, tungsten, cobalt) and can be formed using any suitable method, such as damascene, dual damascene, etc. Note that the number and location of conductive features in the interconnect structure 148 are for illustrative purposes only and are not intended to be limiting. Other conductive features may be formed at other locations. Furthermore, some of the formed conductive features may not be present in other locations. Figure 15 In the cross section, therefore in Figure 15 Invisible (e.g., displayed).

[0072] Figure 16 A flowchart of a method 1000 for forming a semiconductor device according to some embodiments is shown. It should be understood that... Figure 16 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 16 The various steps are shown.

[0073] refer to Figure 16In block 1010, a metal gate structure is formed over a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer. In block 1020, the metal gate structure is recessed below the upper surface of gate spacers extending along opposite sidewalls of the metal gate structure, wherein a recess is formed between the gate spacers after the recess. In block 1030, the sidewalls and bottom of the recess are lined with a semiconductor material. In block 1040, after lining, the recess is filled with a dielectric material. In block 1050, a patterned etch stop layer stack is formed over the dielectric material, semiconductor material, and ILD layer, wherein a first opening in the patterned etch stop layer stack is located directly above a first portion of the dielectric material, semiconductor material, and ILD layer adjacent to the gate spacers. In block 1060, a second opening is formed in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, wherein the second opening exposes the source / drain regions adjacent to the metal gate structure. In box 1070, fill the second opening with conductive material.

[0074] The embodiments can achieve advantages. For example, the disclosed structures and methods reduce the attenuation effect, thereby preventing or reducing device defects caused by short circuits due to the attenuation effect. Measurement results have confirmed that by using the disclosed structures and methods, the defect rate caused by the attenuation effect in production has been reduced by four orders of magnitude.

[0075] According to one embodiment, a method of forming a semiconductor device includes: forming a metal gate structure on a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below the upper surface of gate spacers extending along opposite sidewalls of the metal gate structure, wherein, after the recess is made, recesses are formed between the gate spacers; lining the sidewalls and bottom of the recesses with a semiconductor material; after the lining is made, filling the recesses with a dielectric material; forming a patterned etch stop layer stack on the dielectric material, the semiconductor material, and the ILD layer, wherein a first opening in the patterned etch stop layer stack is located directly above a first portion of the dielectric material, the semiconductor material, and the ILD layer adjacent to the gate spacers; forming a second opening in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, wherein the second opening exposes a source / drain region adjacent to the metal gate structure; and filling the second opening with a conductive material. In one embodiment, the semiconductor material is amorphous silicon. In one embodiment, the dielectric material is silicon nitride. In one embodiment, the method further includes selectively forming an etch stop layer on the upper surface of the ILD layer away from the semiconductor fin before recessing the metal gate structure, wherein a first portion of the semiconductor material contacts the etch stop layer and extends along the etch stop layer. In one embodiment, the method further includes performing a planarization process after filling the recess and before forming the patterned etch stop layer stack, wherein the planarization process removes the first portion of the semiconductor material and the etch stop layer. In one embodiment, the method further includes forming a capping layer on the metal gate structure after recessing and before lining, wherein the capping layer substantially contacts the metal gate structure and the semiconductor material. In one embodiment, forming the second opening includes performing an etching process to remove the first portion of the ILD layer, wherein the etching process recesses the gate spacer more than the dielectric material and the semiconductor material. In one embodiment, forming the patterned etch stop layer stack includes: forming the etch stop layer stack by sequentially forming a first sublayer, a second sublayer, and a third sublayer on the ILD layer, wherein the first sublayer, the second sublayer, and the third sublayer comprise different materials; forming a patterned mask layer on the etch stop layer stack; and using the patterned mask layer as an etch mask to pattern the etch stop layer stack. In one embodiment, the first sublayer is formed of tungsten-doped silicon carbide, the second sublayer is formed of silicon oxide, and the third sublayer is formed of silicon.In one embodiment, the method further includes: after filling the second opening: removing the patterned etch stop layer stack; forming an inter-metal dielectric (IMD) layer on the ILD layer; and forming a first via and a second via extending through the IMD layer, wherein the first via further extends through the dielectric material and the semiconductor material and is electrically coupled to the metal gate structure, wherein the second via is electrically coupled to the conductive material.

[0076] According to one embodiment, a method of forming a semiconductor device includes: forming a first metal gate structure over a fin; forming a second metal gate structure over the fin and adjacent to the first metal gate structure, wherein the first metal gate structure and the second metal gate structure are surrounded by an interlayer dielectric (ILD) layer; recessing the first metal gate structure and the second metal gate structure to form a first opening between first gate spacers and a second opening between the second gate spacers, wherein the first gate spacers are located on opposite sidewalls of the first metal gate structure and the second gate spacers are located on opposite sidewalls of the second metal gate structure; conformally forming a semiconductor material along the sidewalls and bottom of the first opening and the sidewalls and bottom of the second opening; filling the first opening and the second opening by forming a dielectric material on the semiconductor material; and forming a self-aligned contact between the first metal gate structure and the second metal gate structure, wherein the self-aligned contact is electrically coupled to an underlying source / drain region between the first metal gate structure and the second metal gate structure. In one embodiment, forming the self-aligned contact includes, after filling the first opening and the second opening, performing the following operations: forming an etch stop layer stack over the ILD layer, wherein the etch stop layer stack includes a plurality of layers, each of which is formed of a different material; forming a first opening in the etch stop layer stack and over the first metal gate structure and over a first portion of the ILD layer between the first metal gate structure and the second metal gate structure; removing the first portion of the ILD layer to form a second opening in the ILD layer, wherein the second opening exposes the underlying source / drain region; and filling the second opening with a conductive material, wherein the conductive material extends continuously from the first metal gate structure to the second metal gate structure. In one embodiment, forming the etch stop layer stack includes: forming a first layer of tungsten-doped silicon carbide over the ILD layer; forming a second layer of silicon oxide over the first layer; and forming a third layer of silicon over the second layer. In one embodiment, the semiconductor material is amorphous silicon, and the dielectric material is silicon nitride. In one embodiment, the method further includes forming a conductive capping layer on the first metal gate structure and the second metal gate structure after the recess is made and before the semiconductor material is conformally formed. In one embodiment, the conductive material contacts and extends along the upper surface of the conductive capping layer away from the fin.

[0077] According to one embodiment, a method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a metal gate over the fin, wherein the metal gate is surrounded by a dielectric layer; etching the metal gate to reduce the height of the metal gate, wherein, after the etching, a recess is formed over the metal gate and between gate spacers of the metal gate; lining the sidewalls and bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a patterned mask layer over the metal gate and the dielectric layer, wherein a first opening of the patterned mask layer is located directly above a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening exposes an underlying source / drain region; and filling the second opening with a conductive material. In one embodiment, the semiconductor material is amorphous silicon, and the dielectric material is silicon nitride. In one embodiment, the method further includes: selectively forming a capping layer on the metal gate after etching and before lining. In one embodiment, the second opening exposes the sidewall of the gate spacer.

[0078] Here are some examples.

[0079] Example 1. A method of forming a semiconductor device, the method comprising:

[0080] A metal gate structure is formed on a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer.

[0081] The metal gate structure is recessed below the upper surface of the gate spacers, which extend along opposite sidewalls of the metal gate structure, wherein, after the recess is made, recesses are formed between the gate spacers.

[0082] The sidewalls and bottom of the recess are lined with a semiconductor material;

[0083] After the lining is applied, the recess is filled with a dielectric material;

[0084] A patterned etch stop layer stack is formed on the dielectric material, the semiconductor material, and the ILD layer, wherein a first opening in the patterned etch stop layer stack is located directly above a first portion of the dielectric material, the semiconductor material, and the ILD layer adjacent to the gate spacer;

[0085] A second opening is formed in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, wherein the second opening exposes the source / drain region adjacent to the metal gate structure; and

[0086] The second opening is filled with a conductive material.

[0087] Example 2. The method according to Example 1, wherein the semiconductor material is amorphous silicon.

[0088] Example 3. The method according to Example 2, wherein the dielectric material is silicon nitride.

[0089] Example 4. The method according to Example 1 further includes: selectively forming an etch stop layer on the upper surface of the ILD layer away from the semiconductor fin before recessing the metal gate structure, wherein a first portion of the semiconductor material contacts the etch stop layer and extends along the etch stop layer.

[0090] Example 5. The method according to Example 4 further includes: performing a planarization process after filling the recess and before forming the patterned etch stop layer stack, wherein the planarization process removes the first portion of the semiconductor material and the etch stop layer.

[0091] Example 6. The method according to Example 1 further includes: forming a capping layer over the metal gate structure after the recess is made and before the lining is made, wherein the capping layer substantially contacts the metal gate structure and the semiconductor material.

[0092] Example 7. The method according to Example 1, wherein forming the second opening comprises: performing an etching process to remove the first portion of the ILD layer, wherein the etching process causes the gate spacer to be recessed more than the dielectric material and the semiconductor material.

[0093] Example 8. The method according to Example 1, wherein forming the patterned etch stop layer stack comprises:

[0094] An etch stop layer stack is formed by sequentially forming a first sublayer, a second sublayer, and a third sublayer on the ILD layer, wherein the first sublayer, the second sublayer, and the third sublayer comprise different materials;

[0095] A patterned mask layer is formed on top of the etch stop layer stack; and

[0096] The patterned mask layer is used as an etch mask to pattern the etch stop layer stack.

[0097] Example 9. The method according to Example 8, wherein the first sublayer is formed of tungsten-doped silicon carbide, the second sublayer is formed of silicon oxide, and the third sublayer is formed of silicon.

[0098] Example 10. The method according to Example 1 further includes: after filling the second opening, performing the following operations:

[0099] Remove the patterned etch stop layer stack;

[0100] An intermetallic dielectric (IMD) layer is formed on top of the ILD layer; and

[0101] A first via and a second via are formed extending through the IMD layer, wherein the first via further extends through the dielectric material and the semiconductor material and is electrically coupled to the metal gate structure, and wherein the second via is electrically coupled to the conductive material.

[0102] Example 11. A method of forming a semiconductor device, the method comprising:

[0103] A first metal gate structure is formed on the fin;

[0104] A second metal gate structure is formed on the fin and adjacent to the first metal gate structure, wherein the first metal gate structure and the second metal gate structure are surrounded by an interlayer dielectric (ILD) layer.

[0105] The first metal gate structure and the second metal gate structure are recessed to form a first opening between the first gate spacers and a second opening between the second gate spacers, wherein the first gate spacers are located on opposite sidewalls of the first metal gate structure and the second gate spacers are located on opposite sidewalls of the second metal gate structure.

[0106] Semiconductor material is conformally formed along the sidewalls and bottom of the first opening and the sidewalls and bottom of the second opening;

[0107] The first opening and the second opening are filled by forming a dielectric material on the semiconductor material; and

[0108] A self-aligned contact is formed between the first metal gate structure and the second metal gate structure, wherein the self-aligned contact is electrically coupled to the lower source / drain region between the first metal gate structure and the second metal gate structure.

[0109] Example 12. The method according to Example 11, wherein forming the self-aligned contact comprises: after filling the first opening and the second opening, performing the following operations:

[0110] An etch stop layer stack is formed on top of the ILD layer, wherein the etch stop layer stack comprises multiple layers, each of which is formed of a different material;

[0111] A first opening is formed in the etch stop layer and above the first metal gate structure and on the first portion of the ILD layer between the first metal gate structure and the second metal gate structure;

[0112] The first portion of the ILD layer is removed to form a second opening in the ILD layer, wherein the second opening exposes the underlying source / drain region; and

[0113] The second opening is filled with a conductive material, wherein the conductive material extends continuously from the first gate spacer to the second gate spacer.

[0114] Example 13. The method according to Example 12, wherein forming the etch stop layer stack comprises:

[0115] A first layer of tungsten-doped silicon carbide is formed on top of the ILD layer;

[0116] A second layer of silicon oxide is formed on top of the first layer; and

[0117] A third layer of silicon is formed on top of the second layer.

[0118] Example 14. The method according to Example 11, wherein the semiconductor material is amorphous silicon and the dielectric material is silicon nitride.

[0119] Example 15. The method according to Example 11 further includes: forming a conductive capping layer on the first metal gate structure and the second metal gate structure after the recess is made and before the semiconductor material is conformally formed.

[0120] Example 16. The method according to Example 15, wherein the gate contact contacts the upper surface of the conductive cap layer away from the fin and extends along the upper surface.

[0121] Example 17. A method of forming a semiconductor device, the method comprising:

[0122] Forming fins that protrude above the substrate;

[0123] A metal gate is formed on the fin, wherein the metal gate is surrounded by a dielectric layer;

[0124] The metal gate is etched to reduce the height of the metal gate, wherein, after the etching is performed, a recess is formed on the metal gate and between the gate spacers of the metal gate;

[0125] The sidewalls and bottom of the recess are lined with a semiconductor material;

[0126] The recess is filled by forming a dielectric material on the semiconductor material;

[0127] A patterned mask layer is formed over the metal gate and the dielectric layer, wherein a first opening of the patterned mask layer is located directly above a portion of the dielectric layer adjacent to the metal gate;

[0128] Removing a portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening exposes the underlying source / drain region; and

[0129] The second opening is filled with a conductive material.

[0130] Example 18. The method according to Example 17, wherein the semiconductor material is amorphous silicon and the dielectric material is silicon nitride.

[0131] Example 19. The method according to Example 17 further includes: selectively forming a capping layer on the metal gate after etching the metal gate and before performing the lining.

[0132] Example 20. The method according to Example 17, wherein the second opening exposes the sidewall of the gate spacer.

[0133] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: A metal gate structure is formed on a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer. The metal gate structure is recessed below the upper surface of the gate spacers, which extend along opposite sidewalls of the metal gate structure, wherein, after the recess is made, recesses are formed between the gate spacers. The sidewalls and bottom of the recess are lined with a semiconductor material; After the lining is applied, the recess is filled with a dielectric material; A patterned etch stop layer stack is formed on the dielectric material, the semiconductor material, and the ILD layer, wherein a first opening in the patterned etch stop layer stack is located directly above a first portion of the dielectric material, the semiconductor material, and the ILD layer adjacent to the gate spacer; A second opening is formed in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, wherein the second opening exposes the source / drain region adjacent to the metal gate structure; and The second opening is filled with a conductive material.

2. The method according to claim 1, wherein, The semiconductor material is amorphous silicon.

3. The method according to claim 2, wherein, The dielectric material is silicon nitride.

4. The method according to claim 1, further comprising: Before recessing the metal gate structure, an etch stop layer is selectively formed on the upper surface of the ILD layer away from the semiconductor fin, wherein a first portion of the semiconductor material contacts the etch stop layer and extends along the etch stop layer.

5. The method according to claim 4, further comprising: After filling the recess and before forming the patterned etch stop layer stack, a planarization process is performed, wherein the planarization process removes the first portion of the semiconductor material and the etch stop layer.

6. The method according to claim 1, further comprising: After the recess is made and before the lining is made, a capping layer is formed on the metal gate structure, wherein the capping layer substantially contacts the metal gate structure and the semiconductor material.

7. The method according to claim 1, wherein, Forming the second opening includes performing an etching process to remove the first portion of the ILD layer, wherein the etching process causes the gate spacer to be recessed more than the dielectric material and the semiconductor material.

8. The method according to claim 1, wherein, Forming the patterned etch stop layer stack includes: An etch stop layer stack is formed by sequentially forming a first sublayer, a second sublayer, and a third sublayer on the ILD layer, wherein the first sublayer, the second sublayer, and the third sublayer comprise different materials; A patterned mask layer is formed on top of the etch stop layer stack; and The patterned mask layer is used as an etch mask to pattern the etch stop layer stack.

9. The method according to claim 8, wherein, The first sublayer is formed of tungsten-doped silicon carbide, the second sublayer is formed of silicon oxide, and the third sublayer is formed of silicon.

10. The method according to claim 1, further comprising: After filling the second opening, perform the following operations: Remove the patterned etch stop layer stack; An intermetallic dielectric (IMD) layer is formed on top of the ILD layer; as well as A first via and a second via are formed extending through the IMD layer, wherein the first via further extends through the dielectric material and the semiconductor material and is electrically coupled to the metal gate structure, and wherein the second via is electrically coupled to the conductive material.

11. A method of forming a semiconductor device, the method comprising: A first metal gate structure is formed on the fin; A second metal gate structure is formed on the fin and adjacent to the first metal gate structure, wherein the first metal gate structure and the second metal gate structure are surrounded by an interlayer dielectric (ILD) layer. The first metal gate structure and the second metal gate structure are recessed to form a first opening between the first gate spacers and a second opening between the second gate spacers, wherein the first gate spacers are located on opposite sidewalls of the first metal gate structure and the second gate spacers are located on opposite sidewalls of the second metal gate structure. Semiconductor material is conformally formed along the sidewalls and bottom of the first opening and the sidewalls and bottom of the second opening; The first opening and the second opening are filled by forming a dielectric material on the semiconductor material; and A self-aligned contact is formed between the first metal gate structure and the second metal gate structure, wherein the self-aligned contact is electrically coupled to the lower source / drain region between the first metal gate structure and the second metal gate structure.

12. The method according to claim 11, wherein, Forming the self-aligned contact includes performing the following operations after filling the first opening and the second opening: An etch stop layer stack is formed on top of the ILD layer, wherein the etch stop layer stack comprises multiple layers, each of which is formed of a different material; A first opening is formed in the etch stop layer and above the first metal gate structure and on the first portion of the ILD layer between the first metal gate structure and the second metal gate structure; The first portion of the ILD layer is removed to form a second opening in the ILD layer, wherein the second opening exposes the underlying source / drain region; and The second opening is filled with a conductive material, wherein the conductive material extends continuously from the first gate spacer to the second gate spacer.

13. The method according to claim 12, wherein, Forming the etch stop layer stack includes: A first layer of tungsten-doped silicon carbide is formed on top of the ILD layer; A second layer of silicon oxide is formed on top of the first layer; and A third layer of silicon is formed on top of the second layer.

14. The method according to claim 11, wherein, The semiconductor material is amorphous silicon, and the dielectric material is silicon nitride.

15. The method of claim 11, further comprising: After the recess is made and before the semiconductor material is conformally formed, a conductive capping layer is formed on the first metal gate structure and the second metal gate structure.

16. The method according to claim 15, wherein, The gate contact contacts the upper surface of the conductive cap layer away from the fin and extends along that upper surface.

17. A method of forming a semiconductor device, the method comprising: Forming fins that protrude above the substrate; A metal gate is formed on the fin, wherein the metal gate is surrounded by a dielectric layer; The metal gate is etched to reduce the height of the metal gate, wherein, after the etching is performed, a recess is formed on the metal gate and between the gate spacers of the metal gate; The sidewalls and bottom of the recess are lined with a semiconductor material; The recess is filled by forming a dielectric material on the semiconductor material; A patterned mask layer is formed over the metal gate and the dielectric layer, wherein a first opening of the patterned mask layer is located directly above a portion of the dielectric layer adjacent to the metal gate; Removing a portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening exposes the underlying source / drain region; and The second opening is filled with a conductive material.

18. The method according to claim 17, wherein, The semiconductor material is amorphous silicon, and the dielectric material is silicon nitride.

19. The method of claim 17, further comprising: After etching the metal gate and before lining is performed, a capping layer is selectively formed on the metal gate.

20. The method of claim 17, wherein, The second opening exposes the sidewall of the gate spacer.

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