Current sink management circuit, corresponding system and method

Abstract

Current absorption management circuits, corresponding systems and methods are disclosed. Current absorption management for an electronic fuse coupled between a power supply node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch that are connected in parallel between the power supply node and the electrical load node. The high current electronic switch and the low current electronic switch are alternately actuated to: in a first mode, the high current electronic switch is on and the low current electronic switch is off; and in a second mode, the high current electronic switch is off and the low current electronic switch is on. The second mode can be changed to in response to a standby state or sensing a lower current in the electrical load. Conversely, the first mode can be changed to in response to sensing a higher current in the electrical load.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102020000030575, filed on December 11, 2020, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This invention relates to current absorption in management circuits.

[0004] One or more embodiments can be applied to electronic fuses used in various industries. The automotive industry is an example of a field where embodiments can be advantageously used. Background Technology

[0005] An electronic fuse (also known as an e-fuse or eFuse) is an active electronic device that can operate in either a conducting or open state.

[0006] During the on state, current flows to the associated loads, and they absorb the current that should be biased as desired; during the off state, no current flows to the associated loads.

[0007] When the load is reduced, the current absorbed by the eFuse in the on state may decrease and become smaller compared to the "normal" load current.

[0008] Therefore, an electronic fuse is an example of a device in which the current absorbed in the on state is small, but which may eventually act as a battery drain during the load quiescent state, in which the device cannot switch to the off state as long as a (small) current is still supplied to the load during the load quiescent state.

[0009] This makes it unsuitable for using such devices in applications that may involve long-term standby operation, such as power distribution systems, where devices like eFuse may represent a viable alternative to traditional mechanical fuses.

[0010] Automotive power distribution applications are an example of such systems, where electronic fuses can be combined with silicon integrated devices that have high current / low RDSon distribution to effectively provide the main protection function for the wiring harness in a vehicle.

[0011] The ability to have a small current flow to the load, maintain (very) low total current consumption in active standby conditions, and quickly turn on the main power switch (such as a power MOS transistor) represents the desired characteristics of a device for applications as described above.

[0012] There is a need in the art to provide this desired feature in current sink management circuits (such as eFuse) while avoiding making the system more complex, less robust, and / or more expensive in terms of increased module area, component count, or microcontroller (μC) level complexity. Summary of the Invention

[0013] One or more embodiments may involve circuitry.

[0014] One or more embodiments may relate to a corresponding system. A power distribution system used in the automotive industry may be an example of such a system.

[0015] One or more embodiments may involve corresponding methods.

[0016] For simplicity and ease of understanding, the embodiments shown herein will be discussed primarily in conjunction with possible applications in electronic fuses.

[0017] It will also be understood that the embodiments are not necessarily linked to the application.

[0018] More generally, one or more embodiments can be applied to situations where the desired features are the ability to absorb low current in standby mode and to transition quickly from this low-power state to full operating mode without significant discontinuity to the load and system.

[0019] One or more embodiments may include an integrated secondary switch connected in parallel with a primary power switch (e.g., a power MOS transistor), the integrated secondary switch being controlled by a low-current-consuming driver to achieve an on-standby state.

[0020] In one or more embodiments, this on-standby state can be entered in response to a direct command from the microcontroller. In one or more embodiments, a load current sensing feature can be used to automatically detect load deactivation.

[0021] In one or more embodiments, the secondary switch may be integrated into the same device and automatically managed together with the main power switch.

[0022] In one or more embodiments, once standby mode is enabled, load reactivation can be automatically detected, which facilitates the management of the main power switch operation.

[0023] The circuit architecture according to the embodiments facilitates implementation in a variety of devices using different technologies. One or more embodiments contribute to achieving (very) low current consumption in the on-standby state, which results in reduced current discharge from the power source (e.g., a car battery) even during long-term application in a static state. Attached Figure Description

[0024] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0025] Figure 1 This is a functional block diagram of a system employing a current absorption management circuit according to an embodiment of the present invention.

[0026] Figure 2 This is an exemplary block diagram of a first possible option in an embodiment of the present invention.

[0027] Figure 3 This is an example based on Figure 2 A flowchart of possible operations of the embodiments, and

[0028] Figure 4 This is an exemplary block diagram of a second possible option in implementing embodiments of the present invention. Detailed Implementation

[0029] In the following description, one or more specific details are shown, which are intended to provide a thorough understanding of examples of embodiments of the invention. Embodiments may be obtained without one or more of these specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order not to obscure certain aspects of the embodiments.

[0030] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to at least one embodiment is included. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment.

[0031] Furthermore, in one or more embodiments, a particular conformation, structure, or property may be combined in any suitable manner.

[0032] The headings / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0033] Furthermore, throughout the accompanying drawings, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals, and for the sake of brevity, the corresponding descriptions will not be repeated for each figure.

[0034] As discussed, an electronic fuse is typically an example of a device that, although it absorbs a small current in the on state, may ultimately act as a battery drain during the load quiescent state, in which the device cannot switch to the off state as long as it is still supplying a (small) current to the load during the load quiescent state.

[0035] Electronic fuses share the fundamental function of preventing overcurrent from electrical loads coupled to a power source (such as battery voltage in automotive applications) with traditional mechanical fuses. However, electronic fuses may differ from traditional mechanical fuses (which always draw current from the power source before potentially "burning") because electronic fuses can reach a state where they do not draw current from the power source (at least theoretically).

[0036] For simplicity and ease of understanding, the embodiments shown in this article will be discussed primarily in conjunction with possible applications in electronic fuses.

[0037] To reiterate, these embodiments are not linked to the application out of necessity: in fact, one or more embodiments can be applied more generally to situations where the ability to absorb low current in standby mode and to transition quickly from such low-power mode to full operating mode without noticeable discontinuity to the load and system is a desirable feature.

[0038] Figure 1 The functional block diagram generally shows a system 100 employing a “smart” current absorption management circuit (commonly referred to as e-fuse or eFuse) 10.

[0039] like Figure 1 The system 100 shown is configured to controllably supply energy drawn from the power source SS to the electrical load L.

[0040] exist Figure 1 In the (purely illustrative) representation, the power SS is provided by a battery, which is likely the case for system 100 equipped in vehicle V.

[0041] It will be understood that the source SS and the load L may be different elements from those in the embodiment, and the system 100 may only be intended to be coupled to the power source SS (at node VBAT+) and the load L (at node OUT) when the system is installed and configured for operation.

[0042] like Figure 1 As shown, the power supply to the load L is controlled via (power) switch 12. A power MOS transistor (power MOSFET) can be an example of such a switch, which is capable of conducting relatively high current between its source and drain.

[0043] For simplicity and ease of explanation, switch 12 is... Figure 1 The switch 12 is represented as a component of system 100. However, the switch 12 may be a different element than in the embodiment.

[0044] Other conventional methods in this field, such as Figure 1 The functional block diagram of system 100 shows that it may include a wide range of functional palettes.

[0045] like Figure 1As shown, these functions can be arranged as follows:

[0046] Part I, including the I / O interface (in...) Figure 1 The system and safety-related functions that are coordinated on the left side include, for example, parameter setting (Set) 101, self-test (ST) 102, diagnostics (Diag) 103, control (C) 104, watchdog (WD) 105 and emergency operation (limp-home) (LH) 106.

[0047] Part II includes power MOSFET protection, such as back electromotive force (BEMF) clamping (Clamp) 107 and thermal protection (Therm) 108 functions; and

[0048] Part III includes power MOSFET gate driver and sensor functions, such as output voltage sensing (Sense1) 109, charge pump (CP) 110, junction temperature sensing (Temp) 111, power supply voltage (VBAT+) sensing (Sense2) 112, and current sensing (Sense3) 113.

[0049] Generally speaking, unless otherwise indicated below, as Figure 1 The illustrated system architecture can be considered a conventional architecture in the field, which makes it unnecessary to provide a more detailed description.

[0050] The embodiments illustrated herein primarily relate to the possible interactions of function 10 with other functions in the architecture, such as the interaction with power switch 12 and current sensing function 113.

[0051] This can occur, for example, through standby monitoring (SBmont) and standby switch (SBsw) functions, such as... Figure 1 Boxes 114 and 115 in the text are typically represented and are suitable for use as... Figure 2 and Figure 3 The implementation is illustrated.

[0052] For this reason, we will now discuss the collaboration between function 10 and other functions in the architecture with power switch 12. Figure 1 Various possible implementation options for the functional architecture.

[0053] For this purpose, the power switch 12 is shown as having a current path coupled between the power supply SS (at node VBAT+) and the load L (at node OUT) (source-drain in the case of a field-effect transistor such as a MOSFET transistor).

[0054] As mentioned above, the load L can be nominally any type of electrical load; therefore, the embodiments are essentially "transparent" to the nature and characteristics of the load L.

[0055] For general reference, it will be combined Figures 2 to 4 Two implementation options are discussed as examples of possible variations, where:

[0056] and Figure 1 In contrast to the case where switch 12 is included in circuit 10, power switch 12 can be outside circuit 10 (and therefore different from circuit 10), and / or

[0057] In response to external controllers (e.g., microcontrollers or μC, such as combined) Figure 2 The command (as described above), or as a result of automatically activating a low current consumption state without an external command (such as in combination with...). Figure 4 As mentioned above, circuit 10 can be switched to a low current consumption state (on standby state) to deliver a small current to the load.

[0058] As previously stated, for simplicity and ease of interpretation, unless otherwise indicated, the same parts or elements are denoted by the same reference numerals throughout the figures, and for the sake of brevity, the corresponding descriptions will not be repeated for each figure.

[0059] Furthermore, features and details discussed in conjunction with one implementation option can be applied individually or in combination to another implementation option. That is, features or details shown individually or in combination within the framework of an implementation option should not be construed as meaning that such features or details are exclusive to the indications of the implementation option for which the features or details are shown herein.

[0060] exist Figure 2 The diagram shows a current absorption management circuit 10, which is coupled to the power supply SS (at node VBAT+) and the load L (at node OUT) to control the current supply to the load L via the power switch 12.

[0061] The current path through power switch 12 (source-drain in the case of a field-effect transistor such as a MOSFET) is therefore coupled between the power supply SS and the load L, causing the load to be energized, i.e., the current flowing through the load:

[0062] In response to switch 12 being turned on, it is facilitated (allowed), that is, it is made to conduct electricity, and

[0063] In response to switch 12 being opened, it reverses (prevents), that is, it makes it non-conductive.

[0064] The power switch 12 can be alternately turned on (i.e., made to conduct electricity) and turned off (i.e., made to deconduct electricity) by a drive signal generated by the driver 14 and applied to the control node (or gate in the case of a field-effect transistor such as a MOSFET transistor) of the power switch 12 via the node GD.

[0065] Reference numeral 16 indicates a voltage regulator coupled to a power supply SS and configured (in a manner known to those skilled in the art) to provide a regulated power supply voltage Vreg_out to other parts of device 100, such as... Figure 1 The functional block diagram is shown below.

[0066] As discussed below, a voltage regulator may include a high-power section 16A (e.g., an LDO) and a low-power section 16B (e.g., a no-cap pre-regulator).

[0067] Reference numeral 18, as a whole, denotes the portion (subsystem) of circuit 10 used to manage the standby state of circuit 10, as described below.

[0068] This can occur in response to a standby signal received at the input node OSS from the controller MC (e.g., a microcontroller or μC). As shown, the controller MC can be an external controller different from circuit 10.

[0069] like Figure 2 As shown, subsystem 18 includes an active standby logic circuitry 20 sensitive to signals received from controller MC at node OSS and a wake-up signal bypass_vds_sat received from comparator 22. Comparator 22 compares a reference (voltage) threshold Vref_1 with a signal indicating the current intensity flowing into load L at node OUT, as described below, which can be used to facilitate the (rapid) reactivation of main switch 12 to a conductive state.

[0070] Through such Figure 1 The current sensing function of 113 (in a manner known to those skilled in the art) obtains such a reactivation signal.

[0071] As shown in this paper, such a reactivation signal can be simply obtained as the result of a feedback action at node OUT, which is compared with a (possibly adjustable) threshold Vref_1 of the reference supply voltage VBAT+ in comparator 22.

[0072] It is reasonable to assume that the voltage at node OUT (and the voltage drop between node VBAT+ and node OUT) is a function of the output current. In fact, an electronic switch in a conducting state can be considered as a resistor with a resistance value, such as RDSon in the case of a field-effect transistor such as a MOSFET.

[0073] Therefore, by monitoring the voltage at node OUT, a signal suitable for supplying to comparator 22 for comparison with threshold Vref_1 can be easily obtained.

[0074] In one or more embodiments, a secondary bypass switch 12A, such as a (low-power) MOSFET transistor (e.g., a P-channel), can be coupled across nodes VBAT+ and OUT, thereby coupling the current path through it (source-drain in the case of a field-effect transistor such as a MOSFET) between the power supply SS and the load L. Switch 12A is capable of conducting a relatively low current between its source and drain (i.e., substantially lower than the high current capability of power switch 12).

[0075] Alternatively, the reactivation signal can be simply obtained as a result of feedback action based on the voltage value at node OUT, i.e., by monitoring the (source-drain) voltage drop across the secondary bypass switch 12A.

[0076] like Figure 2 As shown, logic circuit device 20 is configured to generate:

[0077] The first signal Switch_GD-on / off, which (via drive circuit 14) is applied to the control node of power switch 12 (the gate in the case of a field-effect transistor such as a MOSFET) to alternately turn it on (conduct) and off (not conduct).

[0078] The second signal, switch_BS-on / off, is applied to the control node of the secondary switch 12A (or the gate in the case of a field-effect transistor such as a MOSFET) to alternately turn it on (conduct) and off (not conduct).

[0079] The third signal stdbyon, such as Figure 1 The functional block diagram shows the other parts assigned to device 100 (in Figure 2 The upper part clearly indicates that a signal stdbyon is supplied to the voltage regulator 16.

[0080] The possible operating sequence of circuit 10 can be considered as an active-standby state.

[0081] This may be a supplement to the conventional on / off states of electronic fuses, namely:

[0082] On state (see also) Figure 3 In the flowchart (box 1000), during this period, the load L coupled to the power supply SS via switch 12 is (fully) energized, making the load L conductive (switch 12A is not conductive), and

[0083] Disconnected state (see also) Figure 3In the flowchart (block 1000A), during this period, since switch 12 (and switch 12A) is not conductive, switch 12 decouples the load L from the power supply SS; for example, in response to... Figure 1 An overcurrent event detected at point 113 can trigger this disconnection state.

[0084] like Figure 1 The operation of the device 100 shown in these two on and off states (see...) Figure 3 Boxes 1000 and 1000A in the flowchart are standard practice in the art, which makes it unnecessary to provide a more detailed description here.

[0085] Furthermore, we will reiterate that the application of electronic fuses will be considered here only by way of non-limiting examples.

[0086] These embodiments are not linked for application to electronic fuses because the on-active-standby state may be advantageous in various devices where it is desirable that a small current can still flow to a load such as L while the total current consumption of circuit 10 is very low (e.g., less than 50 μA, thus improving battery life).

[0087] The ability to switch to (fully) on state when the power switch 12 is turned on quickly (e.g., within 50-100 μs due to the requirement of normal load current) is also desirable.

[0088] like Figure 2 The implementation options shown are illustrated in the example below. Figure 3 In the flowchart, Figure 3 The flowchart assumes that circuit 10 is in a (fully) on state after the start, as illustrated in block 1000.

[0089] As described above, switch 12 can be disconnected (in a non-conductive disconnect state 1000A) to decouple load L from power supply SS in response to an overcurrent event during eFuse operation. This is conventional in the art (making a more detailed description unnecessary here), and is not mandatory for any particular embodiment.

[0090] As illustrated by STDBY, the occurrence of a trigger action may prompt a switch to a low-power on-active standby state.

[0091] This can be indicated by the positive result Y of the check at box 1001; in the event of a negative result N, the circuit simply loops back upstream, thus maintaining (fully) on.

[0092] The triggering action illustrated at STDBY may involve the input node OSS being asserted by the controller MC for a minimum time (e.g., being brought high), while circuit 10 is in the on state, switch 12 is conducting, and load L is energized by power supply SS.

[0093] The asserted input node OSS can be recognized by device 10 as a command to enable the active-standby state. For example, this command can be verified as a result of the input node OSS being pulled down (i.e., brought low).

[0094] In response to entering conduction activity-standby state (e.g.) Figure 3 (Example shown in box 1002), the logic circuit device 20 can:

[0095] On the one hand, the main switch 12 is deactivated via driver 14 (the signal Switch_GD-on / off, indicating the required disconnection condition when the power supply SS is no longer coupled to the load L via switch 12), and

[0096] On the other hand, the secondary switch 12A is enabled to maintain a reduced current supply to the load L (e.g., 350mA-500mA).

[0097] During the on-active-standby state, if the current supplied to the load L exceeds the threshold Iout_stdbyon (e.g., 500mA@VBAT+=13V, T=25℃), this threshold corresponds to Figure 3 If the positive result Y of the check illustrated in the middle frame 1003 is obtained, the logic circuit device 20 can be switched back to the (fully) on state in the following manner:

[0098] On the one hand, the main switch 12 (the signal Switch_GD-on / off indicating the required conduction conditions) can be reactivated via the driver 14, which can happen very quickly;

[0099] On the other hand, the secondary switch 12A is deactivated.

[0100] In the presence of a negative result N from the check represented by box 1003, the circuit simply loops back upstream, thus maintaining the on-active-standby state.

[0101] Information about the current intensity supplied to the load L can be provided to the logic circuit device 20 via comparator 22 in response to a comparison indication in comparator 22 that the current intensity of the load L (e.g., indicated by a reactivation signal, as discussed above, can be obtained as a result of a feedback action based on the voltage at node OUT) has increased to an intensity threshold represented by Vref_1.

[0102] For example, circuit 10 can be configured such that if any pin (e.g., a possible exception represented by an OSS node) is pulled up during a conduction-standby state, such as Iout < 350mA, device 100 will return to a (fully) on state, reactivating power switch 12 and deactivating secondary switch 12A.

[0103] Of course, the quantitative values ​​given here are merely illustrative and non-limiting examples of the embodiments.

[0104] The voltage regulator 16 can be selectively enabled using the signal stdbyon (which indicates conduction activity—standby state is enabled and is assigned to other parts of device 100 by logic circuitry).

[0105] Such as a high-power (and higher-consumption) regulator 16A of a low-dropout (LDO) regulator, during the (fully) on state when power switch 12 is on and secondary switch 12A is off; or

[0106] The low-power (and low-consumption) voltage pre-regulator 16B is in the on-active-standby state, wherein the power switch 12 is off and the secondary switch 12A is on.

[0107] More generally, such as Figure 2 The signal stdbyon from logic circuit device 20 represents the signal that is assigned to... Figure 1 Various other features in the architecture 100, such as the current absorption management circuitry shown in this paper, help switch these features to a low-power state (nominally disconnected), thereby significantly reducing energy absorption.

[0108] This advantageously helps to further reduce energy absorption from the power supply SS during the conduction-standby state.

[0109] Moreover, the wake-up from such a low-power state to a fully operational state can occur rapidly, without significant discontinuity for the load L and the entire system.

[0110] exist Figure 4 Unless the context otherwise indicates, parts or elements similar to those discussed in conjunction with the preceding figures are denoted by the same reference numerals, and therefore, for the sake of brevity, the corresponding descriptions will not be repeated.

[0111] Figure 4 One example of an implementation method, wherein, as Figure 3 The trigger action illustrated at STDBY in the flowchart can be caused by the sensing action of the current through the load L, and no longer involves commands provided by the external controller MC.

[0112] In such Figure 4In the circuit 10 shown, a sensing transistor 12B (e.g., a MOSFET transistor) is provided, which has a current path (source-drain in the case of a field-effect transistor such as a MOSFET transistor) coupled across nodes VBAT+ and OUT and a control node, the control node (gate in the case of a field-effect transistor such as a MOSFET transistor) being coupled to the control node GD of the power switch 12 (gate in the case of a field-effect transistor such as a MOSFET transistor).

[0113] The current (feedback) path of sensing transistor 12B is also coupled to (multiple) sensing nodes MS, which are configured to be optionally coupled to ground GND via (e.g., external) sensing resistor SR.

[0114] Figure 24 is in Figure 4 The value in the diagram represents another comparator that compares the signal at node MS (e.g., voltage) with another (possibly adjustable) threshold Vref_2 referenced to ground. The output signal from comparator 24 is applied to logic circuit device 20.

[0115] During the (fully) on state, such as Figure 4 The device shown will be able to detect (via a feedback current sensing network 12B, SR that supplies a signal to comparator 24 to be compared with a threshold Vref_2) a situation in which the current through the main switch 12 and thus through the load L has dropped to the lower threshold defined by Vref_2 (e.g., 250mA@VBAT=+13V, T=25°C).

[0116] Optionally, the sensing network 12B, SR can be configured to operate at a very low current density, and the resistor SR can be selected accordingly (a resistance value of 420 kΩ has been found to be a wise choice) to generate Vms = 4.15V @ Iout = 250mA.

[0117] Here, again, these quantitative values ​​are merely illustrative and non-limiting examples of the embodiments.

[0118] When this detection occurs (see...) Figure 3 In the STDBY configuration, after a fixed time (e.g., approximately 150 μs), the circuit will automatically enter the active standby state, such as... Figure 3 The flowchart is shown in box 1002.

[0119] Here again, during the on-active-standby state, if the current supplied to the load L exceeds the threshold Iout_stdbyon indicated by the positive result Y of the check represented by block 1003 (e.g., 500mA@VBAT+=13V, T=25℃), the logic circuit device 20 can switch back to the (fully) on state. In the presence of a negative result N of the check represented by block 1003, the circuit simply loops back upstream, thus maintaining the on-active-standby state.

[0120] exist Figure 4 In the illustrated case, information regarding the current intensity supplied to the load L can be provided to the logic circuit device 20 via comparator 22, as previously mentioned. Figure 2 The discussion focuses on the feedback action based on the voltage at node OUT.

[0121] Here again, circuit 10 can be configured such that if any pin (e.g., a possible exception represented by an OSS node) is pulled up during, for example, an active-standby state with Iout < 350mA, device 100 will return to the (fully) on state, reactivating power switch 12 and deactivating secondary switch 12A.

[0122] Once again, the signal stdbyon, which indicates that the conduction activity—standby state—is enabled and is distributed by the logic circuitry to other parts of device 100, can be utilized in voltage regulator 16 to selectively enable:

[0123] A high-power (and higher-consumption) regulator 16A, such as a low-dropout (LDO) regulator, can be activated during the (fully) on state when power switch 12 is on and secondary switch 12A is off; or

[0124] The low-power (and low-consumption) voltage pre-regulator 16B can be activated during the on-active-standby state when the power switch 12 is off and the secondary switch 12A is on.

[0125] More generally, as well as Figure 4 The middle is allocated from the logic circuit device 20 Figure 1 The various other functions in the architecture 100, as shown by the stdbyon signal, and the current sink management circuitry as illustrated herein, help switch these functions to a low-power state (nominally off), thereby significantly reducing energy absorption.

[0126] This advantageously helps to further reduce energy absorption from the power supply SS during the conduction-standby state.

[0127] Moreover, the wake-up from such a low-power state to a fully operational state can occur rapidly, without significant discontinuity for the load L and the entire system.

[0128] In short, a circuit as illustrated herein (e.g., 10) may include:

[0129] The first node (e.g., VBAT+) and the second node (e.g., OUT) are configured to be coupled (respectively) to a power supply (e.g., SS) and an electrical load (e.g., L), the electrical load being configured to be powered by the power supply (e.g., SS) via an electronic switch (e.g., 12) having a control node; and

[0130] A third node (e.g., GD) is configured to be coupled to the control node of the electronic switch to switch the electronic switch between a conductive state (e.g., 1000) (where the electrical load is coupled to the power source via the electronic switch) and a non-conductive state (e.g., 1000A, where the electrical load cannot be coupled to the power source via the electronic switch).

[0131] The circuits illustrated herein may also include:

[0132] A secondary electronic switch (e.g., 12A) located between the first and second nodes;

[0133] A control logic circuit device (e.g., 20), coupled to the third node and the secondary electronic switch, provides a first switch control signal (e.g., Switch_GD-on / off) applied (e.g., via 14) to the third node and a second switch control signal (e.g., Switch_BS-on / off) applied to the secondary electronic switch. The control logic circuit device (20) is configured to provide the first switch control signal and the second switch control signal alternately:

[0134] In the first operating mode (e.g., 1000), a first switch control signal drives the electronic switch to a conductive state, and a second switch control signal drives the secondary electronic switch to a non-conductive state; and

[0135] In the second operating mode (e.g., 1002), a first switch control signal drives an electronic switch to a non-conductive state, and a second switch control signal drives a secondary electronic switch to a conductive state, wherein an electrical load is coupled to a power source via the secondary electronic switch.

[0136] The circuit illustrated herein may include a fourth node (e.g., OSS) configured to receive a standby signal (e.g., MC), wherein circuit control logic circuitry is configured to switch to a second operating mode (e.g., from the first operating mode) in response to the standby signal (e.g., 1001) received at the fourth node.

[0137] The circuit illustrated herein may include a current sensing circuit device (e.g., 12B, SR, 24) configured to sense the intensity of a current flowing through an electrical load. The current sensing circuit device is coupled to a control logic circuit device configured to switch from the first operating mode to the second operating mode in response to a drop in the current flowing through the electrical load to a lower threshold (e.g., Vref_2).

[0138] In the circuit illustrated herein, the current sensing circuit device may include a sensing transistor (e.g., 12B) having a control node coupled to the third node and a current path through the sensing transistor, the current path including a current feedback line from the first node (e.g., VBAT+) to another node (e.g., MS) configured to be coupled to ground via a resistor (e.g., SR).

[0139] The circuits illustrated herein may include current sensing circuitry (e.g., 22 and 12A) sensitive to the intensity of current flowing through an electrical load, the current sensing circuitry being coupled to control logic circuitry, wherein the control logic circuitry is configured to switch from the second operating mode to the first operating mode in response to an increase in the current flowing through the electrical load to an upper limit threshold (e.g., determined by Vref_1).

[0140] The circuit illustrated herein may include a power regulator circuit (e.g., 16) having a first power regulator portion (e.g., 16A) and a second power regulator portion (e.g., 16B), the second power regulator portion having lower energy absorption than the first power regulator portion, wherein a control logic circuitry means is coupled (e.g., stdbyon) to the power regulator circuit and configured to enable the first power regulator portion during a first operating mode and enable the second power regulator portion during a second operating mode.

[0141] In the circuit illustrated herein, the secondary electronic switch (e.g., 12A) may include a low-power electronic switch.

[0142] With an RDSon resistor of approximately 10 ohms (at full V) GS Electronic switches such as MOSFET transistors (see below) can be examples of such low-power switches.

[0143] The circuits illustrated herein may include the electronic switches having control nodes (e.g., such as...). Figure 1 (as shown), and the secondary electronic switch may include a low-power electronic switch configured to be traversed by a current of less intensity than the current traversing the electronic switch during conduction.

[0144] Systems illustrated herein (e.g., power distribution systems for the automotive industry) may include:

[0145] Power supply (e.g., SS);

[0146] Electrical load (e.g., L);

[0147] An electronic switch (e.g., 12) having a control node for switching the electronic switch between a conductive state and a non-conductive state in which an electrical load is coupled to a power source via the electronic switch (where the electrical load is not coupled to the power source via the electronic switch); and

[0148] A circuit (e.g., 10), where switch 12 is a component distinct from the circuit – such as Figure 2 and Figure 4 As shown, or as Figure 1 (As shown in the circuit), as illustrated herein, a first node (e.g., VBAT+) is coupled to a power source (e.g., SS), a second node (e.g., OUT) is coupled to an electrical load (e.g., L), and a third node (e.g., GD) is coupled to the control node of an electronic switch (e.g., 12).

[0149] Systems illustrated herein may include energy absorption circuitry powered by the power source (e.g., SS) (e.g., see [link to relevant documentation]). Figure 1 Functions I, II, III in system 100, in response to the control logic circuit device (e.g., 20) in the circuit (e.g., 10) being actuated in the second operating mode (e.g., 1002, where the signal stdbyon is assigned to...). Figure 1 In System 100, functions I, II, and III) allow the energy absorption circuit device to be set to a low energy absorption mode.

[0150] A method of operating a circuit or system as illustrated herein may include: actuating control logic circuitry (e.g., 20) to alternately:

[0151] In the first operating mode (e.g., 1000), a first switch control signal (e.g., Switch_GD-on / off) drives an electronic switch (e.g., 12) to a conductive state, and a second switch control signal (e.g., Switch_BS-on / off) drives a secondary electronic switch (e.g., 12A) to a non-conductive state; and

[0152] In the second operating mode (e.g., 1002), a first switch control signal (e.g., Switch_GD-on / off) drives an electronic switch (e.g., 12) to a non-conductive state, and a second switch control signal (e.g., Switch_BS-on / off) drives a secondary electronic switch (e.g., 12A) to a conductive state, wherein an electrical load (e.g., L) is coupled to a power source (e.g., SS) via the secondary electronic switch.

[0153] Without prejudice to the fundamental principles, details and embodiments may be changed, even significantly changed, relative to the description by way of example only, without departing from the scope of protection.

[0154] The claims are an integral part of the technical teachings provided herein regarding the embodiments.

[0155] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: The first node is configured to be coupled to the power supply; The second node is configured to be coupled to an electrical load; The third node is configured to be coupled to the control node of an electronic switch, which is coupled between the power supply and the electrical load; A secondary electronic switch is coupled between the first node and the second node; A control logic circuit device is configured to provide a first switch control signal, which is applied to the control node of the electronic switch through the third node to control the switching of the electronic switch between a conductive state and a non-conductive state, the conductive state being used to deliver a first current level from the power supply to the electrical load. The control logic circuit device is further configured to provide a second switch control signal, which is applied to the control node of the secondary electronic switch to control the switching of the secondary electronic switch between a conductive state and a non-conductive state, wherein the conductive state is used to deliver a second current level from the power supply to the electrical load, wherein the second current level is lower than the first current level. The first switch control signal and the second switch control signal control the electronic switch and the secondary electronic switch, such that: In the first operating mode, the first switch control signal switches the electronic switch to the conductive state to transmit the first current level to the second node, and the second switch control signal switches the secondary electronic switch to the non-conductive state. as well as In the second operating mode, the first switch control signal switches the electronic switch to the non-conductive state, and the second switch control signal switches the secondary electronic switch to the conductive state to transmit the second current level to the second node; The circuit also includes: A power regulator circuit device having a first power regulator section and a second power regulator section, wherein the second power regulator section has a lower energy absorption than the first power regulator section. and The control logic circuit device is further configured to enable the first power regulator portion during the first operating mode, or to enable the second power regulator portion during the second operating mode.

2. The circuit of claim 1, further comprising a fourth node configured to receive a standby signal, wherein the control logic circuitry is configured to switch from the first operating mode to the second operating mode in response to an assertion of the standby signal.

3. The circuit according to claim 1, further comprising: A current sensing circuit device is configured to sense the current intensity flowing through the electrical load; and The control logic circuit device is configured to switch from the first operating mode to the second operating mode in response to the current sensing circuit device detecting that the current flowing through the electrical load has dropped to a lower threshold.

4. The circuit of claim 3, wherein the current sensing circuit device includes a sensing transistor having a control node and a current path through the sensing transistor, the control node being coupled to the third node, the current path being included in a current feedback line from the first node to another node, the other node being coupled to ground via a resistor.

5. The circuit according to claim 1, further comprising: A current sensing circuit device is configured to sense the intensity of the current flowing through the electrical load; and The control logic circuitry is configured to switch from the second operating mode to the first operating mode in response to the current sensing circuitry detecting that the current flowing through the electrical load has increased to an upper limit threshold.

6. The circuit of claim 1, wherein the electronic switch is a higher power transistor for transmitting the first current level, and the secondary electronic switch is a lower power transistor for transmitting the second current level.

7. The circuit of claim 1, wherein the electronic switch is a first conductivity type MOSFET device, and the secondary electronic switch is a second conductivity type MOSFET device.

8. The circuit according to claim 1, further comprising: The power supply is coupled to the first node; The electrical load is coupled to the second node; as well as The electronic switch has the control node, which is coupled to the third node.

9. The circuit according to claim 8, wherein the electronic switch is an external device.

10. The circuit of claim 8 further includes an energy absorption circuit device powered by the power supply, wherein, in response to the second operating mode, the energy absorption circuit device can be configured to a low energy absorption mode.

11. A circuit comprising: The first transistor is controllable to deliver a first current level to the electrical load in the on state; The second transistor is controllable to deliver a second current level to the electrical load in an on state, wherein the second current level is less than the first current level. A control logic circuit device is configured to provide a first switch control signal to the control node of the first transistor and a second switch control signal to the control node of the second transistor; in: In the first operating mode, the control logic circuit device generates the first switch control signal to switch the first transistor to the on state to deliver the first current level to the electrical load, and generates the second switch control signal to switch the second transistor to the off state; and In the second operating mode, the control logic circuit device generates the second switch control signal to switch the second transistor to the on state to deliver the second current level to the electrical load, and generates the first switch control signal to switch the first transistor to the off state. The circuit also includes: A power regulator circuit device includes a first power regulator section and a second power regulator section, wherein the second power regulator section has a lower energy absorption than the first power regulator section; and The control logic circuit device is further configured to enable the first power regulator portion during the first operating mode, or to enable the second power regulator portion during the second operating mode.

12. The circuit of claim 11, wherein the control logic circuit device switches from the first operating mode to the second operating mode in response to receiving a standby signal.

13. The circuit according to claim 11, further comprising: A current sensing circuit device is configured to sense the intensity of the current flowing through the electrical load; and The control logic circuit device is configured to switch from the first operating mode to the second operating mode in response to the current sensing circuit device detecting that the current flowing through the electrical load has dropped to a lower threshold.

14. The circuit of claim 13, wherein the current sensing circuit device includes a sensing transistor having a control node and a current path, the control node being shared with the control node of the first transistor, and the current path being included in a current feedback line.

15. The circuit according to claim 13, further comprising: A current sensing circuit device is configured to sense the current intensity flowing through the electrical load; and The control logic circuit device is configured to switch from the second operating mode to the first operating mode in response to the current sensing circuit device detecting that the current flowing through the electrical load increases to an upper limit threshold.

16. The circuit of claim 11, wherein the first transistor is a higher power transistor and the second transistor is a lower power transistor.

17. The circuit of claim 11, wherein the first transistor has a first conductivity type and the second transistor has a second conductivity type.

18. The circuit of claim 11, wherein the second transistor is integrated into the control circuit, and the first transistor is located outside the control circuit.

Images