Programming methods for storage devices, storage devices and storage systems

Abstract

This application discloses a programming method, storage device, and storage system for a storage device. The storage device includes multiple planes. The method includes: programming at least two of the multiple planes using a programming voltage that increases in a first-step increment; verifying the at least two planes; disabling the plane with the verification error when it is determined that there is one of the at least two planes; and programming the non-disabled plane using a programming voltage that increases in a second-step increment when one of the at least two planes is disabled; wherein the second-step increment is smaller than the first-step increment.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a programming method for a memory device, a memory device, and a memory system. Background Technology

[0002] Non-volatile memory is widely used in personal computers, telecommunications, consumer electronics, and other fields. Electrically erasable programmable read-only memory (EEPROM) and flash memory are among the most widely used non-volatile memories.

[0003] Based on their structural configuration, memory devices can be categorized into single-plane and multi-plane types. Single-plane memory devices consist of memory arrays organized into a single plane, while multi-plane memory devices consist of memory arrays organized into multiple planes. When programming multi-plane memory devices, two or more planes can be programmed simultaneously to improve programming efficiency; this method of programming two or more planes simultaneously is called multi-plane programming. Summary of the Invention

[0004] In a first aspect, embodiments of this application provide a programming method for a storage device, the storage device comprising a plurality of planes; the method includes:

[0005] At least two of the plurality of planes are programmed using a programming voltage that increases in increments from the first step.

[0006] If the at least two planes are verified and it is determined that there is a plane with a verification error among the at least two planes, then the plane with the verification error is disabled.

[0007] When one of the at least two planes is disabled, the non-disabled plane is programmed using a programming voltage that increases in a second-step increment;

[0008] The second step increment is smaller than the first step increment.

[0009] In one alternative implementation, the second step increment is determined based on the number of disabled planes.

[0010] In one alternative implementation, each of the planes includes a plurality of memory cells arranged in rows and columns; the programming of at least two of the plurality of planes using a programming voltage increased in increments of the first step includes:

[0011] Using a programming voltage that increases in increments from the first step, a plurality of selected memory cells in at least two of the plurality of planes are programmed.

[0012] In an optional implementation, the method further includes:

[0013] When programming at least two of the plurality of planes using a programming voltage that increases in increments from the first step, a pass voltage that increases in increments from the third step is applied to a plurality of unselected memory cells in the plurality of planes.

[0014] In an optional implementation, the method further includes:

[0015] When programming the undisabled plane using a programming voltage that increases in a second-step increment, a pass voltage that increases in a fourth-step increment is applied to a plurality of unselected memory cells in the undisabled plane;

[0016] The fourth step increment is less than the third step increment.

[0017] In one optional implementation, the range of the first step increment is 0.15V-0.5V, and the range of the second step increment is 0.1V-0.45V.

[0018] In one optional implementation, when the number of disabled planes is a first value, the second step increment is a second value; when the number of disabled planes is a third value, the second step increment is a fourth value; wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the third value.

[0019] In one optional implementation, the step of verifying the at least two planes to determine that there is a plane with a verification anomaly among the at least two planes includes:

[0020] Each of the at least two planes is verified to verify whether the plane has reached a predetermined programming state; when the number of verifications of a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with a verification anomaly among the at least two planes.

[0021] In an optional implementation, the method further includes:

[0022] When at least two planes are disabled, programming of the at least two planes is terminated.

[0023] Secondly, embodiments of this application provide a storage device, including:

[0024] A storage array that includes multiple planes;

[0025] A row driver for applying a programming voltage that increases in a first-step increment to at least two of the plurality of planes;

[0026] A control logic circuit is used to verify the at least two planes, and when it is determined that there is a plane with verification anomalies among the at least two planes, the plane with verification anomalies is disabled.

[0027] The row driver is also configured to program the non-disabled planes using a programming voltage increased in a second-step increment when one of the at least two planes is disabled.

[0028] The second step increment is smaller than the first step increment.

[0029] In one alternative implementation, the second step increment is determined based on the number of disabled planes.

[0030] In one alternative implementation, each of the planes includes a plurality of memory cells arranged in rows and columns; the row driver is specifically configured to apply a programming voltage, incremented by a first step, to a plurality of memory cells selected in at least two of the plurality of planes.

[0031] In one alternative implementation, the row driver is further configured to apply a pass voltage that is increased in a third step increment to a plurality of unselected memory cells in at least two of the plurality of planes.

[0032] In an alternative implementation, the row driver is further configured to apply a pass voltage that is increased in a fourth step increment to a plurality of unselected memory cells in the plane that are not disabled;

[0033] The fourth step increment is less than the third step increment.

[0034] In one optional implementation, the range of the first step increment is 0.15V-1V, and the range of the second step increment is 0.1V-0.45V.

[0035] In one optional implementation, when the number of disabled planes is a first value, the second step increment is a second value; when the number of disabled planes is a third value, the second step increment is a fourth value; wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the third value.

[0036] In one optional implementation, the control logic circuit is specifically configured to verify each of the at least two planes to verify whether the plane has reached a predetermined programming state; when the number of verifications of a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with verification anomalies among the at least two planes.

[0037] In an alternative implementation, the control logic circuit is further configured to terminate programming of the at least two planes when both planes are disabled.

[0038] Thirdly, embodiments of this application provide a storage system, including:

[0039] One or more storage devices as described in any one of the second aspects; and

[0040] A storage controller coupled to the storage device. Attached Figure Description

[0041] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0042] Figure 1 A timing diagram of multi-plane programming provided for embodiments of this application;

[0043] Figure 2 A schematic diagram of the implementation flow of a programming method for a storage device provided in this application embodiment. Figure 1 ;

[0044] Figure 3 Programming voltage timing diagrams for single-plane programming and multi-plane programming provided in embodiments of this application;

[0045] Figure 4 Schematic diagram of the implementation flow of the programming method for the storage device provided in the embodiments of this application Figure 2 ;

[0046] Figure 5 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of a storage cell array provided in an embodiment of this application. Detailed Implementation

[0048] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0049] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0050] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0051] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] To achieve more precise control over the threshold voltage distribution of the programmed memory cells, incremental step pulse programming (ISPP) mode is frequently used. In ISPP mode, the programming voltage applied to the word line gradually increases during repeated programming cycles. The programming voltage increases in a predetermined step increment (ΔV), also known as the "rise rate." In the programming sequence, the cell threshold voltage of the programmed memory cell increases at a predetermined rate for each programming cycle. For programming non-volatile memory devices, each programming cycle typically includes a programming period and a programming check period. During the programming period, the selected memory cell is programmed under a given bias condition, and the programming voltage is applied to the corresponding word line. During the programming check period, the programmed memory cell is checked to see if it has reached the target threshold voltage condition. The programming check operation is similar to the read operation, except that the read data is not output to the outside of the device.

[0054] In this embodiment of the application, during the ISPP programming process, after each application of the programming voltage, the threshold voltage Vth of some memory cells will be greater than the verification voltage Vverify, while the threshold voltage Vth of other memory cells will still be less than the verification voltage Vverify. After increasing the programming voltage multiple times and performing programming, the threshold voltage Vth of all the memory cells within the set range will eventually be greater than the verification voltage Vverify, thereby completing the programming process.

[0055] During the verification operation, a verification voltage Vverify is applied to the word line corresponding to the programmed memory cell to verify whether the programmed memory cell has reached the target threshold voltage. If it has not reached the threshold, the selected memory cell is verified as a failure; if it has reached the threshold, the selected memory cell is verified as a success.

[0056] Figure 1 A timing diagram of multi-plane programming provided for embodiments of this application, such as... Figure 1 As shown, in multi-plane programming, the programming speed is determined by the slowest plane. Therefore, when the programming speed of the slowest plane is much lower than that of other planes, the other planes are easily disturbed by neighboring planes (NPD).

[0057] Therefore, this application proposes the following embodiments. Embodiments of this application provide a programming method for a storage device. Figure 2 A schematic diagram of the implementation flow of a programming method for a storage device provided in this application embodiment. Figure 1 The storage device includes multiple planes; such as Figure 2 As shown, the method includes the following steps:

[0058] Step 210: Program at least two of the plurality of planes using a programming voltage that is increased in increments from the first step;

[0059] Step 220: Verify the at least two planes, and if it is determined that there is a plane with verification anomalies among the at least two planes, disable the plane with verification anomalies;

[0060] Step 230: When at least one of the at least two planes is disabled, the non-disabled plane is programmed using a programming voltage that increases in a second step increment; wherein the second step increment is less than the first step increment.

[0061] In this embodiment, the storage unit can be a Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), Quad-Level Cell (QLC), Penta-Level Cell (PLC), or a higher level type. Each SLC unit can store 1 bit of data, each MLC unit can store 2 bits of data, each TLC unit can store 3 bits of data, each QLC unit can store 4 bits of data, and each PLC unit can store 5 bits of data. Each storage unit can hold one of Q possible data states, where Q is a positive integer equal to or greater than 2. For example, for SLC, Q = 2; for MLC, Q = 4; for TLC, Q = 8; for QLC, Q = 16; and for PLC, Q = 32. The Q possible data states can include an erase state S(0) and programming states S(1) to S(Q-1), where programming state S(1) is the lowest programming state and programming state S(Q-1) is the highest programming state. In one example, the TLC can be programmed into one of eight possible data states, where programming state S(1) is the lowest programming state and programming state S(7) is the highest programming state.

[0062] A memory cell can be initially set to an erase state S(0), and then a series of programming and verification operations can be performed on the memory cell to program it to the corresponding target programming state. The series of programming and verification operations can start from the lowest programming state S(1) and proceed to higher programming states until the threshold voltage Vth of the selected memory cell reaches the corresponding verification voltage level of the corresponding target programming state. In some embodiments, the minimum threshold voltage of the threshold voltage distribution curves of programming states S(1) to S(Q-1) can be used as the verification voltages of programming states S(1) to S(Q-1), respectively. Each programming cycle can include a programming operation and a subsequent verification operation. In the programming operation, some memory cells can be selected and programmed into the programming state in a row-by-row manner from the first row to the Nth row, or from the Nth row to the first row. In the subsequent verification operation, the selected memory cells can be verified to have reached the programming state in a row-by-row manner from the first row to the Nth row, or from the Nth row to the first row. In this way, the memory cell can be programmed to the corresponding target programming state.

[0063] This embodiment uses multi-plane programming of four planes as an example for illustration. It should be noted that the number of planes included in the storage device can be greater than or equal to four.

[0064] In this embodiment, the second step increment ΔV2 can be determined based on the number of disabled planes. Specifically: the four planes are programmed using a programming voltage increased by the first step increment ΔV1; after verifying each plane, if a plane with verification anomalies is found among the four planes, the plane with verification anomalies is disabled; at this time, the second step increment ΔV2 can be determined based on the number of disabled planes. In some embodiments, when the number of disabled planes is a first value, the second step increment is a second value; when the number of disabled planes is a third value, the second step increment is a fourth value; wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the third value. For example, when the number of disabled planes is 1, the second step increment ΔV2 can be 0.15V; when the number of disabled planes is 2, the second step increment ΔV2 can be 0.1V; when the number of disabled planes is 3, the second step increment ΔV2 can be 0.05V. Here, the second step increment ΔV2 can decrease as the number of disabled planes increases.

[0065] Here, the specific process of programming the four planes using a programming voltage increased by the first step increment ΔV1 is as follows: The four planes are programmed using an initial programming voltage, and then the initial programming voltage is increased by the first step increment ΔV1, i.e., the four planes are programmed again using the initial programming voltage + ΔV1, and so on, until the selected memory cell in the four planes reaches the predetermined programming state or the target programming state. It should be noted that during the programming process using a programming voltage increased by the first step increment ΔV1, a verification operation can be performed after each application of the programming voltage, or a verification operation can be performed after every Z applications of the programming voltage. Z is greater than or equal to 2.

[0066] In this embodiment, each of the at least two planes is verified to determine whether it has reached a predetermined programming state. If the number of verifications for a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with a verification anomaly among the at least two planes. Here, the predetermined number of verifications is the maximum failure count corresponding to the predetermined programming state. The failure count is the count of the number of times the plane verification failed.

[0067] In this embodiment of the application, for each plane, when the number of verifications for the plane has not reached a predetermined number and the plane has not reached the predetermined programming state, the number of verifications is incremented.

[0068] In this embodiment, each plane includes a plurality of memory cells arranged in rows and columns. When programming a plurality of selected memory cells in the four planes using a programming voltage increased by a first-step increment ΔV1, a pass voltage increased by a third-step increment ΔV3 is applied to a plurality of memory cells not selected in at least two of the plurality of planes. For example, during the programming process of a predetermined programming state S(q), an initial programming voltage Vpgm1 is applied to multiple selected memory cells in the four planes, while an initial pass voltage Vpass1 is applied to multiple unselected memory cells in the four planes. After verification, programming operations continue for memory cells that failed verification (failed to reach the predetermined programming state S(q)). A second programming voltage Vpgm2 = Vpgm1 + ΔV1 is applied to multiple memory cells in the four planes that did not reach the predetermined programming state S(q), while a second pass voltage Vpass2 = Vpass1 + ΔV3 is applied to multiple unselected memory cells in the four planes; ..., until all selected memory cells in the four planes reach the predetermined programming state S(q) or a plane with a verification anomaly exists. Here, the initial programming voltage Vpgm1 and the initial pass voltage Vpass1 are the initial programming voltage and the initial pass voltage corresponding to the predetermined programming state S(q).

[0069] In this embodiment, when one of the four planes is disabled, a programming voltage increased by a second step increment ΔV2 is used to program the undisabled plane. Simultaneously, a pass voltage increased by a fourth step increment ΔV4 is applied to multiple unselected memory cells in the undisabled plane; wherein the fourth step increment ΔV4 is less than the third step increment ΔV3. Here, the undisabled plane is the plane that has reached a predetermined programming state S(q). If the predetermined programming state S(q) is not the target programming state, then the predetermined programming state S(q) is set to the next programming state S(q+1). For example, during programming in a predetermined programming state S(q+1), an initial programming voltage Vpgm1 is applied to multiple selected memory cells in the non-disabled plane, while an initial pass voltage Vpass1 is applied to multiple unselected memory cells in the non-disabled plane. After verification, programming operations continue for memory cells that failed verification (failed to reach the predetermined programming state). A second programming voltage Vpgm2 = Vpgm1 + ΔV2 is applied to multiple memory cells in the non-disabled plane that did not reach the predetermined programming state S(q+1), while a second pass voltage Vpass2 = Vpass1 + ΔV4 is applied to multiple unselected memory cells in the non-disabled plane; ..., until all selected memory cells in the non-disabled plane reach the predetermined programming state S(q+1) or a verification anomaly occurs in the non-disabled plane. Here, the initial programming voltage Vpgm1 and the initial pass voltage Vpass1 are the initial programming voltage and initial pass voltage corresponding to the predetermined programming state S(q+1).

[0070] In this embodiment, for each plane, it is verified whether the selected multiple memory cells have reached a predetermined programming state. If more than a preset number of the selected multiple memory cells fail to reach the predetermined programming state, the plane verification fails; if less than a preset number of the selected multiple memory cells fail to reach the predetermined programming state, the plane verification passes.

[0071] In this embodiment, the range of the first step increment is 0.15V-0.5V, and the range of the second step increment is 0.1V-0.45V. In one embodiment, the first step increment is approximately 0.1V higher than the second step increment. In another embodiment, the difference between the first step increment and the second step increment is 0.07V. In yet another embodiment, the difference between the first step increment and the second step increment is 0.13V, 0.15V, or 0.18V.

[0072] In this embodiment of the application, programming of the at least two planes is terminated when at least two planes are disabled. For example, when all four planes are disabled, multi-plane programming of the four planes is terminated.

[0073] Figure 3 The programming voltage timing diagrams for single-plane and multi-plane programming provided in embodiments of this application are shown. The horizontal axis represents time, and the vertical axis represents voltage. Analysis Figure 3 The programming process reveals that the programming voltage Vpgm changes faster in single-plane programming mode, meaning the charging time for Vpgm in single-plane programming mode is shorter than that in multi-plane programming mode. Therefore, at the same programming voltage Vpgm, the hold time for Vpgm in multi-plane programming mode is shorter than that in single-plane programming mode. In other words, multi-plane programming requires a longer charging time compared to single-plane programming. Based on this, in the multi-plane programming model, when a plane is disabled (i.e., the number of programmed planes decreases), the charging time of the programming voltage Vpgm for subsequent planes will decrease, while their hold time will increase, leading to an increase in programming time. Therefore, in this case, reducing the programming voltage step increment (reducing the programming voltage) balances the charging and hold times of the programming voltage Vpgm for each plane, thereby controlling the overall programming time and improving programming efficiency.

[0074] Figure 4 Schematic diagram of the implementation flow of the programming method for the storage device provided in the embodiments of this application Figure 2 ,like Figure 4 As shown, the method includes the following steps:

[0075] Step 410: Programming preparation.

[0076] Step 420: Apply programming voltage to selected memory cells in the multiple planes; apply pass voltage to unselected memory cells in the multiple planes.

[0077] Step 430: Verify multiple planes to determine if there are any planes with verification anomalies; if yes, proceed to step 440; if no, proceed to step 420.

[0078] Step 440: Determine if all planes have verification anomalies; if yes, proceed to step 490; if no, proceed to step 450.

[0079] Step 450: Disable the plane with the verification anomaly and reduce the step increment of the programming voltage and the pass voltage.

[0080] Step 460: Determine if the programming state is the target programming state; if not, proceed to step 470; if yes, proceed to step 480.

[0081] Step 470: Increment the programming state, and execute step 420 in parallel for those that are not disabled.

[0082] Step 480: Multiplane programming passed.

[0083] Step 490: Multiplane programming failed.

[0084] This embodiment uses multi-plane programming of four planes as an example, with TLC memory cells as the storage units. During multi-plane programming, four planes in the storage device are programmed. Programming voltages are applied to selected memory cells in the four planes, and pass voltages are applied to unselected memory cells in the four planes.

[0085] The selected memory cells in the four planes are verified to determine whether they have reached a predetermined programming state S(1). If more than a preset number of memory cells fail to reach the predetermined programming state S(1), the plane verification fails. If fewer than a preset number of memory cells fail to reach the predetermined programming state S(1), the plane verification passes.

[0086] If plane verification fails, the next step is to determine whether the verification failure count is less than the maximum failure count (predetermined number of times) of programming state S(1). In some embodiments, the maximum failure count can be 4. If the verification failure count is less than the maximum failure count, the verification failure count is incremented by 1. When the verification failure count is not less than the maximum failure count, it is determined that there is a plane with verification anomaly among the four planes. At this time, the plane with verification anomaly is disabled, and the step increment of programming voltage and pass voltage is reduced.

[0087] For planes that are not disabled, determine whether their programming state is the target programming state; if the programming state is not the target programming state, increment the programming state, that is, the programming state is incremented to S(2). Program the planes that are not disabled to programming state S(2) with the reduced programming voltage and the step increment of the through voltage. Here, if the step increment of the programming voltage and the step increment of the through voltage in the programming process of programming state S(1) are the first step increment and the third step increment respectively, and the step increment of the programming voltage and the step increment of the through voltage in the programming process of programming state S(2) are the second step increment and the fourth step increment respectively, then the second step increment is lower than the first step increment, and the fourth step increment is less than the third step increment.

[0088] Here, the programming process of programming state S(2) is similar to that of programming state S(2), so it will not be described again. If there is a plane with a verification error during the programming process of programming state S(2), the plane with the verification error is disabled, and the step increment of programming voltage and through voltage is reduced. The programming state is incremented to S(3). The planes that are not disabled are programmed with programming state S(3) using the step increment of programming voltage and through voltage reduced again. Here, if the step increment of programming voltage and through voltage in the programming process of programming state S(2) is the second step increment and the fourth step increment respectively, and the step increment of programming voltage and through voltage in the programming process of programming state S(3) is the fifth step increment and the sixth step increment respectively, then the fifth step increment is lower than the second step increment, and the sixth step increment is less than the fourth step increment.

[0089] If the current programming state S(3) is the target programming state, then the multi-plane programming is successful, and the multi-plane programming process ends. It should be noted that during this multi-plane programming process, only the planes that have not encountered any verification exceptions (and have not been disabled) have completed programming.

[0090] It should be noted that if any plane has a verification anomaly during the above process, the multi-plane programming will fail and the multi-plane programming will be terminated.

[0091] In some embodiments, the control logic circuitry may generate a status report indicating the programming result upon exiting the programming loop. The status report may indicate programming success when at least one of the multiplanes completes programming to its highest state. The status report may indicate programming failure when all multiplanes are disabled before completing programming to their highest state. The status report may be sent to the host or the memory controller.

[0092] The technical solution provided in this application offers a programming method for a storage device. When programming multiple planes with a first-step incremental programming voltage, if the plane verification reaches a predetermined number of times, subsequent programming of that plane is prohibited. During subsequent programming, the programming voltage increment is reduced, and the non-disabled planes are programmed with a second-step incremental programming voltage. In this embodiment, disabling planes that fail verification reduces programming interference during multi-plane programming. When a plane is disabled in the multi-plane programming process, a reduced programming voltage increment is used to balance the charging and holding times of the programming voltage.

[0093] Based on the same technical concept as the programming method of the aforementioned storage device, embodiments of this application provide a storage device. Figure 5 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application, such as... Figure 5 As shown, the storage device 500 includes:

[0094] Includes a storage array with multiple 510 planes;

[0095] A row driver 520 is used to apply a programming voltage that increases in a first-step increment to at least two of the plurality of planes;

[0096] The control logic circuit 530 is used to verify the at least two planes, and when it is determined that there is a plane with verification anomalies among the at least two planes, the plane with verification anomalies is disabled.

[0097] The row driver 520 is also configured to program the non-disabled planes using a programming voltage increased in a second-step increment when a plane is disabled in one of the at least two planes;

[0098] The second step increment is smaller than the first step increment.

[0099] It should be noted that, Figure 5 The following description uses a storage device 500 with a dual-plane structure as an example. The storage device 500 may include peripheral circuitry; wherein, the peripheral circuitry may include: control logic circuitry 530, voltage generation circuitry 540, row driver 520, and column driver 550. Although a dual-plane structure is used in this embodiment, it should be understood that other numbers of planes may be used within the scope of this application. When using a multi-plane programming mode, plane 510 can be programmed simultaneously.

[0100] In some embodiments, the storage device 500 includes peripheral circuitry and a storage array comprising a plurality of planes 510; the peripheral circuitry is configured to: apply a programming voltage that increases in a first-step increment to at least two of the plurality of planes; verify the at least two planes and, if a plane with a verification anomaly is determined to exist among the at least two planes, disable the plane with the verification anomaly; and, if a plane among the at least two planes is disabled, program the plane that is not disabled using a programming voltage that increases in a second-step increment; wherein the second-step increment is less than the first-step increment.

[0101] In practical applications, control logic circuit 530 can be coupled to voltage generation circuit 540, row driver 520, and column driver 550. Voltage generation circuit 540 can be coupled to row driver 520. Row driver 520 can be coupled to plane 510 via drain select line DSL1, word lines WL1(1) to WL1(N), and serial select line SSL1, where N is a positive integer, for example, N = 128. Row driver 12 can be coupled to another plane 510 via drain select line DSL2, word lines WL2(1) to WL2(N), and serial select line SSL2. Column driver 550 can be coupled to plane 510 via bit lines BL1(1) to BL1(M), where M is a positive integer, for example, M = 131072. Column driver 550 can be coupled to another plane 510 via bit lines BL2(1) to BL2(M). Each of planes 510 can contain multiple blocks, each block can contain multiple pages, and each page can contain multiple memory cells. Memory cells in plane 510 can be addressed via word lines WL1(1) to WL1(N) and bit lines BL1(1) to BL1(M), and memory cells in another plane 510 can be addressed via word lines WL2(1) to WL2(N) and bit lines BL2(1) to BL2(M).

[0102] Control logic circuit 530 can communicate with the host or memory controller to receive data for storage in plane 510 and send data acquired from plane 510. Control logic circuit 530 can receive commands, addresses, or data from the host or memory controller and generate column address signals Scadr1, Scadr2, row address signal Sradr, and voltage control signal Svc. In response to the voltage control signal Svc from control logic circuit 530, voltage generation circuit 540 can generate voltages for read, program, erase, and verify operations. The voltage generated by voltage generation circuit 540 may exceed the power supply voltage provided to the storage device. Row driver 520 can operate in response to the row address signal Sradr from control logic circuit 530 to select word lines for read, program, erase, and verify operations. Column driver 550 can operate in response to the column address signals Scadr1 and Scadr2 from control logic circuit 530 to generate bit line signals to select bit lines for read, program, erase, and verify operations.

[0103] In this embodiment, the row driver 520, the column driver 550, and the plurality of planes 510 are all coupled and controlled by the control logic circuit 530. The row driver is configured to apply word line drive voltages to at least two planes that are simultaneously performing programming operations in multi-plane programming mode.

[0104] In practical applications, the control logic circuit 530 controls the voltage generation circuit to output a low-level initial programming voltage / initial turn-on voltage, and controls the row driver to apply the initial programming voltage to the selected word lines in the plane, and to apply the initial turn-on voltage to the unselected word lines.

[0105] In this embodiment of the application, the second step increment is determined based on the number of disabled planes.

[0106] In this embodiment of the application, each of the planes 510 includes a plurality of memory cells arranged in rows and columns; the row driver 520 is specifically configured to apply a programming voltage that increases in a first-step increment to a plurality of memory cells selected in at least two of the plurality of planes.

[0107] In this embodiment of the application, the row driver 520 is further configured to apply a pass voltage that is increased in a third step increment to a plurality of memory cells that are not selected in at least two of the plurality of planes.

[0108] In this embodiment of the application, the row driver 520 is further configured to apply a pass voltage that is increased by a fourth step increment to a plurality of unselected memory cells in the plane that are not disabled; wherein the fourth step increment is less than the third step increment.

[0109] In this embodiment of the application, the range of the first step increment is 0.15V-0.5V, and the range of the second step increment is 0.1V-0.45V.

[0110] In this embodiment of the application, the control logic circuit 530 is specifically used to verify each of the at least two planes to verify whether the plane has reached a predetermined programming state; when the number of verifications of a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with verification anomalies among the at least two planes.

[0111] In this embodiment of the application, the control logic circuit 530 is further configured to terminate the programming of the at least two planes when both planes are disabled.

[0112] It should be noted that the description of the storage device above is similar to the description of the programming method embodiment of the storage device above, and has similar beneficial effects as the programming method embodiment of the storage device, therefore, it will not be repeated. For technical details not disclosed in the storage device of the embodiments of this application, please refer to the description of the programming method of the storage device in the embodiments of this application for understanding.

[0113] Figure 6 This is a schematic diagram of a memory cell array provided in an embodiment of this application. Each plane may contain multiple blocks. Memory cells in the memory cell array can be addressed via word lines (WL) and bit lines (BL). Figure 6 As shown, the memory cell array may include multiple memory cells 310, a serial select unit 320, and a ground select unit 330. Memory cell 310 may be a floating-gate transistor or a charge-trapping transistor, and each of the memory cell 310, serial select unit 320, and ground select unit 330 may include a control terminal, a first terminal, and a second terminal. A drain select line DSL may be coupled to the control terminal of the serial select unit 320, and bit lines BL may be coupled to the first terminal of the serial select unit 320. Memory cells 310 may be arranged to be coupled to rows of memory cells corresponding to word lines WL. Word lines WL may be coupled to the control terminals of memory cells in the first row and to the control terminals of memory cells in the Nth row, and the first terminals of memory cells 310 may be coupled to the second terminals of the serial select unit 320. A serial select line SSL may be coupled to the control terminal of the ground select unit 330, the first terminal of the ground select unit 330 may be coupled to the second terminal of the memory cell 310, and the second terminal of the ground select unit 330 may be coupled to the common-source line CSL. The common source line (CSL) can provide ground voltage.

[0114] This application also provides a storage system, including the aforementioned storage device; and a storage controller coupled to the storage device.

[0115] In some embodiments, the storage device may specifically be a 3D NAND memory.

[0116] Specifically, the storage system can be a device with storage capabilities, such as a computer, smartphone, smart TV, smart set-top box, smart router, digital camera, or SSD. The storage system of this application typically also includes a controller, input / output devices, and a display device. The storage device is used to store files or data and is accessible to the controller. Specifically, the storage controller can write data to and read data from the storage device (i.e., the storage device provided in this application). The input / output devices are used to input instructions or output signals, and the display device visualizes the signals, thus realizing the various functions of the storage system.

[0117] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0118] The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A programming method for a storage device, the storage device comprising a plurality of planes; the method comprising: At least two of the plurality of planes are programmed using a programming voltage that increases in increments from the first step. If the at least two planes are verified and it is determined that there is a plane with a verification error among the at least two planes, then the plane with the verification error is disabled. When one of the at least two planes is disabled, the non-disabled plane is programmed using a programming voltage that increases in a second-step increment; The second step increment is less than the first step increment, and the second step increment is determined based on the number of disabled planes.

2. The programming method for the storage device according to claim 1, wherein, When the number of disabled planes is a first value, the second step increment is a second value; when the number of disabled planes is a third value, the second step increment is a fourth value; wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the third value.

3. The programming method for the storage device according to claim 1, wherein, Each of the planes includes a plurality of memory cells arranged in rows and columns; the programming of at least two of the plurality of planes using a programming voltage increased in increments of the first step includes: Using a programming voltage that increases in increments from the first step, a plurality of selected memory cells in at least two of the plurality of planes are programmed.

4. The programming method for the storage device according to claim 3, wherein, The method further includes: When programming at least two of the plurality of planes using a programming voltage that increases in increments from the first step, a pass voltage that increases in increments from the third step is applied to a plurality of unselected memory cells in the plurality of planes.

5. The programming method for the storage device according to claim 4, wherein, The method further includes: When programming the undisabled plane using a programming voltage that increases in a second-step increment, a pass voltage that increases in a fourth-step increment is applied to a plurality of unselected memory cells in the undisabled plane; The fourth step increment is less than the third step increment.

6. The programming method for the storage device according to claim 1, wherein, The range of the first step increment is 0.15V-0.5V, and the range of the second step increment is 0.1V-0.45V.

7. The programming method for the storage device according to claim 1, wherein, The step of verifying the at least two planes to determine if there is a plane with a verification anomaly includes: Each of the at least two planes is verified to verify whether the plane has reached a predetermined programming state; when the number of verifications of a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with a verification anomaly among the at least two planes.

8. The programming method for the storage device according to claim 1, wherein, The method further includes: When at least two planes are disabled, programming of the at least two planes is terminated.

9. A storage device, comprising: A storage array that includes multiple planes; A row driver for applying a programming voltage that increases in a first-step increment to at least two of the plurality of planes; A control logic circuit is used to verify the at least two planes, and when it is determined that there is a plane with verification anomalies among the at least two planes, the plane with verification anomalies is disabled. The row driver is also configured to program the non-disabled planes using a programming voltage increased in a second-step increment when one of the at least two planes is disabled. The second step increment is less than the first step increment, and the second step increment is determined based on the number of disabled planes.

10. The storage device according to claim 9, wherein, When the number of disabled planes is a first value, the second step increment is a second value; when the number of disabled planes is a third value, the second step increment is a fourth value; wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the third value.

11. The storage device according to claim 9, wherein, Each of the planes includes a plurality of memory cells arranged in rows and columns; the row driver is specifically configured to apply a programming voltage, which is increased in increments of the first step, to a plurality of memory cells selected in at least two of the plurality of planes.

12. The storage device according to claim 11, wherein, The row driver is also configured to apply a pass voltage that is increased in a third step increment to a plurality of unselected memory cells in at least two of the plurality of planes.

13. The storage device according to claim 12, wherein, The row driver is also configured to apply a pass voltage that is increased in a fourth step increment to a plurality of unselected memory cells in the plane that are not disabled; The fourth step increment is less than the third step increment.

14. The storage device according to claim 9, wherein, The range of the first step increment is 0.15V-1V, and the range of the second step increment is 0.1V-0.45V.

15. The storage device according to claim 9, wherein, The control logic circuit is specifically used to verify each of the at least two planes to verify whether the plane has reached a predetermined programming state; when the number of verifications of a plane reaches a predetermined number and the plane has not reached the predetermined programming state, it is determined that there is a plane with verification anomalies among the at least two planes.

16. The storage device according to claim 9, wherein, The control logic circuit is also configured to terminate programming of the at least two planes when both planes are disabled.

17. A storage system, comprising: One or more storage devices as described in any one of claims 9 to 16; as well as A storage controller coupled to the storage device.

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