Memory management method and device, storage system and computer readable medium

Abstract

The application discloses a memory management method and device, a storage system and a computer readable medium, and relates to the technical field of mobile terminals. The method comprises the following steps: determining a target pre-erasing mode in an automatic mode and an active mode. In the automatic mode, the memory automatically performs a pre-erasing operation on the memory. In the active mode, the memory performs a pre-erasing operation based on an instruction sent by the host. A pre-erasing operation is performed on the memory based on the target pre-erasing mode. Therefore, for the automatic pre-erasing mode and the host-triggered pre-erasing mode, one of the two modes can be freely selected to perform a pre-erasing operation in the automatic mode and the active mode, so that the pre-erasing operation is more reasonable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mobile terminals, and more particularly, to a memory management method and device, a storage system, and a computer readable medium. BACKGROUND

[0002] Currently, in flash memory, especially in NAND type flash memory, a pre-erase operation is usually required to be performed. Generally, when the current block is full of data and switches to a new block, the new block is first erased and then data is written. SUMMARY

[0003] The present application provides a memory management method and device, a storage system, and a computer readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a memory management method applied to a host of a storage system, wherein the storage system further comprises a memory, and the host is connected to the memory. The method comprises: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; and performing a pre-erase operation on the memory based on the target pre-erase mode.

[0005] In a second aspect, the present application further provides a memory management device applied to a host of a storage system, wherein the storage system further comprises a memory, and the host is connected to the memory. The device comprises: a determination unit and an erasing unit. The determination unit is configured to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host. The erasing unit is configured to perform a pre-erase operation on the memory based on the target pre-erase mode.

[0006] In a third aspect, the present application further provides a storage system, comprising: a host; a memory; the host is connected to the memory, and the host is configured to perform the above-mentioned method.

[0007] In a fourth aspect, the present application further provides a computer readable medium, wherein the readable storage medium stores a program code executable by a processor, and the program code, when executed by the processor, causes the processor to perform the above-mentioned method.

[0008] The memory management method, device, storage system and computer readable medium provided by the application determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the storage system automatically performs a pre-erase operation on the storage system, in the active mode, the storage system performs a pre-erase operation based on an instruction sent by the host; and a pre-erase operation is performed on the storage system based on the target pre-erase mode. Therefore, for the automatic pre-erase mode and the host triggered pre-erase mode, one of the automatic mode and the active mode can be freely selected to perform a pre-erase operation, so that the pre-erase operation is more reasonable.

[0009] Other features and advantages of the application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0011] Figure 1 A schematic diagram of the storage system provided by the embodiment of the application is shown;

[0012] Figure 2 A method flowchart of the memory management method provided by an embodiment of the application is shown;

[0013] Figure 3 An interaction schematic diagram of the automatic mode and the active mode provided by another embodiment of the application is shown;

[0014] Figure 4 An effect schematic diagram of the automatic mode and the active mode provided by another embodiment of the application is shown;

[0015] Figure 5 A format schematic diagram of the UPIP provided by an embodiment of the application is shown;

[0016] Figure 6 A schematic diagram of the EHS field provided by an embodiment of the application is shown;

[0017] Figure 7 A method flowchart of the memory management method provided by another embodiment of the application is shown;

[0018] Figure 8 A schematic diagram of the UPIP provided by another embodiment of the application is shown;Figure 7 a schematic diagram of the S780 step in FIG. 8;

[0019] Figure 9 A module block diagram of a memory management apparatus provided by an embodiment of the present application is shown;

[0020] Figure 10 A storage unit for storing or carrying program code for implementing the method according to the embodiments of the present application is shown. DETAILED DESCRIPTION

[0021] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0022] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] Currently, in flash memory, especially NAND type flash memory, it is usually necessary to perform a pre-erase operation. Generally, in a host system using a universal flash storage (UFS) as a storage device, the firmware of the UFS manages the medium (NAND flash) in units of virtual blocks (VB). When the UFS device switches to a new block after the current block is full, the new block is first subjected to an erase process (on the order of milliseconds), and then data is written (programmed). This is because the medium in the erase state has poor stability, and cannot be used for data writing after a certain period of time.

[0024] Pre-erase operation refers to a process of performing an erase operation on a block where data to be written is located before performing a flash memory write operation. This process is usually managed and performed by a controller. In NAND type flash memory, data can only be erased and written in blocks. Therefore, if new data is to be written to a block that already stores old data, the entire block needs to be erased first, and then the write operation is performed. This results in an operation process called "Erase-Write". The purpose of the pre-erase operation is to perform an erase operation on the block storing data in advance before performing the actual write operation, in order to reduce the write delay. In this way, the controller does not need to perform an erase operation when the actual write operation is performed, thereby speeding up the write speed of the memory and reducing the errors that may occur during writing. In actual applications, for flash memory, the pre-erase operation is usually managed and performed by the controller. When the controller receives a request for a write operation, it checks whether the block where the data is located has been erased. If the block has not been erased, the controller will automatically perform an erase operation before performing the write operation.

[0025] Due to the above-mentioned erase-before-write strategy, the flash memory (for example, a UFS device) cannot write for a certain number of milliseconds under heavy write pressure. Therefore, pre-erasing a part of the block to reduce the time spent on block switching can significantly improve the write performance of the device, while reducing the maximum delay caused by the erase action during the block switching process.

[0026] However, the inventors have found in their research that the current pre-erase scheme usually has the following disadvantages:

[0027] 1) Relatively fixed pre-erase capacity threshold: In the current device autonomous pre-erase scheme, the pre-erase capacity is determined by the device itself, and the pre-erase is performed to the set threshold when idle. In order to obtain greater performance benefits, the threshold should be as large as possible; but considering stability and the case of too few idle blocks, the threshold cannot be too large. Therefore, the device will choose a threshold that balances the benefits and risks. This threshold is relatively fixed and cannot adapt to changes in host write actions.

[0028] 2) Stability risk of pre-erased blocks: Currently, the device cannot know the host's write actions, and the pre-erase threshold is relatively fixed, so there will always be a part of pre-erased blocks in the device. When the host does not write for a period of time, the pre-erased blocks are prone to stability risks.

[0029] Therefore, it is extremely important to set a reasonable pre-erase strategy.

[0030] In order to overcome the above-mentioned defects, the embodiments of the present application provide a memory management method, which can adaptively adjust the pre-erase mode in combination with the actual data write situation of an electronic device.

[0031] It should be noted that the memory management method provided by the embodiments of the present application is applied to a system composed of a host using a flash memory, as shown in the figure, the storage system 10 includes a host 100 and a memory 200, the host 100 is connected with the memory 200. Exemplarily, the host 100 can be an electronic device, which can be a smartphone, a tablet computer, an electronic book and the like, which can run an application program. In the embodiments of the present application, the host 100 is a smartphone. The memory 200 can be the flash memory described above, for example, the memory 200 is UFS. Figure 1

[0032] It can be understood that the memory 200 can be the built-in memory of the host 100, that is, the memory 200 can be integrated into the mainboard of the host 100, used as the ROM of the smartphone, used for storing the operating system, the application program and the user data. In addition, the memory 200 can be the external memory of the host 100, that is, the peripheral of the host 100, for example, taking the memory 200 as UFS as an example, the host 100 is connected with the memory 200 through the USB interface, of course, the UFS storage device can also be designed as a plug-in storage card, similar to the traditional SD card or microSD card. In this way, the user can insert the UFS storage device into the USB interface of the smartphone, and transmit and access data through the USB interface. In the embodiments of the present application, whether the memory 200 is the external memory or the built-in memory of the host 100 is not limited, and the host is used to execute the embodiments described below.

[0033] Please refer to Figure 2 The method is applied to the host described above, in order to facilitate the description, the following embodiments are described taking the memory as UFS as an example, of course, the memory can also be other types, which are not limited, and the method includes S201 to S202.

[0034] S201: determining a target pre-erase mode in an automatic mode and an active mode.

[0035] ​As an implementation, the host can generally use two pre-erase modes, namely an automatic mode and an active mode. The automatic mode, namely Auto mode, in which the UFS automatically performs a pre-erase operation. When the host sends a write command, the UFS device automatically detects the state of the target physical block and performs an erase operation if necessary. In this mode, the host does not need to explicitly send a pre-erase command, and the erase operation is handled by the UFS device itself. The active mode, namely Host Trigger mode, in which the host needs to explicitly send a pre-erase command to trigger the erase operation. After the host sends the pre-erase command, the UFS device will perform the erase operation according to the requirements of the command. In this mode, the host can more accurately control when to perform the erase operation. That is, in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on the instructions sent by the host.

[0036] Please refer to Figure 3 , Figure 3 The difference between the automatic mode and the active mode is shown. In the automatic mode, the host sends a first erase instruction, namely Write(10)EHS:open auto pre erase, and the storage device enters the automatic mode in response to the first erase instruction. In the automatic mode, 2GB of idle physical blocks are pre-erased to obtain 2GB of pre-erase blocks, and then the host performs a write operation, namely Write cmds,use pre erase blocks, and the memory detects that the pre-erase blocks are used, and automatically pre-erases 2GB of idle physical blocks again, and so on, until the automatic mode is closed, namely Write(10)EHS:close auto pre erase. From the above, it can be seen that in the automatic mode, the pre-erase operation is automatically triggered by the host, and the pre-erase operation is triggered by the host according to the return information of the memory, which will be described in detail later. Figure 3 It can be seen that in the active mode, each pre-erase operation is actively triggered by the host, specifically, it can be actively triggered according to the return information of the memory, which will be described in detail later.

[0037] Specifically, the beneficial effects of the automatic mode and the active mode are as shown in Figure 4

[0038] ​As can be seen, the host trigger mode is fully controllable by the pre-erase host, which can effectively prevent the stability risk caused by the pre-erase block remaining, but the io coverage is lower than that of the auto mode, mainly because the host trigger mode triggers pre-erase after a large number of write ios, which has a certain lag and cannot guarantee that all ios enjoy the pre-erase benefit. Based on the foregoing condition for sending the second erase operation, it can be seen that the second erase instruction is sent only when the write rate is greater than the current first specified threshold. Therefore, before the write rate reaches the first specified threshold, multiple write operations may have been performed. As shown in Figure 4 , in the host trigger mode, the write operation in the time period filled with diagonal lines cannot enjoy the pre-erase benefit.

[0039] The auto mode has higher io coverage, but the host is not fully controllable. If it is always on, the erase block may not be used all the time, which may cause stability problems. Therefore, for the first scenario, it can be determined that there is a large amount of sequential writing, and the auto mode can be enabled to maximize the pre-erase benefit of the write operation. The io coverage refers to the ratio of the time period in which the write operation enjoys the pre-erase benefit to the entire time period of the write operation. The pre-erase benefit refers to the use of the pre-erase block by the write operation.

[0040] In this application, based on the characteristics of the foregoing host trigger mode and auto mode, a mode can be selected as the target pre-erase mode based on actual needs in the auto mode and the host trigger mode, so as to perform the pre-erase operation.

[0041] As an implementation, the embodiments of the present application can determine the target pre-erase mode based on the application scenario of the storage system. Exemplarily, the application scenario can be a scenario of writing data to the UFS of the storage system. As described above, the purpose of the pre-erase operation is to perform an erase operation on the data in the storage device before writing new data, so as to ensure the stability and security of data writing. Therefore, for different data write amounts, the capacity of the physical block of the pre-erase operation should be different. In order to make the pre-erase operation more reasonable, it is necessary to determine the current data writing situation of the storage system, that is, the application scenario, before determining the pre-erase operation mode.

[0042] As an implementation form, the application scenario can reflect the data write amount of the storage system at present or in a future time period, and therefore, a plurality of scenarios can be preset, and each scenario corresponds to different data write amount. The data write amount represents the data write amount that can occur in the scenario, for example, can be the maximum data write amount in the scenario, that is, the historical peak value of the data write amount in the scenario, or can be the historical average value of the data write amount in the scenario. Therefore, for different scenarios, the data amount in the UFS written before the current time can be determined by analyzing the historical time period, the data range of the data write amount corresponding to the current historical time period is determined by counting the data amount in the UFS written in the historical time period, and the current application scenario is determined based on the scenarios corresponding to the different data ranges preset.

[0043] As an implementation form, after determining the application scenario, the target pre-erase mode is determined in the automatic mode and the active mode based on the application scenario.

[0044] In the embodiments of the present application, the application scenario of the storage system can be divided into a first scenario and a second scenario, wherein the data write amount of the first scenario is greater than that of the second scenario. It should be noted that the preset data write amount represents the data write capability corresponding to the scenario, that is, the estimation of the maximum data write amount in the scenario.

[0045] It can be understood that in the embodiments of the present application, the first scenario is a scenario with a large amount of data write compared with the second scenario, that is, the storage system in the first scenario has the possibility of writing a large amount of data into the storage in sequence, and in the second scenario, the amount of data written into the storage is usually small.

[0046] As another implementation form, the target pre-erase mode can also be determined by the application program running on the host. For example, the application program running on the host is determined, and the target pre-erase mode is determined in the automatic mode and the active mode based on the running application program. Since different application programs have different write amount requirements and different write rate requirements, different application programs can have different requirements for the automatic mode and the active mode, and therefore, different application programs can correspond to different modes, so as to obtain a mode correspondence relationship, and based on the mode correspondence relationship, it can be determined whether the active mode or the automatic mode should be used for the current application program. Details will be described in subsequent embodiments.

[0047] In the embodiments of the present application, the different pre-erase modes correspond to different pre-erase strategies, which can specify the timing of the pre-erase operation, the capacity of the pre-erase block, and the like. The pre-erase block refers to a physical block in the memory on which the pre-erase operation is performed, and the capacity of the pre-erase block can refer to the number of physical blocks of a specified capacity in the memory on which the pre-erase operation is performed.

[0048] Therefore, by the above-described correspondence relationship, the pre-erase mode corresponding to the current application scenario of the storage system can be determined as the target pre-erase mode for the memory.

[0049] S202: performing a pre-erase operation on the memory based on the target pre-erase mode.

[0050] As described above, different pre-erase modes specify pre-erase strategies such as the timing of the pre-erase operation, the capacity of the pre-erase block, and the execution subject of the pre-erase operation. After the target pre-erase mode corresponding to the current application scenario of the storage system is determined, a pre-erase operation is performed on the memory based on the target pre-erase strategy corresponding to the target pre-erase mode. In subsequent embodiments, different pre-erase operations will be described according to different pre-erase modes.

[0051] It should be noted that after the target pre-erase mode is determined, a pre-erase instruction corresponding to the target pre-erase mode can be determined, and the pre-erase instruction is sent to the memory to enable the memory to perform a pre-erase operation based on the pre-erase instruction. In the embodiments of the present application, the host can send a pre-erase instruction to the memory in three ways.

[0052] The first way is to add the pre-erase instruction in a preset field of a specified instruction to be sent to the memory to obtain a target instruction, and send the target instruction to the memory to enable the memory to perform a pre-erase operation based on the pre-erase instruction. The specified instruction to be sent to the memory can be a write or read instruction currently required by the host to send to the memory, i.e., a WRITE / READ instruction. The preset field can be an EHS field or other field of the specified instruction.

[0053] In the embodiments of the present application, the specified instruction is a read or write instruction in a UFS protocol information unit (UPIU), and the preset field is an extra header segment (EHS). As shown in the format of the UPIU, Figure 5 As can be seen, the EHS field is included in the UPIU, and the definition of the EHS field in the UPIU is as follows: Figure 6As shown. It can be seen that the EHS can define the type, parameters and specific content of the specific instruction, so that the pre-erase command can be added in the EHS.

[0054] It can be understood that the UPIU is a basic protocol used for communication in the UFS, which is a standard command format used when controlling and data transmission between UFS devices, and contains command and data structures for communication. In the UPIU, various read and write commands, status information, error codes, and some additional header information such as Extra Header Segment (EHS) are included. Among them, the EHS is part of the UPIU, which contains extended header information for carrying some additional control information or metadata. The EHS can be used to transmit some auxiliary information specific to the command or data transmission to support more complex operations or provide additional context information.

[0055] Exemplarily, the identification of the pre-erase command can be determined first, and then the EHS data structure is configured. According to the definition in the UFS specification, the data structure of the pre-erase command to be added in the EHS needs to be determined. This may include command type, command parameter, length field, etc. Then, the data structure and identification of the pre-erase command are encapsulated in the EHS field of the UPIU. It should be noted that the EHS field is an extension of the aforementioned specified instruction.

[0056] In addition, the memory needs to be adaptively configured so that after receiving the specified instruction, it can parse the EHS field of the instruction to obtain the pre-erase command and execute the pre-erase command if the execution condition is met. The implementation of the execution condition can refer to the subsequent embodiments and will not be described here.

[0057] Therefore, by adding the pre-erase command in the preset field of the specified instruction to be sent to the memory, the pre-erase command is included in the specified instruction that is originally to be sent to the memory, so that a separate pre-erase command does not need to be sent outside the specified instruction. That is, no additional interaction is required due to the separate sending of a pre-erase command, which can prevent the real-time performance of the user from being affected.

[0058] In the second mode, a pre-erase command corresponding to the target pre-erase mode is obtained, the pre-erase command is generated into a pre-erase instruction based on the UPIU protocol, and the pre-erase instruction is sent to the memory to make the memory perform a pre-erase operation based on the pre-erase instruction. Illustratively, the UPIU instruction (i.e., the pre-erase instruction) containing the erase command is sent to the UFS device in the manner of creating an erase command (Erase Command) data packet, encapsulating the Erase Command into the UPIU, configuring the UPIU header information, and sending the UPIU, to trigger the pre-erase operation. For example, a single UPIU is used to issue a pre-erase instruction, such as a pre-erase vendor command defined by a WRITE BUFFER command. The WRITE BUFFER command can include some of the following functions: write data: the command can instruct the storage device to receive a certain amount of data and write the data into the buffer of the device; buffer management: the WRITE BUFFER command can involve management of the internal buffer of the device, including clearing, refreshing, or allocating the buffer; data transmission preparation: some storage devices can use the WRITE BUFFER command to prepare data transmission, so that the data can be effectively transmitted to a specific location in the memory. Illustratively, according to the UFS memory specification, a specific vendor command is defined using the WRITE BUFFER command to perform the erase operation. The specific structure and content of the vendor command need to be constructed according to the specification document of the UFS memory. In the vendor command, the command code and parameters can be defined to instruct the memory to perform the erase operation. The Vendor Command is sent, i.e., the constructed vendor command is sent to the UFS memory using the UPIU.

[0059] It should be noted that the difference between the second mode and the first mode is that in the first mode, the host sends a specified instruction, and the pre-erase command is in the preset field of the specified instruction as extended information of the specified instruction in the preset field. For example, the specified instruction is a write instruction of the UPI U protocol, and the pre-erase command belongs to the extension of the write instruction. The host sends the specified instruction to the memory, and the memory obtains the pre-erase command by analyzing the content of the preset field of the specified instruction. At the same time, the memory responds to the specified instruction and performs an operation corresponding to the specified instruction. For example, the specified instruction is a write instruction, and the memory will simultaneously respond to the write instruction to perform a write operation and respond to the pre-erase command to perform a pre-erase operation. In the second mode, the pre-erase instruction sent by the host is a pre-erase instruction directly defined by the UPI U protocol. Therefore, the memory receives the instruction and responds to the pre-erase instruction to perform a pre-erase operation.

[0060] In the third mode, the pre-erase instruction is sent through a query request, a task management request, or other requests. The query request is used to query the attributes and state of the memory, and the task management request can be used to manage and control the task execution of the memory. That is, the pre-erase command can be added to the request.

[0061] It should be noted that the above three modes can be used to send the pre-erase command in the embodiments of the present application, but considering the reduction of the interaction with the memory, in the embodiments of the present application, the pre-erase command corresponding to the target pre-erase mode is sent in the first mode.

[0062] Therefore, the embodiments of the present application can determine the pre-erase mode for the memory based on the current data write situation of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, thereby making the pre-erase operation more in line with the current data write demand of the storage system, and making the setting of the pre-erase operation more reasonable.

[0063] Please refer to Figure 7 The method is applied to the host described above. In order to facilitate description, the memory is taken as an example of UFS in the following embodiments, and of course the memory can be of other types, which is not limited. The method comprises S710-S780.

[0064] S710: Determine the application program running on the host.

[0065] As described above, the target pre-erase mode can be determined by the application program running on the host, so in the embodiments of the present application, the application program running on the host is determined first.

[0066] As an implementation, taking a host as a smart phone as an example, the running application can be an application running in the foreground and / or the background of the smart phone. In the embodiments of the present application, the running application can be an active application, which can refer to an application running in the foreground in a current time period and currently running in the foreground or the background, an application writing data to the memory in the current time period, an application currently running in the foreground, or an application currently reading and / or writing data.

[0067] For the case that the active application is an application running in the foreground in a current time period and currently running in the foreground or the background, the current time period can be a time period of a specified length of time before the current time, so that the active application can include an application currently running in the foreground and an application switched from the foreground to the background in the current time period. That is, considering that the application recently switched to the background by the user can be switched to the foreground again, so that the application running in the foreground in the current time period is all regarded as the active application, that is, the aforementioned running application.

[0068] For the case that the active application is an application writing data to the memory in a current time period and currently running in the foreground or the background, the electronic device determines an application currently running in the foreground or the background of the electronic device as a candidate application, and then finds an application writing data to the memory in the current time period from the candidate application as the active application, that is, the aforementioned running application. Among them, the application writing data to the memory can be further limited to an application writing a data amount greater than a specified data amount to the memory. Therefore, the application writing data in the recent time period among the applications currently running in the foreground and the background of the electronic device can be regarded as the active application, that is, the application running in the host.

[0069] In the embodiments of the present application, the active application refers to an application currently running in the foreground of the electronic device, that is, the implementation of determining the application running in the host determines the application currently running in the foreground of the host, that is, the application currently running in the foreground of the electronic device.

[0070] S720: Determine whether there is a specified application in the running application.

[0071] As an implementation, the specified application can be an application in an application list, which can be an application list of applications with a large number of sequential write operations, for example, a certain game application performs package installation operation or version update operation, and a large number of sequential write operations exist. Among them, a large number of sequential write operations refer to continuous write operations within a preset time period, and the amount of data written is greater than a preset data amount. It can be understood that the application in the application list can be manually added, or it can be determined by the host according to whether each application in the statistical period has a large number of sequential write operations, which is not limited here.

[0072] Therefore, after the host determines the running application, the running application is taken as an active application, and is matched with each specified application in the application list to determine whether there is an application identical to the specified application. Assuming that the running application is the application currently running in the foreground, it is determined whether the application belongs to the specified application of the application list, if yes, S730 is executed, otherwise, S750 is executed.

[0073] As an implementation, if there is a specified application in the running application, it is determined that the target pre-erase mode is the automatic mode, and the application scenario of the host is the first scenario; if there is no specified application in the running application, it is determined that the target pre-erase mode is the active mode, and the application scenario of the host is the second scenario. In the embodiments of the present application, the two application scenarios, i.e., the presence of the specified application in the running application and the absence of the specified application in the running application, can be named as the first scenario and the second scenario, respectively. It can be understood that in some embodiments, the first scenario and the second scenario can not be set, and in the case that the specified application exists in the running application, the target pre-erase mode is directly determined as the automatic mode, and in the case that the specified application does not exist in the running application, the target pre-erase mode is directly determined as the active mode. By using the first scenario and the second scenario, the scenario of the active mode and the scenario of the automatic mode are more conveniently described.

[0074] S730: It is determined that the application scenario of the host is the first scenario.

[0075] That is, in the case that the specified application exists in the running application, it is determined that the application scenario of the host is the first scenario.

[0076] As mentioned above, the application scenario can include a first scenario and a second scenario, and the data write amount of the first scenario is greater than the data write amount of the second scenario. The specified application programs in the application list are the application programs that are determined to have a large amount of sequential write operations, so when the specified application programs are running, the application programs are likely to perform a large amount of sequential write operations, so the application scenario in which the specified application programs run is defined as the first scenario, and the corresponding application scenario in which the specified application programs do not run is defined as the second scenario, which meets the condition that the data write amount of the first scenario is greater than the data write amount of the second scenario.

[0077] S740: determining that the target pre-erase mode for the memory is an automatic mode.

[0078] If the application scenario is the first scenario, it is determined that the target pre-erase mode for the memory is an automatic mode, that is, for the application scenario with a large amount of sequential write, an application list is pre-set, and the automatic mode is started during the application activities.

[0079] S750: sending a first erase instruction to the memory to trigger the memory to enter the automatic mode.

[0080] The pre-erase instruction corresponding to the automatic mode is the first erase instruction, and the function of the first erase instruction is to trigger the memory to enter the automatic mode. It can be understood that the sending mode of the first erase instruction can adopt any one of the three modes described above, and in the embodiments of the present application, the first erase instruction can be sent by the first mode.

[0081] As an embodiment, the memory corresponds to a device management unit, which can be a controller within the memory, and in addition, in a host system using universal flash storage (UFS) as a storage device, the firmware of the UFS manages the medium (NAND flash) in units of virtual blocks (VB). In UFS, the storage area is divided into multiple physical blocks (Physical Block), each physical block contains multiple sectors (Sector), and the size of each sector is usually 512 bytes or 4KB. The virtual block is a layer of logical mapping built on the physical block, which combines multiple physical blocks into a logical block and allocates a virtual address to the logical block. Through the mapping of the virtual block, more efficient data reading and writing and management can be achieved. For example, in UFS, if a bad block occurs, the virtual block can automatically exclude the block from the logical block and migrate the data to other available physical blocks, thereby ensuring the integrity and reliability of the data. In addition, the virtual block can also realize the functions of high-speed random read and write operation of UFS, optimization and support of TRIM command, etc.

[0082] It can be understood that in the UFS memory, the pre-erase operation is usually performed by the controller inside the memory, i.e. the aforementioned device management unit. For example, the UFS controller inside the memory is responsible for managing and performing the erase operation. The controller of the memory can perform the erase operation by searching for the idle physical block through the VB.

[0083] Exemplarily, the embodiment that the first erase instruction is sent to the memory to trigger the memory to enter the automatic mode can be:

[0084] In the automatic mode, a first erase instruction is sent to the memory; the memory erases a first capacity of free physical blocks in the memory as pre-erased blocks; if it is detected that the amount of data written into the pre-erased blocks is greater than a threshold value, the operation of erasing the first capacity of free physical blocks in the memory as pre-erased blocks is performed again until the automatic mode ends. The first capacity can be a pre-erased capacity specified by the host in the first erase instruction, that is, the host triggers the memory to automatically trigger the pre-erasing operation, and reserves a pre-erased physical space of the first capacity, that is, a pre-erased block. A free physical block refers to a storage block on a storage medium (such as a solid state disk, a flash memory, etc.) that has not been used or allocated to any data. A physical block is the smallest writable unit of a storage medium, and usually has a fixed size. In a storage device, physical blocks are organized into continuous blocks for storing data. When data is deleted or moved, the corresponding physical blocks become free physical blocks and can be reused to store new data. Therefore, the capacity of a pre-erased block usually refers to the number of physical blocks based on which the pre-erasing operation is performed.

[0085] That is, in the automatic mode, after the host starts the pre-erasing of the Auto mode of the memory through the first erase instruction, specifies the pre-erased capacity (that is, the first capacity) and the VB use mode, the UFS device will automatically pre-erase to the first capacity after the idle of the read operation and / or the write operation. The VB use mode is described in the subsequent content. When the pre-erased blocks are consumed by the write operation, the device automatically pre-erases according to its own idle to supplement the pre-erased blocks to the set capacity. When the host issues a command to close the Auto mode, the device stops the automatic pre-erasing. The blocks that have been pre-erased will be gradually consumed by the subsequent write.

[0086] Therefore, the host can specify the following contents in the pre-erasing command: a) pre-erasing mode: automatic mode (Auto mode) or active mode (Host trigger mode); b) VB use mode: including the currently commonly used NAND flash SLC / TLC / QLC mode, and the medium use mode of new media such as MRAM / PCM / XL-Flash, etc.; c) capacity configuration: the host can configure the capacity size of the pre-erasing within a certain range.

[0087] S760: determining that the application scenario of the host is a second scenario.

[0088] That is, in the case where it is determined that there is no specified application in the running application program, it is determined that the application scenario of the host is the second scenario.

[0089] S770: determining that the target pre-erasing mode for the memory is the active mode.

[0090] The second scenario and the active mode can refer to the foregoing.

[0091] S780: sending a second erase instruction to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space.

[0092] In the active mode, a second erase instruction is sent to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space, that is, in the active mode, the host specifies the capacity of the pre-erase space as a second capacity, and the memory erases the free physical blocks of the second capacity to obtain a pre-erase space of the second capacity, that is, a pre-erase block. Therefore, when the host detects that the specified application is active at the application layer, it determines that the application scenario is the first scenario, and issues an instruction to start the automatic mode, that is, the open auto preerase instruction, to the drive layer, and then the drive layer issues a pre-erase command to open the auto mode, that is, the first erase instruction, to the memory. For example, the drive layer uses the EHS field of the write(10) command to issue a pre-erase command to open the auto mode, that is, the first erase instruction is sent to the memory in the first mode described above. The write(10) is a write command, and "(10)" represents a 10-byte write command for writing data.

[0093] It should be noted that in the automatic mode, the host also needs to determine whether the automatic mode is ended. If the automatic mode is ended, the host needs to send a first closing instruction to the memory, which is used to close the automatic mode. Wherein, determining whether the automatic mode is ended can be returning to execute the determination that the host is running the application again. The end of the automatic mode can include entering the active mode, or neither the active mode nor the automatic mode, for example, no application is currently running. Similarly, the active mode can also determine whether the active mode is ended in this way.

[0094] In addition, the NAND flash has different usage modes for a physical block, that is, SLC / MLC / TLC / QLC modes, and the number of bits that can be stored in each minimum unit is different for different modes. Generally, the storage bits of the minimum unit corresponding to SLC / MLC / TLC / QLC are 1 bit / 2 bit / 3 bit / 4 bit respectively. Therefore, in the case of pre-erase operation of the memory, the pre-erase instruction corresponding to the target pre-erase mode is sent at the same time, and the usage mode corresponding to the pre-erase operation is also sent, so that the memory performs the pre-erase operation in the usage mode, that is, the host can specify the usage mode of the pre-erase VB.

[0095] As an implementation, the precondition for the memory to respond to the pre-erase instruction is different in different usage modes.

[0096] Exemplarily, if the host specifies the VB usage mode of the current pre-erase operation as SLC (Single-Level Cell) mode, the precondition for the memory to respond to the pre-erase instruction is that the write booster (WB) buffer of the memory is available. That is, the case of WB available buffer size! = 0, that is, the WB buffer is not empty, the pre-erase operation in SLC mode issued by the host can be executed by the memory. If the WB buffer of the memory is not available, the memory will return a failure information to the host, and the host knows that the current pre-erase operation cannot be successfully executed through the failure information.

[0097] It can be understood that SLC mode is a memory operation mode in UFS device, which uses higher cell density (that is, each storage cell stores one bit) to realize larger capacity and provides faster data transmission speed. In SLC mode, the UFS device usually has a dedicated WB (Write Booster) buffer. The WB buffer is usually a high-speed storage area used to temporarily store write data from the host system for batch writing to the storage medium of the UFS device at an appropriate time.

[0098] When the host system needs to perform a write operation, data is first written to the WB buffer of the UFS device. However, before performing the erase operation, the UFS device must ensure that the data in the WB buffer has been completely written to the storage medium to avoid data loss or inconsistency. Therefore, in SLC mode, the UFS device usually checks whether the WB buffer is empty before performing the erase operation. If the WB buffer still contains data to be written, the UFS device will first reasonably arrange and batch write these data to the memory, and then perform the erase operation. Therefore, when the WB buffer is not empty, a failure information is returned, and the host needs to send a pre-erase instruction again.

[0099] In addition, if the use mode of the current pre-erasing operation specified by the host is in the TLC or QLC mode, the memory responds to the precondition of the pre-erasing instruction that the number of the current free physical blocks meets the preset requirement, wherein the preset requirement can be that the number of the free physical blocks is greater than a first number, wherein the first number can be set according to the actual use requirement, and the number of the free physical blocks is less than or equal to the first number, which represents that the number of the free physical blocks of the memory is insufficient. Therefore, in the case that the memory determines that the number of the current free physical blocks is less than or equal to the first number, the failure information is returned to the host.

[0100] It should be noted that, in the case that the application program currently running in the electronic device is not the specified application program, it means that the current application scenario does not involve a large amount of data writing, that is, there is no large sequential writing, which means that there can be a write data operation at present, but the amount of data written is not large, and it also means that the current can be in a data writing scenario or the data written is very small, so it is necessary to determine whether it belongs to the case where the amount of data written is not large by the write rate. Therefore, as shown in FIG. 7, S780 can include S781-S789. Figure 8

[0101] S781: In the active mode, the current write rate of the memory is obtained.

[0102] ​It should be noted that the current write rate is the write rate in the preset time length corresponding to the current time, that is, the write rate can be the amount of data written to the memory in the preset time length corresponding to the current time. Therefore, the implementation of obtaining the current write rate of the memory can be to obtain the number of specified write commands sent to the memory in the preset time length corresponding to the current time, and take the number as the write rate, wherein the specified write command is used to write a data block of a specified data size. For example, the specified data size is 512 KB. Generally, for a larger data write operation, it is usually cut by the block layer of the operating system to adapt to the characteristics of the underlying storage device. In the current storage device, the read and write operations of data are performed in blocks, and the size of the block can be configured according to the specific storage device and file system. Common block sizes are 512 KB, 1 KB, 2 KB, 4 KB, etc. In the embodiments of the present application, the size of the data block is 512 KB, so the specified write command is used to write a data block of 512 KB. Therefore, the number of data blocks written can measure the amount of data written in a period of time, and since the specified write command is used to write a data block of a specified data size, the number of specified write commands can reflect the size of the amount of data written, so the number of specified write commands sent to the memory in the preset time length corresponding to the current time is taken as the write rate. For example, the preset time length is 100 ms, so the write rate is represented by the number n of 512 KB chunksize write commands in 100 ms, wherein chunksize refers to a parameter for controlling the block size or buffer size of the data write operation.

[0103] It can be understood that the preset time length corresponding to the current time is a corresponding time period, which can be named as a current time period, the time length of the current time period is the preset time length, and the end time of the current time period is the current time, so if the current time changes, although the preset time length is the same, the current time period is still different.

[0104] S782: Obtain the current first specified threshold.

[0105] The first specified threshold is used to determine whether the current write rate needs to trigger a pre-erase operation through an active mode, and the first specified threshold can be variable, and its variable manner can be referred to the subsequent description. Since the first specified threshold is variable, before each time of performing the determination of whether the write rate is greater than the current first specified threshold, the current first specified threshold needs to be obtained first.

[0106] S783: Determine whether the write rate is greater than the current first specified threshold.

[0107] S784: sending the second erase instruction to the memory.

[0108] If the write rate is greater than the current first specified threshold, S784 is performed, if the write rate is less than or equal to the current first specified threshold, S781 is returned to perform, of course, the step of determining the application running on the host and the subsequent steps are also returned to perform.

[0109] It should be noted that the sending mode of the second erase instruction sent to the memory can refer to the foregoing description, which will not be repeated here.

[0110] S785: obtaining the reply information returned by the memory for the currently sent second erase instruction.

[0111] In the embodiments of the present application, after the memory receives the first erase instruction or the second erase instruction, the host is sent reply information, which can include failure information, success information, first information and second information. Wherein, the failure information (fail) indicates that the memory cannot perform the current pre-erase operation, such as the command requires the pre-erase mode of VB, but the WB buffer is 0, or the insufficient empty block, etc. The implementation mode of the memory sending the failure information (fail) can refer to the foregoing embodiments, which will not be repeated here. In the case that the memory successfully performs the pre-erase operation, the success information (Success) is sent to the host, which indicates that the pre-erase operation of the corresponding set capacity is completed. For example, the first erase instruction is used to instruct the memory to automatically erase the first capacity of idle physical blocks, that is, each pre-erase operation can obtain the first capacity of pre-erase blocks; the second erase instruction is used to instruct the memory to obtain the second capacity of pre-erase blocks, so the success information is returned after the memory successfully corresponds to the capacity of the pre-erase block.

[0112] As an implementation mode, the host sends the second erase instruction to the memory in the case that the current write rate is greater than the current first specified threshold, and the memory determines whether the current remaining capacity of the pre-erase space obtained by the last pre-erase operation is lower than the second specified threshold after receiving the second erase instruction, if it is lower than the second specified threshold, the first information is returned, if it is greater than or equal to the second specified threshold, the second information is returned. Based on the second erase instruction, the pre-erase operation is performed in the case that the first information or the second information is returned. Wherein, the last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time. The first information and the second information reflect the efficiency of the second erase instruction issued this time.

[0113] It can be understood that the first information efficient is used to represent that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation on the memory is lower than the second specified threshold, and the second information inefficient is used to represent that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation on the memory is higher than or equal to the second specified threshold. It can be seen that after receiving the first information, the host can determine that the capacity of the pre-erase space obtained by the last pre-erase operation on the memory is insufficient, that is, there is not enough space to be written with data, so the first information is returned to notify the host that the use efficiency of the pre-erase block obtained by the current pre-erase operation is relatively high, that is, the issuing efficiency of the second erase instruction this time is relatively high. Similarly, after receiving the second information, the host can determine that the capacity of the pre-erase space obtained by the last pre-erase operation on the memory is still sufficient, that is, there is a certain space that has not been written with data, and then the second information is returned to the host to notify the host that the use efficiency of the pre-erase block obtained by the current pre-erase operation is relatively low, that is, the issuing efficiency of the second erase instruction this time is relatively low.

[0114] S786: determining whether the reply information is the first information or the second information.

[0115] S787: increasing the first specified threshold.

[0116] S788: decreasing the first specified threshold.

[0117] As described above, the precondition for sending the second erase instruction to the memory is that it is determined that the current is the active mode, and the current write rate of the memory is greater than the current first specified threshold, so by changing the first specified threshold, the frequency of sending the second erase instruction to the memory can be adjusted, that is, the host dynamically adjusts the issuing frequency of the pre-erase. It can be seen that if the first specified threshold is increased this time, the next time when the write rate is used to determine whether to issue the second erase instruction, the write rate needs to be greater in order to meet the condition that the write rate next time is greater than the first specified threshold used next time, that is, the write operation needs to be more aggressive in order to send the second erase instruction, which can reduce the issuing frequency of the second erase instruction to a certain extent, and similarly, if the first specified threshold is decreased this time, the next time when the write rate is used to determine whether to issue the second erase instruction, the write rate can be smaller to meet the condition that the write rate next time is greater than the first specified threshold used next time, that is, it is easier to trigger the sending of the second erase instruction, which can increase the issuing frequency of the second erase instruction.

[0118] Therefore, it is determined whether the reply information is the first information or the second information, if the first information, the first specified threshold is decreased, and if the second information, the first specified threshold is increased.

[0119] S789: waiting for the current pre-erase to be written with data.

[0120] After the first information or the second information is returned, the memory performs the pre-erase operation, and waits for the current pre-erase to be written with data. It should be noted that if the active mode is not ended, i.e., if the application scenario is still the second scenario, the step of obtaining the current write rate of the memory and the subsequent steps are returned to be executed. That is, the write rate detection is continued, and the first specified threshold used next time is the first specified threshold after being adjusted based on the first information or the second information this time.

[0121] As an implementation, the first specified threshold has an initial value, and at the end of the current active mode or the start of the next active mode, the first specified threshold is initialized, i.e., set to the initial value. In addition, the first specified threshold also has an upper limit value and a lower limit value, so that the first specified threshold will not blindly increase or decrease. Therefore, the implementation of the above-mentioned if the reply information is the first information, the first specified threshold is decreased, can be that if the reply information is the first information, it is determined whether the current first specified threshold is less than or equal to the lower limit value, if less than or equal to the lower limit value, the first specified threshold is kept as the lower limit value, and if greater than the lower limit value, the first specified threshold is decreased. Similarly, the implementation of the above-mentioned if the reply information is the second information, the first specified threshold is increased, can be that if the reply information is the second information, it is determined whether the current first specified threshold is greater than or equal to the upper limit value, if greater than or equal to the upper limit value, the first specified threshold is kept as the upper limit value, and if less than the upper limit value, the first specified threshold is increased.

[0122] Therefore, in the first scenario, i.e., in the case where there are a large number of write operations, the automatic mode is adopted, so that the memory can automatically perform the pre-erase operation in time through the current free physical state, avoiding the host actively triggering the pre-erase operation not in time. In the case where there are no a large number of write operations, the active mode can be used to avoid the long-term existence of the pre-erase block in the memory, thereby avoiding the stability risk.

[0123] Therefore, through the detection of the running specified application program, it can be determined whether to enter the active mode or the automatic mode, so that in the scenario where there are a large number of sequential writes, the pre-erase benefit of the write operation is increased through the automatic mode.

[0124] Please refer to Figure 9Fig. 9 shows a structural block diagram of a memory management apparatus 900 provided by an embodiment of the present application. The apparatus can include a determining unit 901 and an erasing unit 902.

[0125] The determining unit 901 is configured to determine a target pre-erasing mode in an automatic mode and an active mode. In the automatic mode, the memory automatically performs a pre-erasing operation on the memory. In the active mode, the memory performs a pre-erasing operation based on an instruction sent by the host.

[0126] Further, the determining unit 901 is further configured to determine an application program running on the host, and determine the target pre-erasing mode in the automatic mode and the active mode based on the running application program.

[0127] Further, the determining unit 901 is further configured to determine that the target pre-erasing mode is the automatic mode if there is a specified application program in the running application program, and determine that the application scenario of the host is a first scenario; and determine that the target pre-erasing mode is the active mode if there is no specified application program in the running application program, and determine that the application scenario of the host is a second scenario.

[0128] The erasing unit 903 is configured to perform a pre-erasing operation on the memory based on the target pre-erasing mode.

[0129] Further, the erasing unit 903 is further configured to send a first erasing instruction to the memory, and trigger the memory to enter the automatic mode. In the automatic mode, the memory automatically performs a pre-erasing operation on idle physical blocks in the memory to obtain a pre-erasing space.

[0130] Further, the erasing unit 903 is further configured to send a second erasing instruction to the memory in the active mode, and instruct the memory to perform a pre-erasing operation on idle physical blocks in the memory to obtain a pre-erasing space.

[0131] Further, the erasing unit 903 is further configured to acquire a current write rate of the memory in the active mode, and send the second erasing instruction to the memory if the write rate is greater than a current first specified threshold.

[0132] Further, the erasing unit 903 is further configured to acquire a number of specified write commands sent to the memory in a preset time length corresponding to a current time, and take the number as the write rate, wherein the specified write command is used to write a data block of a specified data size.

[0133] Further, the erasing unit 903 is further configured to: if the write rate is greater than a specified threshold, after sending the erasing instruction to the memory, acquire reply information returned by the memory for the currently sent second erasing instruction; if the reply information is first information, decrease the first specified threshold, wherein the first information is used to represent that a current remaining capacity of a pre-erasing space obtained by a last pre-erasing operation on the memory is lower than a second specified threshold, wherein the last pre-erasing operation refers to a pre-erasing operation performed before the second erasing instruction is received this time; if the reply information is second information, increase the first specified threshold, wherein the second information is used to represent that the current remaining capacity of the pre-erasing space obtained by the last pre-erasing operation on the memory is higher than or equal to the second specified threshold; if the application scenario is still the second scenario, return to perform the step of acquiring the current write rate of the memory and subsequent steps.

[0134] Further, the erasing unit 903 is further configured to: acquire a pre-erasing command corresponding to the target pre-erasing mode; add the pre-erasing command in a preset field of a specified instruction to be sent to the memory, to obtain a target instruction; and send the target instruction to the memory, so that the memory performs a pre-erasing operation based on the pre-erasing command.

[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and module can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0136] In several embodiments provided in the present application, the coupling between the modules can be electrical, mechanical or other forms of coupling.

[0137] In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can exist physically independently, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0138] Please refer to Figure 10 which shows a structural block diagram of a computer readable medium provided by an embodiment of the present application. The computer readable medium 1000 stores program code, which can be called and executed by a processor to perform the method described in the foregoing method embodiments.

[0139] The computer-readable medium 1000 can be an electronic storage such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk or a ROM. Alternatively, the computer-readable medium 1000 comprises a non-transitory computer-readable storage medium. The computer-readable medium 1000 has a storage space for the program code 1010 for performing any of the method steps of the above-described methods. These program codes can be read from or written to one or more computer program products. The program code 1010 can be compressed, for example, in an appropriate form.

[0140] To sum up, the memory management method, device, storage system and computer readable medium provided by the application determine the application scenario of the storage system, determine the target pre-erase mode for the memory among the preset multiple pre-erase modes based on the application scenario, and perform a pre-erase operation on the memory based on the target pre-erase mode. Therefore, the pre-erase mode for the memory can be determined based on the current data write condition of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, so that the pre-erase operation is more in line with the current data write requirement of the storage system, and the setting of the pre-erase operation is more reasonable.

[0141] In addition, the VB is pre-erased, a large amount of time for erasing the VB in the sequential writing process is saved, the sequential writing performance of the storage system is improved, and the delay peak (i.e., the maximum delay) caused by erasing the VB is reduced. The host and the device are linked, the VB is pre-erased on demand through scene recognition. The stability risk of the existing solution is improved while the maximum benefit is ensured. The first solution does not use an independent command, but uses the EHS field or the reserved field of the UPI U, which does not affect the use performance of the user.

[0142] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, but not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A memory management method characterized by comprising: A host applied to a storage system, the storage system further comprising a memory, the host being connected with the memory, the method comprising: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host, and each pre-erase operation is triggered by the host actively, wherein the pre-erase operation refers to an operation of erasing a block where data is written in advance before a memory write operation is performed; performing a pre-erase operation on the memory based on the target pre-erase mode.

2. The method of claim 1, wherein, The determining of the target pre-erase mode in the automatic mode and the active mode comprises: determining an application program running on the host; determining the target pre-erase mode in the automatic mode and the active mode based on the running application program.

3. The method of claim 2, wherein, The determining of the target pre-erase mode in the automatic mode and the active mode based on the running application program comprises: if there is a specified application program in the running application program, determining that the target pre-erase mode is the automatic mode; if there is no specified application program in the running application program, determining that the target pre-erase mode is the active mode.

4. The method of claim 1, wherein, The target pre-erase mode is the automatic mode, and the performing of the pre-erase operation on the memory based on the target pre-erase mode comprises: sending a first erase instruction to the memory to trigger the memory to enter the automatic mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on an idle physical block in the memory to obtain a pre-erase space.

5. The method of claim 1, wherein, The target pre-erase mode is the active mode, and the performing of the pre-erase operation on the memory based on the target pre-erase mode comprises: in the active mode, sending a second erase instruction to the memory to instruct the memory to perform a pre-erase operation on an idle physical block in the memory to obtain a pre-erase space.

6. The method of claim 5, wherein, The sending of the second erase instruction to the memory in the active mode comprises: in the active mode, obtaining a current write rate of the memory; if the write rate is greater than a current first specified threshold, sending the second erase instruction to the memory.

7. The method of claim 6, wherein, The obtaining of the current write rate of the memory comprises: obtaining a number of specified write commands sent to the memory in a preset time length corresponding to a current time, and taking the number as the write rate, wherein the specified write command is used to write a data block of a specified data size.

8. The method of claim 6, wherein, After the sending of the erase instruction to the memory if the write rate is greater than a specified threshold, the method further comprises: obtaining reply information returned by the memory for the currently sent second erase instruction; if the reply information is first information, decreasing the first specified threshold, wherein the first information is used to represent that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation on the memory is lower than a second specified threshold, wherein the last pre-erase operation refers to a pre-erase operation performed before the second erase instruction is received this time; if the reply information is second information, increasing the first specified threshold, wherein the second information is used to represent that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation on the memory is higher than or equal to the second specified threshold; if the active mode has not ended, returning to perform the step of obtaining the current write rate of the memory and subsequent steps.

9. The method according to any one of claims 1 to 8, characterized in that, the pre-erase operation performed on the memory based on the target pre-erase mode comprises: obtaining a pre-erase command corresponding to the target pre-erase mode; adding the pre-erase command in a preset field of a specified instruction to be sent to the memory to obtain a target instruction; sending the target instruction to the memory to enable the memory to perform a pre-erase operation based on the pre-erase command.

10. The method according to any one of claims 1 to 8, characterized in that, The memory is a general flash memory.

11. A memory management device, comprising: The device is applied to a host of a storage system, the storage system further comprising the memory, the host being connected with the memory, and the device comprising: a determination unit configured to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host, and each pre-erase operation is actively triggered by the host, wherein the pre-erase operation refers to an operation of erasing a block where data is written in advance before a write operation of the memory is performed; an erasing unit configured to perform a pre-erase operation on the memory based on the target pre-erase mode.

12. A storage system, characterized by comprise: a host; a memory; the host is connected with the memory, and the host is configured to perform the method according to any one of claims 1-10.

13. A computer readable medium characterized by The computer readable medium stores processor-executable program code, and the program code, when executed by the processor, causes the processor to perform the method according to any one of claims 1-10.

14. A memory management method, comprising: The device is applied to a memory of a storage system, the storage system further comprising a host, and the method comprises: receiving a second erase instruction sent by the host; in response to the second erase instruction, performing a pre-erase operation, wherein each pre-erase operation is triggered based on a second erase instruction sent by the host; the pre-erase operation refers to an operation of erasing a block where data is written in advance before a write operation of the memory is performed.

15. The method of claim 14, wherein, The memory is a general flash memory.

16. A memory management method, comprising: The device is applied to a memory of a storage system, the storage system further comprising a host, and the method comprises: receiving a first erase instruction sent by the host; In response to the first erasing instruction, an automatic mode is entered, in which the memory automatically performs a pre-erasing operation on the memory, and the memory erases a first capacity of free physical blocks in the memory as pre-erased blocks; if it is detected that the amount of data written into the pre-erased blocks is greater than a threshold value, the operation of erasing a first capacity of free physical blocks in the memory as pre-erased blocks is performed again until the automatic mode ends, wherein the pre-erasing operation refers to an operation of erasing blocks in which data is written in advance before a memory writing operation is performed.

17. The method of claim 16, wherein, The memory is a universal flash memory.

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