Cache manager and control component

Abstract

The application provides a cache manager and a control component. The cache manager comprises an interface, an allocation module and a memory. The interface receives a cache allocation request and sends the cache allocation request to the allocation module. The interface receives first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module allocates N idle memory blocks and generates the first cache index information. The memory blocks are located in a cache, N is a positive integer, and the first cache index information comprises indexes of the N memory blocks. The memory stores indexes of at least N memory blocks. The cache manager implemented by hardware replaces the software management cache in the prior art, thereby reducing the interaction times between software and hardware when allocating a cache in the control component, improving the information interaction speed inside the control component, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.

Description

TECHNICAL FIELD

[0001] The present application relates to storage technology, and in particular, to a cache manager and a control component. BACKGROUND

[0002] Figure 1 A block diagram of a solid state storage device is shown. The solid state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid state storage device 102 can be coupled in various ways, including but not limited to connecting the host and the solid state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transmission between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) coupled to the NVM chip 105 and configured to issue commands to the NVM chip 105 in a manner complying with an interface protocol of the NVM chip 105, to operate the NVM chip 105, and to receive command execution results output from the NVM chip 105. Known NVM chip interface protocols include “Toggle”, “ONFI”, and the like.

[0007] With the rapid growth of information, a single data transmission between a storage device and a host carries a large amount of data, and is affected by the storage characteristics of flash memory, so that direct data transmission between the host and the flash memory is not possible. Therefore, a buffer is usually provided in the control component to temporarily store the data to be transmitted. With the buffer, the process of data transmission by the control component is divided into two stages, one stage being data transmission between the host and the buffer, and the other stage being data transmission between the buffer and the storage device. Therefore, the prior art realizes data transmission from the host to the flash chip, but inevitably increases the number of information interactions within the control component when the data is transmitted in two stages, thereby causing the technical problem of long data transmission time between the host and the flash chip. SUMMARY

[0008] To solve the technical problem of long data transmission time between the host and the flash chip in the prior art, the present application provides a buffer manager and a control component.

[0009] According to a first aspect of the present application, a first cache manager according to the first aspect of the present application is provided, comprising an interface, an allocation module and a memory, wherein the interface receives a cache allocation request and sends the cache allocation request to the allocation module; and the interface receives first cache index information returned by the allocation module and outputs the first cache index information; in response to the cache allocation request, the allocation module allocates N free storage blocks and generates the first cache index information, the storage blocks are located in the cache, N is a positive integer, and the first cache index information comprises indexes of the N storage blocks; and the memory stores indexes of at least N storage blocks.

[0010] In the embodiment, the cache manager implemented by hardware is used to replace the software cache management in the prior art, so that the number of interactions between software and hardware in the control component when allocating the cache is reduced, the information interaction speed in the control component is improved, and the technical effect of reducing the data transmission time between the host and the flash memory chip is achieved.

[0011] According to the first cache manager according to the first aspect of the present application, a second cache manager according to the first aspect of the present application is provided, and the cache manager further comprises a release module, wherein the interface receives a cache release request and sends the cache release request to the release module, the cache release request carries second cache index information, the second cache index information comprises indexes of M storage blocks to be released, the storage blocks to be released are located in the cache, and M is a positive integer; in response to the cache release request, the release module writes the indexes of the M storage blocks into the memory, so that the storage blocks to be released become free storage blocks.

[0012] According to the first or second cache manager according to the first aspect of the present application, a third cache manager according to the first aspect of the present application is provided, and the memory comprises at least one storage space, each storage space has equal length, and each storage space stores an index of a storage block.

[0013] According to one of the first to third cache managers according to the first aspect of the present application, a fourth cache manager according to the first aspect of the present application is provided, and the allocation module manages a first pointer, the first pointer points to a first storage space, the first storage space stores indexes of free storage blocks, and two storage spaces adjacent to both sides of the first storage space respectively store indexes of free storage blocks and indexes of allocated storage blocks; when the N storage blocks are allocated, the allocation module reads indexes of N storage blocks from the first storage space to the Nth storage space; the first pointer is modified so that the first pointer points to a second storage space, the second storage space is the N+1th storage space starting from the first storage space, and the second storage space stores indexes of free storage blocks.

[0014] According to the first to fourth cache managers of the first aspect of the present application, the fifth cache manager of the first aspect of the present application is provided, the release module manages a second pointer, the second pointer points to a third storage space, the third storage space stores indexes of allocated storage blocks, and two storage spaces adjacent to the third storage space respectively store indexes of free storage blocks and indexes of allocated storage blocks; when the M storage block indexes are written into the memory, the release module obtains the M storage block indexes from the cache release request; the M storage block indexes are written into continuous M storage spaces starting from the third storage space in sequence; the second pointer is modified so that the second pointer points to a fourth storage space, the fourth storage space is the M+1th storage space starting from the third storage space, and the fourth storage space stores indexes of allocated storage blocks.

[0015] According to the third cache manager of the first aspect of the present application, the sixth cache manager of the first aspect of the present application is provided, the indexes of the storage blocks are stored in the memory in the form of an array or a linked list, and the array or the linked list corresponds to the at least N storage spaces.

[0016] According to the second aspect of the present application, the first control component of the second aspect of the present application is provided, which comprises a command manager, a first direct memory access (DMA) unit, a second DMA unit, a cache, and a cache manager as described in any one of the above first aspects, wherein the command manager sends a first data movement request to the first DMA unit, the first data movement request comprising a source address and a working mode; when the working mode is the first mode, in response to the first data movement request, the first DMA unit accesses the source address, obtains first data in the source address, and sends a cache allocation request to the cache manager; in response to the cache allocation request, the cache manager allocates N storage blocks and returns cache index information to the first DMA unit; after receiving the cache index information, the first DMA unit moves the first data to the N storage blocks according to the indexes of the N storage blocks.

[0017] According to the first control component of the second aspect of the present application, the second control component of the second aspect of the present application is provided, when the working mode in the first data migration request is the second mode, the first data migration request further comprises a target address; before sending the first data migration request to the first DMA unit, the command manager sends the cache allocation request to the cache manager; in response to the cache allocation request, the cache manager allocates the N storage blocks for the first data and returns cache index information to the command manager; the command manager acquires the target address according to the index of the N storage blocks.

[0018] According to the second control component of the second aspect of the present application, the third control component of the second aspect of the present application is provided, when the working mode is the second mode, in response to the first data migration request, the first DMA unit migrates the first data from the storage space corresponding to the source address to the N storage blocks.

[0019] According to one of the first to third control components of the second aspect of the present application, the fourth control component of the second aspect of the present application is provided, before sending the first data migration request to the first DMA unit, the command manager acquires a first command and generates the first data migration request according to the first command, the first command is a read command or a write command; when the first command is a write command, the source address in the first data migration request is a host address; when the first command is a read command, the source address in the first data migration request points to a flash memory.

[0020] According to one of the first to fourth control components of the second aspect of the present application, the fifth control component of the second aspect of the present application is provided, after migrating the first data to the N storage blocks, the first DMA unit returns completion information to the command manager to represent that the first data has been migrated to the cache; after receiving the completion information, the command manager sends a second data migration request to the second DMA unit, the second data migration request comprising a source address and a target address; in response to the second data migration request, the second DMA unit accesses the source address, acquires second data in the source address, and migrates the second data to the storage space corresponding to the target address.

[0021] According to the fifth control component of the second aspect of the present application, the sixth control component of the second aspect of the present application is provided, when the first command is a write command, the source address in the second data migration request is the physical address of the N storage blocks, and the target address points to a flash memory; when the first command is a read command, the source address in the second data migration request is the physical address of the N storage blocks, and the target address points to a host.

[0022] According to the seventh control component of the second aspect of the present application, the eighth control component of the second aspect of the present application is provided, the first data move request further comprises a feedback mode, the feedback mode indicates that the first DMA unit returns a completion information to the command manager every X first messages are moved, and the X is a positive integer less than or equal to N.

[0023] According to the seventh control component of the second aspect of the present application, the eighth control component of the second aspect of the present application is provided, the first data move request further comprises a feedback mode, the feedback mode indicates that the first DMA unit returns a completion information to the command manager every X first messages are moved, and the X is a positive integer less than or equal to N.

[0024] According to the first or sixth control component of the second aspect of the present application, the ninth control component of the second aspect of the present application is provided, after the second data is moved to the storage space corresponding to the target address, the second DMA unit sends a cache release request to the cache manager, and the cache release request carries the index of the storage block where the second data is located; in response to the cache release request, the cache manager saves the index of the storage block where the second data is located, so as to complete the resource release of the storage block where the second data is located.

[0025] The present application provides cache allocation and release management of the cache manager, instead of the cache management function of the firmware in the control component, thereby reducing the interaction times of software and hardware in the control component. The present application uses hardware and hardware interaction mode with faster interaction speed, solves the problem of long data transmission time between the host and the flash chip in the prior art, and achieves the effect of improving the interaction speed of the control component in the data transmission process, thereby improving the data transmission speed of the control component and reducing the data transmission time. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0027] Figure 1 The block diagram of the storage device in the prior art is shown in the figure;

[0028] Figure 2A The structure diagram of the cache manager provided by the embodiment of the present application is shown in the figure;

[0029] Figure 2BA state diagram of data stored in a memory according to an embodiment of the present application is provided;

[0030] Figure 2C A relationship diagram of a storage space and a pointer according to an embodiment of the present application is provided;

[0031] Figure 3A A structure diagram of a control component according to an embodiment of the present application is provided;

[0032] Figure 3B A flow diagram of the control component executing a read command according to an embodiment of the present application is provided;

[0033] Figure 4A A structure diagram of a DMA unit according to an embodiment of the present application is provided;

[0034] Figure 4B A diagram of a flip-flop storing and transmitting data according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0036] The terms "first", "second", and "third" and the like in the specification of the present application, the claims, and the drawings are used to distinguish different objects, but are not used to limit a particular order. In addition, the terms "include" and "have" and their various variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0037] The "embodiment" mentioned in the present application means that the specific features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art explicitly or implicitly understand that the embodiments described in the present application can be combined with other embodiments.

[0038] "Multiple" in the present application refers to two or more than two. "And / or" describes the association between the associated objects, indicating that there may be three relationships, for example, A and / or B, indicating that there are three cases of A alone, A and B together, or B alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0039] Figure 2A A structure diagram of a cache manager is given in the present application. As shown in Figure 2A The cache manager 200 includes an interface 201, an allocation module 202, a memory 203 and a release module 204. The interface 201 is coupled with the allocation module 202, and the interface 201 is also coupled with the release module 204. The allocation module 202 and the release module 204 are both coupled with the memory 203.

[0040] The interface 201 receives a cache allocation request and sends the cache allocation request to the allocation module 202. In response to the cache allocation request, the allocation module 202 allocates N free storage blocks, and generates first cache index information, the storage blocks are located in the cache, N is a positive integer, and the first cache index information includes the indexes of the N storage blocks. The allocation module 202 feeds back the first cache index information to the interface 201, and the interface 201 receives the first cache index information returned by the allocation module 202 and outputs the first cache index information. The memory 203 stores the indexes of at least N storage blocks. N is a positive integer, for example, N is equal to 64.

[0041] Specifically, the allocation module 202 manages the data stored in the memory 203, so that after receiving the cache allocation request, the allocation module 202 reads the data in the memory 203 to obtain the indexes of the N free storage blocks.

[0042] The interface 201 also receives a cache release request and sends the cache release request to the release module 204. The cache release request carries second cache index information, and the second cache index information includes the indexes of M storage blocks to be released, M being a positive integer. In response to the cache release request, the release module 204 writes the indexes of the M storage blocks into the memory 203, so that the storage blocks to be released become free storage blocks.

[0043] In the present application, the storage blocks are located in the cache, and the cache and the cache manager 200 have a mapping relationship, but the cache and the cache manager 200 do not necessarily need to be coupled. Except for the storage blocks used for the first time or erased data, the free storage blocks and the storage blocks to be released in the cache usually have data written in them. The difference between the free storage blocks and the storage blocks to be released is that the data in the free storage blocks has completed the data transmission between the host and the flash chip, that is, the data in the free storage blocks does not need to be used continuously. The data in the storage blocks to be released has not completed the data transmission between the host and the flash chip, that is, the data in the storage blocks to be released is still in use.

[0044] Optionally, in order to facilitate management, the memory 203 includes at least one storage space, when the memory 203 includes a plurality of storage spaces, the length of each storage space is equal, and each storage space stores the index of a storage block. For example, Figure 2B A schematic diagram in which the memory 203 includes 50 storage spaces is given, Figure 2B The length of each storage space in the memory 203 is 4 bytes, and the index of the storage block in each storage space is also 4 bytes. In the present embodiment, the length of the storage space can be adjusted according to the length of the index of the storage block, which is not limited herein.

[0045] Further optionally, the index of the storage block in the memory 203 is stored in the form of an array or a linked list, and the array or the linked list corresponds to at least N storage spaces. For example, Figure 2B The 50 storage spaces in the memory 203 correspond to the form of an array.

[0046] Optionally, the allocation module 202 and the release module 204 in the present embodiment manage the data in the memory 203 by using a pointer.

[0047] Specifically, Figure 2C A schematic diagram of the relationship between the storage space, the first pointer and the second pointer is given. Figure 2C There are 40 storage spaces in the memory 203. As Figure 2CAs shown, the allocation module 202 manages a first pointer 205, the first pointer 205 points to a first storage space C31, the first storage space C31 stores indexes of free storage blocks, and two storage spaces (C30 and C32) adjacent to the first storage space C31 store indexes of free storage blocks and indexes of allocated storage blocks respectively, wherein the storage space C32 stores indexes of free storage blocks, and the storage space C30 stores indexes of allocated storage blocks. When allocating N storage blocks, the allocation module 202 reads indexes of N storage blocks from N continuous storage spaces starting from the first storage space C31; modifies the first pointer 205 so that the first pointer points to a second storage space, the second storage space is the N+1th storage space starting from the first storage space C31, and the second storage space stores indexes of free storage blocks. For example, N=5, and the second storage space is the storage space C36.

[0048] Continuing to refer to Figure 2C , the release module 204 manages a second pointer 207, the second pointer 207 points to a third storage space C15, the third storage space C15 stores indexes of allocated storage blocks, and two storage spaces (C14 and C16) adjacent to the third storage space C15 store indexes of free storage blocks and indexes of allocated storage blocks respectively, wherein the storage space C14 stores indexes of free storage blocks, and the storage space C16 stores indexes of allocated storage blocks. When writing indexes of M storage blocks into the memory 203, the release module 204 obtains indexes of M storage blocks from the cache release request; writes the indexes of M storage blocks into M continuous storage spaces starting from the third storage space C15 in sequence; modifies the second pointer 207 so that the second pointer 207 points to a fourth storage space, the fourth storage space is the M+1th storage space starting from the third storage space C15, and the fourth storage space stores indexes of allocated storage blocks. For example, M=10, and the fourth storage space is the storage space C25.

[0049] Referring to Figure 3A , the control component 300 includes a command manager 301, a direct memory access (DMA) unit 302, a DMA unit 303, a cache 304, and the cache manager 200 as in the above embodiments. The command manager 301 generates a first data moving request or a second data moving request in response to a received read / write command. The control component 300 is coupled with the host 310 and the flash chip 320.

[0050] The read command and the write command both indicate data transmission between the host and the flash chip, however, since the data cannot be directly transmitted between the host and the flash chip, a buffer (for example, a Dynamic Random Access Memory, DRAM) is usually used as a transfer station of the data in the prior art. Thus, when a read command or a write command is executed, the data transmission is performed in two stages, one stage is data transmission between the host and the buffer, and the other stage is data transmission between the buffer and the flash chip. The first data moving request and the second data moving request in the embodiment correspond to the two stages. For example, the command manager 301 receives a read command, the first data moving request generated by the command manager 301 indicates moving first data from the flash chip 320 to the buffer 304, and the second data moving request generated by the command manager 301 indicates moving second data from the buffer 304 to the host 310. For another example, the command manager 301 receives a write command, the first data moving request generated by the command manager 301 according to the write command indicates moving first data from the host 310 to the buffer 304, and the second data moving request generated by the command manager 301 indicates moving second data from the buffer 304 to the flash chip 320. In the embodiment, the first data is data whose source address points to the host 310 or the flash chip 320, and the second data is data whose source address points to the buffer 304. It should be noted that the first DMA unit in the present application is a DMA unit for executing the first data moving request, and the second DMA unit is a DMA unit for executing the second data moving request. Figure 3A The DMA unit 302 and the DMA unit 303 in the embodiment can execute both the first data moving request and the second data moving request, that is, the first DMA unit and the second DMA unit in the present application are not limited to a certain fixed DMA unit.

[0051] Specifically, in response to the read command or the write command, the command manager 301 sends the first data moving request to the first DMA unit, and the first data moving request includes a source address and a working mode. In the embodiment, the working mode includes a first mode and a second mode, where the first mode is a mode of requesting allocation of the buffer by the DMA unit, and the second mode is a mode of allocating the buffer by the CPU. Optionally, the command manager 301 determines the first DMA unit according to the type of the read / write command or the source address. For example, the command manager 301 receives a read command, the read command carries a logical page address of the flash as the source address, and the first DMA unit is the DMA unit 303. The command manager 301 sends the first data moving request to the DMA unit 303.

[0052] The embodiment is described below taking that the command processor 301 receives a write command as an example.

[0053] In the first mode, in response to the first data migration request, the DMA unit 302 accesses the source address, obtains the first data in the source address, and sends a cache allocation request to the cache manager 200. Specifically, the DMA unit 302 learns that the working mode in the first data migration request is the first mode, generates the cache allocation request, and sends the cache allocation request to the cache manager 200.

[0054] In response to the cache allocation request, the cache manager 200 allocates N storage blocks and returns cache index information to the DMA unit 302. The storage blocks in this embodiment are located in the cache 304, and N is a positive integer. The cache index information includes the indexes of the N storage blocks, for example, the cache index information is the physical addresses of the N storage blocks. After receiving the cache index information, the DMA unit 302 migrates the first data to the N storage blocks according to the indexes of the N storage blocks.

[0055] In the second mode, the first data migration request further includes a target address. Specifically, in the second mode, the cache allocation is performed by the command manager 301, and the command manager 301 carries the indexes of the allocated N storage blocks in the first data migration request sent to the command manager 301, so that the command manager 301 directly obtains the target address.

[0056] For example, before sending the first data migration request to the DMA unit 302, the command manager 301 sends a cache allocation request to the cache manager 200. In response to the cache allocation request, the cache manager 200 allocates N storage blocks for the first data and returns cache index information to the command manager 301. The command manager 301 obtains the target address according to the indexes of the N storage blocks.

[0057] Alternatively, in the second mode, in response to the first data migration request, the DMA unit 302 migrates the first data from the storage space corresponding to the source address to the N storage blocks. The DMA unit 302 directly obtains the source address and the target address from the first data migration request, so that the DMA unit 302 directly accesses the source address to obtain the first data and sends the first data to the N storage blocks.

[0058] Alternatively, before sending the first data migration request to the DMA unit 302, the command manager 301 obtains a first command and generates the first data migration request according to the first command, the first command being a read command or a write command; when the first command is a write command, the source address in the first data migration request is a host address; and when the first command is a read command, the source address in the first data migration request points to a flash memory.

[0059] Optionally, after the first data is moved to the N storage blocks, the DMA unit 302 returns completion information to the command manager 301 to indicate that the first data has been moved to the cache 304. In this embodiment, the data movement of one stage is completed before the data movement of another stage is started. In this application, the DMA unit 302 sends the completion information to the command manager 301 after the data movement is completed to inform the command manager 301 that the next stage of data movement can be continued.

[0060] After receiving the completion information, the command manager 301 sends a second data movement request to the DMA unit 303, and the second data movement request includes a source address and a target address. In response to the second data movement request, the DMA unit 303 accesses the source address, obtains the second data in the source address, and moves the second data to the storage space corresponding to the target address. In this embodiment, the source address points to the cache 304, the target address points to the flash chip 320, the DMA unit 303 accesses the source address, obtains the second data from the N storage blocks, and stores the second data in the flash chip 320. It should be noted that, in order to distinguish the two stages of data transmission, the first data movement request corresponds to the first data, and the second data movement request corresponds to the second data. For a write command, the second data is actually the first data stored in the N storage blocks.

[0061] In some embodiments, when the first command is a write command, the source address in the second data movement request is the physical address of the N storage blocks, and the target address is the logical page address of the flash chip 320. When the first command is a read command, the source address in the second data movement request is the physical address of the N storage blocks, and the target address is the host address.

[0062] In some embodiments, when the first data is moved to the N storage blocks, the first DMA unit divides the first data into N first messages, and moves the N first messages to the N storage blocks in sequence, each storage block stores a different first message, and each first message has the same length. For example, N = 24, and the first command is a read command. Then, the DMA unit 303 divides the first data into 24 first messages with the same length, and moves the 24 first messages to the 24 storage blocks in sequence.

[0063] Optionally, when the second data is moved to the storage space corresponding to the target address, the second DMA unit divides the second data into a plurality of second messages, and moves the plurality of second messages to the storage space corresponding to the target address in sequence.

[0064] In some embodiments, the first data migration request further comprises a feedback mode, the feedback mode indicating that the first DMA unit returns one completion information to the command manager per migration of X first messages, X being a positive integer less than or equal to N. For example, the first command is a read command, X = 6, and N = 24. Then, the DMA unit 303 feeds back completion information to the command manager 301 four times per migration of 6 first messages. The completion information represents the current state of the migrated data. For example, the first feedback of the completion information indicates that 6 first messages have been migrated to the cache 304, and the second feedback of the completion information indicates that another 6 first messages have been migrated to the cache 304. Alternatively, the second data migration request comprises a feedback mode, which can be referred to the description of the feedback mode of the first data migration request, and will not be described herein.

[0065] Alternatively, after the second data is migrated to the storage space corresponding to the target address, the second DMA unit sends a cache release request to the cache manager, the cache release request carrying the index of the storage block where the second data is located. In response to the cache release request, the cache manager saves the index of the storage block where the second data is located, to complete the release of the resources of the storage block where the second data is located. For example, the second data migration request instructs the DMA unit 303 to migrate the second data from the cache 304 to the flash chip 320. After the second data is migrated to the flash chip 320, the DMA unit 303 sends a cache release request to the cache manager 200, the cache release request carrying the index of the storage block where the second data has been migrated. The cache manager 200 saves the index of the storage block, to complete the release of the resources of the storage block, so that the storage block pointed by the index becomes an idle storage block, and the data can be stored in the storage block again.

[0066] Alternatively, the command manager 301 in the present application can be replaced by a CPU.

[0067] Figure 3B A flowchart of the process of the control component 300 executing a read command is shown. The process of the control component 300 processing a read command is described below by taking the read command as an example.

[0068] In step S310, the control component 300 sends the read command to the command manager 301. In step S320, the command manager 301 generates a first data migration request according to the read command, and sends the first data migration request to the DMA unit 303. The first data migration request carries the source address of the logical page address of the flash chip 320, and the working mode is the first mode. In step S330, the DMA unit 303 sends a cache allocation request to the cache manager 200, and accesses the logical page address of the flash chip 320 to obtain the first data, in response to the first data migration request.

[0069] At step S340, the DMA unit 303 receives the target address fed back by the cache manager 200, moves the first data to the storage space corresponding to the target address, and feeds back completion information to the command manager 301. The target address is a physical address in the cache 304. At step S350, the command manager 301 sends a second data moving request to the DMA unit 302, where the source address in the second data moving request is a physical address in the cache 304, and the target address is a host address. At step S360, the DMA unit 302 moves the second data from the cache 304 to the host, and sends a cache release request to the cache manager 200, where the cache release request carries the physical address in the cache 304. At step S370, after moving the second data, the DMA unit 302 feeds back completion information to the command manager 301 to indicate that the read command is executed.

[0070] Referring to Figure 4A , Figure 4A A structure diagram of a direct memory access (DMA) unit is given, where the DMA unit 400 includes a control logic module 401, a timing module 402, a buffer register 403, and a flip-flop 404.

[0071] The DMA unit 400 receives a data moving request, where the data moving request carries a source address and a working mode. In this embodiment, the data moving request is generated by a command manager or a CPU in response to a read / write command. For example, the command manager generates the data moving request in response to a read command, where the source address in the request points to a flash memory chip or a cache. For another example, the data moving request is generated by the CPU in response to a write command, where the source address in the request points to a host or a cache. In addition to the host and the command manager, the data moving request can also be generated by other devices with command processing capability, which is not limited herein. The data moving request in this embodiment carries the source address and the working mode, and optionally carries a target address according to the working mode. The working mode herein is the same as described in the foregoing embodiments, which is not repeated herein. In a first mode, the data moving request does not carry the target address; in a second mode, the data moving request carries the target address.

[0072] When the source address points to the host or the flash memory chip, the DMA unit 400 accesses the source address to obtain first data in response to the data moving request. For example, when the source address is a host address, the DMA unit 400 controls the bus to access the host address, thereby obtaining the first data from the host. For another example, when the source address is a logical page address of the flash memory chip, the DMA unit 400 controls the bus to access the flash memory chip through a media interface controller, thereby obtaining the first data from the flash memory chip.

[0073] The DMA unit 400 outputs a cache allocation request to obtain the target address after a preset time period from accessing the source address, and the preset time period is greater than or equal to 0. In this embodiment, the cache allocation request is output to a device that manages the cache. For example, if the cache is managed by a cache manager, the cache allocation request is sent to the cache manager. For another example, if the cache is managed by firmware, the DMA unit 400 sends the cache allocation request to a CPU (the firmware runs on the CPU). After receiving the cache allocation request, the corresponding device (for example, the cache manager and the CPU) allocates a plurality of memory blocks (the memory blocks are located in the cache) and returns the indexes of the memory blocks to the DMA unit 400. According to the indexes of the memory blocks, the target address can be obtained, or the indexes of the memory blocks are the target address. After obtaining the target address, the DMA unit 400 moves the first data to the memory space where the target address is located. The preset time period in this embodiment is related to the device that manages the cache. For example, when the cache manager is used, the preset time period is 3us. When the firmware manages the cache, the preset time period is 10us. The preset time period can also be 0. The preset time period is configured in the initialization process of the DMA unit 400, or the preset time period can be carried in the data move request.

[0074] Specifically, after receiving the data move request, the DMA unit 400 parses the data move request by the control logic module 401 to obtain a parsing result. In this embodiment, the data move request has a fixed format. The control logic module 401 extracts the information required for data move from the data move request according to a preset rule and stores the information in a corresponding register. The preset rule is related to a communication protocol, which is not limited here. For example, the source address in the data move request is stored in an address register (not shown in the figure).

[0075] According to the analysis result, the control logic module 401 controls the bus to access the source address. In this embodiment, when sending the data transfer request to the DMA unit 400, the CPU gives the control right of the bus to the DMA unit 400, and the DMA unit 400 does not need to request the control right of the bus, which reduces the interaction behavior and improves the data transmission efficiency. It should be noted that the data transfer request sent to the DMA unit 400 is not necessarily the CPU. The control logic module 401 sends a timing start signal to the timing module 402. In this embodiment, the timing module 402 receives an externally input clock signal, thereby realizing timing and maintaining the same time state with external devices. The timing start signal is used to instruct the timing module 402 to start the timing function. In response to the timing start signal, the timing module 402 starts timing, and after the timing time reaches a preset time length, the timing module 402 feeds back a timing completion signal to the control logic module 401. In response to the timing completion signal, the control logic module 401 outputs a cache allocation request. In particular, when the preset time length is 0, no timing is performed, and the control logic module 401 directly outputs the cache allocation request.

[0076] In some embodiments, according to the analysis result, the control logic module 401 controls the bus to access the source address, and the control logic module 401 outputs the cache allocation request. Before receiving the feedback target address, if the first data has been acquired, the flip-flop 404 is used to temporarily save the part of the first data that has been transferred to the DMA unit, until the target address is received. After receiving the target address, the control logic module 401 controls the bus to transfer the data in the flip-flop 404 and part of the first data in the bus to the storage space where the target address is located.

[0077] In this embodiment, the first data is not transferred from the source address to the DMA unit 400 at one time, but is divided into multiple times for transmission, such as one byte at a time. For example, the total length of the first data is 20 bytes, and 1 byte is transmitted each time. Before the target address is acquired, 5 bytes of the first data are transferred to the DMA unit 400, and the flip-flop 404 is used to temporarily save the 5 bytes until the target address is acquired, and then the flip-flop is stopped to save the other 15 bytes. After receiving the target address, the control logic module 401 first transfers the 5 bytes of data in the flip-flop 404 to the storage space where the target address is located according to the time sequence, and then transfers the 15 bytes of data still being transmitted in the bus to the storage space.

[0078] Optionally, after the target address is acquired, the flip-flop 404 is continued to be used to save and transfer the remaining 15 bytes of the first data. Referring to Figure 4B , Figure 4B A schematic diagram of saving and transferring the first data by using the flip-flop 404 is given. Figure 4BThe five flip-flops are flip-flop 404-1, 404-2, 404-3, 404-4 and 404-5. Before the target address is received at T0, the flip-flops 404 store the states of five bytes of data, each flip-flop stores one byte of data, and the flip-flops 404-1, 404-2, 404-3, 404-4 and 404-5 store the data D1, D2, D3, D4 and D5 respectively. After the target address is received at T1 and one byte of data has been transmitted, the flip-flops 404-1, 404-2, 404-3, 404-4 and 404-5 store the data D2, D3, D4, D5 and D6 respectively. At T2, only three bytes of data remain to be transmitted, and the flip-flops 404-1, 404-2, 404-3, 404-4 and 404-5 store the data D18, D19, D20, 0 and 0 respectively.

[0079] In another embodiment, according to the analysis result, the control logic module 401 controls the bus to access the source address. After the first data is received, the control logic module 401 outputs a buffer allocation request and temporarily stores the part of the first data that has been transmitted to the DMA unit 400 in the buffer register 403 until the target address is received. After the target address is received, the control logic module 401 controls the bus to move the data in the buffer register 403 and the part of the first data in the bus to the storage space where the target address is located. In this embodiment, the buffer allocation request is sent after the first data is received, and the capacity of the flip-flop cannot meet the amount of data that needs to be temporarily stored, so the buffer register is used to temporarily store the data, thereby saving hardware resources.

[0080] In one embodiment, the part of the first data that has been transmitted to the DMA unit is temporarily stored in the flip-flop 404 until the target address is received, including: the control logic module 401 sends a start signal to the flip-flop 404 every period until the target address is received to stop sending the start signal; and the flip-flop 404 stores the timing state of the part of the first data received in the current period after receiving the start signal. Optionally, the flip-flop 404 is a D-type flip-flop. The flip-flop 404 stores one byte of data when receiving the start signal. One byte of data is transmitted into the DMA unit 400 every period, so the start signal is sent every period to make the flip-flop 404 store the data entered into the DMA unit 400 in the current period.

[0081] In some embodiments, when the source address points to the cache, the DMA unit accesses the source address to obtain the second data. When the source address points to the cache, the data movement request further carries a target address. The control logic module 401 controls the bus to move the second data to a storage space corresponding to the target address. For example, the target address is a host address, and the second data is moved from the cache to the host. The control logic module 401 outputs a cache release request carrying a cache index of the source address to complete resource release.

[0082] In one embodiment, outputting the cache release request carrying the cache index of the source address includes: the control logic module 401 outputs a cache release request carrying a cache index corresponding to a fixed length of data after moving the fixed length of data; or the control logic module 401 outputs a cache release request carrying a cache index corresponding to the second data after moving the second data.

[0083] In this embodiment, the control logic module 401 outputs the cache release request in multiple ways. For example, a cache release request is outputted once every 4 bytes of data are moved, and the cache release request carries a cache index corresponding to the 4 bytes of data. For another example, the control logic module 401 sends a cache release request after moving the second data, and the cache release request includes a cache index corresponding to the second data as a whole. The way of outputting the cache release request in this embodiment can be configured when the DMA unit 400 is initialized, which is not limited herein.

[0084] In some embodiments, if the data movement request further includes a target address, the DMA unit 400 moves the first data to a storage space corresponding to the target address after obtaining the first data from the source address. In this embodiment, the control logic module 401 directly moves the first data to the storage space corresponding to the target address after accessing the source address, without temporarily saving the data by using the flip-flop 404 or the buffer memory 403.

[0085] Optionally, the DMA unit 400 in the present application can be used in combination with the cache manager 200 and the control component 300 in the above embodiments, and the use mode can refer to the description in the above, which is not expanded herein. When used in combination, since the DMA unit 400 and the cache manager 200 are both hardware, the interaction mode between the DMA unit 400 and the cache manager 200 is a very fast hardware interaction mode, so that the interaction speed inside the control component 300 can be further reduced, and the technical effect of further improving the data transmission speed between the host and the flash chip is achieved.

[0086] While the examples of the present application are described with reference to the drawings, they are merely examples and are not intended to limit the present application. Changes, additions and / or deletions can be made to the embodiments without departing from the scope of the present application.

[0087] The above description is merely illustrative of the application and is not intended to limit the scope of the application. Any changes and / or modifications which come within the scope of the present application as disclosed herein are intended to be embraced by the above description. The scope of the application should be determined by the scope of the claims below.

Claims

1. A control unit, characterized by The control unit comprises a command manager, a first direct memory access (DMA) unit, a second DMA unit, a cache and a cache manager, wherein the cache manager comprises an interface, an allocation module and a memory. The command manager sends a first data movement request to the first DMA unit, and the first data movement request comprises a source address and a working mode. When the working mode is a first mode, the first DMA unit accesses the source address to obtain first data in the source address and sends a cache allocation request to the cache manager in response to the first data movement request. The interface receives the cache allocation request and sends the cache allocation request to the allocation module. In response to the cache allocation request, the allocation module of the cache manager allocates N free memory blocks and generates first cache index information. The memory blocks are located in the cache, N is a positive integer, the first cache index information comprises indexes of the N memory blocks, and the memory stores the indexes of at least N memory blocks. The interface receives the first cache index information returned by the allocation module and returns the first cache index information to the first DMA unit. After receiving the first cache index information, the first DMA unit moves the first data to the N memory blocks according to the indexes of the N memory blocks. When the working mode in the first data movement request is a second mode, the first data movement request further comprises a target address.

2. The control unit according to claim 1, wherein Before sending the first data movement request to the first DMA unit, the command manager sends the cache allocation request to the cache manager. The interface receives the cache allocation request and sends the cache allocation request to the allocation module. In response to the cache allocation request, the allocation module of the cache manager allocates the N memory blocks for the first data and returns cache index information to the command manager. The command manager obtains the target address according to the indexes of the N memory blocks. When the working mode is the second mode, the first DMA unit moves the first data from a memory space corresponding to the source address to the N memory blocks in response to the first data movement request.

3. The control unit of claim 2, wherein 4. The control unit according to any one of claims 1-3, wherein After moving the first data to the N memory blocks, the first DMA unit returns completion information to the command manager to indicate that the first data has been moved to the cache. After receiving the completion information, the command manager sends a second data movement request to the second DMA unit, and the second data movement request comprises a source address and a target address. In response to the second data movement request, the second DMA unit accesses the source address to obtain second data in the source address and moves the second data to a memory space corresponding to the target address. The cache manager further comprises a release module.

5. The control unit of claim 4, wherein ​ After the second data is moved to the storage space corresponding to the target address, the second DMA unit sends a cache release request to the cache manager, the cache release request carrying second cache index information of the storage block where the second data is located, the second cache index information including indexes of M storage blocks to be released, the M storage blocks to be released being located in the cache, M being a positive integer; The interface receives the cache release request and sends the cache release request to the release module, and in response to the cache release request, the release module of the cache manager writes indexes of the M storage blocks where the second data is located into the memory, so that the M storage blocks to be released become idle storage blocks, completing resource release of the storage block where the second data is located.

6. The control unit according to claim 1 or 5, wherein The memory includes at least one storage space, each storage space having equal length, and each storage space storing an index of a storage block.

7. The control unit of claim 1, wherein The allocation module manages a first pointer, the first pointer pointing to a first storage space, the first storage space storing an index of an idle storage block, and two storage spaces adjacent to the first storage space respectively storing an index of an idle storage block and an index of an allocated storage block; When the N storage blocks are allocated, the allocation module reads indexes of N storage blocks from the first storage space to the Nth storage space in sequence; The first pointer is modified so that the first pointer points to a second storage space, the second storage space being the N+1th storage space from the first storage space, and the second storage space storing an index of an idle storage block.

8. The control unit of claim 5, wherein The release module manages a second pointer, the second pointer pointing to a third storage space, the third storage space storing an index of an allocated storage block, and two storage spaces adjacent to the third storage space respectively storing an index of an idle storage block and an index of an allocated storage block; When the indexes of the M storage blocks are written into the memory, the release module obtains the indexes of the M storage blocks from the cache release request; The indexes of the M storage blocks are written into the third storage space to the Mth storage space in sequence; The second pointer is modified so that the second pointer points to a fourth storage space, the fourth storage space being the M+1th storage space from the third storage space, and the fourth storage space storing an index of an allocated storage block.

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