Imaging device and control method

Abstract

An imaging device (100) includes a plurality of pixels (110) arranged in a matrix, each of the plurality of pixels (110) including a photoelectric conversion section (1) that converts light into signal charge and a charge accumulation section (FD) that accumulates the signal charge, and a control circuit that causes, until a trigger signal for instructing start of exposure is accepted, pixels belonging to at least one row among the plurality of pixels (110) to sequentially perform, in units of rows or in units of multiple rows, a reset operation that initializes a potential of the charge accumulation section (FD), and that, after the trigger signal is accepted, causes the plurality of pixels (110) to simultaneously perform an exposure operation that accumulates the signal charge to the charge accumulation section (FD) without causing the pixels belonging to at least one row among the plurality of pixels (110) to perform the reset operation.

Description

Technical Field

[0001] This disclosure relates to imaging devices, etc., which have a photoelectric conversion unit that receives light and generates electrical charge. Background Technology

[0002] In recent years, digital cameras have been widely used in various fields, such as camcorders, digital cameras, surveillance cameras, and vehicle cameras. These digital cameras use either CCD (Charge Coupled Device) or CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging elements, with CMOS gradually becoming the mainstream. This is because CMOS solid-state imaging elements can be manufactured using general CMOS processes, thus utilizing existing facilities, ensuring a stable supply, and allowing peripheral circuitry to coexist within the same chip, enabling high-speed signal readout and achieving high speed / high resolution, among other advantages.

[0003] In CMOS solid-state imaging devices, for example, the CDS (Correlated Double Sampling) technology disclosed in Patent Document 1 is widely used.

[0004] Here, we will provide a detailed explanation of general CDS technology.

[0005] Patent Document 1 Figure 2 The pixel circuit shown consists of a PD (photodetector) section for detecting light signals, an FD (floating diffusion) section for converting the charge generated in the PD section into a voltage signal and temporarily holding it, a TX transistor for transferring the charge signal from the PD section to the FD section, a RES transistor for resetting the voltage in the FD section, an AMP transistor for amplifying the voltage signal in the FD section, and a SEL transistor for outputting the amplified signal. Generally, the PD section is composed of a photodiode. The TX transistor is controlled by a signal... The RES transistor is controlled by a control signal. Control, the SEL transistor is controlled by a control signal control.

[0006] As a driver for pixels, as shown in Figure 6 of Patent Document 1, firstly... The voltage level is set high to turn on the RES transistor, resetting the charge accumulated in the FD section. Next, the voltage level is set high again. To turn off the RES transistor, it must be brought to a low level, after which... The SEL transistor is turned on by becoming high, thereby outputting a reset voltage. At this time, the reset voltage contains reset noise, known as kTC noise, thus causing time-varying fluctuations. Afterwards, it is... A high level is applied to turn on the TX transistor, thereby transferring the signal charge accumulated in the PD section to the FD section. Subsequently, the high level is applied to... A low level is used to turn off the TX transistor, outputting a signal voltage. This signal voltage is a voltage that changes relative to the reset voltage by the amount corresponding to the accumulated signal charge. Therefore, in subsequent circuits, by obtaining the difference between the reset voltage (in other words, the reset charge) and the signal voltage (in other words, the reset charge + the signal charge), kTC noise can be eliminated, and only the voltage corresponding to the accumulated signal charge can be detected.

[0007] The above explains CDS technology, which effectively suppresses reset noise (kTC noise) generated when resetting the pixel. The suppression of reset noise by CDS technology is one of the important reasons why CMOS solid-state imaging devices have gradually become mainstream.

[0008] Prior art literature

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2010-129705

[0011] Patent Document 2: Japanese Patent Application Publication No. 2008-28516

[0012] Patent Document 3: Japanese Patent Application Publication No. 2014-78870

[0013] Patent Document 4: Japanese Patent Application Publication No. 2001-177084

[0014] Patent Document 5: Japanese Patent Application Publication No. 2010-258682 Summary of the Invention

[0015] The problem to be solved by the present invention

[0016] In the field of imaging devices, there is a need for imaging devices capable of shortening the delay from the trigger signal indicating the start of exposure until the start of exposure while reducing noise. The object of this disclosure is to provide an imaging device, etc., capable of shortening the delay from the trigger signal indicating the start of exposure until the start of exposure while reducing noise.

[0017] Methods for solving problems

[0018] One aspect of the present disclosure relates to an imaging device comprising a plurality of pixels arranged in a matrix and a control circuit. Each of the plurality of pixels includes a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge. The control circuit, until receiving a trigger signal indicating the start of exposure, causes pixels belonging to at least one row among the plurality of pixels to sequentially perform a reset operation to initialize the potential of the charge storage unit, either row by row or multiple rows by multiple rows. After receiving the trigger signal, the control circuit does not cause pixels belonging to at least one row among the plurality of pixels to perform the reset operation, but instead causes the plurality of pixels to simultaneously perform an exposure operation to store the signal charge in the charge storage unit.

[0019] One aspect of this disclosure relates to a control method for a camera device having a plurality of pixels arranged in a matrix. Each of the plurality of pixels includes a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge. In this control method, until a trigger signal indicating the start of exposure is received, pixels belonging to at least one row of the plurality of pixels are sequentially reset to initialize the potential of the charge storage unit, either row-wise or in multiple rows. After receiving the trigger signal, pixels belonging to at least one row of the plurality of pixels are not reset, but the plurality of pixels simultaneously perform an exposure operation to store the signal charge in the charge storage unit.

[0020] Invention Effects

[0021] According to one aspect of the present disclosure, the camera device can shorten the delay from the trigger signal indicating the start of exposure to the start of exposure while reducing noise. Attached Figure Description

[0022] Figure 1A This is a schematic diagram illustrating an exemplary circuit configuration of the camera device according to Embodiment 1.

[0023] Figure 1B This is a schematic diagram illustrating the exemplary circuit configuration of the pixels of the camera device according to Embodiment 1.

[0024] Figure 1C This is a diagram schematically illustrating other exemplary circuit configurations of the pixels of the imaging device according to Embodiment 1.

[0025] Figure 2 This is a cross-sectional view schematically showing the device structure of the pixels of the camera device according to Embodiment 1.

[0026] Figure 3This is a diagram schematically illustrating other exemplary circuit configurations of the pixels of the imaging device according to Embodiment 1.

[0027] Figure 4 This is a diagram illustrating an example of the photoelectric conversion characteristics of an organic photoelectric conversion film.

[0028] Figure 5A This is a timing diagram used to illustrate an example of the operation in the camera device involved in the comparative example.

[0029] Figure 5B This is a flowchart illustrating an example of the actions in the camera device involved in the comparative example.

[0030] Figure 5C This is a flowchart illustrating other examples of actions within the camera device involved in the comparative example.

[0031] Figure 6A This is a timing diagram illustrating an example of the operation in the camera device according to Embodiment 1.

[0032] Figure 6B This is a flowchart illustrating an example of the operation in the camera device according to Embodiment 1.

[0033] Figure 6C This is a timing diagram used to illustrate other examples of the operation in the camera device according to Embodiment 1.

[0034] Figure 6D This is a flowchart illustrating other examples of the operation in the camera device according to Embodiment 1.

[0035] Figure 7 This is a flowchart illustrating another example of the operation in the camera device according to Embodiment 1.

[0036] Figure 8 This is a schematic diagram illustrating an example of the configuration of the camera device according to Embodiment 2.

[0037] Figure 9 This is a block diagram illustrating an example of the configuration of the camera system according to Embodiment 3. Detailed Implementation

[0038] (The insights that form the basis of this disclosure)

[0039] In the aforementioned CDS technology, the transfer of signal charge generated in the PD section, which detects the optical signal, to the FD section, which converts it into a voltage signal, is based on the premise of complete transfer. To achieve complete transfer, issues such as increased process complexity and manufacturing costs arise.

[0040] In addition, as disclosed in Patent Document 2, a solid-state imaging element with a pixel structure that realizes a global shutter has recently been proposed as a solid-state imaging element that can capture images of high-speed moving objects without distortion.

[0041] In the solid-state imaging element disclosed in Patent Document 2, after transferring the charge of the PD section of all pixels to the FD section, readout is performed sequentially row by row. Therefore, the CDS technique, which reads out the reset voltage before reading out the signal voltage of the FD section, cannot be applied. Instead, the FD section is reset after reading out the signal voltage, the reset voltage is read out, and the difference between the signal voltage and the reset voltage is obtained. However, the reset noise contained in the signal voltage is not related to the reset noise contained in the reset voltage, resulting in the following problem: reset noise cannot be removed, and random noise is greater compared to reading out using the aforementioned CDS technique.

[0042] In addition, recently, as a solution to the problem of reduced sensitivity caused by the decrease in the area of ​​the photodetector (PD) section due to the reduction in the area of ​​each pixel as the pixel count increases, an organic CMOS sensor using an organic photoelectric conversion film in the PD section, as disclosed in Patent Document 3, has been proposed. This organic CMOS sensor, by providing an organic photoelectric conversion film as a light-receiving section above the readout circuit, can achieve a large light-receiving area even with a reduction in pixel size, thus enabling high sensitivity.

[0043] On the other hand, sensors that use photoelectric conversion films, such as organic CMOS sensors, have a structure that electrically connects the PD section and the semiconductor layer with metal wiring, thus making it impossible to completely transfer signal charge. Therefore, generally speaking, a structure that reads out the signal charge of the PD section by electrically connecting the PD section and the FD section is used to avoid incomplete transfer of noise and afterimages.

[0044] Therefore, when the voltage change due to the charge accumulated during exposure is detected in the FD section, the signal voltage of the FD section is read out. Then, the reset voltage after the FD section is reset is read out, and the difference between the signal voltage and the reset voltage is obtained. However, the reset noise contained in the signal voltage is not correlated with the reset noise contained in the reset voltage. Therefore, the following problem exists: reset noise cannot be removed, and random noise is greater compared to readout using the CDS technique described above.

[0045] As such, although CDS technology is effective in suppressing reset noise, it has the following problems: the manufacturing cost increases as the process becomes more complex, which makes it unsuitable for CMOS solid-state imaging elements with effective structures in terms of both functionality and performance.

[0046] In addition, for example, a technique for removing reset noise row by row without using CDS technology has been proposed, as disclosed in Patent Document 4.

[0047] However, when using methods to remove reset noise line by line, especially in specifications for industrial cameras, commercial playback cameras, and medical cameras, when exposure begins based on an external trigger signal, particularly when an instruction signal indicating the simultaneous exposure of at least two pixels or the entire area to begin exposure is input, time is consumed in removing the reset noise of each pixel line by line before exposure. As a result, a time delay of several milliseconds to tens of milliseconds occurs from the issuance of the trigger signal until the start of exposure, causing problems such as the inability to photograph the desired object and the inability to perform high-speed inspection. The trigger signal may be, for example, a signal emitted in response to other mechanical actions or a signal emitted due to a person pressing the shutter button.

[0048] In the solid-state imaging element disclosed in Patent Document 5, although a configuration that enables high-speed exposure to be started by pre-setting two trigger signals is adopted, signal control becomes complicated.

[0049] Therefore, in view of the above, the object of this disclosure is to provide an imaging device having a solid-state imaging element that can properly remove reset noise and start exposure at high speed in response to external trigger signals.

[0050] A summary of one aspect of this disclosure is as follows.

[0051] One aspect of the present disclosure relates to an imaging device comprising a plurality of pixels arranged in a matrix and a control circuit. Each of the plurality of pixels includes a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge. The control circuit, until receiving a trigger signal indicating the start of exposure, causes pixels belonging to at least one row among the plurality of pixels to sequentially perform a reset operation to initialize the potential of the charge storage unit, either row by row or multiple rows by multiple rows. After receiving the trigger signal, the control circuit does not cause pixels belonging to at least one row among the plurality of pixels to perform the reset operation, but instead causes the plurality of pixels to simultaneously perform an exposure operation to store the signal charge in the charge storage unit.

[0052] Therefore, after receiving the trigger signal, the control circuit does not reset the multiple pixels belonging to at least one row, but performs the exposure operation instead. Thus, compared to the case where all pixels are reset after receiving the trigger signal, the time from receiving the trigger signal to the exposure operation is shortened. Furthermore, since the pixels belonging to at least one row are reset until the trigger signal is received, the potential is initialized before the signal charge is accumulated. In particular, when the reset operation is performed while suppressing reset noise, the noise in the signal charge of the pixels belonging to at least one row is reduced. Therefore, the imaging device according to this method can shorten the delay from the trigger signal indicating the start of exposure to the start of exposure while reducing noise.

[0053] Alternatively, for example, the control circuit may cause all pixels among the plurality of pixels to perform the reset action sequentially, either row-by-row or multi-row-by-multiple-row, until it receives the trigger signal.

[0054] Therefore, until the trigger signal is received, a reset action is performed on multiple pixels belonging to all rows. Thus, the potential is initialized before the signal charge is accumulated. In particular, when the reset action is performed while suppressing reset noise, the noise in the signal charge of all multiple pixels is reduced.

[0055] Alternatively, for example, the control circuit may cause the pixels belonging to at least one row among the plurality of pixels to perform the reset action multiple times until it receives the trigger signal.

[0056] Therefore, the control circuit performs multiple reset operations on pixels belonging to at least one row until a trigger signal is received. Thus, in pixels that undergo multiple reset operations, the charge accumulated in the charge storage area due to dark current, etc., after one reset operation, is reinitialized through the reset operation. Consequently, noise caused by the charge accumulated due to dark current, etc., is reduced, and the imaging device according to this method can further reduce noise.

[0057] Alternatively, for example, the control circuit may cause the plurality of pixels to repeatedly perform the reset action sequentially, either in rows or in multiple rows, until it receives the trigger signal.

[0058] Therefore, the control circuit repeatedly resets multiple pixels until a trigger signal is received. Thus, the charge accumulated in the charge storage section due to dark current, etc., after each reset is performed, is repeatedly initialized through the reset action. Consequently, noise caused by the charge accumulated due to dark current, etc., is reduced, and the imaging device according to this method can further reduce noise.

[0059] Alternatively, for example, after the exposure operation, the control circuit may, starting from the row where the reset operation begins, sequentially cause the plurality of pixels to perform a readout operation that outputs a signal corresponding to the signal charge accumulated in the charge accumulation section, either row by row or multiple rows by multiple rows.

[0060] Therefore, the rows that begin during the reset and readout operations are common, thus preventing the control circuit from becoming too complex. Furthermore, the readout data is continuously read from up to down or from down to up in time, thus maintaining the continuity of the resulting image.

[0061] Alternatively, for example, the control circuit may sequentially cause the plurality of pixels to perform the reset action in row-by-row or multi-row-by-multiple-row units until a row different from the row that started the reset action is performed. After the exposure action, starting from the next row in sequence after the row that ended the reset action, the plurality of pixels may sequentially perform a readout action in row-by-row or multi-row-by-multiple-row units to output a signal corresponding to the signal charge accumulated in the charge accumulation unit.

[0062] Therefore, the time from reset to readout is approximately the same for each row. Consequently, the difference in charge accumulated in the charge storage area due to dark current and other factors after the reset operation between rows becomes smaller. As a result, the noise difference between multiple pixels is reduced.

[0063] Alternatively, for example, each of the plurality of pixels may include a feedback circuit that negatively feeds back the potential of the charge accumulation section during the reset action.

[0064] Therefore, the reset noise generated during the reset action is reduced. Consequently, the camera device involved in this method can further reduce noise.

[0065] Alternatively, for example, each of the plurality of pixels may include circuitry for suppressing reset noise generated during the reset operation.

[0066] Therefore, the reset noise generated during the reset action is reduced. Consequently, the camera device involved in this method can further reduce noise.

[0067] Alternatively, a voltage supply circuit may also be included. The photoelectric conversion unit includes a counter electrode electrically connected to the voltage supply circuit, a pixel electrode electrically connected to the charge accumulation unit, and a photoelectric conversion layer located between the counter electrode and the pixel electrode. The control circuit causes the voltage supply circuit to apply a voltage to the counter electrode, thereby forming an electric field in the photoelectric conversion layer, which in turn causes the plurality of pixels to perform the exposure operation.

[0068] Therefore, in a stacked imaging device where the reset action is effective on a row-by-row or multi-row basis, the delay from the trigger signal indicating the start of exposure to the start of exposure can be shortened while reducing noise. Furthermore, by applying a voltage to the counter electrode to perform the exposure operation, the complexity of the circuitry can be reduced.

[0069] Furthermore, one aspect of the control method disclosed herein relates to a control method for an imaging device comprising a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge. In this control method, until a trigger signal indicating the start of exposure is received, pixels belonging to at least one row of the plurality of pixels sequentially perform a reset operation to initialize the potential of the charge storage unit, either row-wise or in multiple rows-wise. After receiving the trigger signal, pixels belonging to at least one row of the plurality of pixels are not reset, but the plurality of pixels simultaneously perform an exposure operation to store the signal charge in the charge storage unit.

[0070] Therefore, upon receiving the trigger signal, the exposure operation is performed without resetting multiple pixels belonging to at least one row. Thus, compared to resetting all pixels after receiving the trigger signal, the time from receiving the trigger signal to the exposure operation is shortened. Furthermore, since the reset operation is performed on multiple pixels belonging to all rows until the trigger signal is received, the potential is initialized before the signal charge is accumulated, and noise in the signal charge is reduced, particularly when the reset operation is performed while suppressing reset noise. Therefore, the control method described in this invention can shorten the delay from the trigger signal indicating the start of exposure to the start of exposure while reducing noise.

[0071] Hereinafter, embodiments of the imaging device and the like related to this disclosure will be described with reference to the accompanying drawings. Furthermore, while the following embodiments and drawings are used to describe this disclosure, they are merely illustrative and not intended to limit this disclosure to these embodiments.

[0072] Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, constituent elements, the arrangement and connection methods of constituent elements, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit this disclosure.

[0073] Furthermore, elements that are necessary for the operation of a camera device or effective in improving performance, but are not required in this disclosure, have been omitted in this specification. Also, the accompanying drawings are merely conceptual diagrams, and scale, shape, etc., are not taken into consideration. Therefore, for example, the scale, etc., need not be consistent across drawings. Furthermore, in each drawing, substantially identical components are given the same reference numerals, and repetitive descriptions are omitted or simplified.

[0074] Furthermore, in this specification, terms such as "equal" to indicate the relationship between elements, terms such as "square" or "circle" to indicate the shape of elements, and numerical ranges are not merely expressions of a strict meaning, but are intended to also include substantially equivalent ranges, such as differences of a few percent.

[0075] Furthermore, in this specification, the terms "above" and "below" do not refer to the absolute spatial orientation of upward (vertical above) and downward (vertical below), but are used as terms defined by relative positional relationships based on the stacking order in a layered structure. Moreover, the terms "above" and "below" are applied not only to situations where two constituent elements are arranged with a gap between them and other constituent elements exist between them, but also to situations where two constituent elements are arranged closely together and are adjacent to each other.

[0076] (Implementation Method 1)

[0077] First, refer to Figures 1A to 3 This section explains the structure of the camera device 100 involved in this embodiment.

[0078] [Structure of the camera device]

[0079] Figure 1A This diagram schematically illustrates an exemplary circuit configuration of the imaging device 100 according to this embodiment. The imaging device 100, as an example, is a stacked imaging element having a photoelectric conversion layer stacked on a semiconductor substrate. The imaging device 100 includes a plurality of pixels 110 and peripheral circuitry. The peripheral circuitry includes a control circuit that controls the operation of the plurality of pixels 110. The control circuitry receives a trigger signal from an external source, causing the plurality of pixels 110 to perform an exposure operation.

[0080] Multiple pixels 110 are arranged in a two-dimensional manner to form a photosensitive area, also known as a pixel area. Alternatively, the multiple pixels 110 can be arranged in a one-dimensional manner. In this case, the imaging device 100 is a line sensor.

[0081] In the illustrated example, multiple pixels 110 are arranged in both row and column directions. In this specification, row and column directions refer to the directions in which rows and columns extend, respectively. That is, the vertical direction is the column direction, and the horizontal direction is the row direction.

[0082] Each pixel 110 is connected to a power line 120. A predetermined power supply voltage is supplied to each pixel 110 via the power line 120. Additionally, as shown, the imaging device 100 has an accumulation control line 130 that applies the same fixed voltage to all photoelectric conversion layers that perform photoelectric conversion of incident light. However, in cases where other controls such as suppressing fluctuations are required, the voltage can be applied in several segments.

[0083] The peripheral circuitry includes a voltage supply circuit 140, a vertical scanning circuit 141, a column signal processing circuit 142, a horizontal signal readout circuit 143, and a constant current source 144. The vertical scanning circuit 141 is also referred to as a "row scanning circuit," and the horizontal signal readout circuit 143 is also referred to as a "column scanning circuit." The column signal processing circuit 142 and the constant current source 144 can be configured for each column of the pixels 110 arranged in a two-dimensional pattern.

[0084] The following is an example illustrating the construction of a peripheral circuit.

[0085] The voltage supply circuit 140 is connected to the accumulation control line 130. When the camera device 100 is in operation, a predetermined bias voltage is applied to the opposing electrode 1b of the pixel 110 (details to be described later) via the accumulation control line 130 through the voltage supply circuit 140. The operation of the voltage supply circuit 140 is controlled by the control circuit.

[0086] The vertical scan circuit 141 is connected to the selection control signal line CON7 and the amplification control signal line CON3. The amplification control signal line CON3 is also referred to as the "band control signal line," and the selection control signal line CON7 is also referred to as the "address signal line." The vertical scan circuit 141 is part of a control circuit that controls the operation of multiple pixels 110. The vertical scan circuit 141 selects multiple pixels 110 arranged in each row, row by row, by applying a predetermined voltage to the selection control signal line CON7. This performs the reading of the signal voltage of the selected pixel 110 and the reset of the pixel electrode, as described later.

[0087] Each column of pixel 110 is electrically connected to a column signal processing circuit 142 via a corresponding column signal readout signal line 170. The signal readout signal line 170 is also referred to as a "vertical signal line." The column signal processing circuit 142 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion). A horizontal signal readout circuit 143 is electrically connected to multiple column signal processing circuits 142 corresponding to the columns of pixel 110A. The horizontal signal readout circuit 143 sequentially reads signals from the multiple column signal processing circuits 142 onto a horizontal common signal line 180.

[0088] The following describes an example of the circuit configuration for pixel 110.

[0089] Figure 1B This diagram schematically illustrates the exemplary circuit configuration of the pixel 110 of the imaging device 100 according to this embodiment. The pixel 110 includes a photoelectric conversion unit 1, an amplifier 2, a band control unit 3, a charge storage unit FD, and an output selection unit 5. The photoelectric conversion unit 1 detects light and converts it into signal charge. The charge storage unit FD stores the signal charge generated by the photoelectric conversion unit 1. The amplifier 2, the band control unit 3, the charge storage unit FD, and the output selection unit 5 form a readout circuit 50.

[0090] The photoelectric conversion unit 1 converts light into signal charge. The readout circuit 50 reads the signal charge generated by the photoelectric conversion unit 1. The photoelectric conversion unit 1 includes, for example, a pixel electrode 1a, a counter electrode 1b, and a photoelectric conversion layer 1c spaced between the pixel electrode 1a and the counter electrode 1b. The pixel electrode 1a is electrically connected to the charge storage unit FD. The counter electrode 1b is electrically connected to... Figure 1A The accumulation control line 130 shown is connected and electrically connected to the voltage supply circuit 140 via the accumulation control line 130. For example, by applying a reference voltage Vp to the counter electrode 1b and connecting one end of the node forming the charge accumulation section FD to the pixel electrode 1a, the signal charge generated by the photoelectric conversion layer 1c of the photoelectric conversion section 1 can be accumulated in the charge accumulation section FD.

[0091] The charge storage unit FD is connected to the photoelectric conversion unit 1 via a wiring layer. The charge storage unit FD stores the signal charge generated by the photoelectric conversion unit 1. The charge storage unit FD is also connected to the input of the amplifier 2. The amplifier 2 amplifies the signal corresponding to the signal charge stored in the charge storage unit FD and outputs it to the band control unit 3 and the output selection unit 5.

[0092] Amplifier 2 and band control unit 3 form a feedback circuit 30 via charge accumulation unit FD. Band control unit 3 includes band control circuit 13. At least three different voltages are supplied to band control circuit 13 from voltage control circuit. Band control circuit 13 has band control function by being supplied with such voltages. Voltage control circuit is, for example, part of vertical scan circuit 141. Band control circuit 13 applies band limit to the output signal of amplifier 2 and outputs it to charge accumulation unit FD. In feedback circuit 30, the signal read from charge accumulation unit FD is amplified by amplifier 2, applied band limit by band control circuit 13, and fed back to charge accumulation unit FD.

[0093] Feedback circuit 30 causes the signal from photoelectric conversion unit 1 to be negatively fed back to charge storage unit FD via amplification transistor 42. In other words, feedback circuit 30 is a circuit that negatively feeds back the potential of charge storage unit FD during the reset operation described later.

[0094] Amplifier 2 includes an amplifying transistor 42 and a switching circuit 20 including a first switching element 11 and a second switching element 12. The transistor in the readout circuit 50 is, for example, an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The electrical connections of the readout circuit 50 are described below. Alternatively, the amplifier 2 of pixel 110 may not have the switching circuit 20, and the switching circuit 20 may be included in peripheral circuitry.

[0095] The gate of the amplifying transistor 42 is connected to the charge storage section FD. The band control section 3 includes a band control transistor 46. The output selection section 5 includes a selection transistor 44. One of the source and drain of the amplifying transistor 42 is connected to one of the source and drain of the band control transistor 46 and one of the source and drain of the selection transistor 44. The other of the source and drain of the band control transistor 46 is connected to the charge storage section FD. An RC filter circuit is formed using the band control transistor 46 and the parasitic capacitance in the charge storage section FD.

[0096] The gate of the band control transistor 46 is connected to the amplification control signal line CON3. The state of the band control transistor 46 is determined by the voltage of the amplification control signal line CON3. For example, when the voltage of the amplification control signal line CON3 is high, the band control transistor 46 is turned on. As a result, a feedback path is formed through the charge storage section FD, the amplification transistor 42, and the band control transistor 46.

[0097] If the voltage on the amplification control signal line CON3 decreases, the resistive component of the bandgap control transistor 46 increases. Therefore, the bandgap of the bandgap control transistor 46 narrows, and the frequency range of the feedback signal narrows. If the voltage on the amplification control signal line CON3 becomes an even lower low level, the bandgap control transistor 46 turns off. As a result, no feedback path is formed.

[0098] The other of the source and drain of the selection transistor 44 is connected to the signal readout signal line 170. The gate of the selection transistor 44 is controlled by the selection control signal line CON7. The state of the selection transistor 44 is determined by the voltage of the selection control signal line CON7. For example, when the voltage of the selection control signal line CON7 is high, the selection transistor 44 is turned on. As a result, the amplification transistor 42 is electrically connected to the signal readout signal line 170. When the voltage of the selection control signal line CON7 is low, the selection transistor 44 is turned off. As a result, the amplification transistor 42 is electrically disconnected from the signal readout signal line 170.

[0099] One of the source and drain terminals of the amplifying transistor 42 is connected to the switching circuit 20. Specifically, the other of the source and drain terminals of the amplifying transistor 42 is connected to the first voltage source VA1 via the first switching element 11. Additionally, the other of the source and drain terminals of the amplifying transistor 42 is also connected to the second voltage source VA2 via the second switching element 12. The switching circuit 20 is controlled by control signals V1 and V2, thereby switching the voltage applied to the other of the source and drain terminals of the amplifying transistor 42 to either voltage Va1 or voltage Va2. The voltage Va1 of the first voltage source VA1 is, for example, ground voltage GND. The voltage Va2 of the second voltage source VA2 is, for example, the power supply voltage VDD. The switching circuit 20 can be configured for each pixel, or, to reduce the number of elements per pixel, can be shared by multiple pixels.

[0100] The output selection unit 5 is connected to the signal readout signal line 170. The signal readout signal line 170 is shared by at least two pixels. The signal amplified by the amplifier 2 is output to the signal readout signal line 170 via the output selection unit 5.

[0101] The signal readout signal line 170 is connected to the constant current source 144. When the selection transistor 44 is turned on, a source follower circuit is formed by the selection transistor 44, the amplification transistor 42, and the constant current source 144. The signal corresponding to the signal charge accumulated in the charge storage section FD is output to the signal readout signal line 170 and read out to the outside. Furthermore, the constant current source 144 can be set for each pixel, or it can be shared by multiple pixels to reduce the number of components per pixel.

[0102] Furthermore, the photoelectric conversion unit 1 is not limited to this configuration, and may also be other components with photoelectric conversion functions such as photodiodes. Figure 1C This is a schematic diagram illustrating an exemplary circuit configuration of the pixel 115 of the camera device according to this embodiment. Figure 1C The difference between pixel 115 and pixel 110 is that pixel 115 has a photoelectric conversion unit 1d instead of photoelectric conversion unit 1. The configuration of pixel 115, except for the photoelectric conversion unit 1d, is the same as that of pixel 110. Figure 1C As shown, pixel 115 includes a photoelectric conversion section 1d composed of a photodiode. For example, by applying a reference voltage Vp to one end of the photoelectric conversion section 1d and connecting one end of the node forming the charge accumulation section FD to the other end of the photoelectric conversion section 1d, the signal charge generated by the photoelectric conversion section 1d can be accumulated in the charge accumulation section FD.

[0103] The pixel structure of the camera device 100 described in this embodiment will now be explained.

[0104] Figure 2 This is a cross-sectional view schematically illustrating the device structure of the pixels 110 of the camera device 100 according to this embodiment. Figure 2 In the illustrated configuration, pixel 110 includes a semiconductor substrate 62 supporting the photoelectric conversion unit 1. The semiconductor substrate 62 is, for example, a silicon substrate. Figure 2 As shown, the photoelectric conversion unit 1 is disposed above the semiconductor substrate 62. In this example, interlayer insulating layers 63A, 63B, and 63C are stacked on the semiconductor substrate 62, and a stack of pixel electrode 1a, photoelectric conversion layer 1c, and counter electrode 1b is disposed on interlayer insulating layer 63C. The pixel electrode 1a is divided per pixel, and the pixel electrode 1a is spatially separated between two adjacent pixels 110, thereby electrically separating two adjacent pixel electrodes 1a. In addition, the photoelectric conversion layer 1c and the counter electrode 1b may also be formed across multiple pixels 110. The signal charge generated by the photoelectric conversion unit 1 is accumulated in a charge accumulation node 41 located between the gate of the amplifying transistor 42 and the photoelectric conversion unit 1. The charge accumulation node 41 is an example of the charge accumulation unit FD described above.

[0105] Photoelectric conversion unit 1, for example Figure 2 As shown, it includes a pixel electrode 1a, a counter electrode 1b opposite to the pixel electrode 1a, and a photoelectric conversion layer 1c located between the pixel electrode 1a and the counter electrode 1b.

[0106] The pixel electrode 1a is an electrode used to read out the signal charge generated by the photoelectric conversion unit 1. At least one pixel electrode 1a is present for each pixel 110. The pixel electrode 1a is electrically connected to the gate electrode 42e of the amplifying transistor 42 and the impurity region 62d.

[0107] The pixel electrode 1a is formed using a conductive material. The conductive material is, for example, a metal such as aluminum or copper, a metal nitride, or polycrystalline silicon that has been made conductive by doping with impurities.

[0108] The counter electrode 1b is, for example, a transparent electrode formed of a transparent conductive material. The counter electrode 1b is disposed on the light-incident side of the photoelectric conversion unit 1. Therefore, light transmitted through the counter electrode 1b is incident on the photoelectric conversion layer 1c.

[0109] Furthermore, "transparent" in this specification means that at least a portion of the wavelength range of light to be detected is transmitted, and it does not necessarily mean that light is transmitted across the entire wavelength range of visible light.

[0110] The counter electrode 1b is formed, for example, by using a transparent conductive oxide (TCO) such as ITO (indium tin oxide).

[0111] The photoelectric conversion layer 1c receives incident light and generates electron-hole pairs. The material used for the photoelectric conversion layer 1c can be, for example, a semiconducting inorganic material or a semiconducting organic material. For example, the photoelectric conversion layer 1c is an organic photoelectric conversion film.

[0112] An amplification transistor 42, a selection transistor 44, and a band control transistor 46 are formed on a semiconductor substrate 62.

[0113] The amplifying transistor 42 includes: impurity regions 62a and 62b formed on a semiconductor substrate 62, a gate insulating layer 42g located on the semiconductor substrate 62, and a gate electrode 42e located on the gate insulating layer 42g. The impurity regions 62a and 62b function as either the drain or source of the amplifying transistor 42. The impurity regions 62a and 62b, and the impurity regions 62c, 62d, and 62e described later, are, for example, n-type impurity regions.

[0114] The selection transistor 44 includes: impurity regions 62a and 62c formed on the semiconductor substrate 62, a gate insulating layer 44g located on the semiconductor substrate 62, and a gate electrode 44e located on the gate insulating layer 44g. The impurity regions 62a and 62c function as the drain or source of the selection transistor 44. In this example, the amplifying transistor 42 and the selection transistor 44 share the impurity region 62a, thereby electrically connecting the source (or drain) of the amplifying transistor 42 to the drain (or source) of the selection transistor 44.

[0115] The band-domain control transistor 46 includes: impurity regions 62d and 62e formed in the semiconductor substrate 62, a gate insulating layer 46g located on the semiconductor substrate 62, and a gate electrode 46e located on the gate insulating layer 46g. The impurity regions 62d and 62e function as the drain or source of the band-domain control transistor 46.

[0116] In the semiconductor substrate 62, component separation regions 62s are provided between adjacent pixels 110 and between the amplification transistor 42 and the band control transistor 46. The component separation regions 62s electrically separate adjacent pixels 110. Furthermore, by providing component separation regions 62s between adjacent pixels 110, leakage of signal charge accumulated in the charge accumulation node 41 is suppressed.

[0117] Within the interlayer insulating layer 63A, a contact plug 65A is formed that connects to the impurity region 62d of the bandgap control transistor 46, a contact plug 65B is formed that connects to the gate electrode 42e of the amplification transistor 42, and a wiring 66A connecting the contact plugs 65A and 65B. Thus, the impurity region 62d (e.g., the drain) of the bandgap control transistor 46 is electrically connected to the gate electrode 42e of the amplification transistor 42. Figure 2 In the illustrated configuration, a plug 67A and a wiring 68A are also formed within the interlayer insulating layer 63A. Furthermore, by forming the plug 67B and wiring 68B within the interlayer insulating layer 63B, and the plug 67C within the interlayer insulating layer 63C, the wiring 66A is electrically connected to the pixel electrode 1a. The contact plugs 65A, 65B, 66A, 67A, 68A, 67B, 68B, and 67C are typically made of metal.

[0118] exist Figure 2 In the illustrated configuration, a color filter 72 is disposed on the counter electrode 1b. Additionally, a microlens 74 is disposed on the color filter 72. Although not shown, a protective layer for protecting the photoelectric conversion unit 1 may also be disposed between the color filter 72 and the microlens 74. The material of the protective layer is, for example, SiON or AlO.

[0119] The imaging device 100 described above can be manufactured using general semiconductor manufacturing processes. In particular, when a silicon substrate is used as the semiconductor substrate 62, it can be manufactured using various silicon semiconductor processes.

[0120] Here, the photoelectric conversion operation is explained. Light input from the outside is focused by the microlens 74 of each pixel 110, and only the desired wavelength is transmitted through the color filter 72 and incident on the photoelectric conversion unit 1. In the photoelectric conversion unit 1, the light is converted into electric charge. Under the condition that an electric field is generated by applying a voltage between the counter electrode 1b and the pixel electrode 1a, the converted charge is collected by the pixel electrode 1a and accumulated in the charge accumulation node 41, in other words, the charge accumulation unit FD.

[0121] The following describes other examples of pixels involved in this embodiment. Figure 3 This is a schematic diagram illustrating an exemplary circuit configuration of the pixel 110A of the imaging device according to this embodiment. Figure 3 The difference between pixel 110A shown and pixel 110 described above is that it has a band control unit 3A instead of a band control unit 3. The following explanation focuses on the differences from pixel 110, omitting or simplifying the explanation of common points.

[0122] In pixel 110A, a readout circuit 50A is formed by amplifier 2, band control unit 3A, charge storage unit FD and output selection unit 5.

[0123] Feedback circuit 30A causes the signal from photoelectric conversion unit 1 to be negatively fed back to charge storage unit FD via amplification transistor 42. In other words, feedback circuit 30A is a circuit that negatively feeds back the potential of charge storage unit FD during the reset operation described later.

[0124] The band control unit 3A includes a band control circuit 13A and a reset circuit 14A.

[0125] The band control circuit 13A is a circuit that suppresses reset noise generated during the reset operation described later. The band control circuit 13A includes a band control transistor 46A, a first capacitor element 9, and a second capacitor element 10. In this specification, "capacitor element" means a structure with a dielectric material such as an insulating film spaced between electrodes. Furthermore, "electrode" is not limited to electrodes formed of metal and is interpreted broadly to include polysilicon layers, etc. The electrode may also be part of a semiconductor substrate. The first capacitor element 9 and the second capacitor element 10 may, for example, be MIM (Metal Insulator Metal) capacitors or MIS (Metal Insulator Semiconductor) capacitors. The reset circuit 14A includes a reset transistor 48.

[0126] The following describes the electrical connections of the 50A readout circuit.

[0127] The gate of amplifying transistor 42 is connected to the charge storage section FD. One of the source and drain of amplifying transistor 42 is connected to one of the source and drain of band control transistor 46A. One of the source and drain of amplifying transistor 42 is also connected to one of the source and drain of selection transistor 44. The other of the source and drain of band control transistor 46A is connected to one end of the first capacitor element 9. A reference voltage VR1 is applied to the other end of the first capacitor element 9. Thus, an RC filter circuit is formed by the band control transistor 46A and the first capacitor element 9.

[0128] The other end of the source and drain of the band-domain control transistor 46A is also connected to one end of the second capacitor element 10. Furthermore, the other end of the second capacitor element 10 is connected to the charge storage section FD. In this specification, the node formed between the band-domain control transistor 46A, the first capacitor element 9, and the second capacitor element 10 is referred to as "RD".

[0129] The gate of the band control transistor 46A is connected to the amplification control signal line CON3. The state of the band control transistor 46A is determined by the voltage of the amplification control signal line CON3. For example, when the voltage of the amplification control signal line CON3 is high, the band control transistor 46A is turned on. At this time, the feedback circuit 30A is formed by the charge storage section FD, the amplification transistor 42, the band control transistor 46A, and the second capacitor element 10.

[0130] If the voltage of the amplification control signal line CON3 decreases, the resistive component of the band control transistor 46A increases. Therefore, the band of the band control transistor 46A narrows, and the frequency domain of the feedback signal narrows.

[0131] When a feedback path is formed, the signal output by the band-domain control transistor 46A is attenuated in the attenuation circuit formed by the second capacitor element 10 and the parasitic capacitance of the charge accumulation section FD, and then fed back to the charge accumulation section FD. If the capacitance of the second capacitor element 10 is set to Cc, and the parasitic capacitance of the charge accumulation section FD is set to Cfd, then the attenuation rate is represented by Cc / (Cc+Cfd).

[0132] If the voltage of the amplification control signal line CON3 further decreases to a low level, the band control transistor 46A is turned off, and no feedback path is formed.

[0133] The charge storage section FD is also connected to one of the source and drain of the reset transistor 48. The other of the source and drain of the reset transistor 48 is connected to RD. Thus, the voltage of one of the source and drain of the amplifying transistor 42 (the output voltage of the amplifier 2) is applied to the reset transistor 48. The gate of the reset transistor 48 is connected to the reset control signal line CON2, and the state of the reset transistor 48 is determined by the voltage of the reset control signal line CON2. The reset transistor 48 negatively feeds the signal from the photoelectric conversion unit 1 to the charge storage section FD via the amplifying transistor 42. With this configuration, the voltage change of the charge storage section FD before and after the reset transistor 48 is turned off can be reduced, and noise can be suppressed more quickly.

[0134] [Pixel Actions]

[0135] Next, the operation of the plurality of pixels 110 in the imaging device 100 will be explained. The control circuit of the imaging device 100 causes the plurality of pixels 110 to perform an exposure operation of accumulating signal charge in the charge accumulation section FD, a reset operation of initializing the potential of the charge accumulation section FD, and a readout operation of outputting a signal corresponding to the signal charge accumulated in the charge accumulation section FD. The basic operation is the same when using pixel 110A or pixel 115 instead of pixel 110.

[0136] First, the exposure operation of accumulating signal charge to the charge accumulation unit FD will be explained. The control circuit causes multiple pixels 110 to undergo exposure operation through the following actions.

[0137] Figure 4 This diagram illustrates an example of the photoelectric conversion characteristics of an organic photoelectric conversion film, using the characteristics of photoelectric conversion layer 1c as an example. (See diagram for example.) Figure 4 As shown, the photoelectric conversion characteristics of the organic photoelectric conversion film are as follows: the voltage V of the counter electrode 1b ITO The higher the voltage, the higher the sensitivity of the organic photoelectric conversion film. For example, if the pixel electrode 1a provided in each pixel 110 is set to the reset voltage VRST, and a HIGH voltage is supplied to the counter electrode 1b common to all pixels, a high voltage V is generated between the counter electrode 1b and the pixel electrode 1a. H Therefore, the organic photoelectric conversion film has high sensitivity and performs photoelectric conversion. The signal charge generated in the photoelectric conversion layer 1c is collected by the pixel electrode 1a. If a LOW voltage is supplied to the counter electrode 1b, the voltage generated between the counter electrode 1b and the pixel electrode 1a changes to a low voltage V. LTherefore, the sensitivity of the organic photoelectric conversion film decreases, and photoelectric conversion stops. That is, with the pixel electrode 1a in each pixel 110 set to the reset voltage VRST, exposure begins by supplying a HIGH voltage to the common opposing electrode 1b of all pixels, and stops by supplying a LOW voltage to the opposing electrode 1b. Furthermore, at this time... Figure 1B The voltage of the amplification control signal line CON3 shown is low, and the band control transistor 46 is turned off. Additionally, in the case of pixel 110A, Figure 2 The voltages of the reset control signal line CON2 and the amplification control signal line CON3 shown are at a low level, and the band control transistor 46A and the reset transistor 48 are turned off. Therefore, during the exposure operation, signal charge is accumulated in the charge accumulation section FD. In this way, in the imaging device 100 using the photoelectric conversion layer 1c, the photoelectric conversion characteristics, i.e., sensitivity, can be controlled by controlling the voltage applied to the counter electrode 1b. In the imaging device 100 according to this embodiment, by utilizing such control of the photoelectric conversion characteristics (i.e., sensitivity characteristics), a global shutter operation that simultaneously exposes at least two or more pixels 110 can be achieved.

[0138] In the case of an imaging device using a photoelectric conversion layer, as described above, the CDS method cannot be used because the device is configured to not completely transfer charge. Therefore, reset noise (e.g., kTC noise) must be suppressed for each pixel before exposure. A reset operation is also required for the pixels to be exposed before the global shutter exposure begins.

[0139] Next, refer to Figure 1B and Figure 2 This describes the reset operation that initializes the potential of the charge accumulation unit FD. The control circuit performs a reset operation on multiple pixels 110 by means of the following actions. The reset operation is performed row by row on multiple pixels 110. During the reset operation, the potential of the charge accumulation unit FD is initialized, for example, while suppressing reset noise.

[0140] During the reset operation, the voltage of the selection control signal line CON7 is set to a low level. Therefore, the selection transistor 44 is turned off, and the amplification transistor 42 is electrically disconnected from the signal readout signal line 170. Here, the voltage of the amplification control signal line CON3 is set to a high level, turning on the band control transistor 46. Additionally, at this time, the first switching element 11 of the switching circuit 20 is turned on, and a voltage Va1 (e.g., ground voltage GND) is applied to the other of the source and drain of the amplification transistor 42. As a result, the voltage of the charge accumulation section FD (in other words, the voltage of the pixel electrode 1a) becomes equal to the reset voltage VRST. That is, the potential of the charge accumulation section FD is initialized. Furthermore, for example, the voltage of the amplification control signal line CON3 is then set to a voltage between high and low levels, for example, an intermediate voltage. This suppresses reset noise. In this case, if the voltage is set so that the operating band of the band control transistor 46 is narrower than the operating band of the amplification transistor 42, the reset noise suppression effect is further improved. Finally, the voltage of the amplification control signal line CON3 is set to low, turning off the band control transistor 46. This suppresses reset noise while initializing the potential of the charge accumulation section FD.

[0141] In the case of pixel 110A, not only is the voltage of the amplification control signal line CON3 set to a high level, but the voltage of the reset control signal line CON2 is also set to a high level, turning on the reset transistor 48, thereby making the voltage of the charge accumulation section FD equal to the reset voltage VRST. Next, the reset transistor 48 is turned off. Furthermore, for example, by setting the voltage of the amplification control signal line CON3 to a voltage between high and low levels, such as an intermediate voltage, the aforementioned reset noise suppression effect can also be obtained. Finally, the voltages of the reset control signal line CON2 and the amplification control signal line CON3 are set to a low level, turning off the band control transistor 46A.

[0142] Next, refer to Figure 1B and Figure 2 This describes the readout operation, which outputs a signal corresponding to the signal charge accumulated in the charge storage unit FD. The control circuit performs the readout operation on multiple pixels 110 through the following actions. The readout operation is performed row by row on multiple pixels 110.

[0143] During the readout operation, the voltage of the selection control signal line CON7 is set to a high level to turn on the selection transistor 44. Additionally, the switching circuit 20 is controlled so that the voltage between the source and drain of the amplifying transistor 42 becomes Va2 (e.g., the power supply voltage VDD). That is, the second switching element 12 becomes on, and the voltage Va2 is applied to the other side of the source and drain of the amplifying transistor 42. In this state, the amplifying transistor 42 and the constant current source 144 form a source follower circuit. Then, the potential of the charge storage section FD becomes a voltage corresponding to the amount of signal charge stored in the charge storage section FD. Therefore, the voltage of the charge storage section FD corresponding to the amount of signal charge is amplified by the amplifier 2, for example, by approximately 1x, and output to the signal readout signal line 170. At this time, the amplification of the source follower circuit is, for example, approximately 1x. The voltage of the charge storage section FD is amplified by the amplifier 2, for example, by approximately 1x, and output to the signal readout signal line 170.

[0144] This readout operation is performed when the signal charge from the exposure operation is accumulated in the charge storage unit FD, and when the pixel electrode has been reset and the reset voltage VRST has been set. The readout operation when the signal charge from the exposure operation is accumulated in the charge storage unit FD is called "signal readout operation", and the readout operation when the pixel electrode has been reset and the reset voltage VRST has been set is called "reset signal readout operation".

[0145] [The action of the camera device]

[0146] The operation of the camera device 100 will be explained next. Specifically, the operation of the camera device 100's control circuit causing multiple pixels to move will be explained.

[0147] The following describes the operation and issues when using the camera device involved in the comparative example, and the operation and effects when using the camera device 100 involved in this embodiment.

[0148] First, use Figure 5A , Figure 5B and Figure 5C The imaging device involved in the comparative example will be described. The imaging device involved in the comparative example has the same configuration as the imaging device 100 described above, but the operation of each circuit is different from that of the imaging device 100 involved in this embodiment. Hereinafter, an example will be described in which the plurality of pixels 110 of the imaging device involved in the comparative example constitute a pixel array of "row 0 (row 0) to row n (row n) × column 0 (column 0) to column m (column m)".

[0149] Figure 5A This is a timing diagram used to illustrate an example of the operation in the camera device involved in the comparative example. Figure 5BThis is a flowchart illustrating an example of the actions in the camera device involved in the comparative example.

[0150] Figure 5A This indicates the timing of the trigger signal, the timing of the fall (or rise) of the vertical synchronization signal VD, the time-varying magnitude of the voltage applied to the counter electrode 1b of the photoelectric conversion unit 1 (i.e., the bias voltage applied to the photoelectric conversion layer 1c), the overall driving of the multiple pixels 110, and the reset operation, signal readout operation, and exposure operation in each row of the pixel array of the multiple pixels 110. Figure 5A The topmost part indicates the timing of the "trigger signal" used to indicate the start of exposure. Figure 5A The topmost curve, labeled "VD," represents the timing of the rise (or fall) of the vertical synchronization signal VD. Figure 5A The second graph from the top, "Counter Electrode Voltage," represents the time-varying voltage applied from the voltage supply circuit 140 to the counter electrode 1b via the accumulation control line 130. Furthermore, the "Pixel Drive" and "Actions" sections below represent the overall driving of the plurality of pixels 110 and the timing of the actions of each row of the pixel array of the plurality of pixels 110, respectively. The lines for each action represent actions performed sequentially from row 0 to row n. Solid lines represent reset actions, and dashed lines represent signal readout actions.

[0151] like Figure 5A and Figure 5B As shown, firstly, since a reset operation is required for all pixels 110 before the exposure operation, the control circuit of the imaging device involved in the comparative example performs a reset operation on all pixels 110 of all rows from row 0 to row n every at least one row during the reset operation period A (S111). During the reset operation, for example as described above, the reset operation is performed while suppressing reset noise (e.g., kTC noise).

[0152] Next, in the comparative example, the control circuit of the imaging device, with the reset voltage VRST set to suppress reset noise of all pixels 110, applies a HIGH voltage to the counter electrode 1b during exposure operation B, causing the plurality of pixels 110 to undergo exposure operation (S112). The exposure operation is performed simultaneously on at least two or more of the plurality of pixels 110.

[0153] Next, in the comparative example, the control circuit of the imaging device performs signal readout operation on all pixels 110 belonging to rows 0 to n during the signal readout operation period C after the exposure operation. After the signal readout operation, a reset operation is performed on all pixels 110 that have read out signals. After the reset operation, a reset signal readout operation is performed on all pixels 110 (S113). During the reset signal readout operation, the reset signal is read out on at least one row at a time while the noise of all pixels 110 that have read out signals is suppressed and the reset voltage VRST is set.

[0154] Subsequently, the control circuit of the camera device involved in the comparative example receives a trigger signal from the outside, determines the exposure start time, and causes multiple pixels 110 to perform reset operations, exposure operations, and signal readout operations (S114 to S117). In steps S115 to S117, the same operations as in steps S111 to S113 are performed. At this time, from receiving the trigger signal in step S114 to before the exposure operation in step 116, a reset operation needs to be performed for all pixels 110 to be exposed for at least one row at a time, resulting in a long waiting time T1 from receiving the trigger signal from the outside until the exposure operation begins. For example, if the reset operation for each row of FHD (1000 vertical rows) takes 3 microseconds, a waiting time T1 of more than 3 milliseconds is generated, making it impossible to photograph the object to be photographed at the desired shooting time, or to perform continuous shooting for photographing the object to be photographed at the desired shooting time. Therefore, problems such as the inability to perform continuous inspection of multiple objects at high speed arise.

[0155] Figure 5C This is a flowchart illustrating other examples of the actions within the camera device involved in the comparative example. Figure 5C In the example shown, the control circuit of the camera device involved in the comparative example first receives a trigger signal from an external source, causing multiple pixels 110 to perform reset, exposure, and signal readout operations (S121 to S124). In steps S121 to S124, the same operations as those described in steps S114 to S117 are performed. The camera device involved in the comparative example can be as follows... Figure 5B As shown, after the first camera shot for initialization, the start time of the exposure action is determined in accordance with the received trigger signal from the outside, or as follows: Figure 5C As shown, the start time of the exposure operation is determined from the initial receipt of a trigger signal from the outside. Furthermore, the imaging device involved in the comparative example can repeatedly control the timing of the exposure operation based on the trigger signal from the outside, as well as perform internal continuous scanning.

[0156] Next, use Figures 6A to 7The operation of the imaging device 100 according to this embodiment, which is used to solve the above-mentioned problems, will be explained below. An example will be described where the plurality of pixels 110 of the imaging device 100 constitute a pixel array of "row 0 to n rows × column 0 to m columns". Furthermore, the imaging device 100 may also have pixels 110A or 115 instead of pixels 110.

[0157] Figure 6A This is a timing diagram used to illustrate an example of the operation of the camera device 100 according to this embodiment. Figure 6B This is a flowchart illustrating an example of the operation of the camera device 100 according to this embodiment. Figure 6C This is a timing diagram used to illustrate other examples of the operation of the camera device 100 according to this embodiment.

[0158] Figure 6A and Figure 6C and Figure 5A Similarly, it represents the timing of the trigger signal, the timing of the fall (or rise) of the vertical synchronization signal VD, the time-varying magnitude of the voltage applied to the counter electrode 1b of the photoelectric conversion unit 1 (i.e., the bias voltage applied to the photoelectric conversion layer 1c), the overall driving of the multiple pixels 110, and the reset operation, signal readout operation, and exposure operation in each row of the pixel array of the multiple pixels 110.

[0159] like Figure 6A and Figure 6B As shown, firstly, in order to reset the voltage of all pixels 110 before exposure, the control circuit of the imaging device 100 resets multiple pixels 110 in all rows from row 0 to row n during the reset operation period A (S11). During the reset operation, for example as described above, the reset operation is performed at least once per row while suppressing reset noise (kTC noise). Furthermore, in step S11, the control circuit of the imaging device 100 may also reset pixels 110 belonging to at least one row sequentially, row by row. For example, when capturing images in a cropping mode using a portion of pixels 110, the reset operation may also be performed on the row of pixels 110 used.

[0160] Next, with the reset voltage VRST set to suppress reset noise in all pixels 110, the control circuit of the imaging device 100 applies a HIGH voltage to the counter electrode 1b during exposure operation B, causing the pixels 110 to undergo exposure operation (S12). The exposure operation is performed simultaneously on at least two or more of the plurality of pixels 110. The exposure operation can also be performed simultaneously on all pixels 110.

[0161] During the signal readout operation C after the exposure operation, the control circuit of the imaging device 100 causes all pixels 110 belonging to rows 0 to n to perform a signal readout operation for the accumulated pixel signals at least one row at a time. After the readout, a reset operation is performed again for all pixels 110 whose signals have been read out, and a reset signal readout operation is performed for all pixels 110 after the reset operation (S13). During the reset signal readout operation, the reset signal is read out at least one row at a time while the noise of all pixels 110 whose signals have been read out is suppressed and the reset voltage VRST is set.

[0162] In the imaging device described in the comparative example above, after receiving an external trigger signal, a reset operation is required for all pixels 110 to be exposed, at least one row at a time, before the exposure operation. This results in a long waiting time from receiving the external trigger signal until the exposure operation begins. Alternatively, a method is considered whereby a reset operation is performed in advance for all pixels 110 to be exposed, at least one row at a time, regardless of whether an external trigger signal is received. However, if the time from the reset operation to receiving the external trigger signal and then to the start of the exposure operation is long, the accumulation of signal charge and signal readout may be inaccurate due to the influence of minute leakage such as dark current.

[0163] However, in the imaging device 100 according to this embodiment, by providing a period (pre-reset operation period A2) for repeatedly performing a reset operation for each at least one row after reading the reset signal in step S13, the waiting time from receiving a trigger signal from the outside until the start of the exposure operation can be shortened. Specifically, during the pre-reset operation period A2, the control circuit of the imaging device 100 causes the plurality of pixels 110 to perform a reset operation for each at least one row (S14). The reset operation in step S14 is repeated in units of 0 to n rows until the control circuit receives a trigger signal from the outside (S15). In other words, the control circuit of the imaging device 100 sequentially causes the plurality of pixels 110 to repeatedly perform a reset operation in rows until the trigger signal is received.

[0164] Furthermore, if the control circuit of the imaging device 100 receives a trigger signal from the outside in step S15, it performs an interruption process, stopping the reset operation when the processing of the x rows of pixels 110 that is currently being performed ends. Thus, the reset operation in step S14 is repeated a times in units of rows 0 to n, and then proceeds from row 0 to row x. Here, a is an integer greater than or equal to 0. Row x is a row between rows 0 and n. In this way, from steps S13 to S15, the control circuit of the imaging device 100 performs a reset operation to initialize the potential of the charge accumulation section FD sequentially, row by row, until it receives a trigger signal indicating the start of exposure. Additionally, the control circuit of the imaging device 100 performs a reset operation multiple times on pixels 110 belonging to at least one row among the multiple pixels 110 until it receives a trigger signal. Therefore, during the period until the control circuit receives a trigger signal from the outside, signal charge accumulation caused by dark current or the like, which can cause noise, is suppressed.

[0165] Once the reset operation is completed, the control circuit of the imaging device 100 causes at least two or more pixels 110 to undergo an exposure operation (S16). Then, the control circuit of the imaging device 100 causes the multiple pixels 110 to perform a signal readout operation, a reset operation, and a reset signal readout operation (S17). That is, after receiving a trigger signal, the control circuit of the imaging device 100 does not cause at least one row of pixels 110 to undergo a reset operation, but causes the multiple pixels 110 to simultaneously perform an exposure operation to accumulate signal charge in the charge accumulation section FD. By obtaining the difference between the output in the signal readout operation and the output in the reset readout operation, a signal corresponding to the amount of charge generated by photoelectric conversion during the exposure operation can be obtained. In steps S16 and S17, the same operations as in steps S12 and S13 described above are performed.

[0166] In step S17, the control circuit of the camera device 100 can also be as follows: Figure 6A As shown, after the exposure operation, starting from row 0 where the reset operation begins in steps S11 and S13, multiple pixels 110 are sequentially read out row by row. By adopting this configuration, the rows at the beginning of the reset operation and the readout operation are common, which can suppress the complexity of the control circuit. In addition, the readout data is read out continuously in time from top to bottom or from bottom to top, thus maintaining the continuity of the image.

[0167] The signal readout operation can be performed sequentially on rows, targeting all pixels 110 belonging to each row; the starting row is not particularly limited. For example, in step S17, the control circuit of the camera device 100 can also perform the operation as follows: Figure 6CAs shown, after the exposure operation, starting from the next row in sequence after the x-row where the reset operation ended in step S14, the multiple pixels 110 are sequentially read out row by row. By employing this configuration, the time from the reset operation to the readout operation for each row is approximately the same. Therefore, the difference in the amount of charge accumulated in the charge accumulation section FD due to dark current and other factors between rows after the reset operation is reduced. Consequently, the noise difference between the multiple pixels 110 is reduced.

[0168] Then, the actions of steps S14 to S17 are repeated. In this way, in the imaging device 100 according to this embodiment, by setting the pre-reset operation period A2, the waiting time T2 from receiving the trigger signal from the outside until the start of the exposure operation can be shortened by more than one line of reset operation time compared to the aforementioned waiting time T1.

[0169] Here, it is explained that in steps S14 and S15, if a trigger signal from the outside is received, the reset operation is stopped when the processing of the currently being processed row ends, but this is not limited to this. This reset operation can be performed as long as it is not executed for pixels 110 belonging to at least one row after receiving a trigger signal from the outside. For example, considering the stability of the surrounding circuits, the reset operation can also be performed on several rows starting from the currently being processed row.

[0170] In addition, Figure 6A and Figure 6B In the example shown, in step S14 ( Figure 6A In the pre-reset operation period (A2), when the reset operation is repeatedly performed in units of rows 0 to n (i.e., 1 frame), the reset operation of the next frame is immediately executed from row 0 after the reset operation of one frame is completed. In other words, when the reset operation is repeatedly performed, there is no gap between the completion of the reset operation of one frame and the start of the reset operation of the next frame. Furthermore, in step S14, a period during which the reset operation is not performed can be set from the completion of the reset operation of one frame until the start of the reset operation of the next frame. The shorter the period during which the reset operation is not performed in step S14, the better noise caused by dark current, etc., can be suppressed; however, it should be set to obtain the image quality required for the intended use. For example, the period during which the reset operation is not performed in step S14 can also be set to within the length of one frame.

[0171] In addition, Figure 6BIn this process, during the execution of steps S11 to S13, that is, before all pixels 110 have completed the reset operation, if the control circuit of the imaging device 100 receives a trigger signal, the control circuit will not interrupt the reset operation or other operations. In this case, for example, the control circuit of the imaging device 100 may discard the received trigger signal or prevent the pixels 110 from immediately starting the exposure operation, and instead perform the exposure operation after step S13. Alternatively, the control circuit of the imaging device 100 may also have a circuit configuration that does not accept trigger signals during the period before all pixels 110 have completed the reset operation.

[0172] Figure 6D This is a flowchart illustrating other examples of actions within the camera device 100. Figure 6D In the example shown, the control circuit of the imaging device 100 first resets all pixels 110 belonging to rows 0 to n (S21). In step S21, the same action as in step S11 described above is performed. After the reset action in step S21, the control circuit of the imaging device 100 also resets multiple pixels 110 at least once per row (S22). The reset action in step S22 is repeated in units of rows 0 to n until the control circuit receives a trigger signal from the outside (S23). If a trigger signal is received, the control circuit of the imaging device 100, once the reset action is completed, causes multiple pixels 110 to simultaneously undergo an exposure action (S24). Then, the control circuit of the imaging device 100 causes multiple pixels 110 to perform a signal readout action, a reset action, and a reset signal readout action (S25). Then, steps S22 to S25 are repeated. In steps S22 to S25, the same action as in steps S14 to S17 described above is performed.

[0173] The camera device 100 can be like Figure 6B As shown, after the first camera shot for initialization, the pre-reset action period A2 is set, and the start time of the exposure action is determined accordingly based on the received trigger signal from the outside. Alternatively, it can be done as follows: Figure 6D As shown, the pre-reset operation period A2 is set from the beginning, and the start time of the exposure operation is determined in accordance with the trigger signal received from the outside. In addition, the camera device 100 can repeatedly control the timing of the exposure operation based on the trigger signal from the outside and perform internal continuous scanning.

[0174] Figure 7 This is a flowchart illustrating another example of the actions within the camera device 100. In this example, the control circuitry of the camera device 100 causes multiple pixels 110 to interact with... Figure 6BThe same actions as steps S11 and S12 are performed as steps S31 and S32. Next, the control circuit of the camera device 100 causes the multiple pixels 110 to perform signal readout and reset actions (step S33). That is, in step S33, no further action is performed. Figure 6B The reset signal readout action is shown in step S13. Next, the control circuit of the camera device 100 causes the multiple pixels 110 to perform interaction with... Figure 6B The same actions as steps S14 to S16 are performed as steps S34 to S36. Then, the control circuit of the imaging device 100 causes the multiple pixels 110 to perform signal readout and reset operations (step S37). In step S37, the same actions as in step S33 are performed. In this example, by obtaining the difference between the output in the signal readout operation and, for example, the output corresponding to the state where the reset voltage VRST has been set, a signal corresponding to the amount of charge accumulated in the charge accumulation unit FD can be obtained.

[0175] (Implementation Method 2)

[0176] Next, Embodiment 2 will be described. In Embodiment 2, an imaging device having a laminated structure with at least two substrates will be described.

[0177] Figure 8 This is a schematic diagram illustrating an example of the configuration of the camera device 101 according to this embodiment. Figure 8 As shown, the camera device 101 includes a first substrate 2000 and a second substrate 2100 stacked with the first substrate 2000.

[0178] The first substrate 2000 is located above the second substrate. The first substrate 2000 has a pixel array 111. The pixel array 111 has, for example, a structure in which the aforementioned pixels 110, pixels 110A, or pixels 115 are arranged in a matrix.

[0179] The second substrate 2100 includes: an analog-to-digital converter (AD converter) 2200 that receives signal output (specifically, analog signals) from each pixel included in the pixel array 111 and converts it into digital signals; a memory 2400 that stores the signals obtained by converting the analog-to-digital converter 2200 into digital signals; and an arithmetic processing circuit 2300 that performs arithmetic processing on the signals obtained by converting the analog-to-digital converter 2200 into digital signals.

[0180] The first substrate 2000 and the second substrate 2100 are electrically connected by the connecting part 2500.

[0181] In this stacked configuration, for example, pixels 110, 110A, or 115 for implementing the imaging device 100 described above are disposed on the first substrate 2000, and circuits for controlling the counter electrode 1b of the photoelectric conversion unit 1 and circuits for interrupt control logic are disposed on the second substrate 2100. By disposing the circuits for controlling the counter electrode 1b of the photoelectric conversion unit 1 and the circuits for interrupt control logic on the second substrate 2100, the circuits for control logic can be freely constructed regardless of the pixel area of ​​the pixels included in the pixel array 111. The placement of each circuit on either the first substrate 2000 or the second substrate 2100 is determined according to the purpose and is not particularly limited. Specifically, for example, pixels 110, 110A, or 115 are disposed on the first substrate 2000, and the vertical operation circuit 141, voltage supply circuit 140, column signal processing circuit 142, and horizontal signal readout circuit 143 are disposed on the second substrate 2100. Alternatively, the switching circuit 20 may be omitted from pixels 110, 110A, or 115, and the switching circuit 20 may be disposed on the second substrate 2100. Alternatively, the constant current source 144 may be omitted from the first substrate 1000, and the constant current source 144 may be disposed on the second substrate 2100.

[0182] exist Figure 8 In the example shown, the imaging device 101 has a stacked structure of two substrate layers, but it is not limited to this. It can also be a stacked structure of three or more substrate layers, or a structure in which multiple sub-substrates are stacked on a single substrate layer. The substrate connection portion 2500 can be as follows: Figure 8 The settings shown can be configured per column, per region, or per pixel.

[0183] (Implementation Method 3)

[0184] Next, Embodiment 3 will be described. In Embodiment 3, a camera system equipped with the above-described imaging device will be described. Figure 9 This is a block diagram illustrating an example of the configuration of the camera system 1000 according to Embodiment 3.

[0185] The camera system 1000 according to this embodiment includes an imaging device 102, an optical system 1001 such as a lens for focusing light, a camera signal processing unit 1002 for processing the data captured by the imaging device 102 and outputting it as an image or data, and a system controller 1003 for controlling the imaging device 102 and the camera signal processing unit 1002.

[0186] The optical system 1001 is a lens or the like used to focus light onto the imaging surface of the imaging device 102. Light passing through the optical system 1001 is incident on the photoelectric conversion unit 1 of the imaging device 102, where it undergoes photoelectric conversion to generate a signal charge. The imaging device 102 can, for example, be the imaging device 100 or 101 described in the above embodiments.

[0187] The camera signal processing unit 1002 functions as a signal processing circuit that processes the output signal from the imaging device 102. The camera signal processing unit 1002 performs processes such as gamma correction, color interpolation, spatial interpolation, automatic white balance, distance measurement calculation, and wavelength information separation. The camera signal processing unit 1002 can be implemented, for example, by a DSP (Digital Signal Processor).

[0188] The system controller 1003 controls the camera system 1000 as a whole. The system controller 1003 can be implemented, for example, by a microcomputer.

[0189] The camera system 1000 in this embodiment, by using the imaging device 100 or 101 as described in the above embodiments as the imaging device 102, can shorten the delay time from receiving a trigger signal from the outside until the entire light-receiving surface begins exposure. Therefore, a highly available camera system 1000 can be provided, with a short waiting time until the exposure begins, enabling imaging of the desired object when imaging is desired, or enabling high-speed inspection.

[0190] (Other implementation methods)

[0191] The above describes one or more imaging devices and camera systems based on various embodiments, but this disclosure is not limited to these embodiments.

[0192] For example, in the above embodiment, the reset action in step S14 starts immediately after the action in step S13 ends, but it can also start after a gap after the action in step S13 ends, within the range that the image quality required for the purpose of use can be obtained.

[0193] Furthermore, in the above embodiment, during the reset operation, by electrically connecting the charge storage unit FD to the switching circuit 20, the voltage of the charge storage unit FD becomes equal to the reset voltage VRST, but this is not a limitation. Alternatively, a reference voltage may be applied to the charge storage unit FD from a circuit different from the switching circuit 20 to perform the reset operation.

[0194] Furthermore, in the above embodiment, the photoelectric conversion unit 1 includes a pixel electrode 1a, a counter electrode 1b, and a photoelectric conversion layer 1c. However, a charge transport layer or a charge blocking layer may also be included between the photoelectric conversion layer 1c and the pixel electrode 1a or the counter electrode 1b. This further suppresses the occurrence of dark current, thereby further reducing noise.

[0195] Furthermore, in the above embodiments, the reset operation and signal readout operation are described as being performed row by row. However, multiple signal lines can also be provided for each column, and the reset operation and signal readout operation can be performed row by row. This enables high-speed operation. The configuration of providing multiple signal lines for each column is described in detail in the applicant's patent application, U.S. Patent Publication No. 10,225,500. The entire disclosure of that application is incorporated herein by reference.

[0196] Furthermore, in practical applications of the imaging device disclosed herein, it is also contemplated that the trigger signal may be received during a period other than the pre-reset operation period. For example, if the trigger signal is received before the pre-reset operation begins, the trigger signal may be ignored. Alternatively, the exposure operation may begin after the trigger signal is received and a reset operation is performed for all rows of pixels. Alternatively, if the trigger signal is received during the exposure period, the trigger signal may be ignored. Alternatively, the exposure operation may be performed again after the signal readout and reset operations have been completed. Alternatively, the exposure operation may be performed again after the reset operation has been performed. Alternatively, the exposure operation may be interrupted midway and then resumed after the reset operation. Performing the operations described above when the trigger signal is received during a period other than the pre-reset operation period, as long as the operations described in the technical solution of this disclosure are performed, is also included within the scope of the claims of this disclosure.

[0197] Furthermore, any modifications conceived by those skilled in the art to this embodiment, and any combination of constituent elements in different embodiments, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0198] Industrial applicability

[0199] The imaging device disclosed herein can be used in various camera systems and sensor systems, such as digital cameras, medical cameras, surveillance cameras, vehicle cameras, digital SLR cameras, and digital mirrorless single-lens cameras.

[0200] Explanation of reference numerals in the attached figures:

[0201] 1.1d photoelectric conversion unit

[0202] 1a Pixel Electrode

[0203] 1b Counter electrode

[0204] 1c photoelectric conversion layer

[0205] 2 Amplifiers

[0206] 3. 3A Band Domain Control Unit

[0207] 5 Output Selection Section

[0208] 9. First capacitor element

[0209] 10. Second capacitor element

[0210] 11 First Switching Element

[0211] 12. Second Switching Element

[0212] 13. 13A Bandwidth Control Circuit

[0213] 14A Reset Circuit

[0214] 30A Feedback Circuit

[0215] 41 Charge accumulation node

[0216] 42 Amplifying Transistors

[0217] 42g, 44g, 46g gate insulating layer

[0218] 42e, 44e, 46e gate electrodes

[0219] 44 Select Transistor

[0220] 46, 46A band-controlled transistors

[0221] 48 Reset transistor

[0222] 50A Readout Circuit

[0223] 62 Semiconductor substrate

[0224] Impurity regions 62a, 62b, 62c, 62d, 62e

[0225] 62s component separation region

[0226] Interlayer insulation layers 63A, 63B, 63C, and 63D

[0227] 65A and 65B contact plugs

[0228] 66A, 68A, 68B wiring

[0229] Plugs 67A, 67B, 67C, 67D, and 67E

[0230] 72 Color Filters

[0231] 74 microlenses

[0232] Camera devices 100, 101, and 102

[0233] 110, 110A, 115 pixels

[0234] 111 pixel array

[0235] 120 power cord

[0236] 130 Accumulation Control Line

[0237] 141 Vertical Scanning Circuit

[0238] 142-column signal processing circuit

[0239] 143 Horizontal Signal Readout Circuit

[0240] 144 Constant Current Source

[0241] 170 signal readout signal line

[0242] 180° Horizontal Common Signal Line

[0243] 1000 Camera System

[0244] 1001 Optical System

[0245] 1002 Camera Signal Processing Unit

[0246] 1003 System Controller

[0247] 2000 1st substrate

[0248] 2100 2nd base board

[0249] 2200 Analog-to-Digital Converter Circuit

[0250] 2300 arithmetic processing circuit

[0251] 2400 memory

[0252] 2500 Connecting Part

[0253] CON2 Reset control signal line

[0254] CON3 Amplification control signal line

[0255] CON7 Select control signal line

Claims

1. An imaging device comprising: a plurality of pixels arranged in a matrix, each including a photoelectric conversion section that converts light into signal charge, and a charge accumulation section that accumulates the signal charge; and a control circuit, the control circuit performs: until a trigger signal for instructing exposure start is accepted, causing pixels belonging to at least one row among the plurality of pixels to sequentially perform, in units of rows or in units of multiple rows, a pre-reset operation of initializing a potential of the charge accumulation section, after the trigger signal is accepted, not causing the pixels belonging to at least one row among the plurality of pixels to perform the pre-reset operation, but causing the plurality of pixels to simultaneously perform an exposure operation of accumulating the signal charge to the charge accumulation section, after the exposure operation, causing the plurality of pixels to perform a signal readout operation, a reset operation, and a reset signal readout operation, after the reset signal readout operation, the pre-reset operation is started, and the pre-reset operation is performed until the trigger signal for instructing exposure start is accepted.

2. The imaging device according to claim 1, the control circuit causes all of the plurality of pixels to sequentially perform, in units of rows or in units of multiple rows, the pre-reset operation until the trigger signal is accepted.

3. The imaging device according to claim 1 or 2, the control circuit causes the pixels belonging to at least one row among the plurality of pixels to perform the pre-reset operation multiple times until the trigger signal is accepted.

4. The imaging device according to claim 1 or 2, the control circuit causes the plurality of pixels to sequentially repeat, in units of rows or in units of multiple rows, the pre-reset operation until the trigger signal is accepted.

5. The imaging device according to claim 1 or 2, the control circuit causes the plurality of pixels to sequentially perform, in units of rows or in units of multiple rows, a readout operation of outputting a signal corresponding to the signal charge accumulated in the charge accumulation section, from a row at which the pre-reset operation is started, after the exposure operation.

6. The imaging device according to claim 1 or 2, the control circuit performs: sequentially causing the plurality of pixels to perform the pre-reset operation, in units of rows or in units of multiple rows, until a row different from a row at which the pre-reset operation is started, after the exposure operation, sequentially causing the plurality of pixels to perform, in units of rows or in units of multiple rows, a readout operation of outputting a signal corresponding to the signal charge accumulated in the charge accumulation section, from a row sequentially next to a row at which the pre-reset operation is ended.

7. The imaging device according to claim 1 or 2, each of the plurality of pixels includes a feedback circuit that negatively feeds back the potential of the charge accumulation section in the pre-reset operation.

8. The imaging device according to claim 1 or 2, each of the plurality of pixels includes a circuit that suppresses pre-reset noise generated in the pre-reset operation.

9. The imaging device according to claim 1 or 2, the pre-reset operation includes an operation of negatively feeding back the potential of the charge accumulation section. ​ ​ 10. The imaging device according to claim 1 or 2, the imaging device further includes a voltage supply circuit, The photoelectric conversion section includes: an opposing electrode electrically connected to the voltage supply circuit, a pixel electrode electrically connected to the charge accumulation section, and a photoelectric conversion layer between the opposing electrode and the pixel electrode, the control circuit causes the voltage supply circuit to apply a voltage to the opposing electrode, causes an electric field to be formed within the photoelectric conversion layer, and thereby causes the plurality of pixels to perform the exposure operation.

11. A control method of an imaging device that includes a plurality of pixels arranged in a matrix, each of the plurality of pixels including a photoelectric conversion section that converts light into signal charge and a charge accumulation section that accumulates the signal charge, in the control method, until a trigger signal for instructing exposure start is accepted, causing pixels belonging to at least one row among the plurality of pixels to sequentially perform a pre-reset operation that initializes a potential of the charge accumulation section in units of rows or in units of multiple rows, after the trigger signal is accepted, not causing the pixels belonging to at least one row among the plurality of pixels to perform the pre-reset operation, and causing the plurality of pixels to simultaneously perform an exposure operation that accumulates the signal charge to the charge accumulation section, after the exposure operation, causing the plurality of pixels to perform a signal readout operation, a reset operation, and a reset signal readout operation, the pre-reset operation is started after the reset signal readout operation, and is performed until the trigger signal for instructing exposure start is accepted.

12. The control method according to claim 11, the pre-reset operation includes an operation that negatively feeds back the potential of the charge accumulation section.

Images