Optical sensor package and method of fabricating an optical sensor package

Abstract

Embodiments of the present disclosure relate to an optical sensor package and a method of fabricating an optical sensor package. The molding bracket is formed of a single body portion made of a laser direct structuring (LDS) material and includes a blind hole having a bottom surface. The single body portion includes a bottom plate body portion defining a rear side and a bottom surface of the blind hole and an outer peripheral wall body portion defining a side wall surface of the blind hole. After LDS activation, electroplating is followed to produce: die attach pads and bond pads at the bottom surface; land grid array (LGA) pads at the rear side; and vias extending through the bottom plate body portion, the vias electrically connecting between the die attach pad and one LGA pad and between the bond pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad, and wire bonding is performed to the bond pads. A wafer-level manufacturing process is used to form the molding bracket.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of U.S. Provisional Patent Application No. 63 / 125,738, filed on December 15, 2020, which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to packages for integrated circuit chips, and more particularly to packages for integrated circuit chips that perform optical sensor functions (e.g., light emission and light detection). Background Art

[0004] Many common optical sensor applications require the use of an integrated circuit chip configured as a light emitter and an integrated circuit chip configured as a light detector. An example of such an optical sensor application is a time-of-flight (ToF) sensor, which utilizes a light emitter integrated circuit chip in the form of a vertical cavity surface emitting laser (VCSEL) or a light emitting diode (LED) and a light detector integrated circuit chip in the form of a photodiode. These optical integrated circuit chips must be packaged, and the packages must be easy to manufacture, rugged, and inexpensive. Summary of the Invention

[0005] In one embodiment, the package includes: a molded carrier formed from a single body portion of laser direct structuring (LDS) material, the molded carrier including a rear side and a front side, the front side having a blind hole extending into the single body portion of the molded carrier, the blind hole being separated by a sidewall surface and a bottom surface, wherein the single body portion includes: a bottom plate body portion having a lower surface defining the rear side and an upper surface defining the bottom surface of the blind hole, and an outer peripheral wall body portion, an outer surface of which defines the outer surface of the molded carrier and an inner surface of which defines at least a portion of the sidewall surface of the blind hole.

[0006] The package further includes: a first die attach pad located on the bottom surface of the blind hole; a first bonding pad located on the bottom surface of the blind hole; a plurality of land grid array (LGA) pads located on the rear side; and a plurality of through holes extending through the bottom plate body portion to electrically connect the die attach pad to one LGA pad and the bonding pad to another LGA pad; wherein the first die attach pad, the first bonding pad, the LGA pads, and the through holes are formed by plating on the LDS activation surface of the molded carrier.

[0007] In one embodiment, a method includes: molding a laser direct structuring (LDS) material to form a single body portion of a wafer-level molding carrier, the carrier including a rear side and a front side, the molding carrier having a plurality of blind holes extending from the front side into the single body portion, each blind hole defined by a sidewall surface and a bottom surface, wherein the single body portion includes: a bottom plate body portion having a lower surface defining the rear side and an upper surface defining the bottom surface of the blind holes; and a plurality of wall body portions having inner surfaces defining the sidewall surfaces of the blind holes.

[0008] The method further includes: laser drilling an opening through the bottom plate body portion at each blind hole; activating the sidewalls of the through holes; activating portions of the bottom surface and the rear side; electroplating the activated sidewalls to form through holes extending through the bottom plate body portion; electroplating the activated portions to form die attach pads at the bottom surface of each blind hole; bonding pads on the bottom surface of each blind hole; and land grid array (LGA) pads opposite each die attach pad and bonding pad. The through holes electrically connect each die attach pad to one LGA pad and each bonding pad to another LGA pad.

[0009] The method further includes cutting certain portions of the wall body portions to separate the wafer-level molding carrier into a plurality of components. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To better understand the embodiments, reference is now made, by way of example only, to the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B shows an orthogonal cross-sectional view of an optical sensor package;

[0012] Figure 2 shows Figures 1A to 1B a plan view of the front side of the optical sensor package substrate in

[0013] Figure 3 shows Figures 1A to 1B a plan view of the rear side of the optical sensor package substrate;

[0014] Figure 4 is Figures 1A to 1B a perspective view of the optical sensor package in

[0015] Figure 5A and Figure 5B shows an orthogonal cross-sectional view of the optical sensor package;

[0016] Figure 6 is Figures 5A - 5B a perspective view of the cover structure of the optical sensor package in

[0017] Figure 7A and 7BShows an orthogonal cross-sectional view of an optical sensor package;

[0018] Figure 8 is Figures 7A - 7B a perspective view of the lid structure of the optical sensor package in;

[0019] Figure 9A and 9B Shows an orthogonal cross-sectional view of an optical sensor package;

[0020] Figure 10 is Figures 9A to 9B a perspective view of the molding carrier of the optical sensor package;

[0021] Figure 11 Shows Figures 9A to 9B a top view of the optical sensor package in;

[0022] Figure 12 Shows Figures 9A to 9B a bottom view of the optical sensor package in;

[0023] Figure 13A and 13B Shows an orthogonal cross-sectional view of an optical sensor package;

[0024] Figure 14A and 14B Shows an orthogonal cross-sectional view of an optical sensor package;

[0025] Figure 15A and 15B Shows an orthogonal cross-sectional view of an optical sensor package;

[0026] Figure 16A and 16B Shows an orthogonal cross-sectional view of an optical sensor package; and

[0027] Figures 17A to 17I - 2 Shows the steps of various methods of fabricating an optical sensor package. DETAILED DESCRIPTION

[0028] Referring to Figure 1A and Figure 1B which shows an orthogonal cross-sectional view of the optical sensor package 10. The substrate layer 12 has a front side 14 and a back side 16. For example, the substrate layer 12 can be made of an organic material having a laminated structure typically including multiple layers. An example of such a substrate 12 is commonly referred to as a printed circuit board (PCB). Figure 2 Shows a plan view of the front side 14 of the substrate layer 12, Figure 3A plan view of the rear side 16 of the substrate layer 12 is shown. A plurality of die attach pads 20 are mounted to the front side 14 of the substrate layer 12. A plurality of bond pads 22 are also mounted on the front side 14 of the substrate layer 12. The front side 14 of the substrate layer 12 may further include a plurality of metal traces (see reference numeral 15), forming a redistribution layer (RDL), which is electrically connected to the die attach pads 20 and / or the bond pads 22. A plurality of land grid array (LGA) pads 26 are mounted to the rear side 16 of the substrate layer 12. A plurality of metal vias 28 extend through the substrate layer 12 to electrically interconnect each die attach pad 20 (or the metal traces of the RDL connected thereto, if used) to a corresponding one of the LGA pads 26, and to electrically interconnect each bond pad 22 (or the metal traces of the RDL connected thereto, if used) to a corresponding one of the LGA pads 26.

[0029] Integrated circuit chips 30 are mounted to the die attach pads 20 on the front side 14 of the substrate layer 12. Each integrated circuit chip 30 includes an optical integrated circuit 32 and bond pads 34 located on the top (or front) surface. For example, the integrated circuit chip 30 may include a chip 30a having a light emitter for the optical integrated circuit 32 in the form of a vertical cavity surface emitting laser (VCSEL) or a light emitting diode (LED), and a chip 30b having a photodetector for the optical integrated circuit 32 in the form of a photodiode. The bottom (or rear) surface of the integrated circuit chip 30 is mounted to the die attach pad 20 using a conductive adhesive (not explicitly shown). Bond wires 38 electrically connect each bond pad 34 of the integrated circuit chip 30 to a corresponding one of the bond pads 22 for the substrate layer 12. It should be noted that when positioning the vias for the bond pads 22, it is very important that the via positions are offset from the wire bonding regions of the bond wires 38. Using the RDL metal traces 15 can provide a way to effectively offset the via positions away from the wire bonding regions of the bond pads 22.

[0030] A cover structure 40 is mounted on the front side 14 of the substrate layer 12. The cover structure 40 may have Figures 1A to 1B , Figures 5A - Figure 5B and Figures 7A - Figure 7B many different configurations as shown. In the configuration shown in Figures 1A to 1B , the cover structure 40 includes a cover frame 42, which is formed by an outer peripheral wall 44 and inner walls 46 joining two opposite sides of the outer peripheral wall; having a perspective view as shown in Figure 4 . The cover frame 42 is generally made of an opaque material. The bottom edge of the cover frame is connected to the front side 14 of the carrier 12 by an adhesive layer (not explicitly shown). In the configuration shown in Figures 5A - Figure 5B , the cover structure 40 includes a cover frame 42 and a transparent cover 50 (e.g., including a filter and / or optical elements), and the transparent cover 50 is mounted to the upper edge of the cover frame by an adhesive layer (not explicitly shown); having as shown inFigure 6 The perspective view shown. In Figures 7A - Figure 7B the configuration shown, the cover structure 40 includes a housing 60, the housing 60 includes an outer peripheral wall 62, an inner wall 64 joining two opposite sides of the outer peripheral wall, and a cover member (or front wall) 66; having as Figure 8 the perspective view shown. The housing 60 is generally made of an opaque material. The bottom edge of the housing 60 is connected to the front side 14 of the bracket 12 by an adhesive layer (not explicitly shown). The cover member 66 includes openings 68 aligned with the positions of the optical integrated circuits 32 of each integrated circuit chip 30. The transparent optical element 70 (e.g., including a filter and / or an optical element) is mounted on the bottom surface 72 of the cover member 66 at each opening 68 position by an adhesive layer (not explicitly shown).

[0031] Refer to Figure 9A and Figure 9B , in which an orthogonal cross-sectional view of the optical sensor package 100 is shown. The molded bracket 112 is made of a single body material and includes a front side 114 and a rear side 116. A plurality of blind holes 118 extend from the front side 114 into the single body of the molded bracket 112. Each blind hole 118 is defined by a side wall surface 120 and a bottom surface 122. The depth of each opening 118 is less than the thickness of the molded bracket 112. The material for the molded bracket 112 is a laser direct structuring (LDS) material.

[0032] As is known to those skilled in the art, LDS is a technique of molding (e.g., injection molding) a resin containing an additive to form a single body. A laser beam can be applied to the surface of the single body so as to transfer a desired pattern thereon by activating the additive. Then a conductive pattern (matching the desired activated additive pattern) is plated onto the laser-treated surface using a metallization process (e.g., electroless plating involving metals such as copper, nickel, and / or gold). The conductive pattern can include, for example, pad structures (for forming die attach pads, pads, and / or land grid array (LGA) pads) and line structures (for forming metal traces of a redistribution layer (RDL)). The LDS technique can also be used to form openings and pass through the single body, and when the single body is plated (or filled) with metal, an interconnect structure such as a via is formed.

[0033] The single body of the molded bracket 112 includes a bottom plate body portion 130, whose lower surface defines the rear side 116 and whose upper surface defines the bottom surface 122 of each blind hole 118. The single body of the molded bracket 112 also includes an outer peripheral wall body portion 132, whose outer surface defines the outer surface of the molded bracket 112 and whose inner surface defines a part of the side wall surface 120 of each blind hole 118. The single body of the molded bracket 112 also includes an inner wall body portion 134 connecting two opposite sides of the outer peripheral wall body portion 132, whose sides define the other parts of the side wall surface 120 of each blind hole 118.Figure 10 Shows a perspective view of a single body portion of the molded carrier 112.

[0034] Figure 11 Shows a top view of the optical sensor package 100 (i.e., looking down on the front side 114), and Figure 12 shows a bottom view of the optical sensor package 100 (i.e., looking up at the rear side 116).

[0035] At least one die attach pad 140 is mounted to the molded carrier 112 at the bottom surface 122 of each blind via 118. At least one bond pad 142 is also mounted on the molded carrier 112 at the bottom surface 122 of each blind via 118. The bottom surface 122 may also include a plurality of metal traces (see reference numeral 145) forming a redistribution layer (RDL) that is electrically connected to the die attach pad 140 and / or the bond pad 142. A plurality of land grid array (LGA) pads 26 are mounted on the rear side 16 of the molded carrier 112. A plurality of metal vias 148 extend through the bottom plate body portion 130 of the molded carrier 112 to electrically interconnect each die attach pad 140 (or the metal traces of the RDL connected thereto, if used) to a corresponding one of the LGA pads 146, and to electrically interconnect each pad 142 (or the metal traces of the RDL connected thereto, if used) to a corresponding one of the LGA pads 146.

[0036] The metal vias 148 are formed in the molded carrier 112 using LDS process technology. A hole that completely extends through the bottom plate body portion 130 of the molded carrier 112 is opened at the location where the via 148 is needed using a laser. This is achieved using well-known laser drilling techniques. LDS activation of the additive of the LDS material is then performed using laser exposure on the sidewalls of the hole. After the LDS activation of the sidewalls, the activated sidewalls are electroplated with a conductive material such as copper, nickel, and / or gold. Conventional electroplating techniques (e.g., including electroless plating processes) can be used for this step.

[0037] The die attach pad 140, the bond pad 142, and the RDL metal traces (if used) are formed on the bottom surface 122 of each blind via 118 in the molded carrier 112 using LDS process technology. Using laser exposure, LDS activation of the additive of the LDS material is performed at the locations on the bottom surface 122 where the die attach pad 140, the bond pad 142, and the RDL metal traces are needed, according to a pattern corresponding to the desired shapes of the die attach pad 140, the bond pad 142, and the RDL metal traces. After the LDS activation of the bottom surface 122, the activated portion of the bottom surface 122 is plated with a conductive material such as copper, nickel, and / or gold. Conventional electroplating techniques can be used for this step (e.g., including electroless plating processes).

[0038] The LGA pads 146 and the RDL metal traces (if used) are formed on the rear side 116 of the molding bracket 112 using LDS processing technology. At the positions where the LGA pads 146 and the RDL metal traces are required, laser exposure is used to perform LDS activation on the LDS material additive at the rear side 116 according to a pattern corresponding to the desired shapes of the LGA pads 146 and the RDL metal traces. After the LDS activation of the rear side 116, the activated portion of the rear side 116 is plated with a conductive material such as copper, nickel, and / or gold. Conventional electroplating techniques can be used for this step (e.g., including electroless plating processes).

[0039] The integrated circuit chips 150 are mounted to the die attach pads 140 at the bottom surfaces 122 of each blind via 118. Each integrated circuit chip 150 includes an optical integrated circuit 152 and bonding pads 154 located on the top (or front) surface. For example, the integrated circuit chip 150 can include a chip 150a having a light emitter in the form of a vertical cavity surface emitting laser (VCSEL) or a light emitting diode (LED) for the optical integrated circuit 152 and a chip 150b having a photodetector in the form of a photodiode for the optical integrated circuit 152. The bottom (or rear) surface of the integrated circuit chip 150 is mounted to the die attach pad 140 using a conductive adhesive (not explicitly shown). Bonding wires 158 electrically connect each bonding pad 154 of the integrated circuit chip 150 to a corresponding one of the bonding pads 142 at the bottom surface 122 of each blind via 118. It should be noted that when positioning the vias of the pads 142, it is important that the via positions are offset from the bonding areas of the bonding wires 158. Using the RDL metal traces 145 can provide a method for effectively offsetting the via positions away from the bonding areas of the pads 142.

[0040] A protection structure 160 can be used to protect the integrated circuit chips 150. As Figures 13A - Figure 13B 、14A - Figure 14B and 15A - Figure 15B shown, the protection structure 160 can have many different configurations. In Figures 13A - Figure 13B the configuration shown, the protection structure 160 includes a transparent material 162 that fills each blind via 118 in the molding bracket 112. In Figures 14A - Figure 14B the configuration shown, the protection structure 160 further includes a cover layer 164 that extends over the coplanar front side 114 of the molding bracket 112 and the front surface 166 of the transparent material filling 162. The cover layer 164 is preferably made of an opaque resin material that is transfer molded onto an assembly or structure including the molding bracket 112 and the transparent material 162 filling, or is molded separately and attached to the assembly using an adhesive. The cover layer 164 includes openings 168 that are aligned with the positions of the optical integrated circuits 152 of each integrated circuit chip 150. InFigures 15A - Figure 15B In the configuration shown, the protection structure 160 includes a transparent plate 170 attached to the front side 114 of the molding carrier 112. For example, the transparent plate 170 can be made of a glass material.

[0041] In one embodiment, as Figures 9A - Figure 9B , Figures 13A - Figure 13B , Figures 14A - Figure 14B and Figures 15A - Figure 15B any implementation shown, the molding carrier 112 having LDS - manufactured die attach pads 140, bond pads 142, LGA pads 146, and RDL metal traces may include a solder mask layer 180 as shown in Figures 16A - Figure 16B . The layer 180 can be provided on both the bottom surface 122 of each blind via 118 and the rear side 116 of the molding carrier 112 (as shown in Figures 16A - Figure 16B ). Alternatively, the layer 180 can be provided only on the rear side 116 of the molding carrier 112. The layer 180 includes openings 182 located at the positions of the die attach pads 140, bond pads 142, and LGA pads 146 (and will typically cover the RDL metal traces, if present).

[0042] Now refer to Figures 17A to 17I - 2 for a description of a wafer - level method of manufacturing an optical sensor package. Figure 17A shows the result of a molding process where a laser - direct structuring (LDS) material is molded to form a wafer - level carrier 112' including a plurality of blind vias 118. Note the wall body portions 132' between some of the openings 118, and the width W of the openings 118 is sufficient to allow cutting, thereby forming two peripheral wall body portions 132. For example, the molding process can utilize well - known injection molding techniques where the LDS material is injected into a cavity defined by a closed two - part mold, and the first and second molds of the two - part mold form the faces 114, 116, and the openings 118. Figure 17B shows the results of performing laser drilling, LDS surface activation, and plating operations that define the die attach pads 140, bond pads 142 (not explicitly shown), LGS pads 146, through - holes 148, and RDL metal traces (if required). Figure 17C shows the performance results of a process for depositing and patterning the solder mask layer 180. Note that Figure 17C shows that the solder mask layer 180 is present on both the bottom surface of each opening 118 and the rear side of the carrier 112'. This is just one example implementation, and in an alternative implementation, the solder mask layer 180 is provided only on the rear side of the carrier 112'. Any suitable deposition or printing process can be used to provide the patterned solder mask layer 180. Figure 17DShows the performance results of the process of connecting the integrated circuit chip 150 to the die attachment pad 140. The chip 150 can be mounted in the opening 118 using any suitable pick and place operation. Figure 17E Shows the execution results of the process of electrically connecting the bonding pads of the chip 150 to the bonding pads 142 (not explicitly shown) using bonding wires 158. The electrical connection can be performed using any suitable wire bonding operation.

[0043] As described above, there are various options for providing the protection structure 160 to protect the integrated circuit chip 150. Regarding Figures 13A - Figure 13B the configuration shown, Figure 17F - 1 Shows the performance results of the process for depositing the transparent material 162, which fills each blind hole 118 in the wafer-level molding carrier 112'. Figure 17F - 2 Shows the results of the process of separating the components by cutting (reference 190) the wall 132' to produce individual optical sensor packages.

[0044] Regarding Figures 14A - Figure 14B the configuration shown in Figure 17G - 1 Shows the results of the process for depositing the transparent material 162, which fills each blind hole 118 in the wafer-level molding carrier 112'. Figure 17G - 2 Shows the execution results of the process for providing the cover layer 164 (with an opening 168), which extends over the coplanar front side of the wafer-level molding carrier 112' and the front surface filled with the transparent material 162. The cover layer 164 is preferably made of an opaque resin material, which is transfer molded onto the component or structure including the wafer-level molding carrier 112' and the transparent material 162 filled, or is molded separately and attached to the component using an adhesive. Figure 17G - 3 Shows the execution results of the process of separating the components by cutting (reference 190) the wall 132' to produce individual optical sensor packages.

[0045] Regarding Figures 15A - Figure 15B the configuration shown in Figure 17H - 1 Shows the execution results of the process of connecting the transparent wafer 192 to the front side of the wafer-level molding carrier 112'. Figure 17H - 2 Shows the execution results of the process of separating the components by cutting (reference numeral 190) the wall 132' and the wafer 192 to produce individual optical sensor packages, where each package includes a transparent plate 170.

[0046] In Figures 15A - Figure 15B an alternative embodiment of the configuration shown, Figure 17I - 1 Shows the execution results of the process of separating the components by cutting (reference 190) the wall 132' to produce multiple components, each component including a molding machine carrier 112. Figure 17I - 2Shows the execution result of the process of connecting the transparent plate 170 to the front side of the molding bracket 112 for each individual component.

[0047] Although the present invention has been described in detail in the drawings and the foregoing description, such description and description are to be regarded as illustrative or exemplary, and not restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in light of the drawings, the present invention, and the appended claims.

Claims

1. An encapsulation, comprising: A molding bracket formed by a single body portion made of laser direct structuring (LDS) material. The molding bracket includes a rear side and a front side, and has a blind hole extending from the front side into the single body portion of the molding bracket. The blind hole is defined by a side wall surface and a bottom surface. Wherein the single body portion includes: a bottom plate body portion and a peripheral wall body portion. The bottom plate body portion has a lower surface defining the rear side and an upper surface defining the bottom surface of the blind hole. The outer surface of the peripheral wall body portion defines the outer surface of the molding bracket, and the inner surface of the peripheral wall body portion defines at least a part of the side wall surface of the blind hole; A first die attachment pad located on the bottom surface of the blind hole; A first bonding pad located on the bottom surface of the blind hole; A plurality of land grid array (LGA) pads located on the rear side; and A plurality of through holes extending through the bottom plate body portion to electrically connect the die attachment pad to one LGA pad and the bonding pad to another LGA pad; Wherein the first die attachment pad, the first bonding pad, the LGA pads, and the through holes are formed by plating at the LDS activation surface of the molding bracket.

2. The encapsulation according to claim 1, further comprising: An integrated circuit chip mounted to the first die attachment pad and electrically connected to the first bonding pad by a first bonding wire.

3. The encapsulation according to claim 2, further comprising a protection structure, the protection structure including a transparent material filling the blind hole and covering the integrated circuit chip.

4. The encapsulation according to claim 3, wherein the protection structure further includes a cover layer extending over the front side of the molding bracket and the front surface of the transparent material.

5. The encapsulation according to claim 4, wherein the cover layer is made of an opaque material.

6. The encapsulation according to claim 4, wherein the cover layer is made of a resin material.

7. The encapsulation according to claim 4, wherein the cover layer is a transfer molding structure.

8. The encapsulation according to claim 4, wherein the cover layer adheres to the front side of the molding bracket and the front surface of the transparent material filler.

9. The encapsulation according to claim 4, wherein the integrated circuit chip includes an optical integrated circuit, and wherein the cover layer includes an opening aligned with the position of the optical integrated circuit of the integrated circuit chip.

10. The encapsulation according to claim 2, further comprising a protection structure, the protection structure including a transparent plate extending over the blind hole and covering the integrated circuit chip.

11. The encapsulation according to claim 1, further comprising a solder mask layer on the bottom surface of the blind hole, the solder mask layer including openings exposing at least a part of the first die attachment pad and the first bonding pad.

12. The package according to claim 1 further includes a solder mask layer on the rear side of the molding bracket, the solder mask layer including openings that expose at least a portion of the LGA pads.

13. The package according to claim 1, wherein the single body portion further includes an inner wall body portion that joins two opposite sides of the outer peripheral wall body portion, the inner wall body portion having another portion of the side wall surface that defines the blind hole.

14. The package according to claim 13 further includes: a second die attach pad at the bottom surface and a second bonding pad at the bottom surface, wherein the second die attach pad and the second bonding pad are located on opposite sides of the inner wall body portion from the first die attach pad and the first bonding pad.

15. The package according to claim 14 further includes: a first integrated circuit chip mounted to the first die attach pad and electrically connected to the first bonding pad by a first bonding wire; and a second integrated circuit chip mounted to the second die attach pad and electrically connected to the second bonding pad by a second bonding wire.

16. A method of manufacturing an optical sensor package, including: molding a laser direct structuring (LDS) material to form a single body portion of a wafer-level molding bracket, the molding bracket including a rear side and a front side, the molding bracket having a plurality of blind holes extending from the front side into the single body portion, each blind hole defined by a side wall surface and a bottom surface, wherein the single body portion includes: a bottom plate body portion having a lower surface that defines the rear side and an upper surface that defines the bottom surface of the blind hole, and a plurality of wall portions having inner surfaces that define the side wall surfaces of the blind holes; laser drilling through holes in each blind hole that extend through the bottom plate body portion; activating the side walls of the through holes; activating portions of the bottom surface and the rear side; electroplating the activated side walls to form through holes that extend through the bottom plate body portion; electroplating the activated portions to form die attach pads at the bottom surface of each blind hole, bonding pads at the bottom surface of each blind hole, and plane grid array (LGA) pads opposite each die attach pad and bonding pad, wherein the through holes electrically connect each die attach pad to one LGA pad and each bonding pad to another LGA pad; and cutting through certain portions of the wall portions to separate the wafer-level molding bracket into a plurality of components.

17. The method according to claim 16 further includes: attaching integrated circuit chips to each die attach pad and connecting bonding wires between each integrated circuit chip and one of the bonding pads.

18. The method according to claim 17 further includes: filling each blind hole with a transparent material that covers the integrated circuit chips.

19. The method according to claim 18, further comprising molding a cover layer that extends over the front side of the molding carrier at the wafer level and over the front surface of the transparent material filling each blind via.

20. The method according to claim 19, wherein the cover layer is made of an opaque material.

21. The method according to claim 19, wherein the cover layer is made of a resin material.

22. The method according to claim 19, wherein each integrated circuit chip includes an optical integrated circuit, and the method further comprises: forming the cover layer to include an opening aligned with the location of the optical integrated circuit of the integrated circuit chip.

23. The method according to claim 18, further comprises: mounting a cover layer that extends over the front side of the wafer-level molding carrier and over the front surface of the transparent material filling each blind via.

24. The method according to claim 23, wherein the cover layer is made of an opaque material.

25. The method according to claim 23, wherein the cover layer is made of a resin material.

26. The method according to claim 23, wherein each integrated circuit chip includes an optical integrated circuit, and the method further comprises: forming the cover layer to include an opening aligned with the location of the optical integrated circuit of the integrated circuit chip.

27. The method according to claim 17, further comprises: attaching a transparent wafer to the wafer-level molding carrier, the transparent wafer extending over the plurality of blind vias and covering the integrated circuit chip.

28. The method according to claim 17, further comprises: after the dicing, attaching a transparent plate to each component, the transparent plate extending over the blind vias and covering the integrated circuit chip.

29. The method according to claim 16, further comprises: depositing a solder mask layer on the bottom surface of each blind via, the solder mask layer including an opening that exposes at least a portion of the die attach pad and the bonding pad.

30. The method according to claim 16, further comprises: depositing a solder mask layer on the rear side of the wafer-level molding carrier, the solder mask layer including an opening that exposes at least a portion of the LGA pad.

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