A method for improving memory access performance based on three-dimensional DRAM memory controller

Abstract

The present invention discloses a method for improving memory access performance based on a three-dimensional DRAM memory controller, and proposes an interface cache mechanism and a row hit processing mechanism for a new large-bit-width three-dimensional DRAM. If a user memory access request hits data cached in the interface cache, the memory access can be directly responded to by the interface cache. If the user memory access request misses the interface cache but a row hit occurs, the memory controller can respond to the memory access by executing a small number of DRAM storage array operations. If the user memory access request simultaneously results in an interface cache miss and a row miss, the memory controller can respond to the memory access by executing conventional DRAM storage array operations. The present invention can effectively reduce the number of operations performed by the memory controller on the DRAM storage array and the frequency of data entering and exiting the DRAM storage array, thereby reducing the memory access latency of the arithmetic unit for the required data, improving memory access performance, and reducing memory access power consumption.

Description

Technical Field

[0001] The present invention relates to the field of computer system design, and in particular to a method for improving memory access performance based on a three-dimensional DRAM memory controller. Background Art

[0002] The rapid development of big data and artificial intelligence technologies requires computer systems to process massive amounts of data in ever-faster timeframes. However, the technological advancement of computer storage systems lags far behind that of computer processors, resulting in the main performance bottleneck of current computer systems occurring in the memory access stage. The latest solution to alleviate this "memory wall" bottleneck in computer systems is to employ a new type of three-dimensional DRAM (3D DRAM) as a memory system, providing computer processors with greater data transfer bandwidth and lower power consumption. Furthermore, 3D DRAM typically provides computing units with a data interface width of thousands of bits, hundreds of times wider than traditional DRAM. Furthermore, considering that computer systems typically process single data bits of 32 or 64 bits, failing to efficiently process the large bit-width data on the 3D DRAM data interface will easily lead to wasted performance and power consumption.

[0003] The user's memory access request will be translated by the memory controller into a series of operations on the DRAM storage array. The data will be temporarily stored in the row buffer before being transferred from the DRAM storage array to the data interface. If the row address of the subsequent memory access request is the same as that of the previous memory access request, both memory accesses hit the same row of the DRAM storage array, resulting in a "row hit". At this time, the data can be accessed directly from the row buffer. If the memory controller fails to recognize the row hit behavior, it will first close the opened row in the DRAM storage array through a precharge operation and precharge the bit line. It will then reopen the same row through a row activation operation and read the data out to the row buffer before performing the memory access operation again. This will greatly reduce the memory access performance.

[0004] When the memory controller receives a user's memory access request, if the amount of data accessed in a single transaction is smaller than the 3D DRAM data interface bit width, the advantage of the 3D DRAM's high bandwidth cannot be fully utilized. Especially in the case of sequential address accesses, the memory controller processes the same data across multiple DRAM array operations, resulting in unnecessary increases in memory access latency and power consumption. If the memory controller fails to recognize consecutive row hit requests, it will also perform redundant DRAM array operations, which also reduces memory access performance. Summary of the Invention

[0005] In response to the shortcomings of the existing technology and the need for improvement, the present invention provides a method for improving memory access performance based on a three-dimensional DRAM memory controller, which aims to solve the problem that when the amount of data accessed by the computing unit in a single memory access is smaller than the bit width of the three-dimensional DRAM data interface, continuous address access or memory access with similar addresses causes the memory controller to perform repeated and redundant DRAM storage array operations, resulting in decreased memory access performance and increased power consumption; and to solve the problem that when the two consecutive memory access addresses are both located at the same row position of the DRAM storage array, the memory controller performs redundant DRAM storage array operations, resulting in decreased memory access performance and increased power consumption.

[0006] To achieve the above technical objectives, the technical solution of the present invention is: the first aspect of an embodiment of the present invention provides a method for improving memory access performance based on a three-dimensional DRAM memory controller, specifically: the memory controller receives a memory access request in an initial state, determines whether the memory access request is a write request or a read request, and executes the write request processing process or the read request processing process through the interface cache mechanism and the row hit processing mechanism according to the judgment result.

[0007] Furthermore, the interface cache mechanism and row hit processing mechanism are specifically as follows: if the user memory access request hits the data cached in the interface cache, the memory access is directly responded to by the interface cache; if the user memory access request does not hit the interface cache but a row hit occurs, the memory access only requires the memory controller to execute a read instruction or a write instruction on the DRAM storage array to respond; if the user memory access request simultaneously causes an interface cache miss and a row miss, the memory access is responded to by the memory controller executing a DRAM storage array operation.

[0008] Furthermore, the write request processing flow includes an interface cache write operation and a DRAM storage array write operation; a cache hit detector is used to determine whether a cache hit occurs in the current write request:

[0009] If a cache hit occurs in the write request, the interface cache write operation is performed;

[0010] If a cache miss occurs in a write request and the current write flag register is 1, the memory controller first writes the old data in the interface buffer back to the corresponding location of the DRAM storage array, and then writes the new data to the interface buffer according to this memory access request to perform an interface buffer write operation;

[0011] If a cache miss occurs in a write request and the current write flag register is 0, the interface cache is responsible for responding to the current memory access request.

[0012] Furthermore, the read request processing flow includes an interface cache read operation and a DRAM storage array read operation; a cache hit detector is used to determine whether a cache hit occurs in the current read request:

[0013] If a cache miss occurs in the read request and the write flag register is 0, or a cache hit occurs and both the write flag register and the read flag register are 0, the memory controller reads the requested data from the DRAM storage array to respond to the memory access request;

[0014] If a read request has a cache miss and the write flag register is 1, or a read request has a cache hit and the write flag register is 1 and the read flag register is 0, the memory controller first writes the old data in the interface cache back to the corresponding location of the DRAM storage array, and then reads the requested data from the DRAM storage array according to this memory access request and stores it in the interface cache as a response to this memory access;

[0015] If a cache hit occurs in the read request and the read flag register is 1, an interface cache read operation is performed.

[0016] Furthermore, the DRAM storage array write operation and the DRAM storage array read operation are collectively referred to as DRAM storage array read and write operations; specifically: a row hit detector determines whether a row hit occurs in the current DRAM storage array memory access. If a row hit occurs, the memory controller directly performs read and write operations on the DRAM storage array; if a row miss occurs, the memory controller first performs a precharge operation on the DRAM storage array, then performs a row activation operation for the memory access request, and finally performs a read and write operation.

[0017] Furthermore, the method further includes: before the memory controller switches threads, performing a DRAM storage array write operation to write old data temporarily stored in the interface buffer back to the DRAM storage array.

[0018] A second aspect of an embodiment of the present invention provides a three-dimensional DRAM-based memory controller, comprising an interface buffer, a cache address register, a cache hit detector, a row hit detector, a write flag register, and a read flag register;

[0019] The interface buffer serves as an interface data buffer module at the interface between the computing unit and the DRAM storage array, and is composed of two parts: a data interface buffer and a data mask interface buffer. The data interface buffer temporarily stores write data from user memory access requests or read data from the DRAM storage array. The data mask interface buffer temporarily stores the bit valid status of the write data from the user memory access request.

[0020] The cache address register will store the address of the most recent interface cache write operation initiated by a user memory access request or the address of the DRAM storage array read operation initiated by the memory controller;

[0021] The cache hit detector compares the current memory access request address with the address stored in the cache address register to determine whether it is a cache hit or a cache miss;

[0022] The row hit detector compares the row address of the current memory access request with the row address of the activated DRAM storage array. If the two are the same, it is determined to be a row hit; if the two are different, it is determined to be a row miss.

[0023] The write flag register is used to indicate the state of the interface buffer storing the write data from the user memory access request;

[0024] The read flag register is used to indicate the state of the interface buffer storing the read data from the DRAM storage array.

[0025] Furthermore, when a cache hit occurs, the data interface buffer directly responds to the user memory access request through the data interface cache register; the data mask interface buffer temporarily stores the bit valid state of the write data from the user memory access request, and the valid state is the data mask information when the data in the data interface buffer is written to the DRAM storage array. After the memory controller performs the DRAM storage array write operation, the data mask interface buffer is updated to the full mask state.

[0026] Furthermore, when the interface buffer has been written with data by a user memory access request and the memory controller has not written the data in the interface buffer into the DRAM storage array, the write flag register is set to 1; after the memory controller writes the data in the interface buffer into the DRAM storage array, the write flag register is set to 0; after the system is initialized until the interface buffer is written with data for the first time by a user memory access request, the write flag register remains 0; when the write flag register is 1, the memory controller cannot read data from the DRAM storage array and temporarily store it in the interface buffer.

[0027] Furthermore, when the address stored in the cache address register is the same as the address of the most recent DRAM storage array read operation performed by the memory controller, the read flag register is set to 1, otherwise it is set to 0; after initialization until the memory controller performs the first DRAM storage array read operation, the read flag register remains 0.

[0028] The beneficial effects of the present invention are as follows: the method of the present invention executes a write request processing process or a read request processing process through an interface cache mechanism and a row hit processing mechanism, which can effectively reduce the number of operations of the memory controller on the DRAM storage array and reduce the frequency of data entering and leaving the DRAM storage array, thereby reducing the memory access delay of the computing unit to the required data, improving memory access performance and reducing memory access power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is the memory controller operation state jump diagram;

[0030] Figure 2 Figure 2 is a diagram of the key components of a memory controller. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, like numbers in different figures represent like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0032] The terms used in this invention are for the purpose of describing specific embodiments only and are not intended to limit the invention. The singular forms "a," "the," and "the" used in this invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0033] It should be understood that although the terms "first," "second," "third," etc. may be used in the present invention to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0034] The following describes in detail the memory access performance improvement method based on a three-dimensional DRAM memory controller of the present invention in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0035] The present invention provides a method for improving memory access performance based on a three-dimensional DRAM memory controller, which specifically comprises the following steps: the memory controller receives a memory access request in an initial state, determines whether the memory access request is a write request or a read request, and executes a write request processing flow or a read request processing flow through an interface cache mechanism and a row hit processing mechanism according to the determination result.

[0036] The determination of whether the memory access request is a write request or a read request is specifically as follows: a cache miss or a hit occurs through the read / write request processing flow, and the read / write flag register is 0 or 1 to determine whether the memory access request is a write request or a read request.

[0037] The interface cache mechanism and row hit processing mechanism are specifically as follows: if the user memory access request hits the data cached in the interface cache, the memory access is directly responded to by the interface cache, and no DRAM storage array read or write operation is required; if the user memory access request does not hit the interface cache but a row hit occurs, the memory access only requires the memory controller to execute a read instruction or a write instruction on the DRAM storage array to respond; if the user memory access request simultaneously causes an interface cache miss and a row miss, the memory controller needs to execute a precharge instruction, a row activation instruction, and a read instruction or a write instruction on the DRAM storage array to respond.

[0038] Through the above-mentioned interface cache mechanism and row hit processing mechanism, if the user's memory access request hits the data cached in the interface cache, the memory access is directly responded to by the interface cache, and there is no need to perform DRAM storage array read and write operations, which can optimize the reduction of the number of memory access operations and reduce the memory access power consumption.

[0039] The write request processing flow includes an interface cache write operation and a DRAM storage array write operation; a cache hit detector is used to determine whether a cache hit occurs in the current write request.

[0040] If a cache hit occurs in the write request, the interface cache write operation is performed.

[0041] If a cache miss occurs in a write request and the current write flag register is 1, the memory controller first writes the old data in the interface cache back to the corresponding position of the DRAM storage array, and then writes the new data to the interface cache according to this memory access request to perform an interface cache write operation as a response to this memory access.

[0042] If a cache miss occurs in a write request and the current write flag register is 0, the interface cache is responsible for responding to the current memory access request.

[0043] The read request processing flow includes an interface cache read operation and a DRAM storage array read operation; a cache hit detector is used to determine whether a cache hit occurs in the current read request.

[0044] If a cache miss occurs in the read request and the write flag register is 0, or a cache hit occurs and both the write flag register and the read flag register are 0, the memory controller reads the requested data from the DRAM storage array to respond to the memory access request.

[0045] If a read request has a cache miss and the write flag register is 1, or a read request has a cache hit and the write flag register is 1 and the read flag register is 0, the memory controller first writes the old data in the interface cache back to the corresponding location of the DRAM storage array, and then reads the requested data from the DRAM storage array as a response according to the current memory access request.

[0046] If a cache hit occurs in the read request and the read flag register is 1, an interface cache read operation is performed.

[0047] The DRAM storage array write operation and DRAM storage array read operation are collectively referred to as DRAM storage array read and write operations. When the memory controller performs a DRAM storage array access operation in the write request processing flow or the read request processing flow, the row hit detector determines whether the current DRAM storage array access has a row hit. If a row hit occurs, the memory controller directly performs the read and write operation on the DRAM storage array. If a row miss occurs, the memory controller first performs a precharge operation on the DRAM storage array, then performs a row activation operation for the memory access request, and finally performs the read and write operation.

[0048] Before switching the thread it serves, the memory controller performs a DRAM storage array write operation, writing old data temporarily stored in the interface buffer back to the DRAM storage array to ensure data consistency. This improves memory access performance based on a three-dimensional DRAM memory controller.

[0049] The memory controller provided by the present invention comprises an interface buffer, a buffer address register, a buffer hit detector, a row hit detector, a write flag register and a read flag register.

[0050] The interface buffer serves as an interface data cache module at the interface between the computing unit and the DRAM storage array, and is composed of two parts: a data interface buffer and a data mask interface buffer. The data interface buffer temporarily stores write data from user memory access requests or read data from the DRAM storage array, and has a memory access latency lower than that of the DRAM storage array. When a cache hit occurs, the data interface cache register can directly respond to the user memory access request, thereby improving memory access performance. The data mask interface buffer temporarily stores the bit valid status of the write data from the user memory access request. This status information can be used as data mask information when writing data in the data interface buffer to the DRAM storage array. After the memory controller performs a DRAM storage array write operation, the data mask interface buffer is updated to a fully masked state.

[0051] The cache address register will store the address of the most recent interface cache write operation initiated by a user memory access request or the address of the DRAM storage array read operation initiated by the memory controller, and use this as the activation address of the interface cache.

[0052] The cache hit detector compares the current memory access request address with the address stored in the cache address register. If the two are the same, it is determined to be a cache hit; if the two are different, it is determined to be a cache miss.

[0053] The row hit detector compares the row address of the current memory access request with the row address of the activated DRAM storage array. If the two are the same, it is determined to be a row hit; if the two are different, it is determined to be a row miss.

[0054] The write flag register is used to indicate the status of the interface buffer storing write data from the user memory access request; when the interface buffer has been written with data by the user memory access request and the memory controller has not written the data in the interface buffer to the DRAM storage array, the write flag register is set to 1; when the memory controller writes the data in the interface buffer to the DRAM storage array, the write flag register is set to 0; after the system is initialized until the interface buffer is written with data for the first time by the user memory access request, the write flag register remains 0; when the write flag register is in the state of 1, the memory controller does not allow data to be read from the DRAM storage array and temporarily stores it in the interface buffer.

[0055] The read flag register is used to indicate the status of the interface buffer storing the read data from the DRAM storage array; when the address stored in the cache address register is the same as the address of the memory controller's most recent DRAM storage array read operation, the read flag register is set to 1, otherwise it is set to 0; after system initialization until the memory controller performs the first DRAM storage array read operation, the read flag register remains 0.

[0056] After testing using the method of the present invention, the memory access delay required for the memory controller to process a single memory access request is shown in Table 1. It can be seen from Table 1 below that the interface cache mechanism and row hit processing mechanism proposed by the present invention can reduce the memory access delay of the computing unit for the required data, thereby effectively improving the memory access performance and reducing the memory access power consumption.

[0057] Table 1: Memory access latency table

[0058]

[0059]

[0060] To sum up, the present invention can effectively reduce the number of operations of the memory controller on the DRAM storage array and the frequency of data entering and leaving the DRAM storage array through the interface cache mechanism and the row hit processing mechanism, thereby reducing the memory access delay of the computing unit to the required data, improving memory access performance and reducing memory access power consumption.

[0061] The above embodiments are intended only to illustrate the design concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The scope of protection of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design concepts disclosed in the present invention are within the scope of protection of the present invention.

Claims

1. A method for improving memory access performance based on a three-dimensional DRAM memory controller, characterized in that: Specifically, the memory controller receives a memory access request in an initial state, determines whether the memory access request is a write request or a read request, and executes a write request processing flow or a read request processing flow through an interface cache mechanism and a row hit processing mechanism according to the determination result; The interface cache mechanism and row hit processing mechanism are specifically as follows: If the user memory access request hits the data cached in the interface cache, the memory access is directly responded to by the interface cache; if the user memory access request does not hit the interface cache but a row hit occurs, the memory access only requires the memory controller to execute a read instruction or write instruction to the DRAM storage array to respond; If a user memory access request simultaneously results in an interface cache miss and a row miss, the memory controller executes a DRAM storage array operation to respond to the memory access.

2. The method for improving memory access performance based on a three-dimensional DRAM memory controller according to claim 1, characterized in that: The write request processing flow includes an interface buffer write operation and a DRAM storage array write operation; The cache hit detector is used to determine whether the current write request has a cache hit: If a cache hit occurs in the write request, the interface cache write operation is performed; If a cache miss occurs in a write request and the current write flag register is 1, the memory controller first writes the old data in the interface buffer back to the corresponding location of the DRAM storage array, and then writes the new data to the interface buffer according to this memory access request to perform an interface buffer write operation; If a cache miss occurs in a write request and the current write flag register is 0, the interface cache is responsible for responding to the current memory access request.

3. The method for improving memory access performance based on a three-dimensional DRAM memory controller according to claim 1, characterized in that: The read request processing flow includes an interface buffer read operation and a DRAM storage array read operation; The cache hit detector is used to determine whether the current read request has a cache hit: If a cache miss occurs in the read request and the write flag register is 0, or a cache hit occurs and both the write flag register and the read flag register are 0, the memory controller reads the requested data from the DRAM storage array to respond to the memory access request; If a read request has a cache miss and the write flag register is 1, or a read request has a cache hit and the write flag register is 1 and the read flag register is 0, the memory controller first writes the old data in the interface cache back to the corresponding location of the DRAM storage array, and then reads the requested data from the DRAM storage array according to this memory access request and stores it in the interface cache as a response to this memory access; If a cache hit occurs in the read request and the read flag register is 1, an interface cache read operation is performed.

4. The method for improving memory access performance based on a three-dimensional DRAM memory controller according to claim 2 or 3, characterized in that: The DRAM storage array write operation and DRAM storage array read operation are collectively referred to as DRAM storage array read and write operations; specifically: the row hit detector determines whether a row hit occurs in the current DRAM storage array memory access. If a row hit occurs, the memory controller directly performs read and write operations on the DRAM storage array; if a row miss occurs, the memory controller first performs a precharge operation on the DRAM storage array, then performs a row activation operation for the memory access request, and finally performs a read and write operation.

5. The method for improving memory access performance based on a three-dimensional DRAM memory controller according to claim 1, characterized in that: The method further includes: before the memory controller switches threads, executing a DRAM storage array write operation to write old data temporarily stored in the interface buffer back to the DRAM storage array.

6. A three-dimensional DRAM memory controller, characterized in that: It includes an interface buffer, a cache address register, a cache hit detector, a row hit detector, a write flag register and a read flag register; The interface buffer serves as an interface data buffer module at the interface between the computing unit and the DRAM storage array, and is composed of two parts: a data interface buffer and a data mask interface buffer. The data interface buffer temporarily stores write data from user memory access requests or read data from the DRAM storage array. The data mask interface buffer temporarily stores the bit valid status of the write data from the user memory access request. The cache address register will store the address of the most recent interface cache write operation initiated by a user memory access request or the address of the DRAM storage array read operation initiated by the memory controller; The cache hit detector compares the current memory access request address with the address stored in the cache address register to determine whether it is a cache hit or a cache miss; The row hit detector compares the row address of the current memory access request with the row address of the activated DRAM storage array. If the two are the same, it is determined to be a row hit; if the two are different, it is determined to be a row miss. The write flag register is used to indicate the state of the interface buffer storing the write data from the user memory access request; The read flag register is used to indicate the state of the interface buffer storing the read data from the DRAM storage array.

7. The three-dimensional DRAM memory controller according to claim 6, characterized in that: When a cache hit occurs, the data interface buffer directly responds to the user memory access request through the data interface cache register; the data mask interface buffer temporarily stores the bit valid state of the write data from the user memory access request, and the valid state is the data mask information when the data in the data interface buffer is written to the DRAM storage array. After the memory controller performs the DRAM storage array write operation, the data mask interface buffer is updated to the full mask state.

8. The three-dimensional DRAM memory controller according to claim 6, characterized in that: When the interface buffer has been written with data by the user's memory access request and the memory controller has not written the data in the interface buffer into the DRAM storage array, the write flag register is set to 1; When the memory controller writes data from the interface buffer to the DRAM storage array, the write flag register is set to 0; after the system is initialized until the interface buffer is first accessed by the user and data is written, the write flag register remains 0; when the write flag register is 1, the memory controller cannot read data from the DRAM storage array and temporarily store it in the interface buffer.

9. The three-dimensional DRAM memory controller according to claim 6, characterized in that: When the address stored in the cache address register is the same as the address of the most recent DRAM storage array read operation performed by the memory controller, the read flag register is set to 1, otherwise it is set to 0; after initialization until the memory controller performs the first DRAM storage array read operation, the read flag register remains 0.

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