A memory cell design circuit

Abstract

The present invention discloses a storage unit design circuit, including a first C unit circuit, a second C unit circuit, a first inverter, a second inverter, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the output ends of the first C unit circuit and the second C unit circuit are nodes for storing levels, and when any one or two nodes of the input end of the first C unit circuit or the second C unit circuit, or the output end node, are disturbed and a level jump occurs, they can be restored to the original level. In the present application, when a certain node in the circuit is disturbed and a level jump occurs, it can be restored to the original level, avoiding the erroneous level from being read and causing a control system failure, and the unit circuit composed of each switch tube forms a low-resistance current path to reduce read and write delays.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a storage unit design circuit. Background Art

[0002] In recent years, with the significant improvement in circuit performance and integration, integrated circuits are now widely used in various fields such as aerospace, medical equipment, and electronic vehicles. However, due to the presence of various radiation particles in the radiation environment, integrated circuits are susceptible to particle bombardment and produce single particle effects. The charge generated by a single particle incident can be collected by a single or multiple nodes, causing the stored logic value to undergo a single node upset (Single Node Upset, SNU) or multiple node upset (Multiple Node Upset, MNU), such as: Double Node Upset (DNU). When integrated circuit devices are in sensitive environments such as radiation, it poses a severe challenge to the reliability of the circuit. Especially in the field of aerospace safety, the demand for high-performance integrated circuits with radiation resistance is very urgent.

[0003] Single particle effects have a serious impact on memory cells. On the one hand, in combinational logic circuits, when hit by particles, transient pulses will be generated at the output of the logic gate. If the transient pulse does not undergo logical shielding, electrical shielding, and time window shielding effects, the transient pulse will propagate to the memory cell or latch, and the erroneous data will be latched. On the other hand, when high-energy particles directly hit the memory cell or latch, unreinforced circuit cells may produce single node upsets (SNU) or double node upsets (DNU).

[0004] The main function of the memory cell is to store data information and access data. Among them, static random access memory cells have the characteristics of fast read and write speed and low power consumption, so they are widely used in integrated circuits. In addition, the memory cell design circuit is the most affected by radiation effects in the memory cell. When hit by high-energy particles, the logic values ​​of the nodes inside the circuit may flip, and erroneous data may be read, causing potential system failures. In order to improve the reliability of the circuit, it is of great practical significance to design static random access memory cells that are reinforced against the problem of multi-node flipping caused by single particle effects. Summary of the invention

[0005] The purpose of the present invention is to provide a storage unit design circuit, which can restore a node in the circuit to its original level when a level jump occurs due to interference, thereby preventing the wrong level from being read and causing a control system failure, and the unit circuit composed of each switch tube forms a low-resistance current path to reduce read and write delays.

[0006] To solve the above technical problems, the present invention provides a storage unit design circuit, including a first C unit circuit, a second C unit circuit, a first inverter, a second inverter, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; the control end of the first switch tube and the control end of the second switch tube input a first read-write control signal, the control end of the third switch tube and the control end of the fourth switch tube input a second read-write control signal, the first read-write control signal and the second read-write control signal are complementary, the first end of the first switch tube and the third switch tube input a first bit signal, the second end of the first switch tube and the third switch tube is connected to the output end of the first C unit circuit and the first input end of the second C unit circuit; the first end of the second switch tube and the fourth switch tube is connected to the output end of the second C unit circuit and the second input end of the first C unit circuit, and the second end of the second switch tube and the fourth switch tube input a second bit signal; the input end of the first inverter is connected to the output end of the first C unit circuit, and the output end is connected to the first input end of the first C unit circuit; the input end of the second inverter is connected to the output end of the second C unit circuit, and the output end is connected to the second input end of the second C unit circuit;

[0007] The first switch tube, the second switch tube, the third switch tube and the fourth switch tube are used to access the first signal and the second signal; the first C unit circuit and the second C unit circuit are used to output a level opposite to the level of their own input after a first delay time when the levels of their own first input terminal and second input terminal are the same, so as to save data, and present high impedance at their own output terminal when the levels of their own first input terminal and second input terminal are different;

[0008] The first inverter and the second inverter are used to invert the level of their own input after a second delay time; the second delay time is shorter than the first delay time;

[0009] When the first read-write control signal and the second read-write control signal constitute a preset read-write signal, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are turned on, the output end of the first C unit circuit is stored as the level of the first bit signal or is read through the first bit signal, and the output end of the second C unit circuit is stored as the level of the second bit signal or is read through the second bit signal.

[0010] Preferably, the first C unit circuit or the second C unit circuit includes a first sub-switch tube, a second sub-switch tube, a third sub-switch tube and a fourth sub-switch tube;

[0011] The first end of the first sub-switch tube is connected to a DC power supply, and the second end is connected to the first end of the second sub-switch tube; the second end of the second sub-switch tube is connected to the first end of the third sub-switch tube, the second end of the third sub-switch tube is connected to the first end of the fourth sub-switch tube, and the second end of the fourth sub-switch tube is grounded;

[0012] The control ends of the first sub-switch tube and the third sub-switch tube are connected and serve as the first input end of the first C unit circuit or the second C unit circuit; the control ends of the second sub-switch tube and the fourth sub-switch tube are connected and serve as the second input end of the first C unit circuit or the second C unit circuit; the second end of the second sub-switch tube and the first end of the third sub-switch tube serve as the output end of the first C unit circuit or the second C unit circuit;

[0013] The first sub-switch tube and the second sub-switch tube are used to be turned on when their control terminals are at a low level, and the third sub-switch tube and the fourth sub-switch tube are used to be turned on when their control terminals are at a high level, so that the first C unit circuit or the second C unit circuit outputs a level opposite to its own input level when the levels of its first input terminal and the second input terminal are the same, and presents a high impedance at its own output terminal when the levels of its first input terminal and the second input terminal are different.

[0014] Preferably, the first sub-switch tube and the second sub-switch tube are PMOS, and the third sub-switch tube and the fourth sub-switch tube are NMOS.

[0015] Preferably, the first C unit circuit is specifically used for storing the level of the first bit signal to its own output end when the first switch tube and the third switch tube are turned on and the levels of the first bit signal and the second bit signal are opposite, and for reading the level of its own output end through the first bit signal when the first switch tube and the third switch tube are turned on and the levels of the first bit signal and the second bit signal are the same;

[0016] The second C unit circuit is specifically used to store the level of the second bit signal to its own output end when the second switch tube and the fourth switch tube are turned on and the levels of the first bit signal and the second bit signal are opposite, and to read the level of its own output end through the second bit signal when the second switch tube and the fourth switch tube are turned on and the levels of the first bit signal and the second bit signal are the same.

[0017] Preferably, it also includes:

[0018] An interference simulation verification device is used to inject a simulated interference current into the input node or output node of the first C unit circuit or the second C unit circuit to determine whether the input node or the output node of the first C unit circuit or the second C unit circuit undergoes a level flip and restores its original level when being subjected to the simulated interference current.

[0019] Preferably, the interference simulation verification device is specifically used to inject the simulated interference current into the first input terminal, the second input terminal and the output terminal of the first C unit circuit, and any one of the first input terminal, the second input terminal and the output terminal of the second C unit circuit, so as to determine whether any node undergoes a level flip and restores its original level when being subjected to the simulated interference current.

[0020] Preferably, the interference simulation verification device is specifically used to inject the simulated interference current into the first input terminal, the second input terminal and the output terminal of the first C unit circuit, and two nodes among the first input terminal, the second input terminal and the output terminal of the second C unit circuit, but not to inject the simulated interference current into the output terminal of the first C unit circuit and the output terminal of the second C unit circuit at the same time, so as to determine the situation in which the levels of the two nodes are flipped and restored to their original levels when they are affected by the simulated interference current.

[0021] Preferably, it also includes:

[0022] An area determination module is used to determine the total area of ​​the storage unit design circuit according to the areas of the first C unit circuit, the second C unit circuit, the first inverter, the second inverter, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube.

[0023] Preferably, it also includes:

[0024] A delay determination module is used to determine the write delay time from the time when the first read-write control signal and the second read-write control signal constitute a preset read-write signal to the time when the output end of the first C unit circuit is stored as the level of the first bit signal and the output end of the second C unit circuit is stored as the level of the second bit signal; and determine the read delay time from the time when the first read-write control signal and the second read-write control signal constitute a preset read-write signal to the time when the level of the first bit signal and the level of the second bit signal differ by a preset level.

[0025] Preferably, it also includes:

[0026] A noise margin determination module is used to inject a DC noise source into the output end of the first C unit circuit in the storage unit design circuit in a non-working state to determine the first voltage change data of the output end of the second C unit circuit, inject a DC noise source into the output end of the second C unit circuit in the storage unit design circuit in a non-working state to determine the second voltage change data of the output end of the first C unit circuit, and determine the static noise margin based on the first voltage change data and the second voltage change data; and inject the DC noise source into the output end of the first C unit circuit and the output end of the second C unit circuit respectively when storing levels in the output end of the first C unit circuit and the output end of the second C unit circuit to determine the write static noise margin of the storage unit design circuit; and inject the DC noise source into the output end of the first C unit circuit and the output end of the second C unit circuit respectively when reading the levels of the output end of the first C unit circuit and the output end of the second C unit circuit to determine the read static noise margin of the storage unit design circuit.

[0027] The present invention discloses a storage unit design circuit, including a first C unit circuit, a second C unit circuit, a first inverter, a second inverter, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the output ends of the first C unit circuit and the second C unit circuit are nodes for storing levels, and when any one or two nodes of the input end of the first C unit circuit or the second C unit circuit, or the output end node, are disturbed and a level jump occurs, they can be restored to the original level. In the present application, when a certain node in the circuit is disturbed and a level jump occurs, it can be restored to the original level, avoiding the erroneous level from being read and causing a control system failure, and the unit circuit composed of each switch tube forms a low-resistance current path to reduce read and write delays. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of a storage unit design circuit provided by the present invention;

[0030] Figure 2 A schematic diagram of simulation waveforms of various nodes when the storage unit design circuit provided by the present invention works normally;

[0031] Figure 3A schematic diagram of the structure of a first C unit circuit or a second C unit circuit provided by the present invention;

[0032] Figure 4 A schematic diagram of a simulation waveform of a single node applying a simulated interference current disclosed in the present invention;

[0033] Figure 5 The present invention discloses a schematic diagram of a simulation waveform of applying a simulated interference current to a dual node. DETAILED DESCRIPTION

[0034] The core of the present invention is to provide a storage unit design circuit, which can restore a node in the circuit to its original level when a level jump occurs due to interference, thereby preventing the wrong level from being read and causing a control system failure. The unit circuit composed of each switch tube forms a low-resistance current path to reduce read and write delays.

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Please refer to Figure 1 , Figure 1A schematic diagram of a storage unit design circuit provided by the present invention, the circuit includes a first C unit circuit CE1, a second C unit circuit CE2, a first inverter D1, a second inverter D2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4; a first read-write control signal WL is input to a control end of the first switch tube Q1 and a control end of the second switch tube Q2, a second read-write control signal WLB is input to a control end of the third switch tube Q3 and a control end of the fourth switch tube Q4, the first read-write control signal WL and the second read-write control signal WLB are complementary, a first bit signal BL is input to a first end of the first switch tube Q1 and a third switch tube Q3, and a first bit signal BL is input to a first switch tube Q1 and a third switch tube Q3. The second end of the switch tube Q3 is connected to the output end Q of the first C unit circuit CE1 and the first input end of the second C unit circuit CE2; the first ends of the second switch tube Q2 and the fourth switch tube Q4 are connected to the output end QB of the second C unit circuit CE2 and the second input end of the first C unit circuit CE1, and the second ends of the second switch Q2 and the fourth switch tube Q4 input the second bit signal BLN; the input end of the first inverter D1 is connected to the output end of the first C unit circuit CE1, and the output end is connected to the first input end A of the first C unit circuit CE1; the input end of the second inverter D2 is connected to the output end of the second C unit circuit CE2, and the output end is connected to the second input end B of the second C unit circuit CE2;

[0037] The first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 are used for accessing the first signal and the second signal;

[0038] The first C unit circuit CE1 and the second C unit circuit CE2 are used to output a level opposite to the level of their own input after a first delay time when the levels of their own first input terminal and second input terminal are the same, so as to save data, and present a high impedance at their own output terminal when the levels of their own first input terminal and second input terminal are different;

[0039] The first inverter D1 and the second inverter D2 are used to invert the level of their own input after a second delay time; the second delay time is shorter than the first delay time;

[0040] When the first read-write control signal WL and the second read-write control signal WLB constitute the preset read-write signal, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 are turned on, the output end Q of the first C unit circuit CE1 is stored as the level of the first bit signal BL or is read through the first bit signal BL, and the output end QB of the second C unit circuit CE2 is stored as the level of the second bit signal BLN or is read through the second bit signal BLN.

[0041] The applicant has considered that when the storage unit in the prior art is impacted by radiation particles or leakage current in a radiation environment, the stored data may be flipped, causing the stored data to change. Even worse, after the erroneous data is read, the system processing the data may malfunction, causing safety problems.

[0042] In order to solve the above technical problems, the storage unit design circuit in the present application includes a first C unit circuit CE1, a second C unit circuit CE2, a first inverter D1, a second inverter D2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4, wherein when the first read-write control signal WL and the second read-write control signal WLB constitute a preset read-write signal, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 are turned on, and the output end Q of the first C unit circuit CE1 is pulled to the level of the first bit signal BL by the turned-on first switch tube Q1 and the third switch tube Q3, or the level of the first bit signal BL is pulled to the level of the output end Q of the first C unit circuit CE1 by the turned-on first switch tube Q1 and the third switch tube Q3, and since the first input end of the second C unit circuit CE2 is connected to the output end Q of the first C unit circuit CE1, at this time, the level of the first input end of the second C unit circuit CE2 and the output end Q of the first C unit circuit CE1 are equal. The levels of the first C unit circuit CE1 and the first input terminal of the first C unit circuit CE1 are the same, and the output terminal Q of the first C unit circuit CE1 is connected to the first input terminal of the first C unit circuit CE1 through the first inverter D1, so the level of the first input terminal A of the first C unit circuit CE1 is the opposite level of the level of the output terminal of the first C unit circuit CE1; the output terminal QB of the second C unit circuit CE2 is pulled to the level of the second bit signal BLN by the second switch tube Q2 and the fourth switch tube Q4 after being turned on, or the level of the second bit signal BLN is pulled to the level of the output terminal QB of the second C unit circuit CE2 by the second switch tube Q2 and the fourth switch tube Q4 after being turned on. Since the second input terminal of the first C unit circuit CE1 is connected to the output terminal QB of the second C unit circuit CE2, the second input terminal of the first C unit circuit CE1 is also the level of the input terminal of the second C unit circuit CE2, and the output terminal QB of the second C unit circuit CE2 and the second input terminal of the second C unit circuit CE2 are connected to the second inverter D2, so the level of the second input terminal B of the second C unit circuit CE2 is the opposite level of the level of the output terminal of the second C unit circuit CE2. When the level of the output terminal Q of the first C unit circuit CE1 is pulled to the level of the first bit signal BL and the level of the output terminal QB of the second C unit circuit CE2 is pulled to the level of the second bit signal BLN, the output terminal Q of the first C unit circuit CE1 is stored as the level of the first bit signal BL and the output terminal QB of the second C unit circuit CE2 is stored as the level of the second bit signal BLN; and when the first bit signal BL is pulled to the level of the output terminal Q of the first C unit circuit CE1 and the second bit signal BLN is pulled to the level of the output terminal QB of the second C unit circuit CE2, the level stored at the output terminal Q of the first C unit circuit CE1 and the level stored at the output terminal of the second C unit are read through the levels of the first bit signal BL and the second bit signal BLN, thereby realizing the storage and reading of the levels.

[0043] Specifically, the first bit signal BL and the second bit signal BLN are input to the sense amplifier for comparison and judgment, and it is determined whether the read data is 0 or 1, thereby realizing signal reading.

[0044] In the non-read and non-storage state, for example, the level of the first input terminal A of the first C unit circuit CE1 is high, the level of the second input terminal is also high, and the level of the output terminal is low; the level of the first input terminal of the second C unit circuit CE2 is low, the level of the second input terminal is low, and the output terminal is high. At this time, when there is a level flip, the level protection mechanism of the designed circuit is as follows:

[0045] When the level of the second input terminal of the first C unit circuit CE1 or the first input terminal of the second C unit circuit CE2 is reversed, since the first C unit circuit CE1 and the second C unit circuit CE2 will not change the level of their own output terminals due to the reversal of the level of one of their own input terminals, the level of the second input terminal of the first C unit circuit CE1 is pulled back to the level of the output terminal QB of the second C unit circuit CE2, and the level of the first input terminal of the second C unit circuit CE2 is pulled back to the level of the output terminal Q of the first C unit circuit CE1; accordingly, when the first input terminal A of the first C unit circuit CE1 or the first input terminal A of the second C unit circuit CE2 When the level of the second input terminal B is flipped, the level of the output terminal QB of the first C unit circuit CE1 or the second C unit circuit CE2 will not change, and because the output terminals QB of the first C unit circuit CE1 and the second C unit circuit CE2 are both connected to inverters, the level of the input terminal of the first inverter D1 is maintained at a low level, and the level of the second inverter D2 is maintained at a high level. Therefore, the level of the output terminal of the first inverter D1, that is, the level of the first input terminal A of the first C unit circuit CE1, will be immediately pulled to a high level, and the level of the second input terminal B of the second C unit circuit CE2 will be immediately pulled to a low level, thereby realizing the recovery of the flipped level. In addition, if the levels of the first input terminal A of the first C unit circuit CE1 and the output terminal QB of the second C unit circuit CE2 are simultaneously flipped to a low level, although the second input terminal of the first C unit circuit CE1 will be pulled to a low level, due to the first delay time of the first C unit circuit CE1, the level of the output terminal Q of the first C unit circuit CE1 will not be changed immediately. At this time, the level of the first input terminal of the second C unit circuit CE2 is still at a low level. Since the second delay time is less than the first delay time, before the level of the output terminal Q of the first C unit circuit CE1 is changed, the output terminal of the first inverter D1 will be at a high level first, thereby flipping the level of the first input terminal A of the first C unit circuit CE1 back to a high level, and the levels of the two input terminals of the first C unit circuit CE1 are opposite again, and its own output terminal presents a high impedance, that is, the level of the output terminal Q of the first C unit circuit CE1 will not be changed, and then the level of the output terminal QB of the second C unit circuit CE2 is pulled high again, and the level of the second input terminal of the first C unit circuit CE1 is also restored to a high level, thereby realizing recovery after the level flip. When the levels of the output terminal Q of the first C unit circuit CE1 and the second input terminal B of the second C unit circuit CE2 are flipped at the same time, the corresponding level recovery is as described above, and the present application will not elaborate on this.

[0046] Please refer to Figure 2 , Figure 2The schematic diagram of the simulation waveforms of each node when the storage unit design circuit provided by the present invention works normally is shown in the figure, wherein the voltage waveforms of the second bit signal BLN, the first bit signal BL, the second read / write control signal WLB, the first read / write control signal WL, the second input terminal B of the second C unit circuit CE2, the first input terminal A of the first C unit circuit CE1, the output terminal QB of the second C unit circuit CE2, and the output terminal Q of the first C unit circuit CE1 are shown in sequence.

[0047] Among them, the first switch tube Q1 and the third switch tube Q3 constitute a CMOS (Complementary Metal Oxide Semiconductor) transmission gate (TG), that is, when the first switch tube Q1 is NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor), and the third switch tube Q3 is PMOS (P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor), it constitutes a CMOS, and the control end provided to the two switch tubes is also a complementary signal. If the PMOS gate is a high level and the NMOS gate is a low level, then PMOS and NMOS are cut off, the CMOS transmission gate is in a disconnected state, and the level signal cannot be transmitted. If the PMOS gate is a low level and the NMOS gate is a high level, then PMOS and NMOS are turned on, and the CMOS transmission gate forms a low-resistance current path, and the level signal can be transmitted to reduce the read and write delay. The second switch tube Q2 and the fourth switch tube Q4 also constitute a CMOS, which is not repeated in this application.

[0048] In summary, the present application can restore a node in the circuit to its original level when a level jump occurs due to interference, thereby preventing the wrong level from being read and causing a control system failure, and the unit circuit composed of each switch tube forms a low-resistance current path to reduce read and write delays.

[0049] Based on the above embodiments:

[0050] Please refer to Figure 3 , Figure 3 A schematic structural diagram of a first C unit circuit or a second C unit circuit provided by the present invention.

[0051] As a preferred embodiment, the first C unit circuit CE1 or the second C unit circuit CE2 includes a first sub-switch tube Q11, a second sub-switch tube Q21, a third sub-switch tube Q31 and a fourth sub-switch tube Q41;

[0052] The first end of the first sub-switch tube Q11 is connected to the DC power supply, and the second end is connected to the first end of the second sub-switch tube Q21; the second end of the second sub-switch tube Q21 is connected to the first end of the third sub-switch tube Q31, the second end of the third sub-switch tube Q31 is connected to the first end of the fourth sub-switch tube Q41, and the second end of the fourth sub-switch tube Q41 is grounded;

[0053] The control ends of the first sub-switch tube Q11 and the third sub-switch tube Q31 are connected and serve as the first input end of the first C unit circuit CE1 or the second C unit circuit CE2; the control ends of the second sub-switch tube Q21 and the fourth sub-switch tube Q41 are connected and serve as the second input end B of the first C unit circuit CE1 or the second C unit circuit CE2; the second end of the second sub-switch tube Q21 and the first end of the third sub-switch tube Q31 serve as the output end QB of the first C unit circuit CE1 or the second C unit circuit CE2;

[0054] The first sub-switch tube Q11 and the second sub-switch tube Q21 are used to be turned on when their control terminals are at a low level, and the third sub-switch tube Q31 and the fourth sub-switch tube Q41 are used to be turned on when their control terminals are at a high level, so that the first C unit circuit CE1 or the second C unit circuit CE2 outputs a level opposite to its own input level when the levels of its first input terminal and the second input terminal are the same, and presents a high impedance at its own output terminal when the levels of its first input terminal and the second input terminal are different.

[0055] The present embodiment provides a specific implementation of a first C unit circuit CE1 or a second C unit circuit CE2. Taking the first C unit circuit CE1 as an example, when the first input terminal A and the second input terminal of the first C unit circuit CE1 are at the same level, that is, the control terminals of the first sub-switch tube Q11, the second sub-switch tube Q21, the third sub-switch tube Q31 and the fourth sub-switch tube Q41 are at the same level, there are two situations. One is that the control terminal level of each switch tube is low level, the first sub-switch tube Q11 and the second sub-switch tube Q21 are turned on, and the third sub-switch tube Q31 and the fourth sub-switch tube Q41 are turned off. Since the first end of the first sub-switch tube Q11 is connected to a DC power supply, the first C unit circuit CE1 outputs a high level at this time; secondly, the level of the control end of each switch tube is a high level, and the third sub-switch tube Q31 and the fourth sub-switch tube Q41 are turned on while the first sub-switch tube Q11 and the second sub-switch tube Q21 are turned off. Since the second end of the fourth sub-switch tube Q41 is connected to a DC power supply, the first C unit circuit CE1 outputs a low level at this time; based on this, it can be achieved that when the levels of the first input terminal A and the second input terminal of the first C unit circuit CE1 are the same, the first C unit circuit CE1 outputs a level opposite to the input terminal level.

[0056] When the levels of the first input terminal A and the second input terminal of the first C unit circuit CE1 are different, the first sub-switch tube Q11 and the fourth sub-switch tube Q41 may be turned on while the second sub-switch tube Q21 and the third sub-switch tube Q31 are turned off, or the second sub-switch tube Q21 and the third sub-switch tube Q31 may be turned on while the first sub-switch tube Q11 and the fourth sub-switch tube Q41 are turned off. At this time, the second end of the second sub-switch tube Q21 and the first end of the third sub-switch tube Q31 are neither high level nor low level, and the first C unit circuit CE1 presents high impedance at its output end.

[0057] Correspondingly, the second C unit circuit CE2 has the same structure as the first C unit circuit CE1, which will not be described in detail in this application.

[0058] in, Figure 2 Here, I1 is the level of the control end of the first sub-switch tube Q11 and the third sub-switch tube Q31, and I2 is the level of the control end of the second sub-switch tube Q21 and the fourth sub-switch tube Q41.

[0059] Based on this, the first C unit circuit CE1 or the second C unit circuit CE2 can ensure that when the same level is input to its first input terminal and the second input terminal, it outputs a level opposite to the input level, and outputs high impedance when different levels are input to its first input terminal and the second input terminal, so as to tolerate the single node of its first input terminal or the second input terminal being disturbed and flipped.

[0060] As a preferred embodiment, the first sub-switch tube Q11 and the second sub-switch tube Q21 are PMOS, and the third sub-switch tube Q31 and the fourth sub-switch tube Q41 are NMOS.

[0061] In this embodiment, the first sub-switch tube Q11 and the second sub-switch tube Q21 can be but are not limited to PMOS, wherein the gate of the PMOS is the control end, the drain is the first end, and the source is the second end. The third sub-switch tube Q31 and the fourth sub-switch tube Q41 can be but are not limited to NMOS, wherein the gate of the NMOS is the control end, the drain is the first end, and the source is the second end.

[0062] When the source of the first sub-switch tube Q11 is connected to the drain of the third sub-switch tube Q31 (the source of the second sub-switch tube Q21 is connected to the drain of the fourth sub-switch tube Q41), and the drain of the first sub-switch tube Q11 is connected to the source of the third sub-switch tube Q31 (the drain of the second sub-switch tube Q21 is connected to the source of the fourth sub-switch tube Q41), the source of the first sub-switch tube Q11 and the third sub-switch tube Q31 are turned on at the same time, and the source of the second sub-switch tube Q21 and the fourth sub-switch tube Q41 are turned on at the same time, forming a low-pass current loop to reduce the read and write delays.

[0063] As a preferred embodiment, the first C unit circuit CE1 is specifically used for storing the level of the first bit signal BL to its own output end when the first switch tube Q1 and the third switch tube Q3 are turned on and the levels of the first bit signal BL and the second bit signal BLN are opposite, and for reading the level of its own output end through the first bit signal BL when the first switch tube Q1 and the third switch tube Q3 are turned on and the levels of the first bit signal BL and the second bit signal BLN are the same;

[0064] The second C unit circuit CE2 is specifically used for storing the level of the second bit signal BLN to its own output end when the second switch tube Q2 and the fourth switch tube Q4 are turned on and the levels of the first bit signal BL and the second bit signal BLN are opposite, and for reading the level of its own output end through the second bit signal BLN when the second switch tube Q2 and the fourth switch tube Q4 are turned on and the levels of the first bit signal BL and the second bit signal BLN are the same.

[0065] When storing levels in the output terminals QB of the first C unit circuit CE1 and the second C unit circuit CE2, the first bit signal BL and the second bit signal BLN are first charged to corresponding levels. For example, if a high level is to be stored at the output terminal Q of the first C unit circuit CE1 and a low level is to be stored at the output terminal QB of the second C unit circuit CE2, the first bit signal BL is charged to a high level and maintained, and the second bit signal BLN is charged to a low level and maintained, so as to achieve storage of high and low levels. If a low level is to be stored at the output terminal Q of the first C unit circuit CE1 and a high level is to be stored at the output terminal QB of the second C unit circuit CE2, the first bit signal BL is charged to a low level and maintained, and the second bit signal BLN is charged to a high level and maintained, so as to achieve storage of high and low levels.

[0066] When it is desired to read the level of the output terminal QB of the first C unit circuit CE1 and the second C unit circuit CE2, the first bit signal BL and the second bit signal BLN can be charged to a high level or a low level. For example, the first bit signal BL and the second bit signal BLN are charged to a high level, the output terminal Q of the first C unit circuit CE1 stores a high level, and the output terminal QB of the second C unit circuit CE2 stores a low level. The first bit signal BL will be maintained at a high level, and the second bit signal BLN will be pulled down by the low level of the output terminal QB of the second C unit circuit CE2. The level stored in the first C unit circuit CE1 and the second C unit circuit CE2 can be determined by the level difference between the first bit signal BL and the second bit signal BLN, that is, the level stored in the storage unit in the present application.

[0067] Based on this, the levels of the output terminals QB of the first C unit circuit CE1 and the second C unit circuit CE2 can be conveniently stored and read, which is easy to process.

[0068] As a preferred embodiment, it also includes:

[0069] The interference simulation verification device is used to inject simulated interference current into the input node or output node of the first C unit circuit CE1 or the second C unit circuit CE2 to determine whether the input node or output node of the first C unit circuit CE1 or the second C unit circuit CE2 undergoes level flipping and restores its original level when subjected to the simulated interference current.

[0070] In this embodiment, an interference simulation verification device is also provided, which injects a simulated interference current into the input node or output node of the first C unit circuit CE1 or the second C unit circuit CE2 to determine whether the first C unit circuit CE1 and the second C unit circuit CE2 can prevent the level from flipping and causing the stored level to change when receiving interference.

[0071] For example, the node flip retention and recovery capabilities of the storage cell design circuit in the present application can be verified by using HSPICE simulation, but not limited to. In the model construction of the storage cell design circuit, the 22nmPTM process model can be used, but not limited to. The temperature can also be set to 25 degrees Celsius, but not limited to. The supply voltage can be set to 0.8V. Use a double exponential current source model to simulate the simulated interference current source of particle bombardment, that is:

[0072]

[0073] Where Q is the deposited charge generated by the single particle effect at the internal node, t is the time, I(t) is the interference current generated by the single particle effect at the internal node, τ α is the charge accumulation time constant, τ β is the ion trajectory establishment constant. τ α and τ β The value of depends on different process models. Different processes have different parameters. In this embodiment, two independent current sources are used to simulate the double-node flip caused by the single-particle effect.

[0074] As a preferred embodiment, the interference simulation verification device is specifically used to inject simulated interference current into the first input terminal A, the second input terminal and the output terminal of the first C unit circuit CE1, and any one of the first input terminal, the second input terminal and the output terminal of the second C unit circuit CE2, so as to determine whether any node undergoes a level flip and restores its original level when subjected to the simulated interference current.

[0075] In this embodiment, a simulated interference current is injected into a single node in the first C unit circuit CE1 and the second C unit circuit CE2 to analyze the node flipping phenomenon of the storage cell design circuit when the single-node interference is injected. For example, since the storage cell design circuit in the present application is a symmetrical structure, the single-node flip recovery principle of A, Q, B and QB in the storage cell design circuit is similar.

[0076] When A is affected by analog interference current, because the first C unit circuit CE1 can tolerate single-node errors, and since the QB value remains unchanged, the level of point Q will not be affected by the level flip of point A. Instead, the value of A will be restored by the Q point level through the first inverter D1, thereby realizing the recovery of the single-node flip.

[0077] When Q is disturbed by analog interference current, node A will also be affected. Due to the existence of the second delay time of the first inverter D1, before point A is flipped by the inverter, since QB and nodes B remain unchanged, node Q will restore its original correct value because the levels of the two input terminals of the first C unit circuit CE1 are not reversed. Figure 4 As shown, Figure 4 This is a schematic diagram of a simulation waveform of a single node applying a simulated interference current disclosed in the present invention. It can be observed that the storage unit design circuit in the present application has a single node flip self-recovery capability. Among them, Figure 4 In the figure, there are respectively the voltage waveform of the second input terminal B of the second C unit circuit CE2, the voltage waveform of the first input terminal A of the first C unit circuit CE1, the voltage waveform of the output terminal QB of the second C unit circuit CE2 and the voltage waveform of the output terminal Q of the first C unit circuit CE1. The position indicated by the arrow is the moment when the simulated interference current is injected into the node.

[0078] As a preferred embodiment, the interference simulation verification device is specifically used to inject simulated interference current into two nodes among the first input terminal A, the second input terminal and the output terminal of the first C unit circuit CE1, and the first input terminal, the second input terminal and the output terminal of the second C unit circuit CE2, but does not inject simulated interference current into the output terminal of the first C unit circuit CE1 and the output terminal of the second C unit circuit CE2 at the same time, so as to determine the situation in which the levels of the two nodes are flipped and restored to their original levels when they are subjected to the simulated interference current.

[0079] In this embodiment, the recovery capability of the storage unit design circuit against double node flip is analyzed.

[0080] (1) Node pair<A,B> When both flip at the same time, the fault tolerance characteristics of the first C unit circuit CE1 and the second C unit circuit CE2 show that the flip error can be intercepted by the first C unit circuit CE1 and the second C unit circuit CE2. Therefore, the Q and QB nodes are not affected. Finally, the outputs of the first C unit circuit CE1 and the second C unit circuit CE2 are still correct.<A,B> The level of the node pair may be restored by the first inverter D1 and the second inverter D2.

[0081] (2) Node pair<A,QB> and<Q,B> The analysis is as follows.<B,Q> Take the node pair as an example. When both are flipped at the same time, because A and QB are correct values, before A is flipped by the first inverter D1, the first C unit circuit CE1 will make the Q value in a strong "1" or strong "0" state, so the Q value will quickly recover to the original correct value after flipping, and the B value will also be restored to the correct value through the second inverter D2. Because the circuit structure is symmetrical, similarly,<A,QB> Dual-node rollover recovery can also be achieved.

[0082] (3) Node pair<A,Q> and<QB,B> The analysis is as follows. In this embodiment,<QB,B> Take the node pair as an example. When both flip at the same time, due to the single-node fault tolerance of the first C unit circuit CE1, the Q value will remain the correct value, so the QB value will also recover quickly, and the B value will also recover through the second inverter D2.

[0083] like Figure 5 As shown, Figure 5 The present invention discloses a schematic diagram of a simulation waveform of applying a simulated interference current to a dual node.

[0084] like Figure 5 Shown<Q,A> ,<Q,B> ,<A,B> ,<QB,B> and<A,QB> The nodes are subjected to the simulation waveform of DNU, and it is observed that the storage cell design circuit has DNU self-recovery capability.

[0085] in, Figure 5 In the figure, there are respectively the voltage waveform of the second input terminal B of the second C unit circuit CE2, the voltage waveform of the first input terminal A of the first C unit circuit CE1, the voltage waveform of the output terminal QB of the second C unit circuit CE2 and the voltage waveform of the output terminal Q of the first C unit circuit CE1. The position indicated by the arrow is the moment when the simulated interference current is injected into the node.

[0086] As a preferred embodiment, it also includes:

[0087] The area determination module is used to determine the total area of ​​the storage unit design circuit according to the areas of the first C unit circuit CE1, the second C unit circuit CE2, the first inverter D1, the second inverter D2, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4.

[0088] In this embodiment, the total area of ​​the memory cell design circuit can also be determined, so as to perform corresponding analysis.

[0089] For example, in this embodiment, the width-to-length ratio of the first sub-switch tube Q11 and the third switch tube Q31 in the first C unit circuit CE1 is set to 5.69, and the width-to-length ratio of the second sub-switch tube Q21 and the fourth switch tube Q41 in the second C unit circuit CE1 is set to 5.69, and the width-to-length ratio of the pull-up transistor to the pull-down transistor of the first inverter D1 and the second inverter D2 is 0.92. In this embodiment, Area is used to measure the area overhead, and the calculation formula of Area is:

[0090]

[0091] Where n1 is the number of NMOS, L n MOS(i) and W n MOS(i) is the effective length and width of each NMOS transistor. Correspondingly, n2 is the number of PMOS, L p MOS(i) and W p MOS(i) is the effective length and width of each PMOS transistor. The memory cell design circuit of the present invention includes the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the first C unit circuit CE1, the second C unit circuit CE2, the first inverter D1 and the second inverter D2. After calculation, there are 8 PMOS and 8 NMOS in total. The total area can be calculated to be 8448nm 2 , the area is smaller, and the corresponding cost is also smaller.

[0092] As a preferred embodiment, it also includes:

[0093] The delay determination module is used to determine the write delay time from the time when the first read-write control signal WL and the second read-write control signal WLB form a preset read-write signal to the time when the output terminal Q of the first C unit circuit CE1 is stored as the level of the first bit signal BL and the output terminal QB of the second C unit circuit CE2 is stored as the level of the second bit signal BLN; and determine the read delay time from the time when the first read-write control signal WL and the second read-write control signal WLB form a preset read-write signal to the time when the level of the first bit signal BL and the level of the second bit signal BLN differ by a preset level.

[0094] The write delay of the memory cell design circuit represents the transmission delay from the first read / write control signal WL to the intersection of Q and QB, that is, the time when the level of the first read / write control signal WL is 0.5*Vdd to the time when the output terminal Q of the first C unit circuit CE1 is stored as the level of the first bit signal BL and the time when the output terminal QB of the second C unit circuit CE2 is stored as the level of the second bit signal BLN. This embodiment takes the write delay time of 1.69ps calculated by HSPICE simulation as an example.

[0095] The read delay of the memory cell design circuit represents the transmission delay from the first read / write control signal WL and the second read / write control signal WLB to the voltage difference of 100mV between the first bit signal BL and the second bit signal BLN, that is, the difference from the time when the level of the first read / write control signal WL is 0.5*Vdd to the time when the voltage difference of 100mV between the first bit signal BL and the second bit signal BLN occurs. This embodiment takes the read transmission delay of 12.69ps calculated by HSPICE simulation as an example.

[0096] It should be noted that when the voltage difference between the first bit signal BL and the second bit signal BLN is 100 mV, it can be determined that the levels of the first C unit circuit CE1 and the second C unit circuit CE2 can be read from the first bit signal BL and the second bit signal BLN through the sense amplifier.

[0097] In addition, it can be but not limited to that the first read / write control signal WL is at a high level and the second read / write control signal WLB is at a low level to form a preset read / write signal.

[0098] When WL=1, BL=1 and BLN=1, the high level state is stored at Q point, and the storage unit design circuit is in read 1 mode. Before WL is high, BL and BLN are precharged to high level. When WL=1, because QB point is low level, BLN drops due to charge sharing, while BL is still in high level state. When the level difference between BL and BLN is 100mV, the voltage difference can be detected and amplified by the sensitive amplifier to complete the read 1 operation.

[0099] When WL=1, BL=1 and BLN=1, the Q node stores a low level state, and the memory cell design circuit is in read 0 mode. Before WL is high, BL and BLN are precharged to a high level. When WL=1, because the Q point is low, BL drops due to charge sharing, while BLN remains high. When the level difference between BL and BLN is 100mV, it can be read out through the sensitive amplifier.

[0100] The power consumption of the memory cell design circuit calculated by simulation software is about 8.83nW, which is lower than the power consumption of the static random access memory cell that tolerates single node upset proposed under the same experimental conditions.

[0101] As a preferred embodiment, it also includes:

[0102] A noise margin determination module is used to inject a DC noise source into the output terminal Q of the first C unit circuit CE1 in a non-working storage unit design circuit to determine the first voltage change data of the output terminal QB of the second C unit circuit CE2, inject a DC noise source into the output terminal QB of the second C unit circuit CE2 in the non-working storage unit design circuit to determine the second voltage change data of the output terminal Q of the first C unit circuit CE1, and determine the static noise margin based on the first voltage change data and the second voltage change data; and in a data writing state, when storing a level in the output terminal Q of the first C unit circuit CE1 and the output terminal QB of the second C unit circuit CE2, respectively inject a DC noise source into the output terminal Q of the first C unit circuit CE1 and the output terminal Q of the second C unit circuit CE2, to determine the write static noise margin of the storage unit design circuit; when reading the level of the output terminal Q of the first C unit circuit CE1 and the output terminal QB of the second C unit circuit CE2, respectively inject a DC noise source into the output terminal Q of the first C unit circuit CE1 and the output terminal Q of the second C unit circuit CE2, to determine the read static noise margin of the storage unit design circuit.

[0103] Under the condition of realizing node flip recovery, the working stability of the memory cell design circuit must also be guaranteed. Usually, the static noise margin (SNM) measures the anti-interference ability of the memory cell design circuit. The static noise margin is defined as the maximum DC noise voltage that the memory cell design circuit can withstand, including the hold static noise margin (HSNM), write static noise margin (WSNM) and read static noise margin (RSNM). The larger the value, the better the stability of the memory cell design circuit.

[0104] Hold static noise margin (HSNM) measurement, that is, in the hold state of the memory cell design circuit, add a DC noise source to the two storage nodes (Q, QB) respectively, measure the waveform of the other node, and obtain the value of HSNM (for example, 136mV). The measurement of write static noise margin (WSNM) is similar to the measurement of read static noise margin (RSNM), adding noise sources in the read and write modes of the memory cell design circuit unit (for example, the value of WSNM is 671mV and the value of RSNM is 673mV).

[0105] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0106] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory cell design circuit, characterized in that: The invention comprises a first C unit circuit, a second C unit circuit, a first inverter, a second inverter, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; a first read-write control signal is input to the control end of the first switch tube and the control end of the second switch tube, a second read-write control signal is input to the control end of the third switch tube and the control end of the fourth switch tube, the first read-write control signal and the second read-write control signal are complementary, a first bit signal is input to the first end of the first switch tube and the third switch tube, and a second bit signal is connected to the output end of the first C unit circuit and the first input end of the second C unit circuit; a first bit signal is input to the second end of the second switch tube and the fourth switch tube, and a second bit signal is input to the second end of the second switch tube and the fourth switch tube; an input end of the first inverter is connected to the output end of the first C unit circuit, and an output end is connected to the first input end of the first C unit circuit; an input end of the second inverter is connected to the output end of the second C unit circuit, and an output end is connected to the second input end of the second C unit circuit; The first switch tube, the second switch tube, the third switch tube and the fourth switch tube are used to access the first signal and the second signal; The first C unit circuit and the second C unit circuit are used to output a level opposite to the level of their own input after a first delay time when the levels of their own first input terminal and second input terminal are the same, so as to save data, and present high impedance at their own output terminals when the levels of their own first input terminal and second input terminal are different; The first inverter and the second inverter are used to invert the level of their own input after a second delay time; The second delay time is less than the first delay time; When the first read-write control signal and the second read-write control signal constitute a preset read-write signal, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are turned on, the output end of the first C unit circuit is stored as the level of the first bit signal or is read through the first bit signal, and the output end of the second C unit circuit is stored as the level of the second bit signal or is read through the second bit signal.

2. The memory cell design circuit according to claim 1, wherein: The first C unit circuit or the second C unit circuit includes a first sub-switch tube, a second sub-switch tube, a third sub-switch tube and a fourth sub-switch tube; The first end of the first sub-switch tube is connected to a DC power supply, and the second end is connected to the first end of the second sub-switch tube; the second end of the second sub-switch tube is connected to the first end of the third sub-switch tube, the second end of the third sub-switch tube is connected to the first end of the fourth sub-switch tube, and the second end of the fourth sub-switch tube is grounded; The control ends of the first sub-switch tube and the third sub-switch tube are connected and serve as the first input end of the first C unit circuit or the second C unit circuit; the control ends of the second sub-switch tube and the fourth sub-switch tube are connected and serve as the second input end of the first C unit circuit or the second C unit circuit; the second end of the second sub-switch tube and the first end of the third sub-switch tube serve as the output end of the first C unit circuit or the second C unit circuit; The first sub-switch tube and the second sub-switch tube are used to be turned on when their control terminals are at a low level, and the third sub-switch tube and the fourth sub-switch tube are used to be turned on when their control terminals are at a high level, so that the first C unit circuit or the second C unit circuit outputs a level opposite to its own input level when the levels of its first input terminal and the second input terminal are the same, and presents a high impedance at its own output terminal when the levels of its first input terminal and the second input terminal are different.

3. The memory cell design circuit according to claim 2, wherein: The first sub-switch tube and the second sub-switch tube are PMOS, and the third sub-switch tube and the fourth sub-switch tube are NMOS.

4. The memory cell design circuit according to claim 2, wherein: The first C unit circuit is specifically used for storing the level of the first bit signal to its own output end when the first switch tube and the third switch tube are turned on and the levels of the first bit signal and the second bit signal are opposite, and for reading the level of its own output end through the first bit signal when the first switch tube and the third switch tube are turned on and the levels of the first bit signal and the second bit signal are the same; The second C unit circuit is specifically used to store the level of the second bit signal to its own output end when the second switch tube and the fourth switch tube are turned on and the levels of the first bit signal and the second bit signal are opposite, and to read the level of its own output end through the second bit signal when the second switch tube and the fourth switch tube are turned on and the levels of the first bit signal and the second bit signal are the same.

5. The memory cell design circuit according to claim 1, wherein: Also includes: An interference simulation verification device is used to inject a simulated interference current into the input node or output node of the first C unit circuit or the second C unit circuit to determine whether the input node or the output node of the first C unit circuit or the second C unit circuit undergoes a level flip and restores its original level when being subjected to the simulated interference current.

6. The memory cell design circuit according to claim 5, characterized in that: The interference simulation verification device is specifically used to inject the simulated interference current into the first input terminal, the second input terminal and the output terminal of the first C unit circuit, and any one of the first input terminal, the second input terminal and the output terminal of the second C unit circuit, so as to determine whether any node undergoes a level flip and restores its original level when being subjected to the simulated interference current.

7. The memory cell design circuit according to claim 5, characterized in that: The interference simulation verification device is specifically used to inject the simulated interference current into the first input terminal, the second input terminal and the output terminal of the first C unit circuit, and two nodes among the first input terminal, the second input terminal and the output terminal of the second C unit circuit, but not to inject the simulated interference current into the output terminal of the first C unit circuit and the output terminal of the second C unit circuit at the same time, so as to determine the situation in which the levels of the two nodes are flipped and restored to their original levels when they are affected by the simulated interference current.

8. The memory cell design circuit according to claim 1, wherein: Also includes: An area determination module is used to determine the total area of ​​the storage unit design circuit according to the areas of the first C unit circuit, the second C unit circuit, the first inverter, the second inverter, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube.

9. The memory cell design circuit according to claim 1, wherein: Also includes: A delay determination module is used to determine the write delay time from the time when the first read-write control signal and the second read-write control signal constitute a preset read-write signal to the time when the output end of the first C unit circuit is stored as the level of the first bit signal and the output end of the second C unit circuit is stored as the level of the second bit signal; and determine the read delay time from the time when the first read-write control signal and the second read-write control signal constitute a preset read-write signal to the time when the level of the first bit signal and the level of the second bit signal differ by a preset level.

10. The memory cell design circuit according to claim 1, wherein: Also includes: a noise margin determination module, configured to inject a DC noise source into an output terminal of the first C unit circuit in the storage unit design circuit in a non-working state to determine first voltage change data of an output terminal of the second C unit circuit, inject a DC noise source into an output terminal of the second C unit circuit in the storage unit design circuit in a non-working state to determine second voltage change data of the output terminal of the first C unit circuit, and determine a static noise margin based on the first voltage change data and the second voltage change data; and injecting the DC noise source into the output end of the first C unit circuit and the output end of the second C unit circuit respectively when storing levels into the output end of the first C unit circuit and the output end of the second C unit circuit, so as to determine the write static noise margin of the storage unit design circuit; The DC noise source is injected into the output end of the first C unit circuit and the output end of the second C unit circuit respectively when reading the levels of the output end of the first C unit circuit and the output end of the second C unit circuit to determine the read static noise margin of the storage unit design circuit.

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