Dynamic programming verification of voltage regulation for consistent charge loss within the block

Abstract

This application relates to dynamic programming verification voltage adjustment for consistent charge loss within a block. A threshold voltage distribution shift amount is determined. This threshold voltage distribution shift amount corresponds to the amount of time since the programming of a reference page of a block of a memory device. The programming verification voltage is adjusted based on the threshold voltage distribution shift amount to obtain an adjusted programming verification voltage. Using the adjusted programming verification voltage, subsequent pages of the block are programmed at a time corresponding to the amount of time since the programming of the reference page.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to dynamic programming verification (PV) voltage regulation for in-block storage charge loss (SCL) consistency. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to an aspect of this application, a system is provided. The system includes: a memory device; and a processing means operatively coupled to the memory device to perform operations including: determining a threshold voltage distribution shift amount corresponding to an amount of time following the programming of a reference page of a block of the memory device; adjusting a programming verification voltage based on the threshold voltage distribution shift amount to obtain an adjusted programming verification voltage; and using the adjusted programming verification voltage to program subsequent pages of the block at a time corresponding to the amount of time following the programming of the reference page.

[0004] According to another aspect of this application, a method is provided. The method includes: determining a threshold voltage distribution shift amount corresponding to a time amount following the programming of a reference page of a block of a memory device; adjusting a programming verification voltage based on the threshold voltage distribution shift amount to obtain an adjusted programming verification voltage; and using the adjusted programming verification voltage to program subsequent pages of the block at a time corresponding to the time amount following the programming of the reference page.

[0005] According to another aspect of this application, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to perform operations including: defining a metric derived from one or more parameters associated with a reference page of a block of a memory device; determining, based on the metric, a threshold voltage shift amount corresponding to a time amount following programming of the reference page; adjusting a programming verification voltage based on the threshold voltage shift amount to obtain an adjusted programming verification voltage; storing the adjusted programming verification voltage as programming data; and using the programming data to program subsequent pages of the block at a time corresponding to the time amount following programming of the reference page. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of a method for implementing dynamic programming verification (PV) voltage adjustment to ensure in-block storage charge loss (SCL) consistency according to some embodiments of the present disclosure.

[0009] Figure 3 This is a schematic diagram illustrating dynamic programming verification (PV) voltage adjustment based on the consistency of in-block storage charge loss (SCL) based on a metric corresponding to a reference page, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0011] This disclosure relates to dynamic programmable verification (PV) voltage regulation for in-block storage charge loss (SCL) consistency. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0012] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0013] A memory device may contain multiple bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and may contain a group of memory cells, a group of word lines, a word line, or a single memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device may contain circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device may contain corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types.

[0014] A memory cell can be programmed (written) by applying a voltage to it. This causes the charge to be retained by the memory cell, thus determining the voltage signal V that must be applied to the cell's control electrode to open the cell to inter-cell current between the source and drain electrodes. CG More specifically, for each individual memory cell (with a charge Q stored thereon), a threshold-controlled gate voltage V may exist. T (Also referred to herein as the “threshold voltage” or simply the “threshold”), such that for a given control gate voltage (V0), CG Below the threshold voltage, V CG <V T The source-drain current is low. Once the control gate voltage exceeds the threshold voltage, V CG >V T The current generally increases. Because the actual geometry of the electrodes and gate varies between cells, the threshold voltage can differ even for cells implemented on the same die. Therefore, a memory cell can be characterized as a distribution of threshold voltage P, P(Q,V). T )=dW / dV T , where dW represents the threshold voltage of any given cell in the interval [V] when charge Q is placed on the cell. T V T +dV T The probability within ] .

[0015] Memory devices may have a narrower distribution P(Q,V) compared to the operating range of the control voltages allowed by the cells of the device. T Therefore, multiple non-overlapping distributions P(Q) k V TThe valley line can be fitted to the operating range, allowing for the storage and reliable detection of multiple charge values ​​Q. k k = 1, 2, 3… The distribution (valley lines) is interspersed with voltage intervals (valley tolerances), in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, such valley tolerances can be used to separate various charge states Q. k --The corresponding threshold voltage V of the unit can be detected during the read operation. T The logic state of a cell is determined by which two valley tolerances it exists between. This effectively allows a single memory cell to store multiple bits of information: a memory cell with 2N-1 well-defined valley tolerances and 2N valley operations can reliably store N bits of information. Specifically, this can be achieved by comparing the measured threshold voltage V exhibited by the memory cell. T Read operations are performed with one or more reference voltage levels (read levels) corresponding to a known valley tolerance (e.g., the center of the tolerance) of the memory device.

[0016] Programming verification (PV) is an operation performed during the programming process to determine whether a memory cell is being programmed to its target memory state. However, a phenomenon observed in memory devices is storage charge loss (SCL), also referred to herein as time-voltage shift (TVS), where V... t The charge distribution shifts to the left as the charge decreases with time and / or temperature. That is, V t Distributed shifts can be proportional to the time elapsed during programming operations and can result in a shift of the PV voltage used to perform PV operations. Using SCL, if the programming of different pages within a block is spaced far apart in time, there may be varying degrees of V shift across these pages. t Distribution shift. Due to this inconsistency in V... t Shifting, without impacting performance, can make it difficult to determine the optimal set of read voltages available for most pages in a block. Choosing a suboptimal set of read voltages can lead to higher error handling trigger rates and performance issues. Furthermore, performing automatic calibration for each page read can increase read latency.

[0017] This disclosure addresses the aforementioned and other deficiencies by implementing a memory subsystem that dynamically adjusts the PV voltage for intra-block SCL consistency by actively adjusting a reference PV voltage determined for a (programmed) reference page within the block. The reference page is the first page in the block to be programmed in time relative to other pages in the block, and in some cases, it may be the absolutely first programmed page in the block (i.e., the oldest or first programmed page in the block). The reference page may be a single page or may be contained within a block of page groups.

[0018] More specifically, the memory subsystem can determine (e.g., estimate) the reference V of the reference page.t V distributed over a given amount of time after the reference page programming t Distributed displacement. V t The distributed shift can be determined based on a (quantifiable) metric derived from one or more parameters associated with the reference page. As will be described in further detail herein, the metric can be derived from one or more parameters, including the read sense current, the minimum read voltage, and the time elapsed since the start of programming of the reference page.

[0019] Then, you can use V t The distribution shift amount determines the PV voltage change (relative to a reference PV voltage). Based on this PV voltage change, an adjusted PV voltage is obtained, which can be stored along with other programming metadata and subsequently used to perform PV operations (i.e., real-time PV voltage adjustment) during programming of another page of the block at a given time. The adjusted PV voltage will be the V of the page programmed at a given time. t Distribution and Reference V t Distribution alignment. A similar process can be used to determine additional adjusted PV voltages that can be used to perform PV operations during the programming of additional pages of the block at various times after the programming of the reference page. Therefore, V can be considered by obtaining the adjusted PV voltage of each page in the block that will be programmed after the reference page. t Distributed shifting is used to achieve SCL consistency within a block.

[0020] For example, consider a three-level cell (TLC) memory where each memory cell stores three bits of information, resulting in a total of eight states. A new or updated PV voltage can be obtained by subtracting the old or previous PV voltage from the base shift voltage. More specifically, the base shift voltage can be modulated or adjusted based on a correction factor associated with the corresponding state. For example:

[0021]

[0022]

[0023] …

[0024]

[0025] in, It is the new PV voltage calculated for the i-th state. This is the old PV voltage calculated for the i-th state. This corresponds to the shift measured in state 7, and cfi is the correction factor for state i. For example, cf7 can be 1.0 and cf6 can be 0.8. The correction factor can be obtained through experimental experience and can remain constant throughout the entire lifespan of the memory device.

[0026] The V described in this article t Distributed shifting and PV voltage measurement and adjustment can be implemented at the system level. For example, assuming the system is an SSD, if the SSD's controller / firmware is measuring and adjusting the PV of the individual SSD NAND flash units, the measurement and adjustment can be implemented within the SSD. If the time elapsed between the last write and the current write is short, the SSD can choose to skip the measurement and adjustment.

[0027] Alternatively, the V described in this article t Distributed shifting and PV voltage measurement and adjustment can be implemented at the component level. For example, again assuming the memory device is an SSD, the NAND of an SSD with its own controller / firmware can perform measurements and adjustments independently during write attempts. This component-level implementation is transparent to the system (e.g., the SSD).

[0028] According to the embodiments described herein, the method can be implemented with any suitable memory device architecture. In one embodiment, the method can be implemented with a memory device that implements Replacement Gate NAND (RG NAND) technology. A Replacement Gate (RG) NAND device is a NAND device that implements an RG architecture instead of a Floating Gate (FG) architecture. The RG NAND architecture eliminates the cell gaps common in the FG NAND architecture, thereby reducing or eliminating the capacitance generated by these cell gaps. More specifically, the RG NAND architecture corresponds to a single insulator structure. Compared to the FG NAND architecture, the RG NAND architecture can achieve smaller size, improved read and write latency, and higher transfer rates.

[0029] The advantages of this disclosure include, but are not limited to, improved scalability and minimized write amplification. Improved scalability is achieved by simplifying the determination of a single optimized set of read voltage levels, which reduces the amount of system memory required to track partitions within a block. Write amplification is minimized because blocks do not need to be abandoned to maintain consistency after a certain time limit. Furthermore, a single set of read blocks can be used optimally.

[0030] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing power.

[0033] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0034] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0035] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is shown as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0036] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 may contain one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may contain an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0039] While non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0040] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] The memory subsystem controller 115 may include a processing device comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0042] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0043] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] The memory subsystem 110 includes a programming verification (PV) component 113 that enables dynamic PV voltage adjustment to implement in-block storage charge loss (SCL) consistency. The PV component 113 can determine (e.g., estimate) at least one V corresponding to at least one time amount after programming a reference page of the block (e.g., the oldest or first programmed page). t Distribution shift amount. In some embodiments, the PV component 113 derives (quantifiable) a metric from one or more parameters associated with the reference page and determines V based on the metric. t Distribution shift. More specifically, the metric can be derived from one or more parameters, including the read sense current, minimum read voltage, and the time elapsed since programming began on the reference page.

[0047] PV component 113 can be based on V t The PV voltage is adjusted by distributing the shift amount to obtain an adjusted PV voltage. More specifically, the PV module 113 can be based on V... t The distributed shift amount determines the amount of PV voltage change relative to the reference PV voltage corresponding to the reference page, and the adjusted PV voltage is obtained by modifying the reference PV voltage based on the PV voltage change. PV component 113 can store the adjusted PV voltage as programming metadata. Then, PV component 113 can use the programming metadata to program the page of the block at a time corresponding to the time after the programming of the reference page.

[0048] PV component 113 can implement a similar process to determine additional adjusted PV voltages that can be used to perform PV operations during the programming of additional pages in the block at various times after the programming of the reference page. Therefore, by aligning the reference page with subsequently programmed pages within the block, PV component 113 can implement V on the block. t Consistency. Therefore, V can be taken into account by obtaining the adjusted PV voltage of each page in the block that will be programmed after the reference page. tDistributed shifting is used to achieve SCL consistency within a block. V can be determined at the system level or component level. t Distributed shifting and PV voltage adjustment.

[0049] For example, consider a three-level cell (TLC) memory where each memory cell stores three bits of information, resulting in a total of eight states. A new or updated PV voltage can be obtained by subtracting the old or previous PV voltage from the base shift voltage. More specifically, the base shift voltage can be modulated or adjusted based on a correction factor associated with the corresponding state. For example:

[0050]

[0051]

[0052] …

[0053]

[0054] in, It is the new PV voltage calculated for the i-th state. This is the old PV voltage calculated for the i-th state. Corresponding to the shift measured in state 7, and cf i This is the correction factor for the i-th state. For example, cf7 can be 1.0 and cf6 can be 0.8. The correction factor can be obtained through experimental experience and can remain constant throughout the entire lifespan of the memory device.

[0055] In some embodiments, the memory subsystem controller 115 includes at least a portion of the PV component 113. In some embodiments, the PV component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the PV component 113 and is configured to perform the functions described herein.

[0056] The following text is for reference only. Figure 2 and 3 Further details regarding the operation of PV component 113 are described.

[0057] Figure 2 This is a flowchart of an example method 200 for implementing dynamic programmable verification (PV) voltage adjustment to achieve in-block storage charge loss (SCL) consistency according to some embodiments of this disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1The PV component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0058] In operation 210, the processing logic determines at least one threshold voltage (V) corresponding to at least one time amount following the programming of a reference page of a block of the memory device. t Distributed shift amount. The reference page can be a single page or it can be contained in a page block. In one embodiment, the memory device is an RG NAND device.

[0059] More specifically, the reference page is the first time-programmed page of the block. The term "first time-programmed" should be interpreted herein as referring to a relative time relationship compared to an absolute time relationship. That is, the first time-programmed page of the block is the earliest-programmed page in a particular group of pages. Subsequent time-programmed pages of the block are, or will be, pages programmed at a time after the first time-programmed page. For example, the first time-programmed page of the block can be represented as P. m And each subsequent page in the block can be represented as P. m+1 P m+2 ..., where m is a positive integer. However, in one embodiment, the reference page is the first programmed page of the entire block (i.e., P1).

[0060] In some embodiments, determine V t The shift involves determining V based on a metric corresponding to at least one reference page. t Shift amount. More specifically, the measure may correspond to V of at least one reference page. t Determine V t The shift can further include a limiting metric.

[0061] For example, a limiting metric could include a metric derived from the read sense current. As another example, a limiting metric could include a metric derived from the minimum read voltage. As yet another example, a limiting metric could include a metric derived from the time elapsed since programming began on the reference page.

[0062] In operation 220, the processing logic is based on V. t The distributed shift amount adjusts the PV voltage to obtain an adjusted PV voltage. More specifically, the adjusted PV voltage is a pre-characterized PV voltage that will be used to program the block's pages at a time after the programming of the reference page.

[0063] For example, consider a three-level cell (TLC) memory where each memory cell stores three bits of information, resulting in a total of eight states. A new or updated PV voltage can be obtained by subtracting the old or previous PV voltage from the base shift voltage. More specifically, the base shift voltage can be modulated or adjusted based on a correction factor associated with the corresponding state. For example:

[0064]

[0065]

[0066] …

[0067]

[0068] in, It is the new PV voltage calculated for the i-th state. This is the old PV voltage calculated for the i-th state. Corresponding to the shift measured in state 7, and cf i This is the correction factor for the i-th state. For example, cf7 can be 1.0 and cf6 can be 0.8. The correction factor can be obtained through experimental experience and can remain constant throughout the entire lifespan of the memory device.

[0069] In operation 230, the adjusted PV voltage is stored as programming data. The programming data may further include any data (e.g., metadata) that can be used during page programming.

[0070] In operation 240, the processing logic uses programming data to program subsequent pages on the time frame of the block, corresponding to the time amount after the reference page is programmed. More specifically, an adjusted PV voltage is used to perform PV operations during programming. The adjusted PV voltage takes into account the VL caused by the SCL between the time when programming the reference page and the time when programming subsequent pages on the time frame. t Distribution shift.

[0071] The following will refer to Figure 3 Describe further details regarding operations 210-230.

[0072] Figure 3 Schematic diagram 300 is shown, illustrating an example of dynamic programming verification of in-block storage charge loss (SCL) consistency. More specifically, as will be described in further detail below, schematic diagram 300 illustrates a verification based on V from the reference page. t The corresponding metric is the single threshold voltage (V). t Voltage and Programming Verification (PV) Voltage Changes Over Time.

[0073] Multiple graphs are shown, each corresponding to a specific page of the block. More specifically, graph 310-1 corresponds to the first page of the block, which is a reference page used as the basis for PV voltage variations; graph 310-2 corresponds to the second page of the block, which is a subsequent page at the first time; graph 310-3 corresponds to the third page of the block, which is a subsequent page at the second time; and graph 310-4 corresponds to the fourth page of the block, which is a subsequent page at the third time.

[0074] As shown in curve 310-1, at programming time t1, corresponding to the first V t The first page is programmed at the first PV voltage (PV1) of distribution 312-1. After time n1, due to SCL, the first distribution 312-1 is shifted left by a first amount, and a second PV voltage (PV2) is determined, corresponding to the second distribution 312-2 of the page to be programmed at time t2 = t1 + n1. Continuing this process, after time n2, due to SCL, the second distribution 312-2 is shifted left by a second amount, and a third PV voltage (PV3) is determined, corresponding to the third distribution 312-3 of the page to be programmed at time t3 = t2 + n2. Then, after time n3, due to SCL, the third distribution 312-3 is shifted left by a third amount, and a fourth PV voltage (PV4) is determined, corresponding to the fourth distribution 312-4 of the page to be programmed at time t4 = t3 + n3. The shift amount may not be linear on a linear time scale. In some embodiments, the shift amount is linear on a logarithmic time scale. Therefore, the PV voltage can be actively adjusted based on the reference PV voltage to take into account V during subsequent page programming. t Displacement over time.

[0075] To handle V during subsequent page programming t A shifting operation applies each of the pre-characterized PV voltages shown in curve 310-1 to the corresponding one in the new page being programmed, producing a distribution close to that of the first page. The larger line weights of the distributions in curves 310-1, 310-2, 310-3, and 310-4 (312-1, 312-2, 312-3, and 312-4) indicate the application of PV1, PV2, PV3, and PV4 to the first, second, third, and fourth pages, respectively, during programming.

[0076] As referenced above Figure 1-2 The description can be based on V on the first (reference) page. tThe PV voltage is actively adjusted based on a corresponding metric in the distribution. The amount of shift between each of the distributions can be determined based on any suitable metric. One suitable metric is elapsed time, where the shift can be estimated based on the corresponding elapsed times n1 to n3. For example, the shift over time can be determined by using a table showing the relationship between elapsed time and the shift, etc. Another suitable metric is to directly measure the change seen on the first page after a certain time. For example, if x is the shift measured after n1, then during the programming of the second page, PV2 will be PV1-x.

[0077] Figure 4 An example machine of computer system 400 is shown, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 400 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 The host system (e.g., memory subsystem 110) of the memory subsystem 110 Figure 1 The host system 120, or a system that can be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of PV component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0078] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although indicated as a single machine, the term "machine" should also be considered to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methods discussed herein.

[0079] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0080] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 to perform the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 communicating via network 420.

[0081] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) on which one or more sets of instructions 426 or software embodying any one or more methods or functions described herein are stored. The instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution by computer system 400, the main memory 404 and processing device 402 also constituting machine-readable storage medium. Machine-readable storage medium 424, data storage system 418 and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0082] In one embodiment, instruction 426 includes instructions for implementing a component corresponding to a PV component (e.g., Figure 1 The machine-readable storage medium 424 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0083] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this paper, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0084] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0085] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0087] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0088] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory sub-system comprising: a memory device; and a processing device operatively coupled with the memory device to perform operations comprising: determining a threshold voltage distribution shift amount corresponding to an amount of time after programming of a reference page of a block of the memory device; obtaining a set of correction factors, each correction factor of the set of correction factors corresponding to a respective memory cell state of a set of memory cell states associated with the block, wherein each memory cell state of the set of memory cell states is associated with a respective program verify voltage; for each memory cell state of the set of memory cell states, obtaining a respective adjustment value defined based on the threshold voltage distribution shift amount multiplied by the correction factor for the memory cell state; for each memory cell state of the set of memory cell states, obtaining a respective adjusted program verify voltage by subtracting the respective adjustment value from the respective program verify voltage; and programming a subsequent page of the block relative to the reference page using the adjusted program verify voltages.

2. The memory sub-system of claim 1, wherein the reference page is a first programmed page in time relative to the subsequent page, the subsequent page being relative to the reference page.

3. The memory sub-system of claim 2, wherein the reference page is an absolute first programmed page of the block.

4. The memory sub-system of claim 1, wherein determining the threshold voltage distribution shift amount further comprises defining a metric derived from one or more parameters related to the reference page.

5. The memory sub-system of claim 4, wherein defining the metric further comprises deriving the metric from a read sense current.

6. The memory sub-system of claim 4, wherein defining the metric further comprises deriving the metric from a minimum read voltage.

7. The memory sub-system of claim 4, wherein defining the metric further comprises deriving the metric from a time elapsed since programming of the reference page.

8. A method for a memory device comprising: determining, by a processing device, a threshold voltage distribution shift amount corresponding to an amount of time after programming of a reference page of a block of a memory device; obtaining, by the processing device, a set of correction factors, each correction factor of the set of correction factors corresponding to a respective memory cell state of a set of memory cell states associated with the block, wherein each memory cell state of the set of memory cell states is associated with a respective program verify voltage; for each memory cell state of the set of memory cell states, obtaining, by the processing device, a respective adjustment value defined based on the threshold voltage distribution shift amount multiplied by the correction factor for the memory cell state; for each memory cell state of the set of memory cell states, obtaining a respective adjusted program verify voltage by subtracting the respective adjustment value from the respective program verify voltage; and programming a subsequent page of the block relative to the reference page using the adjusted program verify voltages. for each memory cell state of the set of memory cell states, obtaining, via the processing device, a respective adjusted program verify voltage by subtracting the respective adjustment value from the respective program verify voltage; and programming, using the adjusted program verify voltages, subsequent pages of the block relative to the reference page.

9. The method of claim 8, wherein the reference page is a temporally first programmed page relative to the subsequent pages, the subsequent pages being relative to the reference page.

10. The method of claim 9, wherein the reference page is an absolute first programmed page of the block.

11. The method of claim 8, wherein determining the threshold voltage distribution shift amount further comprises defining a metric derived from one or more parameters related to the reference page.

12. The method of claim 11, wherein defining the metric further comprises deriving the metric from a read sense current.

13. The method of claim 11, wherein defining the metric further comprises deriving the metric from a minimum read voltage.

14. The method of claim 11, wherein defining the metric further comprises deriving the metric from an elapsed time since programming of the reference page.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: defining a metric derived from one or more parameters related to a reference page of a block of a memory device; based on the metric, determining a threshold voltage shift amount corresponding to an amount of time subsequent to programming of the reference page; obtaining a set of correction factors, each correction factor of the set of correction factors corresponding to a respective memory cell state of a set of memory cell states associated with the block, wherein each memory cell state of the set of memory cell states is associated with a respective program verify voltage; for each memory cell state of the set of memory cell states, obtaining a respective adjustment value defined based on the threshold voltage distribution shift amount multiplied by the correction factor for the memory cell state; for each memory cell state of the set of memory cell states, obtaining a respective adjusted program verify voltage by subtracting the respective adjustment value from the respective program verify voltage; storing the adjusted program verify voltages as program data; and programming, using the program data, subsequent pages of the block relative to the reference page.

16. The non-transitory computer-readable storage medium of claim 15, wherein the reference page is a temporally first programmed page relative to the subsequent pages, the subsequent pages being relative to the reference page.

17. The non-transitory computer-readable storage medium of claim 16, wherein the reference page is an absolute first programmed page of the block.

18. The non-transitory computer readable storage medium of claim 15, wherein defining the metric further comprises deriving the metric from a read sense current.

19. The non-transitory computer readable storage medium of claim 15, wherein defining the metric further comprises deriving the metric from a minimum read voltage.

20. The non-transitory computer readable storage medium of claim 15, wherein defining the metric further comprises deriving the metric from a time elapsed since a start of programming of the reference page.

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