Memory test circuit

Abstract

The present invention discloses a test circuit for testing a memory, wherein an input end of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit comprises a first test register group, a second test register group, a first multiplexer, and a plurality of second multiplexers. The first test register group comprises at least one test register. The second test register group comprises at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexer is coupled between the second test register group and the register.

Description

Technical Field

[0001] The present invention relates to memory, and in particular to memory testing. Background Art

[0002] A chip with a specific function (such as a system on a chip (SoC)) usually includes logic circuits, function registers, and memory. Function registers refer to registers that are used by the chip during normal operation (such as when executing the specific function). The tests performed on the chip before it leaves the factory generally include scan testing and memory built-in self-test (MBIST), but both tests cannot test delay faults and stuck-at faults on the path between the function register and the memory. In order to test these two faults, the traditional method is to use random access memory (RAM) sequential automatic test pattern generation (ATPG) tools to generate test patterns, and then use the test patterns to read and write the memory through the scan chain for multiple cycles. However, since the scan chain contains many logic circuits, the generation of test patterns for multiple cycles has a high computational complexity for ATPG, which affects the controllability of ATPG over the memory, resulting in problems such as a long time required to generate test patterns, a large number of test patterns, and low test coverage. Summary of the invention

[0003] In view of the deficiencies of the prior art, an object of the present invention is to provide a memory test circuit to improve the deficiencies of the prior art.

[0004] The present invention discloses a test circuit for testing a memory, wherein an input end of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit comprises a first test register group, a second test register group, a first multiplexer, and a plurality of second multiplexers. The first test register group comprises at least one test register. The second test register group comprises at least one test register. The first multiplexer is coupled between the first test register group and the register. The plurality of second multiplexers are coupled between the second test register group and the register.

[0005] The features, implementations and effects of the present invention will be described in detail as follows with reference to the accompanying drawings and in conjunction with embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1Shown are a memory, a logic circuit, a function register, an MBIST circuit, an MBIST register and a test circuit of the present invention inside a chip;

[0007] Figure 2A and Figure 2B is a circuit diagram showing an embodiment of a test circuit of the present invention;

[0008] Figure 3A and Figure 3B is a circuit diagram showing another embodiment of the test circuit of the present invention;

[0009] Figure 4A and Figure 4B is a circuit diagram showing another embodiment of the test circuit of the present invention; and

[0010] Figure 5A and Figure 5B A circuit diagram showing another embodiment of the test circuit of the present invention. DETAILED DESCRIPTION

[0011] The technical terms used in the following description refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0012] The disclosure of the present invention includes a memory test circuit. Since some components included in the memory test circuit of the present invention may be known components individually, the following description will omit the details of the known components without affecting the full disclosure and feasibility of the device invention.

[0013] Figure 1 The memory, logic circuit, function register, MBIST circuit, MBIST register and the test circuit of the present invention inside the chip are shown, wherein register 110, register 140 and register 170 are function registers, and register 190 is an MBIST register. The test circuit 130 is coupled between the logic circuit 120 and the register 140, and is coupled to the memory 160 through the register 140 and the multiplexer 150. The input end of the register 110 and the output end of the register 170 are coupled to other logic circuits or function registers in the chip (not shown in the figure). In the present disclosure, the register is implemented with a scan D flip-flop, but is not limited to this.

[0014] In the MBIST mode, a control circuit (not shown) inside or outside the chip controls the multiplexer 150 to select the MBIST circuit 180 with a mode control signal BIST_MODE, and obtains the output of the memory 160 through the register 190 .

[0015] In the normal operation mode of the chip, the control circuit controls the multiplexer 150 to select the register 140 instead of the MBIST circuit 180, and controls the test circuit 130 to output the output of the logic circuit 120 (i.e., the function signal SF) instead of the test signal (including the write enable signal WE, the memory address ADDR and the test data DI, which will be described in detail below) with the mode control signal MSM_MODE.

[0016] In the interface test mode (used to test the aforementioned delay faults, stuck-at faults or other faults existing on the path between the functional registers (i.e., registers 140 and 170) and the memory 160), the control circuit controls the multiplexer 150 to select the register 140 instead of the MBIST circuit 180, and controls the test circuit 130 to output a test signal instead of the functional signal SF.

[0017] In some embodiments, the test circuit 130 is electrically connected to the register 140 ; ​​in other words, the test circuit 130 is directly connected to the register 140 , and no other circuits (including but not limited to logic circuits and registers) exist between the two.

[0018] Figure 2A and Figure 2B 1 is a circuit diagram showing an embodiment of a test circuit of the present invention, which is used to test delay faults on the path between the functional registers (ie, registers 140 and 170) and the memory 160. Figure 2A and Figure 2B In the embodiment of the present invention, the test circuit 130 includes a first test register group 210, a multiplexer 220, a second test register group 260, and a multiplexer group 270. The first test register group 210 includes a test register 212, a test register 214, a test register 216, and a test register 218. The second test register group 260 includes a test register 262, a test register 264, a test register 266, and a test register 268. The multiplexer group 270 includes n+1 multiplexers 275 (i.e., multiplexer 275_0, multiplexer 275_1, ..., multiplexer 275_n, where n is a positive integer).

[0019] Please refer to Figure 2A , Figure 2AThe circuit is used to output a write enable signal WE. When the write enable signal WE is at a first level (e.g., a high level) or a first logic (e.g., logic 1), data can be written into the memory 160; when the write enable signal WE is at a second level (e.g., a low level) or a second logic (e.g., logic 0), the memory 160 can only be read. The test register 212, the test register 214, the test register 216, and the test register 218 are electrically connected in sequence (i.e., the input terminal D of the test register 212 is electrically connected to the output terminal Q of the test register 214, the input terminal D of the test register 214 is electrically connected to the output terminal Q of the test register 216, and the input terminal D of the test register 216 is electrically connected to the output terminal Q of the test register 218), so the bit value Y is transmitted in sequence in the four test registers. If the test registers 212, 214, 216, and 218 are rising edge triggered and store the bit values ​​Y1, Y2, Y3, and Y4 in sequence at a certain moment, the first test register group 210 will output the bit values ​​Y1, Y2, Y3, and Y4 in sequence as the write enable signal WE at the next four consecutive rising edges of the clock CLK. The multiplexer 220 is coupled between the first test register group 210 and the register 140, and is used to select the function signal SF or the output of the first test register group 210 according to the mode control signal MSM_MODE.

[0020] Please refer to Figure 2B , Figure 2B The circuit is used to output the test data DI and / or the memory address ADDR. The test register 262, the test register 264, the test register 266 and the test register 268 are electrically connected in sequence, so the bit value Z is transmitted in sequence in the four test registers. The multiplexer group 270 is coupled between the second test register group 260 and the register 140, and is used to select the function signal SF or the output of the second test register group 260 according to the mode control signal MSM_MODE. When the mode control signal MSM_MODE controls the multiplexer group 270 to select the output of the second test register group 260, the output values ​​of the multiplexers 275_0, 275_1, ..., and 275_n (i.e., the bit values ​​B0, B1, ..., Bn, respectively) are all equal to the output of the test register 262. In other words, the multiplexer group 270 outputs the output of the second test register group 260 to the corresponding pins (i.e., data pins and / or address pins) of the memory 160 by broadcasting.

[0021] In some embodiments, the bit value Y and the bit value Z may be generated by the aforementioned control circuit (not shown) located inside or outside the chip. In other words, the test circuit 130 may be set or controlled by the control circuit. For example, under scan testing, the values ​​of the test registers 212-218 and the values ​​of the test registers 262-268 may be directly controlled to logic 0 or logic 1 through a scan chain in a load phase.

[0022] When the control circuit tests the delay fault of the memory 160 , the test signals (ie, the write enable signal WE, the test data DI and the memory address ADDR) received by the memory 160 are as shown in Table 1 below.

[0023] Table 1:

[0024]

[0025] During cycle T1, the test circuit 130 outputs a write enable signal WE=1, outputs a memory address ADDR=a first address, and outputs test data DI=a first value (i.e., the control circuit writes a first value at the first address of the memory 160); during cycle T2, the test circuit 130 outputs a write enable signal WE=1, outputs a memory address ADDR=a second address, and outputs test data DI=a second value (i.e., the control circuit writes a second value at the second address of the memory 160, wherein the second address is not equal to the first address, and the second value is not equal to the first value); during cycle T3, the test circuit 130 outputs a write enable signal WE=0, and outputs a memory address ADDR=a first address (i.e., the control circuit reads the data stored at the first address of the memory 160, and the test data DI can be any value at this time); during cycle T4, the test circuit 130 outputs a write enable signal WE=0, and outputs a memory address ADDR=a second address (i.e., the control circuit reads the data stored at the second address of the memory 160, and the test data DI can be any value at this time). If there is no delay fault, the data read by the control circuit in the first and second read operations should present the first value and the second value respectively. However, if there is a delay fault, at least one bit of the data read by the control circuit the second time presents an erroneous value. The periods T1, T2, T3 and T4 are four consecutive periods of the clock CLK.

[0026] In some embodiments, the contents of the memory address ADDR and the test data DI in the above Table 1 are as shown in Table 2 or Table 3 below.

[0027] Table 2:

[0028]

[0029] Table 3:

[0030]

[0031] In other words, the first address in Table 1 may be one of the maximum address of the memory 160 (i.e., all bits of the memory address ADDR are 1, as shown in Table 2) and the minimum address (i.e., all bits of the memory address ADDR are 0, as shown in Table 3), and the second address is the other. The first value in Table 1 may be one of the maximum value of the test data DI (i.e., all bits of the test data DI are 1, as shown in Table 2) and the minimum value of the test data DI (i.e., all bits of the test data DI are 0, as shown in Table 3), and the second value is the other. In this way, when there is no delay fault in the circuit, the control circuit observes that the output of the register 190 undergoes a level conversion (i.e., from logic 1 (or high level) to logic 0 (or low level), or vice versa).

[0032] According to the embodiments of Table 2 or Table 3, at a certain moment during the test, the test register 212, the test register 214, the test register 216 and the test register 218 store the bit value Y1, the bit value Y2, the bit value Y3 and the bit value Y4 respectively, wherein the bit value Y1 and the bit value Y2 correspond to a write operation (e.g., Y1=Y2=1), and the bit value Y3 and the bit value Y4 correspond to a read operation (e.g., Y3=Y4=0).

[0033] According to the embodiment of Table 2 or Table 3, at a certain moment during the test, the test register 262, the test register 264, the test register 266 and the test register 268 store the bit value Z1, the bit value Z2, the bit value Z3 and the bit value Z4 respectively, wherein the bit value Z1 and the bit value Z3 correspond to the first address and / or the first value (for example, Z1=Z3=1 (as shown in Table 2), or Z1=Z3=0 (as shown in Table 3)), and the bit value Z2 and the bit value Z4 correspond to the second address and / or the second value (for example, Z2=Z4=0 (as shown in Table 2), or Z2=Z4=1 (as shown in Table 3)). Because the first address is not equal to the second address and the first value is not equal to the second value, the bit value Z1 is not equal to the bit value Z2, and the bit value Z3 is not equal to the bit value Z4.

[0034] According to the embodiments of Table 2 or Table 3, Figure 2BThe circuit can be used to output the memory address ADDR and / or the test data DI. More specifically, the content of a set of digital codes B (i.e., B0:Bn) output by the multiplexer group 270 is n+1 bit values ​​1 or n+1 bit values ​​0, and the memory address ADDR is equal to the set of digital codes B (i.e., the length of the memory address ADDR is equal to n+1 bits), or a part of the set of digital codes B (i.e., the length of the memory address ADDR is less than n+1 bits), and / or the test data DI is equal to the set of digital codes B (i.e., the length of the test data DI is equal to n+1 bits), or a part of the set of digital codes B (i.e., the length of the test data DI is less than n+1 bits).

[0035] Figure 3A and Figure 3B 1 is a circuit diagram showing another embodiment of the test circuit of the present invention, which is used to test the delay fault of the memory 160. Figure 3A and Figure 3B In the embodiment of the present invention, the test circuit 130 includes a first test register group 310, a multiplexer 320, an inverter 330, a second test register group 360, a multiplexer group 370, and an inverter 380. The first test register group 310 includes a test register 312 and a test register 314. The second test register group 360 includes a test register 362. The multiplexer group 370 includes n+1 multiplexers 375 (i.e., multiplexer 375_0, multiplexer 375_1, ..., multiplexer 375_n, where n is a positive integer).

[0036] Please refer to Figure 3A , Figure 3A The circuit is used to output a write enable signal WE. The test register 312 is electrically connected to the test register 314. The multiplexer 320 is coupled between the first test register group 310 and the register 140, and is used to select the function signal SF or the output of the first test register group 310 according to the mode control signal MSM_MODE. The inverter 330 is coupled between the test register 312 and the test register 314; more specifically, the input end of the inverter 330 is coupled to the output end Q of the test register 312, and the output end of the inverter 330 is coupled to the input end D of the test register 314. The test register 312 and the test register 314 store the bit values ​​Y1 and Y2 respectively at a certain moment during the test period. Therefore, the first test register group 310 will output the bit values ​​Y1, Y2, and in and are the inverted logic of Y1 and Y2 respectively. Thus, the combination of the first test register group 310 and the inverter 330 can output the write enable signal WE of Table 1, Table 2 or Table 3 (ie, when Y1=Y2=1). In other words, Figure 3A The circuit is Figure 2A The simplified circuit occupies a smaller circuit area.

[0037] Please refer to Figure 3B , Figure 3B The circuit is used to output the test data DI and / or the memory address ADDR. The multiplexer group 370 is coupled between the second test register group 360 and the register 140, and is used to select the function signal SF or the output of the second test register group 360 according to the mode control signal MSM_MODE. The input end of the inverter 380 is coupled to the output end Q of the test register 362, and the output end of the inverter 380 is coupled to the input end D of the test register 362. The test register 362 stores the bit value Z1 at a certain moment during the test, so the second test register group 360 will output the bit values ​​Z1, Z1 and in is the inverted logic of Z1. Thus, the combination of the second test register group 360 and the inverter 380 can output the memory address ADDR and / or the test data DI of Table 2 or Table 3 (for Table 2, Z=1, and for Table 3, Z=0). In other words, Figure 3B The circuit is Figure 2B The simplified circuit occupies a smaller circuit area.

[0038] Figure 4A and Figure 4B 1 is a circuit diagram showing another embodiment of the test circuit of the present invention, which is used to test a stuck-at fault on the path between the functional registers (ie, register 140 and register 170) and the memory 160. Figure 4A and Figure 4B In the embodiment of the present invention, the test circuit 130 includes a first test register group 410, a multiplexer 420, a second test register group 460, and a multiplexer group 470. The first test register group 410 includes a test register 412 and a test register 414. The second test register group 460 includes a test register 462 and a test register 464. The multiplexer group 470 includes n+1 multiplexers 475 (i.e., multiplexer 475_0, multiplexer 475_1, ..., multiplexer 475_n, where n is a positive integer).

[0039] Please refer to Figure 4A , Figure 4AThe circuit is used to output the write enable signal WE. The test register 412 is electrically connected to the test register 414. The multiplexer 420 is coupled between the first test register group 410 and the register 140, and is used to select the function signal SF or the output of the first test register group 410 according to the mode control signal MSM_MODE.

[0040] Please refer to Figure 4B , Figure 4B The circuit is used to output the test data DI and / or the memory address ADDR. The test register 462 is electrically connected to the test register 464. The multiplexer group 470 is coupled between the second test register group 460 and the register 140, and is used to select the function signal SF or the output of the second test register group 460 according to the mode control signal MSM_MODE.

[0041] When the control circuit tests a stuck-at fault on the path between the function registers (ie, registers 140 and 170 ) and the memory 160 , the write enable signal WE, test data DI and memory address ADDR received by the memory 160 are as shown in Table 4 below.

[0042] Table 4:

[0043]

[0044] During cycle T1, the test circuit 130 outputs a write enable signal WE=1, outputs a memory address ADDR=first address, and outputs test data DI=first value (i.e., the control circuit writes the first value at the first address of the memory 160); during cycle T2, the test circuit 130 outputs a write enable signal WE=0, and outputs a memory address ADDR=first address (i.e., the control circuit reads the data stored at the first address of the memory 160). If there is no stuck-at fault, the data read by the control circuit should present the first value. However, if there is a stuck-at fault, at least one bit of the data read by the control circuit presents an erroneous value. Cycles T1 and T2 are two consecutive cycles of the clock CLK.

[0045] In some embodiments, the contents of the memory address ADDR and the test data DI in the above Table 4 are as shown in Table 5 or Table 6 below.

[0046] Table 5:

[0047]

[0048]

[0049] Table 6:

[0050]

[0051] In other words, the first address in Table 4 can be the maximum address (as shown in Table 5) or the minimum address (as shown in Table 6) of the memory 160, and the first value in Table 4 can be the maximum value of the test data DI (as shown in Table 5) or the minimum value of the test data DI (as shown in Table 6).

[0052] According to the embodiments of Table 5 or Table 6, at a certain time during the test, the test register 412 and the test register 414 store the bit value Y1 and the bit value Y2 respectively, where the bit value Y1 corresponds to a write operation (e.g., Y1=1) and the bit value Y2 corresponds to a read operation (e.g., Y2=0).

[0053] According to the embodiment of Table 5 or Table 6, at a certain time during the test, the test register 462 and the test register 464 store the bit value Z1 and the bit value Z2 respectively, wherein the bit value Z1 corresponds to the first address and / or the first value (e.g., Z1=1 (as shown in Table 5), or Z1=0 (as shown in Table 6)), and the bit value Z2 corresponds to the first address (e.g., Z2=1 (as shown in Table 5), or Z2=0 (as shown in Table 6)). Because the first address is equal to the second address, the bit value Z1 is equal to the bit value Z2.

[0054] According to the embodiments of Table 5 or Table 6, Figure 4B The circuit can be used to output the memory address ADDR and / or the test data DI.

[0055] Figure 5A and Figure 5B 1 is a circuit diagram showing another embodiment of the test circuit of the present invention, which is used to test a stuck-at fault on the path between the functional registers (ie, register 140 and register 170) and the memory 160. Figure 5A and Figure 5B In the embodiment of the present invention, the test circuit 130 includes a first test register group 510, a multiplexer 520, an inverter 530, a second test register group 560, and a multiplexer group 570. The first test register group 510 includes a test register 512. The second test register group 560 includes a test register 562. The multiplexer group 570 includes n+1 multiplexers 575 (i.e., multiplexer 575_0, multiplexer 575_1, ..., multiplexer 575_n, where n is a positive integer).

[0056] Please refer to Figure 5A , Figure 5AThe circuit is used to output the write enable signal WE. The multiplexer 520 is coupled between the first test register group 510 and the register 140, and is used to select the function signal SF or the output of the first test register group 510 according to the mode control signal MSM_MODE. The input end of the inverter 530 is coupled to the output end Q of the test register 512, and the output end of the inverter 530 is coupled to the input end D of the test register 512. Figure 5A The circuit is Figure 4A The simplified circuit occupies a smaller circuit area.

[0057] Please refer to Figure 5B , Figure 5B The circuit is used to output the test data DI and / or the memory address ADDR. The multiplexer group 570 is coupled between the second test register group 560 and the register 140, and is used to select the function signal SF or the output of the second test register group 560 according to the mode control signal MSM_MODE. Figure 5B The circuit is Figure 4B The simplified circuit occupies a smaller circuit area.

[0058] The test circuit of the present invention is very concise, and the test signal (including write enable signal WE, memory address ADDR and test data DI) provided by the test circuit to the memory will not pass through the logic circuit, so the test circuit of the present invention has the following advantages: low test pattern complexity, high controllability of the memory, short time required to generate the test pattern, simple test pattern, and high test coverage.

[0059] Please note that in the aforementioned figures, the shapes, sizes and proportions of the components are merely for illustration purposes to help those skilled in the art understand the purpose of the present invention and are not intended to limit the present invention.

[0060] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of this specification.

[0061]

Explanation of symbols

[0062] 110, 140, 170, 190: Register

[0063] BIST_MODE, MSM_MODE: mode control signal

[0064] 150, 220, 275_0, 275_1, 275_n, 320, 375_0, 375_1, 375_n, 420, 475_0, 475_1, 475_n, 520, 575_0, 575_1, 575_n: Multiplexer

[0065] 180: Memory Built-in Self-Test (MBIST) Circuit

[0066] 160: Memory

[0067] 130: Test Circuit

[0068] 120: Logic Circuits

[0069] SF: Functional Signal

[0070] 210, 310, 410, 510: First test register group

[0071] 260, 360, 460, 560: Second test register group

[0072] 270, 370, 470, 570: Multiplexer group

[0073] 212, 214, 216, 218, 262, 264, 266, 268, 312, 314, 362, 412, 414, 462, 464, 512, 562: Test registers

[0074] WE: Write enable signal

[0075] Y, Z, B0, B1, Bn: bit value

[0076] CLK: Clock

[0077] 330, 380, 530: Inverter

Claims

1. A test circuit for testing a memory, wherein an input terminal of the memory is coupled to a register, and the register is coupled to a logic circuit, the test circuit comprising: A first test register group, comprising at least one test register; A second test register group, comprising at least one test register; A first multiplexer coupled between the first test register group and the register; as well as a plurality of second multiplexers coupled between the second test register group and the register; The first test register group includes a first test register and a second test register electrically connected in sequence, and the test circuit further includes: An inverter is coupled between an input terminal of the first test register and an output terminal of the second test register. 2 . The test circuit according to claim 1 , wherein the plurality of second multiplexers output the same bit value. 3 . The test circuit according to claim 1 , wherein the first test register group comprises a first test register, a second test register, a third test register, and a fourth test register electrically connected in sequence. 4 . The test circuit according to claim 1 , wherein the second test register group comprises a first test register, a second test register, a third test register, and a fourth test register electrically connected in sequence.

5. The test circuit according to claim 4, wherein the first test register, the second test register, the third test register and the fourth test register store a first bit value, a second bit value, a third bit value and a fourth bit value respectively, the first bit value is not equal to the second bit value, and the third bit value is not equal to the fourth bit value.

6. The test circuit according to claim 1, wherein the second test register group includes a target test register, the test circuit further comprising: An inverter is coupled between an input terminal of the target test register and an output terminal of the target test register. 7 . The test circuit according to claim 1 , wherein the first test register group comprises a first test register and a second test register electrically connected in sequence. 8 . The test circuit according to claim 1 , wherein the second test register group comprises a first test register and a second test register electrically connected in sequence.

9. The test circuit according to claim 1, wherein the first test register group includes a target test register, the test circuit further comprising: An inverter is coupled between an input terminal of the target test register and an output terminal of the target test register.

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