Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a target layer for forming a target pattern, and a pattern definition layer formed on the target layer; forming a plurality of first openings exposing the top surface of the target layer in the pattern definition layer; forming sidewall layers on the sidewalls of the first openings, the pattern definition layer located between adjacent first openings, and the sidewall layers located on the opposite sidewalls of the pattern definition layer constituting a pattern group; forming a sacrificial layer in the remaining first openings; performing multiple pattern definition processes, each pattern definition process including: removing the pattern definition layer in one or more pattern groups and a portion of the sidewall layer with a certain width at the junction of the pattern definition layer and the sidewall layer, forming a second opening surrounded by the remaining sidewall layers and the target layer; removing the sacrificial layer; using the sidewall layers and the pattern definition layer as masks to etch the target layer at the bottoms of the first openings and the second openings to form the target pattern. The present invention meets the requirement of continuously reducing the pitch of the target pattern.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e., the number of internal interconnect structures on each chip) gradually increases, the geometric size (i.e., the minimum component size that can be produced using the process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to break through the current limitations of lithography equipment and meet the process requirements of increasingly smaller metal interconnect line widths has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is conducive to further reducing the pitch between target patterns.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a plurality of first openings formed in the pattern definition layer to expose a top surface of the target layer, the plurality of first openings extending along a first direction and arranged along a second direction, the second direction and the first direction being perpendicular to each other; forming a sidewall layer on the sidewalls of the first openings, wherein in the second direction, the pattern definition layer located between adjacent first openings and the sidewall layer located on opposite sidewalls of the pattern definition layer constitute a pattern group; forming a sidewall layer on the remaining first openings A sacrificial layer is formed in the opening, the sacrificial layer covering the top of the target layer and the sidewall of the sidewall layer; multiple graphic definition processes are performed, each of the graphic definition processes includes: removing the graphic definition layer in one or more graphic groups and the sidewall layer of a portion of the width at the junction of the graphic definition layer and the sidewall layer along the second direction to form a second opening surrounded by the remaining sidewall layer and the target layer; after performing the graphic definition processes multiple times, the sacrificial layer is removed; after removing the sacrificial layer, the target layer at the bottom of the first opening and the second opening is etched using the sidewall layer and the graphic definition layer as a mask to form a target graphic.

[0007] Optionally, during each of the graphic definition processes, the steps of removing the graphic definition layer in one or more of the graphic groups and a partial width of the sidewall layer at the junction of the graphic definition layer and the sidewall layer include: forming a mask layer with mask openings on the tops of the graphic definition layer, the sidewall layer, and the sacrificial layer, where the mask openings correspond one-to-one to the graphic groups, and the mask openings expose the graphic definition layer in one or more of the graphic groups and a partial width of the sidewall layer at the junction of the graphic definition layer and the sidewall layer; using the mask layer as a mask to etch and remove the graphic definition layer in one or more of the graphic groups and a partial width of the sidewall layer at the junction of the graphic definition layer and the sidewall layer along the mask openings.

[0008] Optionally, the material of the mask layer includes one or both of SOC and SOH.

[0009] Optionally, the steps of forming the graphic definition layer include: forming a graphic material layer on the top of the target layer; doping a partial area of the graphic material layer, and the doped graphic material layer serves as the graphic definition layer; the steps of forming a plurality of first openings exposing the top surface of the target layer in the graphic definition layer include: removing the remaining undoped graphic material layer.

[0010] Optionally, an ion implantation process is used to dope a partial area of the graphic material layer.

[0011] Optionally, in the doping process, the doped ions include boron ions, phosphorus ions, or argon ions.

[0012] Optionally, during each of the graphic definition processes, a dry etching process is used to remove the graphic definition layer in one or more of the graphic groups and a partial width of the sidewall layer at the junction of the graphic definition layer and the sidewall layer.

[0013] Optionally, during each of the graphic definition processes, the width dimension of the removed sidewall layer is 10 angstroms to 50 angstroms.

[0014] Optionally, in the step of forming the sidewall layer on the sidewalls of the first openings, the dimension of the sidewall layer in the second direction is 10 nanometers to 20 nanometers.

[0015] Optionally, the process of forming the sidewall layer includes an atomic layer deposition process.

[0016] Optionally, the material of the graphic definition layer includes amorphous silicon.

[0017] Optionally, the material of the sidewall layer includes one or several of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide.

[0018] Optionally, the material of the sacrificial layer includes an organic material.

[0019] Optionally, the material of the sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate.

[0020] Optionally, the process for removing the sacrificial layer includes one or both of an ashing process and a wet stripping process.

[0021] Optionally, the target layer is a dielectric layer, and the target pattern is an interconnect trench; the forming method further includes: after forming the interconnect trench, forming a metal interconnect line in the interconnect trench.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] The embodiment of the present invention provides a method for forming a semiconductor structure. During each process of pattern definition processing, while removing the pattern definition layer, a part of the sidewall layer with a partial width along the second direction at the junction of the sidewall layer and the pattern definition layer is also removed, forming a second opening surrounded by the remaining sidewall layer and the target layer, so that the dimension of the remaining sidewall layer along the second direction is smaller than the dimension of the sidewall layer along the second direction before the pattern definition processing, and the dimension of the second opening along the second direction meets the process requirements. Subsequently, the target layer is etched using the sidewall layer and the pattern definition layer as masks to form a target pattern, and the remaining sidewall layer is used to define the space between adjacent target patterns. Therefore, by removing a part of the sidewall layer with a partial width at the junction of the sidewall layer and the pattern definition layer, the space between adjacent target patterns is correspondingly reduced. In addition, through the pattern definition processing, in the second direction, the dimension of the second opening is larger than the dimension of the pattern definition layer in the pattern group. Correspondingly, during the process of forming the first opening, the dimension of the pattern definition layer between adjacent first openings in the second direction can be appropriately reduced, that is, the dimension of the first opening along the second direction can be appropriately increased, which correspondingly increases the process window for forming the first opening. In summary, compared with the prior art of directly etching the target layer using the sidewall layer before the pattern definition processing to form a target pattern, it is possible to meet the requirement of continuously reducing the pitch of the target pattern while increasing the process window of the lithography process, thereby facilitating further reduction of the pitch between target patterns. Description of the Drawings

[0024] Figures 1 to 10 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Description

[0025] Currently, due to the limitation of lithography equipment, the line width of the metal interconnects formed in semiconductor devices is too large to meet the process requirements of the increasingly smaller line width of the metal interconnects.

[0026] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a target layer for forming a target pattern, a pattern definition layer is formed on the target layer, and a plurality of first openings exposing the top surface of the target layer are formed in the pattern definition layer, the plurality of first openings extend in a first direction and are arranged in a second direction, and the second direction and the first direction are perpendicular to each other; forming sidewall layers on the sidewalls of the first openings, in the second direction, the pattern definition layer located between adjacent first openings and the sidewall layers located on the opposite sidewalls of the pattern definition layer form a pattern group; forming a sacrificial layer in the remaining first openings, the sacrificial layer covering the top of the target layer and the sidewalls of the sidewall layers; performing multiple pattern definition processes, each pattern definition process includes: along the second direction, removing the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer, forming a second opening surrounded by the remaining sidewall layers and the target layer; after performing multiple pattern definition processes, removing the sacrificial layer; after removing the sacrificial layer, using the sidewall layers and the pattern definition layer as a mask to etch the target layer at the bottoms of the first openings and the second openings to form a target pattern.

[0027] In the solution disclosed in the embodiments of the present invention, during each process of the graphic definition process, while removing the graphic definition layer, a part of the sidewall layer with a certain width at the junction of the sidewall layer and the graphic definition layer along the second direction is also removed, forming a second opening surrounded by the remaining sidewall layer and the target layer, so that the size of the remaining sidewall layer along the second direction is smaller than that of the sidewall layer before the graphic definition process along the second direction, and the size of the second opening along the second direction meets the process requirements. Subsequently, the target layer is etched using the sidewall layer and the graphic definition layer as masks to form a target pattern, and the remaining sidewall layer is used to define the space between adjacent target patterns. Therefore, by removing a part of the sidewall layer at the junction of the sidewall layer and the graphic definition layer, the space between adjacent target patterns is correspondingly reduced. In addition, through the graphic definition process, in the second direction, the size of the second opening is larger than the size of the graphic definition layer in the graphic group. Correspondingly, during the formation of the first opening, the size of the graphic definition layer between adjacent first openings in the second direction can be appropriately reduced, that is, the size of the first opening along the second direction can be appropriately increased, which correspondingly increases the process window for forming the first opening. In summary, compared with the prior art solution of directly etching the target layer using the sidewall layer before the graphic definition process as a mask to form a target pattern, it is possible to meet the requirement of continuously reducing the pitch of the target pattern while increasing the process window of the lithography process, which is beneficial to further reducing the pitch between target patterns.

[0028] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0029] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0030] Reference Figures 1 to 2 , a substrate is provided, the substrate includes a target layer 100 for forming a target pattern, and a graphic definition layer 101 (as Figure 2 shown) is formed on the target layer 100, and a plurality of first openings 102 (as Figure 2 shown) exposing the top surface of the target layer 100 are formed in the graphic definition layer 101, and the plurality of first openings 102 extend along a first direction (such as Figure 1 the X direction shown in (b)) and are arranged along a second direction (such as Figure 1 the Y direction shown in (b)), and the second direction and the first direction are perpendicular to each other.

[0031] Among them, Figure 1 (b) is a top view.Figure 1 (a) is Figure 1 (b) Cross-sectional view along the secant line AB; Figure 2 (b) is the top view, Figure 2 (a) is Figure 2 (b) Cross-sectional view along the secant line AB

[0032] The substrate is used to provide a process platform for subsequent process manufacturing.

[0033] In this embodiment, semiconductor devices such as transistors and capacitors can be formed in the substrate, and functional structures such as resistor structures and conductive structures can also be formed in the substrate.

[0034] The target layer 100 is used as a material layer that needs to be patterned subsequently to form a target pattern.

[0035] Among them, the target pattern can be a gate structure, an interconnect trench in the back end of line (BEOL) process, a fin in a fin field effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork sheet transistor (Forksheet), a hard mask (HM) layer and other patterns.

[0036] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the target layer 100 is patterned to form a plurality of interconnect trenches in the target layer 100, and then metal interconnect lines are formed in the interconnect trenches. The target layer 100 is used to achieve electrical isolation between the metal interconnect lines in the back end process.

[0037] For this reason, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride, etc.

[0038] In this embodiment, the material of the target layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end interconnect lines, and further reduce the back-end RC delay. Specifically, the material of the target layer 100 can be SiOCH.

[0039] In this embodiment, the substrate further includes a hard mask material layer (not shown in the figure) located on the target layer 100, and an etch stop layer (not shown in the figure) located on the hard mask material layer.

[0040] The hard mask material layer is used to form a hard mask layer (not shown in the figure) after subsequent patterning processes.

[0041] Specifically, the pattern is first transferred into the hard mask material layer to form a hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of patterning.

[0042] The subsequent process includes performing multiple pattern definition processes. The etch stop layer is used to define the etch stop position in the etching process of the subsequent pattern definition process, which is beneficial to reducing the loss of the target layer 100 and improving the depth uniformity of the etching process, thereby improving the effect of the subsequent patterning process.

[0043] In this embodiment, the pattern definition layer 101 is formed on the etch stop layer.

[0044] In this embodiment, the steps of forming the pattern definition layer 101 include: as Figure 1 shown, a pattern material layer 161 is formed on the top of the target layer 100, and a first mask layer 160 is formed on the top of the pattern material layer 161. The first mask layer 160 covers a part of the top of the pattern material layer 161; as Figure 2 shown, a doping process is performed on a part of the pattern material layer 161. The pattern material layer 161 doped with ions serves as the pattern definition layer 101.

[0045] The pattern material layer 161 provides a process basis for forming the pattern definition layer 101.

[0046] In this embodiment, the material of the pattern definition layer 101 includes amorphous silicon.

[0047] It should be noted that the lattice structure of the amorphous silicon material has unstable characteristics, and it is easy to dope ions into the pattern material layer 161 by doping the pattern material layer 161 subsequently, so as to change the etching rate of the amorphous silicon material, so that there is an etching selectivity between the undoped pattern material layer 161 and the pattern definition layer 101.

[0048] In this embodiment, an ion implantation process is used to dope a part of the pattern material layer 161.

[0049] It should be noted that the ion implantation process has the characteristics of uniformly implanting ions over a large area, more accurately controlling the ion doping depth, and high repeatability.

[0050] In this embodiment, the doping depth of the doping process is the entire thickness of the pattern material layer 161.

[0051] In the step of doping the pattern material layer 161, the doping ions include boron ions, phosphorus ions or argon ions. As an example, the doping ions are boron ions.

[0052] In this embodiment, the first mask layer 160 is used to block the regions in the pattern material layer 161 that are not desired to be doped.

[0053] Reference Figure 2 , in this embodiment, the step of forming a plurality of first openings 102 exposing the top surface of the target layer 100 in the pattern definition layer 101 includes: removing the remaining pattern material layer 161 that is not doped with ions.

[0054] The first openings 102 provide spatial positions for subsequent formation of sidewall layers and sacrificial layers.

[0055] Reference Figure 3 , a sidewall layer 103 is formed on the sidewalls of the first openings 121. In the second direction (as shown by the Y direction in Figure 3 (b)), the pattern definition layer 101 located between adjacent first openings 121 and the sidewall layer 103 located on the opposite sidewalls of the pattern definition layer 101 constitute a pattern group 190.

[0056] Among them, Figure 3 (b) is a top view, Figure 3 (a) is Figure 3 a cross-sectional view of (b) along the AB cut line.

[0057] The sidewall layer 103 provides a process basis for subsequent etching to remove a part of the width of the sidewall layer 103, and the remaining sidewall layer 103 is used as an etching mask for subsequent etching of the target layer 100.

[0058] It should be noted that in this embodiment, subsequent pattern definition processing will be performed to etch a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 101 and the sidewall layer 103. And in the process of forming the target pattern in the subsequent target layer 100, the remaining sidewall layer 103 will be used as an etching mask. By first removing a part of the width of the sidewall layer 103, the size of the remaining sidewall layer 103 in the second direction becomes smaller, so that a smaller interval can be achieved between subsequent adjacent target patterns.

[0059] In this embodiment, in the step of forming a sidewall layer 103 extending along the first direction (as shown by the X direction in [[ID=3,6]] Figure 3 (a)) on the sidewalls of the first openings 121, the size of the sidewall layer 103 in the second direction is 10 nanometers to 20 nanometers.

[0060] It should be noted that the dimension of the sidewall layer 103 in the second direction should not be too large or too small. If the dimension of the sidewall layer 103 in the second direction is too large, it is likely to overly occupy the spatial position of the first opening 121. During the subsequent graphic definition process, when the width of the removed sidewall layer 103 is fixed, it is also likely to result in an overly large dimension of the remaining sidewall layer 103, which in turn is likely to cause the size of the subsequent formed target graphic to be too small, leading to failure to meet the requirements of the line width of the target graphic, or causing the spacing between the target graphics to fail to reach the minimum design interval, thus affecting the performance of the metal interconnect. Or, during the subsequent graphic definition process, the removal amount of the sidewall layer 103 is relatively large, and the sidewall layer 103 usually has a high etch resistance, thereby increasing the difficulty of the graphic definition process; if the dimension of the sidewall layer 103 is too small, it is likely to cause an overly large remaining space in the first opening 121, which in turn leads to an overly large size of the target graphic formed by etching the target layer 100 using the sidewall layer 103 as a mask, and then leads to failure to meet the requirements of the continuously shrinking line width of the target graphic, thus affecting the performance of the metal interconnect. Therefore, in this embodiment, in the step of forming the sidewall layer 103 extending along the first direction on the sidewall of the first opening 121, the dimension of the sidewall layer 103 in the second direction is 10 nanometers to 20 nanometers. For example, the dimension of the sidewall layer 103 in the second direction is 13 nanometers, 15 nanometers, or 17 nanometers.

[0061] In this embodiment, the process for forming the sidewall layer 103 includes an atomic layer deposition process.

[0062] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the sidewall layer 103 and enabling the sidewall layer 103 to cover the sidewall of the graphic definition layer 101. In other embodiments, a chemical vapor deposition process (Chemical Vapor Deposition, CVD) can also be used to form the first sidewall layer.

[0063] In this embodiment, the material of the sidewall layer 103 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide. In this embodiment, the material of the sidewall layer 103 is titanium oxide. The etching selectivity of the titanium oxide material with respect to amorphous silicon or spin-on glass is relatively large. The sidewall layer 103 can be retained during the subsequent process of removing the sacrificial layer, and the target layer 100 can be etched using the sidewall layer 103 as a mask subsequently.

[0064] In this embodiment, the steps of forming the sidewall layer 103 include: forming a sidewall material layer (not shown in the figure) on the top and sidewalls of the pattern definition layer 101 and the bottom of the first opening 102, removing the sidewall material layer on the top of the pattern definition layer 101 and the bottom of the first opening 102, and using the remaining sidewall material layer as the sidewall layer 103.

[0065] Reference Figure 4 , a sacrificial layer 110 is formed in the remaining first opening 102, and the sacrificial layer 110 covers the top of the target layer 100 and the sidewalls of the sidewall layer 103.

[0066] Wherein, Figure 4 (b) is a top view, Figure 4 (a) is Figure 4 (b) A cross-sectional view along the AB secant line.

[0067] The sacrificial layer 110 provides a spatial position for forming the second opening subsequently.

[0068] In this embodiment, the material of the sacrificial layer 110 includes an organic material.

[0069] It should be noted that the etching selectivity between the organic material and the material of the sidewall layer 103 is relatively large, which is beneficial to removing the sacrificial layer 110 subsequently.

[0070] The material of the sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate.

[0071] In this embodiment, after filling the sacrificial material in the remaining first opening 102, the sacrificial material is also planarized (for example, chemical mechanical polishing treatment). Therefore, the top of the sacrificial layer 110 is flush with the top of the target layer 100.

[0072] Reference Figures 5 to 7 , multiple pattern definition processes are performed. Each pattern definition process includes: along the second direction (as shown by the Y direction in Figure 5 (b)), removing the pattern definition layer 126 in one or more of the pattern groups 190, and a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 126 and the sidewall layer 103, to form a second opening 170 surrounded by the remaining sidewall layer 103 and the target layer 100.

[0073] By performing multiple pattern definition processes, the pattern definition layer 126 in all the pattern groups 190 and a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 126 and the sidewall layer 103 are removed.

[0074] In this embodiment, by forming a second opening 170 surrounded by the remaining sidewall layer 103 and the target layer 100, the dimension of the remaining sidewall layer 103 in the second direction is reduced compared to that of the sidewall layer 103 in the second direction before the graphic definition process, and the dimension of the second opening 170 in the second direction meets the process requirements. Subsequently, the target layer 100 is etched using the sidewall layer 103 and the graphic definition layer 101 as masks to form a target pattern, and the remaining sidewall layer 103 is used to define the space between adjacent target patterns. Therefore, by removing a partial width of the sidewall layer 103 at the junction of the sidewall layer 103 and the graphic definition layer 101, the space between adjacent target patterns is correspondingly reduced. In addition, through the graphic definition process, in the second direction, the dimension of the second opening 170 is larger than that of the graphic definition layer 101 in the graphic group 190. Correspondingly, during the formation of the first opening 102, the dimension of the graphic definition layer 101 between adjacent first openings 102 in the second direction can be appropriately reduced, that is, the dimension of the first opening 102 in the second direction can be appropriately increased, which correspondingly increases the process window for forming the first opening 102. In summary, compared with the prior art solution of directly etching the target layer 100 using the sidewall layer 103 before the graphic definition process as a mask to form a target pattern, it is possible to meet the requirement of continuously reducing the pitch of the target pattern while increasing the process window of the lithography process, thereby facilitating further reduction of the pitch between the target patterns.

[0075] Moreover, the number of times of the graphic definition process is multiple, which is beneficial to increasing the process window of each graphic definition process in the case of continuous reduction of the device feature size.

[0076] In this embodiment, during each graphic definition process, the steps of removing the graphic definition layer 101 in one or more of the graphic groups 190 and a partial width of the sidewall layer 103 at the junction of the graphic definition layer 101 and the sidewall layer 103 include: as Figure 5 shown, a mask layer 120 with a mask opening 126 is formed on the tops of the graphic definition layer 101, the sidewall layer 103, and the sacrificial layer 110. The mask opening 126 corresponds to the graphic group 190 one by one, and the mask opening 126 exposes the graphic definition layer 101 in one or more of the graphic groups 190 and a partial width of the sidewall layer 103 at the junction of the graphic definition layer 101 and the sidewall layer 103; as Figure 6As shown, using the mask layer 120 as a mask, etch away the pattern definition layer 101 in one or more of the pattern groups 190, and a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 101 and the sidewall layer 103 along the mask opening 126.

[0077] In this embodiment, the mask opening 126 corresponds to the pattern group 190 one by one, thereby reducing the damage to the sacrificial layer 110.

[0078] In this embodiment, each pattern definition process only removes the pattern definition layer 126 in one pattern group 190, and a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 126 and the sidewall layer 103, thereby increasing the process window for forming the mask opening 126, and facilitating avoiding the problem that the mask openings 126 above adjacent pattern groups 190 are connected. In particular, as the device feature size continues to decrease, the spacing between adjacent pattern groups 190 becomes smaller and smaller.

[0079] Moreover, during the pattern definition process, the mask opening 126 exposes the pattern definition layer 101 in the pattern group 190 and the top of a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 101 and the sidewall layer 103. Compared with the scheme where the mask opening only exposes the pattern definition layer, this is conducive to reducing the requirement for the alignment accuracy in the lithography process, thereby increasing the process window of the lithography process for forming the mask opening 126.

[0080] In this embodiment, the material of the mask layer 120 includes an organic material. In this embodiment, the material of the mask layer 120 includes one or both of SOC and SOH. In other embodiments, the material of the mask layer can also be other organic materials, such as: one or more of ODL (organic dielectric layer) material, DUO (Deep UV Light Absorbing Oxide) material, and APF (Advanced Patterning Film) material.

[0081] It should be noted that the steps of forming the mask layer 120 include: forming a mask material layer (not shown in the figure) on the top of the sidewall layer 103, the pattern definition layer 101, and the sacrificial layer 110, forming an anti-reflection material coating (not shown in the figure) on the top of the mask material layer, and forming a photoresist layer 122 on the top of the anti-reflection material coating; using the photoresist layer 122 as a mask, etching the anti-reflection material coating and the mask material layer in sequence, and the remaining anti-reflection material coating serves as the anti-reflection coating 121, and the remaining mask material layer serves as the mask layer 120.

[0082] The material of the anti-reflection coating 121 includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0083] In this embodiment, a dry etching process is used to remove the pattern definition layer 101 in the pattern group 190 and a part of the width of the sidewall layer 103 at the junction of the pattern definition layer 101 and the sidewall layer 103.

[0084] The dry etching process is an anisotropic dry etching treatment process. The anisotropic dry etching treatment process has the characteristics of anisotropic etching. Therefore, its longitudinal etching rate is much greater than the lateral etching rate, and quite accurate pattern transfer can be obtained, improving the sidewall topography quality of the second opening 170.

[0085] In this embodiment, during each pattern definition process, the width dimension of the sidewall layer 103 removed is 10 angstroms to 50 angstroms.

[0086] It should be noted that the width dimension of the removed sidewall layer 103 should not be too large or too small. If the width dimension of the removed sidewall layer 103 is too large, it is easy to cause the space of the second opening 170 to be too large, and then cause the target pattern formed by etching the target layer 100 using the sidewall layer 103 as a mask to be too large, and then cause the requirement of continuously reducing the line width of the target pattern not to be met, thus affecting the performance of the metal interconnection line; if the width dimension of the removed sidewall layer 103 is too small, it is easy to cause the space of the second opening 170 to be too small, and then easily cause the size of the subsequent formed target pattern to be too small, and then cause the requirement of the line width of the target pattern not to be met or the distance between the target patterns cannot reach the minimum design interval, thus affecting the performance of the metal interconnection line. For this reason, in this embodiment, during each pattern definition process, the width dimension of the sidewall layer 103 removed is 10 angstroms to 50 angstroms. For example, the width dimension of the removed sidewall layer 103 is 20 angstroms, 30 angstroms or 40 angstroms.

[0087] In this embodiment, after the first pattern definition process is completed, the mask layer 120 is removed.

[0088] It should be noted that in this embodiment, the number of pattern definition processes is the same as the number of pattern groups 190. For example, in this embodiment, only 3 groups of pattern groups 190 are illustrated. Therefore, a total of 3 pattern definition processes are performed, such as Figures 5 to 6 one pattern process is performed, Figure 7The second opening 170 formed after performing the graphic process two more times is shown. The remaining two graphic processes are the same as the first graphic process described above, and will not be elaborated here.

[0089] It should also be noted that in some other embodiments, during each graphic definition process, the graphic definition layer in multiple non-adjacent graphic groups and a part of the sidewall layer with a certain width at the junction of the graphic definition layer and the sidewall layer can be removed. During each graphic definition process, the multiple graphic groups are non-adjacent, which can also increase the process window for forming the mask opening and reduce the probability of connection between adjacent mask openings. Moreover, by performing the graphic definition process multiple times, the graphic definition layer in all graphic groups and a part of the sidewall layer with a certain width at the junction of the graphic definition layer and the sidewall layer can also be removed.

[0090] In other embodiments, according to the actual situation (for example, the distance between adjacent graphic groups is wide enough), during each graphic definition process, the graphic definition layer in multiple adjacent graphic groups and a part of the sidewall layer with a certain width at the junction of the graphic definition layer and the sidewall layer can also be removed.

[0091] Reference Figure 8 , after performing the graphic definition process multiple times, the sacrificial layer 110 is removed.

[0092] Among them, Figure 8 (b) is a top view, Figure 8 (a) is Figure 8 (b) A cross-sectional view along the AB secant line.

[0093] It should be noted that the sacrificial layer 110 is removed to expose the area to be etched.

[0094] In this embodiment, the process of removing the sacrificial layer 110 includes one or both of an ashing process and a wet stripping process.

[0095] During the process of removing organic materials by the ashing process and the wet stripping process, they have the characteristics of high efficiency and low cost, and can reduce the damage to the underlying film layer.

[0096] Reference Figure 9 , after removing the sacrificial layer 110, using the sidewall layer 103 and the graphic definition layer 101 as masks, the target layer 100 at the bottom of the first opening 102 and the second opening 170 is etched to form the target pattern 180.

[0097] Among them, Figure 9 (b) is a top view, Figure 9 (a) is Figure 9 (b) A cross-sectional view along the AB secant line.

[0098] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the target pattern 180 while increasing the process window of the lithography process, which correspondingly improves the pattern accuracy and pattern quality of the target pattern 180.

[0099] It should be noted that the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the sidewall layer 103 and the pattern definition layer 101 as masks, the target pattern 180 is an interconnect trench.

[0100] In this embodiment, a hard mask material layer (not shown in the figure) and an etch stop layer (not shown in the figure) are further formed on the target layer 100, and the bottoms of the first opening 102 and the second opening 170 expose the etch stop layer.

[0101] Therefore, using the sidewall layer 103 and the pattern definition layer 101 as masks, the etch stop layer and the hard mask material layer at the bottoms of the first opening 102 and the second opening 170 are etched in sequence. After the remaining hard mask material layer serves as a hard mask layer (not shown in the figure), the target layer 100 is etched using the hard mask layer as a mask.

[0102] By first transferring the patterns of the first opening 102 and the second opening 170 into the hard mask material layer to form a hard mask layer, it is beneficial to improve the process stability and process effect of etching the target layer 100 and improve the accuracy of pattern transfer.

[0103] Reference Figure 10 , the forming method further includes: after forming the interconnect trench, forming a metal interconnect 181 in the interconnect trench.

[0104] Among them, Figure 10 (b) is a top view, Figure 10 (a) is Figure 10 (b) A cross-sectional view along the AB secant line.

[0105] The metal interconnect 181 is used to realize the electrical connection between the semiconductor structure and an external circuit or other interconnect structures.

[0106] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the line width of the interconnect trench while increasing the process window of the lithography process, and the spacing between adjacent interconnect trenches is easy to meet the design minimum spacing. Correspondingly, it is beneficial to make the spacing of the metal interconnects 181 meet the design minimum spacing, and it is also beneficial to improve the pattern accuracy of the metal interconnects 181, thereby being beneficial to improving the electrical connection performance of the metal interconnects 181.

[0107] In this embodiment, the material of the metal interconnect 181 is copper. In other embodiments, the material of the metal interconnect can also be a conductive material such as aluminum.

[0108] In this embodiment, an electroplating copper method is used to form a metal interconnect line 181 in the interconnect groove.

[0109] Correspondingly, the process of forming the metal interconnect line 181 includes a step of filling a conductive material and a step of planarizing the conductive material to remove the conductive material higher than the top of the dielectric layer.

[0110] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0111] The chemical mechanical polishing process makes the metal interconnect line 181 formed in the interconnect groove have a flat surface, improving the electrical connection effect of the metal interconnect line 181.

[0112] In this embodiment, during the process of forming the metal interconnect line 181, the remaining pattern definition layer 101, sidewall layer 103, etch stop layer, and hard mask layer are also removed, thereby exposing the top surface of the target layer 100 to prepare for subsequent processes.

[0113] The specific description of the metal interconnect line 181 will not be elaborated here.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate includes a target layer for forming a target pattern, a pattern definition layer is formed on the target layer, and a plurality of first openings exposing the top surface of the target layer are formed in the pattern definition layer. The plurality of first openings extend in a first direction and are arranged in a second direction, and the second direction and the first direction are perpendicular to each other; Forming a sidewall layer on the sidewalls of the first openings. In the second direction, the pattern definition layer located between adjacent first openings and the sidewall layer located on the opposite sidewalls of the pattern definition layer constitute a pattern group; Forming a sacrificial layer in the remaining first openings, and the sacrificial layer covers the top of the target layer and the sidewalls of the sidewall layer; Performing multiple pattern definition processes. Each pattern definition process includes: along the second direction, removing the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer, to form a second opening surrounded by the remaining sidewall layer and the target layer; After performing multiple pattern definition processes, removing the sacrificial layer; After removing the sacrificial layer, using the sidewall layer and the pattern definition layer as a mask to etch the target layer at the bottoms of the first opening and the second opening to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein During each pattern definition process, the step of removing the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer includes: Forming a mask layer with mask openings on the tops of the pattern definition layer, the sidewall layer and the sacrificial layer. The mask openings correspond to the pattern groups one by one, and the mask openings expose the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer; Using the mask layer as a mask to etch and remove the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer along the mask openings.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the mask layer includes one or both of SOC and SOH.

4. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the pattern definition layer includes: forming a pattern material layer on the top of the target layer; doping a part of the pattern material layer, and the doped pattern material layer is used as the pattern definition layer; The step of forming a plurality of first openings exposing the top surface of the target layer in the pattern definition layer includes: removing the remaining pattern material layer that is not doped with ions.

5. The method for forming a semiconductor structure according to claim 4, wherein, Using an ion implantation process to dope a part of the pattern material layer.

6. The method for forming a semiconductor structure according to claim 4, wherein, In the doping process, the doped ions include boron ions, phosphorus ions or argon ions.

7. The method for forming a semiconductor structure according to claim 1, wherein, During each pattern definition process, using a dry etching process to remove the pattern definition layer in one or more of the pattern groups and a part of the width of the sidewall layer at the junction of the pattern definition layer and the sidewall layer.

8. The method for forming a semiconductor structure according to claim 1, wherein, During each pattern definition process, the width dimension of the removed sidewall layer is 10 angstroms to 50 angstroms.

9. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the sidewall layer on the sidewall of the first opening, the dimension of the sidewall layer in the second direction is from 10 nanometers to 20 nanometers.

10. The method for forming a semiconductor structure as described in claim 1, wherein, The process of forming the sidewall layer includes an atomic layer deposition process.

11. The method for forming a semiconductor structure according to claim 1, wherein, The material of the pattern definition layer includes amorphous silicon.

12. The method for forming a semiconductor structure as described in claim 1, wherein, The material of the sidewall layer includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein, The material of the sacrificial layer includes an organic material.

14. The method for forming a semiconductor structure as described in claim 13, wherein, The material of the sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide, and tetraethyl orthosilicate.

15. The method for forming a semiconductor structure according to claim 1, wherein The process of removing the sacrificial layer includes one or both of an ashing process and a wet stripping process.

16. The method for forming a semiconductor structure according to claim 1, wherein The target layer is a dielectric layer, and the target pattern is an interconnect trench; The forming method further includes: after forming the interconnect trench, forming a metal interconnect in the interconnect trench.

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