Heat dissipation isolation structure for semiconductor devices

Abstract

The present disclosure provides a heat spreading isolation structure for a semiconductor device. A structure includes an active device over a region of a substrate and a heat spreading isolation structure adjacent to the active device. The isolation structure includes a dielectric layer over a thermally conductive layer. The thermally conductive layer can include polycrystalline graphite. The thermally conductive layer provides a heat spreader that provides a high thermal conduction path with low electrical conduction. The thermally conductive layer can extend into the substrate. The substrate can include an SOI substrate, in which case the thermally conductive layer can extend through the buried insulator thereof.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to a heat dissipation isolation structure for semiconductor devices having a dielectric layer above a thermally conductive layer. Background Technology

[0002] Heat buildup in semiconductor devices degrades performance and reliability. Semiconductor-on-insulator (SOI) devices are particularly prone to overheating because the primary heat conduction path leaving the SOI device passes through poorly thermally conductive structures. For example, one primary heat conduction path runs vertically downwards through the relatively thick buried insulating layer of the SOI substrate. The dielectric layer is a poor thermal conductor. Another primary heat conduction path passes through wiring via small tungsten contacts, which are also poor thermal conductors. Providing improved thermal conductivity for semiconductor devices has proven challenging. Summary of the Invention

[0003] One aspect of this disclosure relates to a structure comprising: an active device located above a region of a substrate; and a heat dissipation isolation structure adjacent to the active device, wherein the isolation structure includes a dielectric layer located above a thermally conductive layer.

[0004] Another aspect of this disclosure includes a heat dissipation isolation structure comprising: a body located in a trench of a substrate and adjacent to an active device on the substrate, the body comprising: a dielectric layer; and a polycrystalline graphite thermally conductive layer located below the dielectric layer.

[0005] One aspect of this disclosure relates to a method comprising: forming a trench between adjacent active semiconductor regions; forming a hydrocarbon-containing material in the trench; introducing a dopant into at least a portion of the hydrocarbon-containing material in the trench to convert the at least a portion of the hydrocarbon-containing material into disordered graphite; converting the disordered graphite into a polycrystalline graphite thermal conductive layer; and forming a dielectric layer over the polycrystalline graphite thermal conductive layer.

[0006] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein like reference numerals denote like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a structure including a thermal isolation structure in a metal-oxide-semiconductor (MOS) environment according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A cross-sectional view of the steps of a method according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of the steps of a method according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a structure including a thermal isolation structure in a bipolar junction transistor environment according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A plan view of a structure including a heat dissipation isolation structure according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A plan view of a structure including a heat dissipation isolation structure according to other embodiments of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a structure including a heat dissipation isolation structure according to an embodiment of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view of a structure including a thermal isolation structure according to other embodiments of the present disclosure is shown, the structure having a wide gate conductor and the end of the gate conductor extending above the thermal isolation structure.

[0016] Figure 9 A cross-sectional view of a structure including a heat dissipation isolation structure extending into a substrate semiconductor substrate according to further embodiments of the present disclosure is shown.

[0017] Figure 10 A cross-sectional view of a structure including a thermally coupled through-silicon via (TSV) heat dissipation isolation structure according to an embodiment of the present disclosure is shown.

[0018] Figure 11 A cross-sectional view of a structure including a thermally coupled through-silicon via (TSV) heat dissipation isolation structure according to other embodiments of the present disclosure is shown.

[0019] Figure 12 A cross-sectional view of a structure including a heat dissipation isolation structure located above an SOI layer on an SOI substrate, according to some other embodiments of the present disclosure, is shown.

[0020] Figure 13 A cross-sectional view of a structure including a thermal isolation structure in a bipolar environment and above a bulk semiconductor substrate, according to an additional embodiment of the present disclosure, is shown.

[0021] Figure 14 A cross-sectional view of a structure including a thermal isolation structure in a bipolar environment and above a bulk semiconductor substrate, according to an embodiment of the present disclosure, is shown.

[0022] Figure 15A cross-sectional view of a structure including a thermal isolation structure in a lateral bipolar environment and above an SOI substrate, according to other embodiments of the present disclosure, is shown.

[0023] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0024] In the following description, reference is made to the accompanying drawings, which form part of this specification, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0025] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0026] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of any of the following, such as "A / B," "A and / or B," and "at least one of A and B," is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B and / or C” and “at least one of A, B and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0027] Embodiments of this disclosure provide a structure including an active device located above a region of a substrate and a thermal isolation structure adjacent to the active device. The isolation structure includes a dielectric layer located above a thermally conductive layer. The thermally conductive layer may include polycrystalline graphite. The thermally conductive layer provides a heat sink that offers a high thermal conductivity path for heat with low conductivity. The thermally conductive layer may extend into the substrate to conduct heat thereto. The substrate may include an SOI substrate, in which case the thermally conductive layer may optionally extend through a buried insulating layer. The thermal isolation structure provides a short path of conduction through the dielectric layer, eliminating the electrical / parasitic costs of other solutions.

[0028] Figure 1 A cross-sectional view of a structure 100 according to an embodiment of the present disclosure is shown. Structure 100 includes an active device 102 located above a region of a substrate 104. Structure 100 also includes at least one thermal isolation structure 110 (two shown) adjacent to the active device 102 (three shown). The thermal isolation structure 110 includes a dielectric layer 112 located above a thermally conductive layer 114. The substrate 104 may include a bulk semiconductor substrate (…). Figure 1 Not shown in the image, see [link / reference]. Figure 13-15Alternatively, a semiconductor-on-insulator (SOI) substrate 116 may be used. The SOI substrate 116 comprises a layered semiconductor-insulator-semiconductor substrate, replacing the more conventional silicon substrate (bulk substrate). The SOI substrate 116 includes a semiconductor-on-insulator (SOI) layer 118 located above a buried insulating layer 120 over a substrate semiconductor substrate 122. The substrate semiconductor substrate 122 may also be referred to as a processed wafer. The SOI layer 118 and the substrate semiconductor substrate 122 may include, but are not limited to: silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of Al… X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Those comprising one or more III-V compound semiconductors with a defined composition, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those having a composition of Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, where A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). The buried insulating layer 120 may include any suitable dielectric, such as, but not limited to, silicon dioxide, i.e., forming a buried oxide (BOX) layer. Strain may occur on a portion or throughout the semiconductor substrate. The precise thicknesses of the buried insulating layer 120 and the SOI layer 118 can vary widely depending on the intended application.

[0029] exist Figure 1 In the SOI layer 118, the heat dissipation isolation structure 110 is located between two portions of the SOI layer 118, that is, between two electrically isolated semiconductor active regions 124A-B or 124B-C. Figure 1 In this configuration, a heat dissipation isolation structure 110 (e.g., its thermally conductive layer 114) extends through the buried insulating layer 120. The thermally conductive layer 114 contacts the substrate semiconductor substrate 122, thereby providing a heat conduction path from the active device 102 to the substrate semiconductor substrate 122. (Heat transport is indicated using thicker line-type arrows in various figures). The upper surface 126 of the thermally conductive layer 114 is not coplanar with the upper surface 128 of the SOI layer 118. Figure 1 In this case, the upper surface 128 of the SOI layer 118 is located above the upper surface 126 of the thermally conductive layer 114.

[0030] Combination Figure 1 , Figure 2-3A method for forming a thermally insulating structure 110 according to one embodiment of the present disclosure is illustrated. For descriptive purposes, the method will be described relative to a metal-oxide-semiconductor (MOS) environment. However, it should be understood that the method, as well as other teachings of the present disclosure, are equally applicable to bipolar devices and / or BiCMOS devices—see [link to relevant documentation]. Figure 4 and Figure 13-15 . Figure 2 An initial structure 130 including an SOI substrate 104 is shown, as described herein. The initial structure 130 is shown after, for example, the formation of semiconductor active regions 124A-C by patterning a mask and etching, and after oxide liner deposition. Thus, the SOI layer 118 is divided into adjacent semiconductor active regions 124A-C.

[0031] Figure 2 Several steps of a method according to embodiments of the present disclosure are also shown. Figure 2 A trench 132 is shown formed between adjacent semiconductor active regions 124A-B and 124B-C. The trench 132 can be formed within the SOI substrate 116 in any manner now known or later developed (e.g., patterned masking and etching). The trench 132 can, for example, be located at the sites within the semiconductor active regions 124A-C that typically require trench isolation for electrical isolation within the SOI layer 118. The trench 132 can be formed in the SOI substrate 104 to any desired depth, where the thermally conductive layer 114 is expected to extend to that depth. Figure 2 In some embodiments, similar to those typically used for shallow trench isolation, trench 132 extends through the buried insulating layer 120 to reach the substrate semiconductor substrate 122. In other embodiments, similar to those typically used for deep trench isolation, trench 132 may extend into the substrate semiconductor substrate 122. Figure 8 Alternatively, trench 132 may extend to the top of the buried insulation layer 120. Figure 7 As will also be described herein, the width of trench 132 can be controlled to select the width of thermally conductive layer 114.

[0032] Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate), and is typically performed using a mask at appropriate locations to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid), which allows the solvent to selectively dissolve a given material (e.g., oxide) while leaving another material (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged, high-energy free radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching uses high-energy ions of a rare gas to bombard the wafer. These high-energy ions approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to create deep, narrow features, such as trenches 132. For example, using any ashing process from... Figure 2 Remove the mask used to form trench 132.

[0033] Figure 2The formation of a hydrocarbon-containing material 134 in trench 132 is also shown. The hydrocarbon-containing material 134 may comprise any hydrocarbon-containing material, such as certain positive resist materials or antireflective coatings (ARCs), which are graphitized upon ion implantation with relatively heavy ions (e.g., inert elements such as argon (Ar)). For example, the hydrocarbon-containing material 134 may comprise a positive resist material, such as an organic planarization layer (OPL). The hydrocarbon-containing material 134 may be deposited in any manner now known or later developed. "Deposition" can include any now-known or later-developed technique suitable for the material to be deposited, including but not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), finite reaction process CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, and vapor deposition. Here, for example, hydrocarbon-containing materials 134 can be formed by spin coating.

[0034] Figure 2 Also shown is a portion 138 forming the mask 136, exposing the hydrocarbon-containing material 134 in the trench 132. The mask 136 exposes the portion 138 where a thermally conductive layer 114 is desired to be formed. In one embodiment, as... Figure 2 As shown, portion 138 may have a narrower width than typical trench isolation, i.e., the width between active regions 124A-B or 124B-C in SOI layer 118. In other embodiments, portion 138 may have the same width as typical trench isolation, i.e., the entire width between active regions 124 in SOI layer 118—see [link to documentation]. Figure 7 In either case, portion 138 is adjacent to at least one of the semiconductor active regions 124A-C, thereby allowing thermal conduction between the active regions 124A-C and the thermally conductive layer 114 formed in portion 138.

[0035] Figure 3 Cross-sectional views of the structure after multiple steps are shown, including the introduction of dopants (straight arrows, e.g., ion implantation) into the hydrocarbon-containing material 134. Figure 2 At least a portion of 138 () Figure 2 In this process, at least a portion of the hydrocarbon-containing material is converted into disordered graphite. In the case of doping by implantation, the dosage and energy level are specified, and / or the final doping level can be specified. This can be achieved by specifying the number of atoms per square centimeter (atoms / cm²).2 The dosage is specified by the energy level (in keV, or kiloelectron volts), thus obtaining the number of atoms per cubic centimeter (atoms / cm³). 3 The doping level (concentration in the substrate). The number of atoms is usually specified in exponential notation, where a number like "3E15" represents 3 multiplied by 10 to the power of 15, or "3" followed by 15 zeros (3,000,000,000,000,000). For example, per cubic centimeter (cm³). 3 There are approximately 1E23 (100,000,000,000,000,000,000) hydrogen and oxygen atoms in water. An example of doping is an implantation dose of approximately 1E15 to 1E16 atoms / cm². 2 Argon (Ar) with an energy of approximately 500 to 1000 keV is used to produce 1E17 to 1E18 atoms / cm². 3 doping level (atoms / cm) 3 It can also be written as cm 3 Although shown as extending to the entire depth of the hydrocarbon-containing material 134, the injection dosage and energy level can be selected to create an effect in the hydrocarbon-containing material 134. Figure 2 A thermally conductive layer 114 reaches any desired depth within the [structure / process]. In a non-limiting example, the energy and dose could be 900 keV and 5e14 cm⁻¹. 3 500kev and 2e15 cm 3 ; and / or 130 keV and 1e16 cm 3 .

[0036] Figure 3 The diagram also illustrates the conversion of disordered graphite (arrows on the curve) into polycrystalline graphite 140, thereby creating a thermally conductive layer 114. This conversion may include annealing, such as a rapid thermal annealing (RTA) process, and the conversion can have any temperature and duration required to create the polycrystalline graphite 140. In a non-limiting example, the temperature could be at least 900 degrees Celsius and last for approximately 5 minutes. The thermally conductive layer 114 can have a resistivity of at least 50 ohm-cm. Figure 3 It is also shown that, for example, known ashing techniques or appropriate wet etching for hydrocarbon-containing materials are used to remove the mask 136 and hydrocarbon-containing material 134 from the upper part of the trench 132. Figure 2 The remaining portion of the polycrystalline graphite thermal conductive layer 114 is left behind.

[0037] return Figure 1A dielectric layer 112 is formed over the polycrystalline graphite thermally conductive layer 114 to complete the heat dissipation isolation structure 110. The dielectric layer 112 can be formed using any suitable deposition technique for the selected material. The dielectric layer 112 may include any material now known or later developed for providing electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2) (shown), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) comprising silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof. In a particular example, the dielectric layer 112 may include silicon oxide.

[0038] Figure 1 The diagram also illustrates subsequent processing including the formation of gate conductors 142 (three are shown). In one non-limiting example, gate conductors 142 may comprise polysilicon. In another example, gate conductors 142 may comprise a metal gate. Although shown as a single material for clarity, the metal gate may comprise one or more conductive components for providing gate terminals for a transistor. For example, the metal gate may comprise a high-dielectric-constant (high-K) layer, a work-function metal layer, and a conductor layer (not all are shown for clarity). The high-K layer may comprise any now-known or hereafter developed high-K material commonly used for metal gates, such as, but not limited to: metal oxides, such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or metal silicates, such as hafnium silicon oxide (HfO2). A1 Si A2 O A3 ) or hafnium oxynitride (Hf A1 Si A2 O A3 N A4A1, A2, A3, and A4 represent relative proportions, each greater than or equal to zero, and A1 + A2 + A3 + A4 (1 being the total relative molar amount). Depending on whether it is used for an NFET or PFET device, the work function metal layer can include various metals, but may include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polysilicon (poly-Si), and / or combinations thereof. The conductor layer can include any gate conductor now known or developed later, such as copper (Cu). A gate cap (not shown), such as a nitride, may also be formed over the gate. The gate conductor 142 may also include spacers, such as silicon nitride, surrounding it. The gate conductor 142 can be formed over the substrate 104 using any IC manufacturing techniques now known or developed thereafter (e.g., material deposition, photolithographic patterning using a mask, and etching, etc.). Structure 100 includes an active device 102 in the form of a MOS transistor 144. As understood in the art, and as will be described herein, structure 100 is used for a bipolar transistor 146 (… Figure 4 In the case of ), the active region structure and / or its sub-components can be varied.

[0039] The heat dissipation and isolation structure 110 can be used as Figure 1 Several alternative arrangements other than those shown are provided, some of which are illustrated and described below.

[0040] The heat dissipation isolation structure 110 is adjacent to the active device 102. For example... Figure 5-6 As shown in the plan view, the heat dissipation isolation structure 110 can also surround the active device 102. Figure 5 In the middle, the link array of the heat dissipation isolation structure 110 surrounds the active region 124, and in Figure 6 In this configuration, a separate thermal isolation structure 110 surrounds a separate active region 124. Any arrangement of the active device 102 or the active region 124 can be electrically isolated by the thermal isolation structure 110, similar to trench isolation.

[0041] As mentioned above, Figure 4 A thermal isolation structure 110 for a bipolar transistor 146 is shown, and in this example more specifically for a bipolar junction transistor (BJT). Here, the thermal isolation structure 110 extends to contact the substrate semiconductor substrate 122, with one structure 110 adjacent to one (left) portion of the collector 150 and another structure 110 adjacent to another (right) portion of the collector 152. The emitter 154 is located above the base 156.

[0042] Figure 7 A cross-sectional view of a thermal isolation structure 110 in a MOS environment is shown, wherein the thermally conductive layer 114 is located directly above the buried insulating layer 120, i.e., in contact with it. In this case, Figure 2 The trench 132 in the middle does not extend into or through the buried insulation layer 120, but only reaches its surface. Figure 7 Contacts 160 adjacent to the thermal isolation structure 110 are also shown. Contacts 160 can be located in any space, allowing for additional thermal conductivity to the adjacent active region 124 and, for example, the substrate semiconductor substrate 122 and / or the back-end process interconnect layer (dashed box) located above the gate conductor 142 with minimal parasitic losses. Any number of contacts 160 can be provided. Although not shown in all embodiments for clarity, contacts 160 provided for thermal conductivity can be employed in any embodiment described herein. Contacts 160 can be formed using any now-known or later-developed process, such as patterned masks, etching contact openings to appropriate depths, and forming conductors within the openings. The conductors can include a refractory metal liner and a contact metal. Refractory metal liners (not labeled for clarity) can include, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), or mixtures thereof. The contact metal can be any contact metal now known or developed in the future, such as, but not limited to, copper (Cu) or tungsten (W); or it can include polycrystalline silicon.

[0043] Figure 7 It also shows that it has a higher ratio Figure 1 The thermally conductive layer 114 shown has a wider range. This configuration can be achieved by making... Figure 2 The portion 138 exposed by the mask 136 is widened to expose the entire width of the groove 132. Here, in completing relative to Figure 1-3 Following the described steps, the thermally conductive layer 114 extends over at least the entire width of the upper portion of the trench 132 in which the hydrocarbon-containing material 134 is formed. As will be readily appreciated, the thermally conductive layer 114 of any width and / or depth can be formed according to the methods described herein.

[0044] Figure 8 It shows the relationship with Figure 1 A similar cross-sectional view of the thermal isolation structure 110 in a MOS environment is shown, but it illustrates that the gate conductor 142 can also be constructed above the thermal isolation structure 110. Here, the end of the gate conductor 142 extends above the thermal isolation structure 110.

[0045] Figure 9-11A cross-sectional view of a heat dissipation isolation structure 110 in a MOS environment is shown, wherein a thermally conductive layer 114 extends into a substrate semiconductor substrate 122. Here, the thermally conductive layer 114 can directly conduct heat to the substrate semiconductor substrate 122. Figure 9 A thermally conductive layer 114 extending into the substrate semiconductor substrate 122 is shown; Figure 10 Two heat dissipation isolation structures 110 are shown, with thermally conductive layers 114 extending into a substrate semiconductor substrate 122, wherein the lower surface 162 of each thermally conductive layer 114 contacts a corresponding through semiconductor via (TSV) 164 in the substrate semiconductor substrate 122; and Figure 11 Two thermal isolation structures 110 are shown, each having a thermally conductive layer 114 extending into a substrate semiconductor substrate 122, wherein the lower surface 162 of the thermally conductive layer 114 contacts a single TSV 164 within the substrate semiconductor substrate 122. The TSV 164 provides additional thermal conductivity through and / or out of the substrate semiconductor substrate 122. The TSV 164 can be formed using any process now known or developed later. The thermally conductive layer 114 can be arranged in any configuration to contact the TSV 164. Figure 9-11 In the embodiments, the formation of the thermally conductive layer 114 may require multiple applications of the hydrocarbon-containing material 134 into the trench and its injection (as opposed to...). Figure 2-3 (as described) to achieve the desired thickness.

[0046] Figure 12 A cross-sectional view of another embodiment is shown, wherein a thermal isolation structure 110 is located above a trench isolation 166 (e.g., silicon oxide) between active regions 124A-C in an SOI layer 118. Here, a dielectric layer 112 is formed over a nitride layer 168 above a thermally conductive layer 114. Contacts 160 may provide additional thermal conductivity to the underlying substrate semiconductor substrate 122 and / or the upper BEOL layer 169. Figure 12 The embodiments can be similar to those relative to Figure 1-3 The described material is formed, but without trench 132 and hydrocarbon-containing material 134 is formed above trench isolation 166. Figure 2 The mask 136 will expose the SOI layer 118 and the portion 138 above the trench isolation 166 therein, which has any desired width.

[0047] Figure 13-15 A cross-sectional view of another embodiment of a heat dissipation isolation structure 110 located above a bulk semiconductor substrate 170 in a bipolar environment is shown. Figure 13 A heat dissipation isolation structure 110 is shown located below the base 172 (with the emitter 174 above it) and above the bulk semiconductor substrate 170. Figure 14A heat dissipation isolation structure 110 is shown, located below the base 176 (with the emitter 178 above it) and above the bulk semiconductor substrate 170, above the trench isolation 179. Figure 15 A heat dissipation isolation structure 110 is shown in an SOI substrate 116 having a lateral bipolar transistor 180 and an adjacent NPN portion 182 (dashed box). The NPN portion 182 is located in the SOI layer 118 of the SOI substrate 116 (shown as being mostly replaced by trench isolation and the NPN portion 182).

[0048] like Figure 1 As shown, the embodiment also includes a heat dissipation isolation structure 110 located in a trench 132 of the substrate 104 and adjacent to the active device 102 on the substrate, and includes a body 190 comprising a dielectric layer 112 and a polycrystalline graphite thermally conductive layer 114 located below the dielectric layer 112. As described herein, the substrate 104 may be in the form of an SOI substrate 116 and includes an SOI layer 118 above a buried insulating layer 120 located above a substrate semiconductor substrate 122. Alternatively, the substrate 104 may include a bulk semiconductor substrate 170 ( Figure 13-14 The main body 190 can extend through the buried insulation layer 120, and as... Figure 5-6 As shown, the body 190 may surround the active device 102. Alternatively, the body 190 may be located above, through, and in contact with the substrate 104 (e.g., the substrate semiconductor substrate 122), or through it and into the substrate 104. Figure 10-11 As shown, the lower surface 162 of the polycrystalline graphite thermal conductive layer 114 can contact the TSV 164 in the substrate 104 (e.g., the substrate semiconductor substrate 122). The polycrystalline graphite thermal conductive layer 114 can have a resistivity of at least about 50 ohm-cm.

[0049] While discrete embodiments of the present disclosure have been described herein, it is to be emphasized that various features of each embodiment may be used in other embodiments to achieve arrangements not expressly described herein but within the scope of the present disclosure.

[0050] Embodiments of the thermal isolation structure 110 provide a short path of conduction through the dielectric without the electrical / parasitic costs of other solutions. More specifically, a polycrystalline graphite thermally conductive layer 114 provides a heat sink material adjacent to the active device in the SOI or bulk substrate. The thermally conductive layer 114 can be created at various locations and in various arrangements, such as a ring buried above or within the insulator 106 and / or around the active device, to conduct heat away from the device, and may be directed toward contacts thermally connected to the substrate and / or BEOL layer. In either case, heat conduction has a shorter path through the dielectric with minimal electrical / parasitic losses through a better thermal conductor.

[0051] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0053] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximately,” and “substantially” are not limited to specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. An “approximate” term applied to a specific value within a range applies to both values ​​and may indicate + / - 10% of said value unless otherwise dependent on the precision of the instrument used to measure the value.

[0054] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A semiconductor structure, comprising: an active device located over a region of a substrate, wherein the substrate comprises a semiconductor-on-insulator (SOI) layer located over a buried insulating layer over a base semiconductor substrate; a heat spreading isolation structure adjacent to the active device, wherein the heat spreading isolation structure comprises a dielectric layer located over and abutting an upper surface of a thermally conductive layer, and wherein the upper surface of the thermally conductive layer is concave and a lower surface of the thermally conductive layer extends into the base semiconductor substrate; and a heat spreading semiconductor through via (TSV) adjacent to the heat spreading isolation structure and located within the base semiconductor substrate, wherein the lower surface of the thermally conductive layer located within the base semiconductor substrate contacts an upper surface of the heat spreading semiconductor through via (TSV) located within the base semiconductor substrate.

2. The semiconductor structure of claim 1, wherein, The heat spreading isolation structure is located between two portions of the SOI layer.

3. The semiconductor structure of claim 1, wherein, The upper surface of the thermally conductive layer is not coplanar with an upper surface of the SOI layer.

4. The semiconductor structure of claim 1, wherein, The heat spreading isolation structure extends through the buried insulating layer.

5. The semiconductor structure of claim 1, wherein, The thermally conductive layer has a resistivity of at least 50 ohm-cm.

6. The semiconductor structure of claim 1, wherein, The thermally conductive layer comprises polycrystalline graphite.

7. The semiconductor structure of claim 1, further comprising a contact adjacent to the heat spreading isolation structure.

8. The semiconductor structure of claim 1, wherein, The active device is a metal-oxide-semiconductor (MOS) transistor.

9. The semiconductor structure of claim 1, wherein, The active device is a bipolar transistor.

10. The semiconductor structure of claim 1, wherein, The heat spreading isolation structure surrounds the active device.

11. A heat spreading isolation structure, comprising: a body located in a trench of a substrate and adjacent to an active device on the substrate, wherein the substrate comprises a semiconductor-on-insulator (SOI) layer located over a buried insulating layer over a base semiconductor substrate, the body comprising: a dielectric layer; and a polycrystalline graphite thermally conductive layer located below the dielectric layer, wherein the dielectric layer abuts an upper surface of the polycrystalline graphite thermally conductive layer, and wherein a lower surface of the polycrystalline graphite thermally conductive layer extends into the base semiconductor substrate, and wherein the lower surface of the polycrystalline graphite thermally conductive layer located within the base semiconductor substrate is not planar.

12. The heat dissipation isolation structure of claim 11, wherein, The body extends through the buried insulating layer.

13. The heat dissipation isolation structure of claim 12, wherein, The lower surface of the polycrystalline graphite thermally conductive layer contacts a semiconductor through via (TSV) in the base semiconductor substrate.

14. The heat dissipation isolation structure of claim 12, wherein, The polycrystalline graphite thermally conductive layer has a resistivity of at least 50 ohm-cm.

15. The heat dissipation isolation structure of claim 12, wherein, The body surrounds the active device.

16. A method for forming a semiconductor structure, comprising: forming a trench in a substrate, the substrate comprising a semiconductor-on-insulator (SOI) layer located over a buried insulating layer over a base semiconductor substrate, the trench between adjacent semiconductor active regions; forming a hydrocarbon-containing material in the trench; introducing a dopant into at least a portion of the hydrocarbon-containing material in the trench to convert the at least a portion of the hydrocarbon-containing material to disordered graphite; converting the disordered graphite into a polycrystalline graphite thermal conducting layer, wherein an upper surface of the polycrystalline graphite thermal conducting layer is concave and a lower surface of the polycrystalline graphite thermal conducting layer extends into the base semiconductor substrate, and wherein the lower surface of the polycrystalline graphite thermal conducting layer located within the base semiconductor substrate contacts an upper surface of a heat spreading semiconductor through via TSV located within the base semiconductor substrate; and forming a dielectric layer over the polycrystalline graphite thermal conducting layer, wherein the dielectric layer abuts the upper surface of the polycrystalline graphite thermal conducting layer.

17. The method of claim 16, wherein, The hydrocarbon-containing material comprises a positive photoresist material.

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