Semiconductor device and method of manufacturing semiconductor device

By designing conductive bonding patterns and dielectric layer structures in semiconductor devices, the problem of difficult conductive pattern alignment is solved, thereby improving the reliability and process stability of semiconductor devices.

CN114639657BActive Publication Date: 2025-10-21SK HYNIX INC
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Patent Information

Application Number
CN202110835730.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-12-16
Filing Date
2021-07-23
Publication Date
2025-10-21
Estimated Expiration
2041-10-21

AI Technical Summary

Technical Problem

As the critical size of conductive patterns in semiconductor devices decreases, it becomes more difficult to align conductive bonding patterns, leading to increased process defects and reduced reliability of semiconductor devices.

Method used

The conductive bonding pattern design includes a contact portion and a pad portion. The contact portion connects to the conductive pattern through an etch stop layer, and the pad portion extends from the contact portion and is wider than the contact portion. The dielectric layer design is combined to stably align and connect the conductive pattern. Contact holes are formed by etching and filled with the conductive bonding pattern.

Benefits of technology

It improves the reliability of semiconductor devices, reduces process defects, and ensures stable alignment and connection of conductive patterns.

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Abstract

The present application relates to semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor memory device and a method of manufacturing a semiconductor memory device are provided. The semiconductor memory device includes a conductive pattern, an etching stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern and a pad portion extending from the contact portion, a first dielectric layer disposed on the etching stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etching stop layer and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
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Citation Information

Patent Citations

  • Semiconductor devices and methods of fabricating the same

    US20180198059A1