Bus system and method for operating a bus system

Abstract

A bus system (1) comprises a first bus (11) and a second bus (12), wherein the first bus (11) is connected to the second bus (12) via a bridge (15) and a multiplexer (16). A first master controller (110) has access to the second bus (12) via the first bus (11), the bridge (15) and the multiplexer (16). A second master controller (120) has access to the second bus (12) via the multiplexer (16). The bridge (15) comprises an arbitration unit (150) configured to allow the first master controller (110) and the second master controller (120) to access the second bus (12) in a manner that does not interfere with or lose access.

Description

[0001] The present disclosure relates to a bus system and a method for operating a bus system.

[0002] A bus system is a digital communication system that transfers data between components inside a processing device (e.g., a computer, a mobile device, a portable watch, or a tablet) or between multiple processing devices. A bus system may include multiple buses, wherein a second bus may be subordinate to a first bus. The components between which data is transferred may include peripheral devices. Here and hereinafter, a peripheral device connected to a first bus is referred to as a first peripheral device, and a peripheral device connected to a second bus is referred to as a second peripheral device.

[0003] The bus system may be based on a so-called Advanced Microcontroller Bus Architecture (AMBA), which includes an Advanced High-Performance Bus (AHB) as a first bus and an Advanced Peripheral Bus (APB) as a second bus. The bus system is timed with the aid of a clock signal. Typically, AMBA defines and requires two clock cycles to access a second peripheral device via AHB and APB. Therefore, the second peripheral device can only be accessed every other clock cycle. Therefore, the maximum data rate on APB is limited to 50% of the maximum data rate of AHB. Most second peripheral devices utilize flip-flops and synchronous memories as storage elements, so that the second peripheral device can access APB in a single clock cycle. Therefore, in a conventional APB, the second peripheral device is idle at least 50% of the time.

[0004] One of the objects of the present bus system is to allow a higher data rate when transferring data via the bus system. Another object is to reduce the idle state time of the second peripheral device. These objects are achieved by the subject matter of the independent claims.

[0005] The bus system includes a first bus and a second bus. The first bus is connected to the second bus via a bridge and a multiplexer. A first master has access to the second bus via the first bus, the bridge and the multiplexer. A second master has access to the second bus via the multiplexer. The bridge includes an arbitration unit, which is configured to determine whether access to the second bus is authorized to the first master or the second master.

[0006] The arbitration unit may be configured to coordinate access of the first master controller and the second master controller to the second bus. For example, the arbitration unit is configured to prevent the first master controller and the second master controller from accessing the second bus at the same time. This improves the utilization of the second bus transmission rate, which improves the data rate when transmitting data through the bus system. In addition, the increase in the utilization of the transmission rate of the second bus reduces the idle state time of the second peripheral device.

[0007] The bus system includes a first bus with a first master controller and a second bus with a second master controller. For example, the first bus is AHB and the second bus is APB. The first master controller can be an AHB master controller and the second master controller can be an APB master controller. For example, the first bus and the second bus are both parallel buses. The second master controller can provide serial-to-parallel conversion data of a serial bus, wherein the serial bus can be based on an I2C bus (I-Squared-C bus), an SPI bus or a UART bus. For example, an on-chip I2C slave (on-chip I-Squared-C slave) is used as the second master controller. The APB register on the second bus can be accessed by an off-chip I2C master controller (off-chip I-Squared-C master).

[0008] The first bus is connected to the second bus via a bridge and a multiplexer. The bridge converts transmissions (read or write) between the first bus and the second bus. For example, the bridge is a modified AHB to APB bridge that converts AHB bus transmissions to APB bus transmissions. The bridge can have a fixed width of one word, which means that the bits written cannot be less than the width of the bridge. For example, an 8-bit portion of a 32-bit APB register cannot be written. The bridge can act as a slave of the first bus or as a master of the second bus. For example, the bridge includes an arbitration unit that is configured to determine whether access to the second bus is authorized to the first master or the second master.

[0009] The first master controller has access to the second bus via the first bus, the bridge and the multiplexer. The second master controller has access to the second bus via the multiplexer. The multiplexer is arranged downstream of the bridge and the second master controller. The bridge controls the multiplexer, through which the data of the first master controller or the second master controller is transmitted to the second bus. In a specific embodiment, the bridge can be adapted to enable the second master controller to access the second bus at any time, regardless of whether the first master controller accesses the second bus. With the aid of the bridge, access to the second bus can be determined without having an access mode bit in the address data sent by the first bus or the second bus. Advantageously, an increased data rate on the second bus is achieved. In addition, the idle state time of the peripheral device is reduced.

[0010] The second master controller can be arranged to control and monitor the second peripheral device independently of the first master controller. For example, the second master controller is arranged to control and monitor the register connected to the second bus. For example, the second master controller reads the data provided by the second peripheral device to monitor the second peripheral device. For example, the second master controller writes the data to the second bus, and the data is read by the second peripheral device. Advantageously, the reliability is improved by checking the second peripheral device through the control and monitoring of the second bus. For example, the second peripheral device can be controlled during the operation of the bus system without accessing the first bus. In addition, the second master controller can advantageously be arranged to provide backdoor access to the second bus for test mode.

[0011] According to one embodiment, the arbitration unit includes a request input terminal, a grant output terminal and a ready output terminal. The input terminal and the output terminal are interfaces for transmitting digital signals. The digital signal can have an active state and an inactive state, wherein the active state can be represented by a logic value of 0 and the inactive state can be represented by a logic value of 1, and vice versa.

[0012] By default, the arbitration unit transmits the ready signal to the first master controller via the ready output. In particular, the arbitration unit is adapted to send the ready signal to the first master controller via the ready output. For example, whenever the second master controller is authorized to access the second bus, the arbitration unit is adapted to set the ready signal to an invalid state. After the second master controller is authorized to access the second bus, the ready signal is set to an invalid state for one clock cycle. The access of the second master controller to the second bus suspends the access of the first master controller to the second bus.

[0013] The second master controller is adapted to send the request signal to the arbitration unit via the request input, and the arbitration unit is adapted to send the authorization signal to the second master controller via the authorization output. For example, the second master controller is adapted to set the request signal to an activated state before accessing the second bus. If access to the second bus is authorized to the second master controller, the arbitration unit is adapted to set the authorization signal to an activated state. The arbitration unit is adapted to set the authorization signal to an activated state at least 1 or 2 clock signal cycles after the request signal is activated. The arbitration unit is adapted to set the authorization signal to an inactive state 1 or 2 clock cycles after the request signal is inactive.

[0014] Advantageously, the arbitration unit is adapted to centrally determine access to the second bus to avoid conflicts of signals from the first master and the second master on the second bus.

[0015] According to one embodiment, the grant output is connected to the select input of a multiplexer. The multiplexer is adapted to connect the first master to the second bus when the grant signal is in an inactive state, and the multiplexer is adapted to connect the second master to the second bus when the grant signal is in an active state. Advantageously, the grant signal has multiple functions, firstly, the grant signal controls the multiplexer to enable the connection between the first master or the second master and the second bus, and secondly, the grant signal indicates whether the second master can access the second bus.

[0016] According to one embodiment, the arbitration unit is adapted to stop and postpone access of the first master to the second bus if the first master addresses a peripheral device connected to the second bus while the grant signal is active. The arbitration unit may be adapted to establish access of the first master to the second bus after the access of the second master to the second bus is completed. In particular, this is one clock cycle after the grant signal is deactivated.

[0017] For example, the arbitration unit stores the addressing of the second peripheral device, continues and completes the stopped access. For example, the arbitration unit includes a storage element, which caches the addressing data and transmission data sent by the first master controller to the second peripheral device. For example, the arbitration unit is configured to set the ready signal to a failed state whenever the authorization signal is in an active state. After the authorization signal is set to a failed state, the ready signal is set to an activated state for a clock cycle. The first master controller pauses by default until the ready signal returns to an activated state. After the authorization signal is set to a failed state and the ready signal is set to an activated state, the arbitration unit can be adapted to provide the cached addressing data and transmission data to the second bus. Advantageously, the ready signal ensures that the data sent by the first master controller through the second bus will not conflict with the data sent by the second master controller through the second bus. In other words, the bridge ensures that the first master controller and the second master controller will not write / read data on / from the second bus at the same time. Therefore, data loss is avoided and a high data rate through the second bus is achieved.

[0018] The bus system according to one of the embodiments defined above can be implemented in a noise cancellation enabled audio system, such as an audio system with active noise cancellation activated. The noise cancellation enabled audio system can be any ear-worn playback device of the noise cancellation enabled audio system, and can for example include in-ear headphones or earbuds, on-ear headphones or over-ear headphones. In addition to headphones, the ear-worn playback device can also be a mobile phone or similar device.

[0019] A method for operating a bus system is also provided. For example, the bus system described herein can be operated by the method. That is, all features disclosed for the bus system are also disclosed for the method, and vice versa.

[0020] According to one embodiment of a method for operating a bus system, the bus system includes a first master controller, a first bus, a second master controller, and a second bus, wherein the first master controller accesses the second bus via the first bus, a bridge, and a multiplexer, and the second master controller is connected to the second bus and the bridge, wherein the bridge has an arbitration unit that authorizes access to the second bus by the first master controller or the second master controller.

[0021] The method comprises the steps of accessing a second bus via the first bus by means of a first master or by means of a second master, wherein the first bus and the second bus are clocked by means of a common clock signal.

[0022] According to one embodiment, the clock signal defines an addressing phase and a transmission phase. Successive clock cycles may define an addressing phase and a transmission phase alternately or in parallel with each other. For example, each access of the first master controller includes an addressing phase and a subsequent transmission phase.

[0023] During the addressing phase, the first master or the second master can send data identifying a second peripheral device connected to the second bus and to / from which data will be transferred. In the transfer phase, data is transferred between the second peripheral device addressed in the previous addressing phase and the master having access to the second bus.

[0024] The second master can send data identifying a second peripheral device connected to the second bus and transfer data from / to the peripheral device in the same clock cycle. This results in a shorter access time for the second master whenever the second peripheral device does not contain an asynchronous memory.

[0025] The arbitration unit can control the second master controller with the aid of the authorization signal. For example, addresses and data are transmitted between the second master controller and the peripheral device only when the authorization signal is in an activated state. For example, by default, the authorization signal is in an invalid state. By setting the request signal to an activated state, the authorization signal can be in an activated state in a first clock cycle or a second clock cycle after the second master controller sends a request to the arbitration unit. The arbitration unit allows the second master controller to access the second bus, even if the second bus is addressed or data is transmitted between the first master controller and the second peripheral device through the second bus. The arbitration unit will suspend the first master controller's access to the second bus until the second master controller completes the access.

[0026] If the first master controller addresses the second peripheral device and the second master controller accesses the second bus at the same time, the arbitration unit postpones the access of the first master controller to the second bus. For example, the arbitration unit provides a ready signal, which pauses the first master controller when the ready signal is in an invalid state. For example, by default, the ready signal is in an active state. If the first master controller addresses a peripheral device connected to the second bus, the arbitration unit activates the ready signal for one clock cycle after transmitting the address. If the second master controller also accesses the second bus at the same time as the first master controller accesses the second bus, the arbitration unit can extend the invalid state of the ready signal by one or more clock cycles.

[0027] According to one embodiment of the method, the first master may access the first peripheral device, and the second master may access the second peripheral device simultaneously.

[0028] When the ready signal is in the inactive state, the addressing of the peripheral device by the first master controller is stored until the ready signal is set back to the active state. After the second master controller completes the access to the second bus, the ready signal is in the active state.

[0029] In other words, after the second master controller completes the access, the arbitration unit authorizes the first master controller to access the peripheral device through the second bus.

[0030] According to one aspect of the proposed principle, the second master controller uses the idle time of the first master controller to access the second bus. By doing so, the original idle state time will decrease according to the number of accesses of the second master controller. This will improve system performance.

[0031] In other words, the access of the second master is performed using an idle time of the first master's access to the second bus to access the second bus.

[0032] According to one embodiment, timing gaps in the APB bus protocol are used to achieve higher data throughput than provided by the default APB protocol.

[0033] According to another aspect of the proposed principles, the second master is capable of operating autonomously, ie independently of any control performed by the first master.

[0034] Further advantages and advantageous refinements and further developments of the bus system and of the method for operating a bus system result from the exemplary embodiments illustrated below in conjunction with the drawings.

[0035] The same, similar or equivalent elements in the drawings are provided with the same reference numerals. The drawings and the mutual proportions of the elements shown in the drawings should not be considered to be drawn to scale. On the contrary, the size of individual elements can be exaggerated for better presentation and / or better comprehensibility.

[0036] Figure 1 A schematic view of an exemplary embodiment of a bus system 1 is shown. The bus system 1 comprises a first bus 11 with a first master 110, a second bus 12 with a second master 120, a bridge 15 and a multiplexer 16. The bus system 1 is arranged to transmit data between the first master 110 and the first peripheral device 10 and / or the second peripheral device 20. The bus system 1 is arranged to transmit data between the second master 120 and the second peripheral device 20. The data can be provided to the first master 110 and / or the second master 120 respectively via their respective data inputs 600. Each data input 600 can carry a separate signal. The data is transmitted via the first bus 11 and / or the second bus 12. In order to time the access of the second bus 12, the signal is transmitted between the first master 110 and the bridge 15, the second master 120 and the bridge 15, and the multiplexer 16 and the bridge 15. In this exemplary embodiment, a digital signal having a logic value of 1 is referred to as being in an active state, and a digital signal having a logic value of 0 is referred to as being in an inactive state.

[0037] The first bus master 110 and the second bus master 120 are arranged to access the second bus 12. Accessing the bus comprises addressing the peripherals 10, 20 connected to the bus 11, 12 being accessed and transferring data to or from the peripherals. The bus system 1 comprises a first peripheral 10 connected to the first bus 11 and a second peripheral 20 connected to the second bus 12. The first peripheral 10 and the second peripheral 20 are, for example, registers, memory units, sensors or actuators.

[0038] The bridge 15 includes an arbitration unit 150, which determines whether the first master controller 110 or the second master controller 120 has the right to access the second bus 12. The bridge includes a request input terminal 151 and a grant output terminal 152. The second master controller 120 is connected to the request input terminal 151. The second master controller 120 is configured to send a request signal 151a to the arbitration unit 150 before sending data to the second bus 12. By default, the request signal 151a is in an invalid state. The arbitration unit 150 returns a grant signal 152a through the grant output terminal 152. Depending on whether the second bus is currently being accessed, the grant signal 152a is either in an activated state or in an invalid state. By default, the grant signal 152a is in an invalid state.

[0039] The grant output 152 is connected to the select input 163 of the multiplexer 16. If the grant signal 152a is in an active state, the first port 161 of the multiplexer is coupled to the bus port 164 of the multiplexer. If the grant signal 152b is in an inactive state, the second port 162 of the multiplexer 16 is coupled to the bus port 164. Data is transmitted from or to the second bus 12 via the bus port 164 of the multiplexer 16.

[0040] The bridge 15 includes a ready output 153, which is configured to send a ready signal 153a to the first master 110. If the ready signal 153a is in an active state, the first master 110 is in a normal operation mode and reads and writes data through the first bus 11. If the ready signal is in an inactive state, the first master 110 is suspended and does not read or write data through the first bus until the ready signal 153a is set to an active state. By default, the ready signal 153a is in an inactive state.

[0041] The bridge 15 comprises a first data link 154 and a second data link 155. In particular, the first bus 11 and the first data link 154 and the second data link 155 and the second port 162 are connected by means of a further bus. The bridge 15 is arranged to read and write data on the first bus 11 via the first data link 154. The bridge 15 is arranged to read and write data on the second bus 12 via the second data link 155.

[0042] The bus system 1, for example the first bus 11 and the second bus 12, is timed by means of a clock signal 500. The clock signal 500 is applied to the first master 110 and the second master 120. For example, the first bus 11 and the second bus 12 are timed by means of a common clock signal 500. The clock signal defines an addressing phase 501 and a transmission phase 502. During the addressing phase 501, the first master 110 and / or the second master 120 writes data onto the first bus 11 and / or the second bus 12, wherein the data identifies the peripheral device 10, 20. During the transmission phase 502, the peripheral device 10, 20 reads data from the first bus 11 and / or the second bus 12 or writes data to the first bus and / or the second bus.

[0043] In the method for operating the bus system 1, the second bus 12 is accessed either by the first master 110 via the first bus 11, the bridge 15 and the multiplexer 16, or by the second master 120 via the multiplexer 16. The first master 110 and / or the second master 120 addresses the second peripheral device during the addressing phase 501.

[0044] In order to address the second peripheral device 20, the first master controller 110 writes the address data of the second peripheral device 20 to the first peripheral device 11. The bridge 15 transmits the address data to the second port 162 of the multiplexer 16 through the first data link 154 and the second data link 155. If the second master controller 120 has no right to access the second bus 12, the grant signal 152a is in a failed state, and the multiplexer 16 transmits the address data from the first master controller 110 to the second bus 12. The address data from the first master controller 110 arrives at the second peripheral device 20. If the second master controller 120 has the right to access the second bus 12 when the first master controller 110 addresses the second peripheral device 20, the ready signal 153a remains in a failed state for one or more clock cycles when the first master controller has started write / read access. The failed state ready signal 153a stops the first master controller 110 until the ready signal 153a is set to an active state. After the second master 120 completes access to the second bus 12 , the arbitration unit 150 sets the ready signal 153 a to an active state. After the second master 120 completes access to the second bus 12 , the first master 110 accesses the second bus 12 .

[0045] In order to access the second bus 12, the second master controller 120 sets the request signal 151a to an active state. If the first master controller 110 does not access the second bus 12, the arbitration unit 150 sets the grant signal 152a to an active state. After receiving the grant signal 152a in the active state, the second master controller 120 sends the address data to the first port 161 of the multiplexer 16. The grant signal 163a in the active state is transmitted to the selection input terminal 163 of the multiplexer 16. Therefore, the multiplexer 16 transmits the address data from the second master controller 120 to the second bus 12 through the first port 161 and the bus port 164.

[0046] Figure 2 700 shows a timing diagram of an exemplary embodiment of a bus system. The timing diagram shows the timing of different signals within the bus system during time 700. Figure 2 , the diagram shows access of the first master 110 to the second bus 12. During a first cycle 1 of a clock signal 500, the first master 110 sends address data 503 to the first bus 11.

[0047] If the address data 503 is a valid address of the second peripheral device 20, the bridge 15 deactivates the ready signal 153a during the second clock cycle 2, i.e., the addressing phase 501. This will halt the first master 110 during the second clock cycle 2. In the addressing phase 501, the bridge 15 links the first bus 11 and the second bus 12.

[0048] In the third clock cycle 3, the bus system is in the transmission phase 502. In this clock cycle 3, the bridge activates the bus enable signal 12a on the second bus 12, which enables data to be transmitted through the second bus 12. The enable signal 12a activates both the address and data links for read or write access from / to the first master 110 to the second bus 12.

[0049] Figure 3 700 shows a timing diagram of an exemplary embodiment of a bus system. The timing diagram shows the timing of different signals within the bus system during time 700. Figure 3 In the embodiment shown, the second master 120 accesses the second bus 12 in one clock cycle. In this embodiment, the addressing phase 501 and the transmission phase 502 are combined.

[0050] In the first clock cycle 1, the second master controller 120 requests access by activating the request signal 151a. In the second clock cycle 2, the request signal 151a causes the bridge 15 to activate the grant signal 152a. If the first master controller 110 performs a write access to the second peripheral device 20 alone, the grant signal 152a is activated in the second cycle 2. The activated grant signal 152a activates the bus enable signal 12a on the second bus for one clock cycle. The bus enable signal 12a will activate both the address and data links for read access or write access to the second bus 12 from / to the second master controller 120.

[0051] Figure 4 700 shows a timing diagram of an exemplary embodiment of a bus system. The timing diagram shows the timing of different signals within the bus system during time 700. Figure 4 In the embodiment shown, the second master 120 accesses the second bus 12 in one clock cycle. In this embodiment, the addressing phase 501 and the transmission phase 502 are combined.

[0052] In the first clock cycle 1, the second master controller 120 requests access by activating the request signal 151a. In the third clock cycle 3, the request signal 151a causes the bridge 15 to activate the grant signal 152a. If the first master controller 110 performs read access to the second peripheral device 20 alone, the grant signal 152a is not activated in the second cycle to allow the first master controller to complete the read access to the second peripheral device 20. The grant signal is activated in the third cycle 3. The activated grant signal 152a activates the bus enable signal 12a on the second bus for one clock cycle. The bus enable signal 12a will activate both the address and data links for read access or write access to the second bus 12 from / to the second master controller 120.

[0053] Figure 5 and Figure 6 Shows Figure 3 and Figure 4 Alternative timing diagram for .

[0054] Figure 5 700 shows a timing diagram of an exemplary embodiment of a bus system. The timing diagram shows the timing of different signals within the bus system during time 700. Figure 5 In the embodiment of FIG. 5 , the second master controller 120 accesses the second bus 12 within two clock cycles (ie, an addressing phase 501 and a subsequent transmission phase 502 ).

[0055] In the first clock cycle 1 , the second master 120 requests access by activating the request signal 151 a .

[0056] The request signal 151a causes the bridge 15 to activate the grant signal 152a in the second clock cycle 2 and the third clock cycle 3. If the first master 110 alone performs a write access to the second peripheral device, the grant signal 152a is activated in the second clock cycle 2.

[0057] The activated grant signal 152a lasts for two clock cycles and activates the bus enable signal 12a on the second bus 120 in the third clock cycle 3. In clock cycle 2, the address and data links for read or write access from / to the second bus 12 are activated. The bus enable signal 12a activates both the address and data links for read access or write access to the second bus 12 from / to the second master 120.

[0058] Figure 6 700 shows a timing diagram of an exemplary embodiment of a bus system. The timing diagram shows the timing of different signals within the bus system during time 700. Figure 6 In the embodiment of FIG. 5 , the second master controller 120 accesses the second bus 12 within two clock cycles (ie, an addressing phase 501 and a subsequent transmission phase 502 ).

[0059] In the first clock cycle 1, the second master 12 requests access by activating the request signal 151a.

[0060] The request signal 151a causes the bridge 15 to activate the grant signal 152a in the third clock cycle 3 and the fourth clock cycle 4. If the first master 110 alone performs a read access from the second peripheral device 20, the grant signal 152a is activated in the third clock cycle 2.

[0061] The activated grant signal 152a lasts for two clock cycles and activates the bus enable signal 12a on the second bus 120 in the fourth clock cycle 4. In clock cycle 3, the address and data links for read or write access from / to the second bus 12 are activated. The bus enable signal 12a activates both the address and data links for read access or write access to the second bus 12 from / to the second master 120.

[0062] Figure 7 A timing diagram of an exemplary embodiment of a bus system is shown. In particular, Figure 7 The dependency of the ready signal 153a on the grant signal 152a is shown. In the first clock cycle 1, the bridge 15 deactivates the ready signal 152a while the grant signal 152a is activated. If the grant signal 152a is deactivated in the first clock cycle 1, the bridge 15 keeps the ready signal 153a deactivated until the end of the second clock cycle 2. If the grant signal 152a is deactivated in the second clock cycle 2 (dashed line), the bridge 15 keeps the ready signal 153a deactivated until the end of the third clock cycle 3 (dashed line). Therefore, after the grant signal 152a is deactivated, the bridge 15 keeps the ready signal 153a deactivated for the duration of an additional clock cycle.

[0063] Figure 8 A timing diagram of an exemplary embodiment of a bus system is shown. In this embodiment, both the first master 110 and the second master 120 attempt to access the second bus 12 within a first clock cycle 1 .

[0064] In the first clock cycle 1, the first master 110 starts a write access by applying the address 503 to the first bus 11. The second master 120 also starts an access in the first clock cycle 1 by activating the request signal 151a.

[0065] In the second clock cycle 2, the first master 110 has already started the write access, so the grant signal 152a and the enable signal 12a are activated in the second cycle 2. This time sequence is similar to Figure 3 The activated grant signal 152a activates the bus enable signal 12a on the second bus 12, which activates both the address and data link for read access and write access from the second master 120 to the second bus 12. The address 503 sent by the first master 110 is stored by the bridge 15.

[0066] In the third clock cycle 3, the ready signal 153a is still deactivated, which halts the first master 110. The bridge 15 sends the previously stored address 503 from the first master 110 to the second bus 12.

[0067] In the fourth clock cycle 4 , the bridge 15 activates a bus enable signal 12 a on the second bus 12 , which activates both the address and data links for read access to the second bus 12 from the first master 110 .

[0068] Description of Reference Numerals

[0069] 1 First clock cycle

[0070] 2 Second clock cycle

[0071] 3 Third clock cycle

[0072] 4 Fourth clock cycle

[0073] 10 First peripheral device

[0074] 11 First Bus

[0075] 12 Second bus

[0076] 12a Bus enable signal for the second bus

[0077] 15 Bridge

[0078] 16 Multiplexer

[0079] 20 Second peripheral device

[0080] 110 First Master Controller

[0081] 120 Second master controller

[0082] 150 Arbitration Units

[0083] 151 Request input

[0084] 151a Request signal

[0085] 152 Authorization output

[0086] 152a Authorization signal

[0087] 153 Ready output

[0088] 153a Ready signal

[0089] 154 First Data Link

[0090] 155 Second Data Link

[0091] 161 First Port

[0092] 162 Second Port

[0093] 163 Select input

[0094] 164 bus ports

[0095] 500 Clock signal

[0096] 501 Addressing Phase

[0097] 502 Transmission Phase

[0098] 503 Address Data

[0099] 504 Transfer Data

[0100] 600 Data input terminal

[0101] 700 hours

Claims

1. A bus system (1), comprising a first bus (11) and a second bus (12), wherein - the second bus (12) is an APB peripheral bus, - said first bus (11) is connected to a second bus (12) via a bridge (15) and a multiplexer (16), - a first master controller (110) has access to a second bus (12) via the first bus (11), a bridge (15) and a multiplexer (16), the first master controller (110) being an AHB master controller, a second master (120) having access to the second bus (12) via the multiplexer (16), the second master (120) being an APB master, the second master (120) being arranged to operate autonomously, i.e. to control and monitor the second peripheral device (20) independently of any control performed by the first master, The bridge (15) comprises an arbitration unit (150) configured to determine whether access to the second bus (12) is granted to the first master controller (110) or to the second master controller (120), wherein: The arbitration unit (150) is configured to prevent the first master controller (110) and the second master controller (120) from accessing the second bus (12) at the same time, thereby improving the utilization rate of the transmission rate of the second bus (12), which reduces the idle state time of a peripheral device (also called a second peripheral device (20)) connected to the second bus (12).

2. The bus system (1) according to claim 1, wherein the arbitration unit (150) controls the multiplexer (16).

3. The bus system (1) according to claim 1, wherein - the arbitration unit (150) comprises a request input terminal (151), a grant output terminal (152) and a ready output terminal (153), - the arbitration unit (150) is adapted to transmit a ready signal (153a) to the first master controller (110) via a ready output terminal (153), - the second master controller (120) is adapted to transmit a request signal (151a) to the arbitration unit (150) via a request input (151), and The arbitration unit (150) is adapted to transmit a grant signal (152a) to the second master controller (120) via a grant output terminal (152).

4. The bus system (1) according to claim 3, wherein - the grant output (152) is connected to the select input (163) of the multiplexer (16), - the multiplexer (16) is adapted to connect the first master (110) to the second bus (12) when the grant signal (152a) is in a deactivated state, - the multiplexer (16) is adapted to connect the second master (120) to the second bus (12) when the grant signal (152a) is in an active state.

5. The bus system (1) according to claim 3 or 4, wherein the arbitration unit (150) is suitable for setting the ready signal (153a) to an invalid state or extending the invalid state of the ready signal (153a) when the second master controller (120) has the right to access the second bus (12).

6. The bus system (1) according to claim 5, wherein the arbitration unit (150) is adapted to stop and postpone the access of the first master (110) to the second bus (12) if the first master (110) addresses a second peripheral device (20) connected to the second bus (12) while the second master (120) has the right to access the second bus (12), and The arbitration unit (150) is adapted to establish the access of the first master (110) to the second bus (12) after the access of the second master (120) to the second bus (12) is completed.

7. The bus system (1) according to claim 1, wherein the first bus (11) and the second bus (12) are both parallel buses.

8. A noise cancellation enabled audio system comprising a bus system (1) according to claim 1.

9. The noise cancellation enabled audio system of claim 8, wherein: The audio system is headphones.

10. A method for operating a bus system (1), the bus system comprising a first master controller (110), a first bus (11), a second master controller (120) and a second bus (12), wherein - the second bus (12) is an APB peripheral bus, - the first master controller (110) accesses the second bus (12) via the first bus (11) and the bridge (15), the first master controller (110) being an AHB master controller, - the second master (120) is connected to the second bus (12) and the bridge (15), the second master (120) being an APB master, the second master (120) being arranged to operate autonomously, i.e. to control and monitor the second peripheral device (20) independently of any control performed by the first master, wherein - the bridge (15) comprises an arbitration unit (150) which authorizes the first master (110) or the second master (120) to access the second bus (12), wherein: The arbitration unit (150) is configured to prevent the first master controller (110) and the second master controller (120) from accessing the second bus (12) at the same time, thereby improving the utilization rate of the transmission rate of the second bus (12), which reduces the idle state time of a peripheral device (also called a second peripheral device (20)) connected to the second bus (12).

11. The method according to claim 10, comprising the steps of: - accessing the second bus (12) by means of the first master (110) via the first bus (11) or by means of the second master (120), wherein - said first bus (11) and second bus (12) are timed by means of a common clock signal (500).

12. The method according to claim 11, wherein the common clock signal (500) defines an addressing phase (501) and a transmission phase (502), wherein - the first master (110) and / or the second master (120) addresses the second peripheral device (20) during an addressing phase (501), and - During the transmission phase (502), data is transmitted between the first master (110) or the second master (120) and the second peripheral device (20).

13. The method according to claim 12, wherein - wherein the arbitration unit (150) grants the second master (120) access to the second bus (12) during the addressing phase (501) and during the transmission phase (502) if the first master (110) does not have access to the second bus (12), and - if the second master (120) does not have access to the second bus (12), the arbitration unit (150) grants the first master (110) access to the second bus (12) during the addressing phase (501) and during the transmission phase (502).

14. The method of claim 10, wherein the arbitration unit (150) suspends the first master (110) from accessing the second bus (12) whenever the second master (120) requests access to the second bus (12).

15. The method according to claim 10, wherein - if the first master controller (110) addresses a second peripheral device (20) connected to the second bus (12) and the second master controller (120) accesses the second bus (12), the arbitration unit postpones the access of the first master controller (110) to the second bus (12), and - storing the addressing of the second peripheral device (20) by the first master controller until the access of the second master controller (120) to the second bus (12) is completed, and - After the second master controller (120) completes the access, the arbitration unit (150) authorizes the first master controller (110) to access the second peripheral device (20) via the second bus (12).

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