Gate driver, circuit and method for detecting a short circuit

Abstract

The subject application of the present disclosure relates to gate drivers, circuits, and methods thereof. In one form, a method for detecting a short circuit includes driving a transistor in response to a drive signal, forming a drain signal of the transistor, generating an inverse signal in response to the drain signal, generating a detection signal when the inverse signal and a control signal are active, and providing the drive signal in an active logic state when the control signal is active and the detection signal is not active, otherwise providing the drive signal in an inactive logic state.

Description

Technical Field

[0001] This disclosure generally relates to fault protection circuits, and more specifically to short-circuit detection circuits for power transistors. Background Technology

[0002] Integrated circuits are covered by various safety mechanisms that place them in a safe state during circuit failure conditions. Gate drivers are circuits used to drive transistors (such as power transistors in switch-mode power supplies) and place them in the desired conduction state. To prevent overheating and damage to transistors or the system, short-circuit protection circuits are used to shut down the transistors during short-circuit conditions. Conventional short-circuit protection circuits determine short-circuit conditions by comparing the drain-source voltage of the protected transistor with a reference voltage. These short-circuit protection circuits typically require voltage level shifters, blanking times, and / or additional reference branch circuitry. These requirements can increase die size, slow down detection time, and / or increase current consumption. Therefore, it is difficult to meet increasingly stringent efficiency standards using known short-circuit detection circuits. Attached Figure Description

[0003] This disclosure will be better understood by referring to the accompanying drawings, in which many features and advantages of this disclosure will be apparent to those skilled in the art, as shown in the drawings:

[0004] Figure 1 A gate driver with short-circuit detection according to one embodiment of the present disclosure is shown in partial block diagram and partial schematic diagram.

[0005] Figure 2 The diagram illustrates what can be used as a tool. Figure 1 Digital processing circuits;

[0006] Figure 3 The display shows how to understand Figure 1 Timing diagram of the signals for the operation of the gate driver;

[0007] Figure 4 A gate driver with short-circuit detection according to another embodiment of the present disclosure is shown in partial block diagram and partial schematic diagram; and

[0008] Figure 5 The use of one embodiment according to this disclosure is shown in the form of partial block diagrams and partial schematic diagrams. Figure 1 or Figure 4 A switch-mode power supply with short-circuit detection circuit.

[0009] The same reference numerals are used in different figures to indicate the same or similar elements. Unless otherwise stated, the word “coupled” and its associated verb form include both direct connection and indirect electrical connection by means known in the art; and unless otherwise stated, any description of direct connection also implies alternative embodiments using suitable forms of indirect electrical connection. Detailed Implementation

[0010] Figure 1 A gate driver 100 with short-circuit detection according to one embodiment of the present disclosure is shown in partial block diagram and partial schematic diagram. The gate driver 100 generally includes a set of terminals labeled “C”, “D”, and “S”, a short-circuit detection circuit 110, a driver 120, and a transistor 130. The short-circuit detection circuit 110 includes an inverter 111, a digital processing circuit 112, and a set of one-time programmable (OTP) fuses 113. The inverter 111 has a first input terminal for receiving a drain signal labeled “Drain”, a second input terminal for receiving a programming signal, a first power supply terminal for receiving a voltage labeled “V+”, a second power supply terminal connected to the S terminal for receiving a voltage labeled “V-”, and a power supply terminal for providing a voltage labeled “C”, “D”, and “S”. The digital processing circuit 112 has a first input terminal for receiving a drive signal labeled "drive", a second input terminal connected to the output terminal of the inverter 111, a third input terminal connected to the C terminal for receiving a control signal labeled "control", a first power supply terminal for receiving V+, a second power supply terminal connected to the S terminal, and an output terminal for providing a detection signal labeled "detect". A set of OTP fuses 113 has an output terminal connected to the second input terminal of the inverter 111 for providing a programming signal. The driver 120 has a first active low input terminal connected to the output terminal of the digital processing circuit 112, a second input terminal for receiving "control", a first power supply terminal for receiving V+, a second power supply terminal connected to the S terminal, and an output terminal for providing "drive". The transistor 130 is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate electrode connected to the output terminal of the driver 120, a drain electrode connected to the input terminal of the inverter 111, and a source electrode. Gate driver 100 can be used to drive the gate of transistors for various circuits, including single-switch power converters for synchronous converters or high-side or low-side drivers. Gate driver 100 can be implemented as a monolithic integrated circuit or combined with other components in a single package to form a multi-chip module. Transistor 130 is shown as an N-channel MOSFET; however, other transistor types can be used.

[0011] exist Figure 1In the illustrated embodiment, the short-circuit detection circuit 110 and the driver 120 are in the same power supply voltage domain. For example, if transistor 130 is an N-channel MOSFET, the first power supply terminal receives V+ from the internal power supply circuit. Figure 1 Not shown, and the second power supply terminal is connected to the source of transistor 130. In an embodiment where transistor 130 is a P-channel MOSFET, the first power supply terminal is connected to the source of transistor 130, and the second power supply terminal receives V- from an internal power supply circuit. Figure 1 Not shown in the diagram. Therefore, the drive circuit is biased depending on the transistor type.

[0012] In operation, gate driver 100 drives transistor 130 while improving short-circuit fault detection by implementing digital short-circuit detection using inverter 111 and digital processing circuitry 112. Compared to known fault detection circuits, gate driver 100 reduces response time and current consumption by using digital short-circuit detection.

[0013] In normal operation, i.e., in the absence of a short circuit, the driver 120 receives "control" and, in response to the state of the "control," drives the transistor 130 to a conductive or non-conductive state via "drive." In its conductive state, the transistor 130 conducts current from its drain terminal to its source terminal. Therefore, when no fault condition occurs, the gate driver 100 controls the switching of the transistor 130 in the desired state according to the "control."

[0014] When a short-circuit condition exists, such as a short circuit from the source terminal of the high-side transistor to ground, the drain-source voltage drop caused by the increased current flowing through the "on" resistance of transistor 130 causes the voltage at the input of inverter 111 to rise above its switching point. If a short-circuit condition occurs, inverter 111 will be in an active state. Provided to digital processing circuit 112. Digital processing circuit 112 according to... The "control" and "drive" functions determine whether a short circuit condition has occurred while transistor 130 is in its conductive state, and if so, activate "detection" accordingly. When "detection" is activated, driver 120 and transistor 130 are disabled for the remainder of the switching operation cycle. Since a short circuit condition is an external fault, the system implementing gate driver 100 can correct the fault condition using various methods. In this case, short circuit detection circuit 110 checks for a short circuit condition in each switching operation cycle and disables driver 120 and transistor 130 on a cycle-by-cycle basis until the short circuit condition is eliminated.

[0015] Compared to known fault detection circuits, gate drivers implementing digital short-circuit detection circuits (such as the short-circuit detection circuit 110 described above) have reduced response time and lower current consumption. Figure 1 In the illustrated implementation, the inverter 111, digital processing circuitry 112, and driver 120 are located in the same power supply voltage domain, thus eliminating the need for a voltage level shifter. Compared to known fault detection circuits, the short-circuit detection circuit 110 can be implemented on a smaller die area by using the inverter 111 to detect short-circuit conditions. Because the short-circuit detection circuit 110 consumes very little current, it can be used during various low-power operations, such as startup operations or power-saving modes. A specific implementation of the short-circuit detection circuit 110 using a "drive" as feedback input to the digital processing circuitry 112 can be implemented without using a blanking circuit. The short-circuit detection circuit 110 can be adapted to protect transistors in a variety of applications, topologies, and power stage structures.

[0016] Figure 2 The diagram illustrates what can be used as a tool. Figure 1 The digital processing circuit 112 is a digital processing circuit 200. The digital processing circuit 200 typically includes a logic gate 210 and a latch circuit 220. The logic gate 210 is an AND gate, which has a first input for receiving a "drive" and a second input for receiving a latch. The latch circuit 220 has a second inverting input terminal, a third input terminal for receiving "control" signals, and an output terminal for providing a setting signal. The latch circuit 220 has a setting input terminal connected to the output terminal of logic gate 210, a reset input terminal for receiving "control" signals, and an output terminal for providing "detection" signals. The latch circuit 220 includes logic gates 221 and 222. Logic gate 221 is a NOR gate, having a first input terminal connected to the output terminal of logic gate 210, a second inverting input terminal for receiving "detection" signals, and an output terminal. Logic gate 222 is a NOR gate, having a first input terminal connected to the output terminal of logic gate 221, a second inverting input terminal for receiving "control" signals, and an output terminal for providing "detection" signals.

[0017] In operation, when in contact with detectors (such as...) Figure 1 When used together with inverter 111, digital processing circuit 200 implements digital short-circuit protection. This protection is applied when "control" and "drive" are active (logic high) and... When inactive (logic high), logic gate 210 maintains its set signal inactive (logic low). If a short circuit is detected, then... It becomes active (logically low state). If... When activated during "Control" and "Drive" activities, logic gate 210 activates the set signal and sets latch circuit 220. While latch circuit 220 is set, "Detection" is activated (logic high), and the gate driver is disabled for the remainder of the switching operation cycle. When "Control" becomes inactive (logic low), latch circuit 220 is reset at the end of the switching operation cycle. In an implementation using cycle-by-cycle short-circuit detection, "Control" and "Drive" are activated at the next switching operation cycle. If the short-circuit condition persists, This will remain active, causing latch circuit 220 to activate "detection" and subsequently disable the gate driver for the remainder of the switching operation cycle.

[0018] Figure 3 Timing diagram 300 is shown, and its display can be used for understanding. Figure 1 Gate driver 100 and Figure 2 The digital processing circuit 200 operates on signals. In timing diagram 300, the horizontal axis represents time in μs, and the vertical axis represents the amplitude of the signal in volts or microamps (μA), depending on the specific situation. Timing diagram 300 includes waveform 310 depicting the voltage at the switching node labeled "VSW", waveform 320 depicting "control", and waveform 330 depicting... Waveform 330 depicts a short-circuit event to ground labeled "short-circuit to ground," waveform 340 depicts a "detection," waveform 350 depicts the "average quiescent current," and waveform 360 depicts the average quiescent current of the short-circuit detection circuit 110 labeled "average quiescent current." Waveform 310 represents a DC voltage that switches between high and low voltage amplitudes according to the operation of the gate driver 100. Waveforms 320, 330, 340, and 350 represent digital signals with two levels (i.e., logic high (high voltage amplitude) and logic low (low voltage amplitude)). Waveform 360 represents the average quiescent current measured in μA. The horizontal axis is divided into time intervals labeled "t0," "t1," "t2," "t3," "t4," "t5," and "t6."

[0019] Figure 3 The operation shown begins at t0, where VSW is at a low voltage amplitude and "controlling" "Short circuit to ground" and "detection" are in a low logic state. At this time, It is active (logic low) because the drain-source voltage drop of the transistor is higher than the switching point threshold of the inverter; however, "detection" remains inactive (logic low) because the "control" and drive signals indicate that the transistor is disabled. At t1, a switching operation cycle is initiated, and "control" is activated (logic high). After the propagation delay, the gate driver turns on the transistor, VSW enters a high voltage amplitude, and It becomes inactive (logic high). At t2, "control" is disabled (logic low). After the propagation delay, the gate driver turns off the transistor, VSW returns to a low voltage amplitude, and It becomes active. During the turn-on time from t1 to t2, no short circuit condition was detected and "detection" remained inactive.

[0020] The operation continues in a new switching cycle at t3, and the corresponding signals are activated and deactivated as at t1. At t4, a short circuit occurs from the source terminal of the transistor to ground, represented by a "short circuit to ground" transition to a logic high state and VSW entering a low voltage amplitude. When a short circuit occurs, the drain-source voltage drop caused by the increased current flowing through the transistor's "on" resistance causes the voltage at the inverter's input to rise above its switching point, and Activation. The digital processing circuit is activated based on "control" and A short-circuit condition is detected during the switching operation cycle of the gate driver, and "detection" is activated accordingly. When "detection" becomes active, the gate driver turns off the transistor for the remainder of the switching operation cycle. At t5, "control" is deactivated, and "detection" is reset. At t6, a new switching operation cycle is initiated, "control" is activated, and the gate driver turns on the transistor after a propagation delay. In this example, the short-circuit condition persists; therefore, the digital processing circuitry reactivates "detection" and disables the gate driver and transistor for the remainder of the switching operation cycle. The average quiescent current remains substantially constant throughout the various switching operation cycles, indicating that the short-circuit detection circuitry has little effect on the average quiescent current when a short-circuit condition is detected. Figure 3 The operation described results in a short-circuit detection circuit with reduced response time. For example, when implemented in 0.18-micron CMOS manufacturing technology, the time between the occurrence of a short-circuit condition and the activation of "detection" by the digital processing circuit is less than 3 nanoseconds (ns).

[0021] Figure 4 A gate driver 400 with short-circuit detection according to another embodiment of the present disclosure is shown in partial block diagram and partial schematic diagram. The gate driver 400 and... Figure 1 The gate driver 100 operates similarly, but with some differences as described below. The gate driver 400 typically includes a set of terminals labeled “V”, “C”, “D”, and “S”, a short-circuit detection circuit 410, a bootstrap diode 440, a bootstrap capacitor 450, and a... Figure 1 The corresponding element is found in the gate driver 100. The short-circuit detection circuit 410 includes a cascode transistor 414 and... Figure 1The corresponding components were found in the short-circuit detection circuit 110. The cascode transistor 414 is an N-channel MOSFET, having a drain connected to the drain of transistor 430, a gate connected to the first power supply terminal for receiving V+, and a source connected to the input of inverter 411. The bootstrap diode 440 has a gate connected to the V terminal for receiving V+. Figure 4 The internal power supply circuit, not shown, receives an anode labeled "PVDD" for the internal power supply voltage and a cathode connected to a first power supply terminal. The bootstrap capacitor 450 has a first terminal connected to the cathode of the bootstrap diode 440 and a second terminal connected to a second power supply terminal. In this embodiment, since transistor 430 is an N-channel MOSFET, the second power supply terminal is connected to the source of transistor 430.

[0022] Apart from the following differences, the gate driver 400 is similar to Figure 1 The gate driver 100 operates. Transistor 430 is a high-voltage transistor whose drain-source voltage is higher than the maximum input voltage of inverter 411. When transistor 430 is off, V- remains grounded, allowing bootstrap diode 440 to charge the potential of bootstrap capacitor 450 to PVDD. When "control" goes high, the high level of "drive" begins to charge the gate of transistor 430. During this period, charge is removed from bootstrap capacitor 450 and delivered to the gate of transistor 430. When transistor 430 is on, V- approaches the drain voltage, causing V+ to approach the sum of the drain voltage and PVDD. This provides sufficient gate-source voltage for transistor 430 to remain conductive while keeping the operating voltages of inverter 411, digital processing circuitry 412, and driver 420 within their respective operating limits. During the period when the gate of transistor 430 is charging and V- has reached the drain voltage, the voltage difference between the drain voltage and V- can be greater than the maximum input voltage of inverter 411. For example, the voltage difference can be 40V, and the maximum input voltage of inverter 411 can be 5V. To protect inverter 411, cascode transistor 414 limits the input voltage of inverter 411 to V+.

[0023] exist Figure 4In this embodiment, transistor 430 is a high-voltage N-channel MOSFET; however, other embodiments of the high-voltage circuit may use other types of transistors with appropriate support circuitry and protection. For example, if transistor 430 is a P-channel MOSFET, then cascode transistor 414 will also be a P-channel MOSFET. In this example, cascode transistor 414 will have a drain connected to the drain of transistor 430, a gate connected to the second power supply terminal for receiving V-, and a source connected to the input of inverter 411. In this example, bootstrap diode 440 and bootstrap capacitor 450 are not used. Furthermore, since transistor 430 is a P-channel MOSFET, the first power supply terminal is connected to the source of transistor 430. Therefore, inverter 411 is protected depending on the transistor and application type.

[0024] Figure 5 The use of one embodiment according to this disclosure is shown in the form of partial block diagrams and partial schematic diagrams. Figure 1 or Figure 4 The short-circuit detection circuit of the switch-mode power supply 500 includes a switch-mode power supply 500. The switch-mode power supply 500 is a DC-DC buck converter that uses short-circuit detection to improve system protection. The switch-mode power supply 500 typically includes an input circuit 510, a switch-mode power converter 520, an output circuit 530, and a supply capacitor 540.

[0025] The input circuit 510 includes an input diode 511, an input inductor 512, and input capacitors 513 and 514. The input diode 511 has a function for input... Figure 1 The DC power supply, not shown, receives the anode and cathode of a supply voltage marked "VSUPPLY". Input inductor 512 has a first terminal connected to the cathode of input diode 511 and a second terminal. Output capacitor 513 has a first terminal connected to the cathode of input diode 511 and a second terminal connected to power supply ground. Input capacitor 514 has a first terminal connected to the second terminal of input inductor 512 and a second terminal connected to ground.

[0026] Switch-mode power converter 520 is an integrated circuit buck converter that regulates the output voltage of switch-mode power supply 500. Switch-mode power converter 520 has a set of terminals labeled "VIN", "SW", "Fault", "FB", "VCC", and "GND". The VIN terminal is connected to the second terminal of the input inductor 512. The "Fault" terminal is connected to external circuitry (…). Figure 5 (Not shown in the image) is used to provide a fault signal. The GND terminal is connected to ground.

[0027] A switch-mode power converter 520 typically includes a controller 521, a high-side driver 522, a high-side transistor 523, a high-side short-circuit detection circuit 524, a low-side driver 525, a low-side transistor 526, a low-side short-circuit detection circuit 527, a fault management circuit 528, and an internal power supply circuit 529. The controller 521 has a feedback input connected to the FB terminal, a fault input connected to the "fault" terminal, a high-side output for providing a high-side control signal labeled "HCONTROL," and a low-side output for providing a low-side control signal labeled "LCONTROL." The high-side driver 522 has a start input, a control input connected to the high-side output of the controller 521, and an output for providing a high-side drive signal labeled "HDRV." The high-side transistor 523 has a gate connected to the output of the high-side driver 522, a drain connected to the VIN terminal, and a source connected to the SW terminal. The high-side short-circuit detection circuit 524 has an input terminal connected to the drain of the high-side transistor 523 for receiving a high-side drain signal labeled "High Drain" and an output terminal connected to the enable input terminal of the high-side driver 522 for providing a high-side detection signal labeled "HDETECT". The low-side driver 525 has a control input terminal connected to the low-side output terminal of the controller 521, an enable input terminal, and an output terminal for providing a low-side drive signal labeled "LDRV". The low-side transistor 526 has a gate connected to the output terminal of the low-side driver 525, a drain connected to the SW terminal, and a source connected to the GND terminal. The low-side short-circuit detection circuit 527 has an input terminal connected to the drain of the low-side transistor 526 for receiving a low-side drain signal labeled "Low Drain" and an output terminal connected to the enable input terminal of the low-side driver 525 for providing a low-side detection signal labeled "LDETECT". The fault management circuit 528 has a first input terminal connected to the output of the high-side short-circuit detection circuit 524, a second input terminal connected to the output of the low-side short-circuit detection circuit 527, and an output terminal connected to the "fault" terminal for providing a fault signal. The internal power supply circuit 529 has an input terminal connected to the VCC terminal and an output terminal for providing an internal voltage labeled "VDD".

[0028] The output circuit 530 includes an output inductor 531, feedback resistors 532 and 533, and an output capacitor 534. The output inductor 531 has a first terminal connected to the SW terminal of the switch-mode power converter 520, and a terminal for supplying power to the load (in...). Figure 5(Not shown) A second terminal provides the output voltage labeled “VOUT”. Feedback resistor 532 has a first terminal connected to the second terminal of output inductor 531 and a second terminal connected to the FB terminal of switch-mode power converter 520 for providing a feedback signal labeled “Feedback”. Feedback resistor 533 has a first terminal connected to the second terminal of feedback resistor 532 and a second terminal connected to ground. Output capacitor 534 has a first terminal connected to the second terminal of output inductor 531 and a second terminal connected to ground. Power supply capacitor 540 has a first terminal connected to the VCC terminal of switch-mode power converter 520 and a second terminal connected to ground.

[0029] During operation, input circuit 510 smooths VSUPPLY at the input of switch-mode power supply 500. Output capacitor 534 stabilizes VOUT (output voltage of switch-mode power supply 500). Switch-mode power converter 520 charges and is powered by supply capacitor 540 via VCC terminal during startup cycle.

[0030] Feedback circuit 530 provides "feedback" as a reduced representation of VOUT to the FB terminal of switch-mode power converter 520. Controller 521 uses this "feedback" to generate HCONTROL and LCONTROL. High-side driver 522 receives HCONTROL and responsively drives high-side transistor 523 to a conducting state and a non-conducting state via HDRV. High-side transistor 523 provides a positive current to output inductor 531 when it is in its conducting state. Low-side driver 525 receives LCONTROL and responsively drives low-side transistor 526 to a conducting state and a non-conducting state via LDRV. Low-side transistor 526 provides a negative current to output inductor 531 when it is in its conducting state. Overall, controller 521, high-side driver 522, and low-side driver 525 alternately control the switching of high-side transistor 523 and low-side transistor 526 to regulate VOUT to the desired voltage.

[0031] During this operation, if a short circuit occurs in the output, the system may be damaged. However, unlike known switch-mode power supplies, the switch-mode power supply 500 implements digital short-circuit detection as previously described. The high-side short-circuit detection circuit 524 senses a "high drain". When the high-side transistor 523 conducts and a short circuit occurs, the high-side short-circuit detection circuit 524 activates HDETECT, thereby disabling the high-side driver 522 and the high-side transistor 523 for the remainder of the switching operation cycle. The low-side short-circuit detection circuit 527 senses a "low drain". When the low-side transistor 526 conducts and a short circuit occurs, the low-side short-circuit detection circuit 527 activates LDETECT, thereby disabling the low-side driver 525 and the low-side transistor 526 for the remainder of the switching operation cycle. The fault management circuit 528 receives both HDETECT and LDETECT and generates a fault signal accordingly.

[0032] Figure 5 The implementation scheme illustrates an exemplary switch-mode power supply 500 using digital short-circuit detection. Figure 5 In the implementation, transistors 523 and 526 are N-channel MOSFETs; however, other implementations may implement different types of MOSFETs. For example, one implementation may use a P-channel MOSFET for the high-side transistor 523. Short-circuit detection circuits 524 and 527 can use any implementation of the various implementations of the described short-circuit detection circuit. For example, in one implementation, the high-side transistor 523 is a high-drain-voltage N-channel MOSFET. In this example, the high-side short-circuit detection circuit 524 is similar to... Figure 4 The short-circuit detection circuit 410. Figure 5 In one embodiment, fault management circuitry 528 generates a fault signal in response to HDETECT or LDETECT. In one embodiment of the switch-mode power converter 520, controller 521 stops generating HCONTROL and LCONTROL in response to a fault signal. In this example, controller 521 may avoid generating HCONTROL and LCONTROL until an external signal is provided to switch-mode power converter 520, switch-mode power converter 520 is restarted, or a predetermined time has elapsed. In another embodiment, the fault signal is provided to an external controller via a “fault” terminal. Switch-mode power converter 520 is described with reference to various terminals and internal circuitry; however, specific implementations of switch-mode power converter 520 may include additional circuitry or terminals not described herein, while implementing digital short-circuit detection. Although switch-mode power supply 500 shows a buck converter topology, other topologies may be used in the embodiment of the short-circuit detection circuitry.

[0033] Various implementations of short-circuit detection circuits and related systems have been described above, in which inverters and digital processing circuits detect short-circuit conditions. For example, in one implementation, the short-circuit detection circuit detects a short circuit by monitoring the drain of a transistor. In another implementation, the short-circuit detection circuit detects a short circuit by monitoring the drain of a high-voltage transistor. In yet another implementation, multiple short-circuit detection circuits are used to monitor the corresponding drains of transistors in the power supply.

[0034] The subject matter disclosed above should be considered exemplary and not limiting, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the true scope of the claims. For example, a particular block of the gate driver or switch-mode power supply may vary in different embodiments. Furthermore, the short-circuit detection circuit, gate driver, digital processing circuit, and switch-mode power supply described above can be used in different architectures. For example, various embodiments of the short-circuit detection circuit can be implemented in single-power transistor applications and multiple-power transistor applications. Additionally, the short-circuit detection circuit described above can be implemented in a separate gate driver, switch-mode power supply controller, switch-mode power converter, or another application for protecting transistors.

[0035] In one embodiment, a gate driver with short-circuit protection for driving the gate of a first transistor that also has a drain and a source includes an inverter, a digital processing circuit, and a driver. The inverter has an input for receiving a drain signal from the drain of the first transistor and an output for providing an inverted signal. The digital processing circuit has a first input coupled to the output of the inverter, a second input for receiving a control signal, and an output for providing a detection signal, wherein the digital processing circuit provides the detection signal in an active logic state in response to the inverted signal and the control signal being in corresponding active states. The driver has a first input coupled to the output of the digital processing circuit, a second input for receiving the control signal, and an output for providing a drive signal, wherein the driver provides the drive signal in an active logic state when the control signal is active and the detection signal is inactive, and otherwise provides the drive signal in an inactive logic state.

[0036] According to one aspect, the inverter has a programmable switching point, and the gate driver further includes a plurality of fuses coupled to the inverter to determine the programmable switching point.

[0037] According to another aspect, the inverter, the digital processing circuit, and the driver are located in a first power supply voltage domain.

[0038] According to another aspect, the digital processing circuit may include a logic gate that provides a setting signal in response to the inverted signal and the control signal, and a latch circuit that is set in response to the setting signal and reset in response to the control signal. According to this aspect, the latch circuit is set in response to the control signal and the inverted signal being active, and wherein the latch circuit is reset when the control signal is inactive. According to this aspect, the latch circuit may be further set in response to the drive signal being active.

[0039] According to another aspect, the inverter, the digital processing circuit, the driver, and the first transistor are combined in a monolithic integrated circuit.

[0040] In another form, the circuit includes a switch-converter, wherein the switch-converter includes a controller, a first driver, a first transistor, and a first short-circuit detection circuit. The controller provides a first control signal in response to a feedback signal. The first driver provides a first drive signal in response to the first control signal. The first transistor conducts a first current to an inductive load in response to the first drive signal, wherein the drain of the first transistor forms a first drain signal. The first short-circuit detection circuit includes a first inverter providing a first inverted signal in response to the first drain signal and a first digital processing circuit providing an active first detection signal when the first inverted signal and the first control signal are respectively active. The first driver provides the first drive signal in an active logic state when the first control signal is active and the first detection signal is inactive, otherwise provides the first drive signal in an inactive logic state.

[0041] According to one aspect, the first inverter has a programmable switching point. According to this aspect, the first short-circuit detection circuit further includes a plurality of fuses coupled to the first inverter for determining the programmable switching point.

[0042] According to another aspect, the controller, the first driver, the first transistor, and the first short-circuit detection circuit are combined within a single integrated circuit die.

[0043] According to another aspect, the first digital processing circuit includes a logic gate responsive to the first inverted signal and the first control signal, the logic gate being configured to provide a setting signal in an active logic state in response to the first inverted signal and the first control signal being active; and a latch circuit responsive to the setting signal and the first control signal, the latch circuit being configured to provide a first detection signal in the active logic state in response to both the setting signal and the first control signal being active, wherein the logic gate further provides the setting signal in response to the first drive signal. According to this aspect, the drain of the second transistor forms a second drain signal, and the switching converter further includes a second short-circuit protection circuit including a second inverter for providing a second inverted signal in response to the second drain signal and a second digital processing circuit for providing a second detection signal in an active state when the second inverted signal and the second control signal are in corresponding active states, wherein the second driver provides the second drive signal in an active logic state when the second control signal is active and the second detection signal is inactive, otherwise provides the second drive signal in an inactive logic state.

[0044] In another form, a method for detecting a short circuit includes driving a transistor in response to a drive signal; forming a drain signal of the transistor; generating an inverted signal in response to the drain signal; generating a detection signal when the inverted signal and a control signal are active; and providing the drive signal in an active logic state when the control signal is active and the detection signal is inactive, otherwise providing the drive signal in an inactive logic state.

[0045] According to one aspect, generating the detection signal includes the inverted signal A setting signal is formed when the control signal (“control”) is active. In this case, forming the setting signal may include pulse the setting signal when the drive signal is active.

[0046] According to another aspect, generating the inverted signal includes using an inverter with a programmable switching point, and activating the inverted signal when the drain signal passes through the programmable switching point. In yet another aspect, the method may further include programming the programmable switching point using a plurality of fuses coupled to the inverter.

[0047] Therefore, to the fullest extent permitted by law, the scope of this invention shall be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be constrained or limited by the detailed description above.

Claims

1. A gate driver having short-circuit protection for driving the gate of a first transistor, the first transistor further having a drain and a source, the gate driver comprising: An inverter having an input for receiving a drain signal from the drain of the first transistor and an output for providing an inverted signal; A digital processing circuit having a first input terminal coupled to the output terminal of the inverter, a second input terminal for receiving a control signal, and an output terminal for providing a detection signal, wherein the digital processing circuit provides the detection signal in an active logic state in response to the inverting signal and the control signal being in corresponding active states; and A driver having a first input terminal coupled to the output terminal of the digital processing circuit, a second input terminal for receiving the control signal, and an output terminal for providing a drive signal, wherein the driver provides the drive signal in an active logic state when the control signal is active and the detection signal is inactive, and otherwise provides the drive signal in an inactive logic state.

2. The gate driver of claim 1, wherein the inverter has a programmable switching point.

3. The gate driver according to claim 1, wherein the digital processing circuit comprises: A logic gate that responds to the inverted signal and the control signal to provide a set signal; and A latch circuit that is set in response to the setting signal and reset in response to the control signal.

4. The gate driver of claim 1, further comprising a second transistor having a drain for receiving the drain signal, a source coupled to the input terminal of the inverter, and a gate coupled to a power supply voltage terminal, wherein the inverter, the digital processing circuit, and the driver are coupled to the power supply voltage terminal.

5. A circuit including a switch converter, the switch converter comprising: Controller, the controller being configured to provide a first control signal in response to a feedback signal; A first driver, the first driver being configured to provide a first drive signal in response to the first control signal; A first transistor, the first transistor being configured to conduct a first current to an inductive load in response to the first drive signal, wherein the drain of the first transistor forms a first drain signal; and A first short-circuit detection circuit, the first short-circuit detection circuit comprising: A first inverter, the first inverter being configured to provide a first inverted signal in response to the first drain signal; and A first digital processing circuit provides a first detection signal indicating that it is in an active state when the first inverted signal and the first control signal are in corresponding active states. The first driver provides the first drive signal in an active logic state when the first control signal is active and the first detection signal is inactive, and otherwise provides the first drive signal in an inactive logic state.

6. The circuit according to claim 5, wherein the first digital processing circuit comprises: A logic gate that responds to the first inverted signal and the first control signal, the logic gate being configured to provide a setting signal in an active logic state in response to the first inverted signal and the first control signal being active; and A latch circuit responsive to the setting signal and the first control signal, the latch circuit being configured to provide a first detection signal in the active logic state in response to both the setting signal and the first control signal being active. The logic gate further provides the setting signal in response to the first drive signal.

7. The circuit of claim 5, wherein the controller provides a second control signal in response to the feedback signal, and the switching converter further comprises: A second driver, the second driver being configured to provide a second drive signal in response to the second control signal; and The second transistor is used to conduct a second current to the inductive load in response to the second drive signal.

8. The circuit according to claim 7, further comprising: An inductor for providing an output voltage in response to the first current and the second current; and A feedback circuit, which provides the feedback signal in response to the output voltage.

9. A method for detecting a short circuit, comprising: Drive the transistor in response to the drive signal; The drain signal of the transistor is formed; An inverted signal is generated in response to the drain signal; A detection signal is generated when the inverting signal and the control signal are active; as well as The drive signal is provided in an active logic state when the control signal is active and the detection signal is inactive; otherwise, the drive signal is provided in an inactive logic state.

10. The method according to claim 9, wherein: The generation of the detection signal further includes: generating a setting signal when the inverting signal and the control signal are active, and setting a latch (220) in response to the setting signal; and The method further includes resetting the latch when the control signal is inactive.

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