Method of protecting a system such as a microcontroller and corresponding system

Abstract

Embodiments of the present disclosure relate to a method of protecting a system such as a microcontroller and a corresponding system. A system comprising a processing unit, a memory configured to store at least one first set of instructions and one second set of instructions for execution by the processing unit, the processing unit being configured to sequentially fetch instructions of the first set and instructions of the second set from the memory for their execution. The system further comprises a controller comprising a first auxiliary memory configured to store a protection criterion, a comparator configured to compare a memory address of each fetched instruction with the protection criterion, and a control circuit configured to trigger a protection mechanism in response to the memory address satisfying the protection criterion, the protection mechanism comprising at least one prohibition of the processing unit to execute again at least a portion of the instructions of the first set during the execution of the instructions of the second set.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of French patent application number 2013505, filed on December 17, 2020, which is incorporated herein by reference. Technical Field

[0003] The implementation methods and embodiments relate to electronic systems such as microcontrollers, especially those electronic systems that include memory, and more particularly to the protection of these systems, especially the protection of the system's boot instructions or initialization instructions. Background Technology

[0004] With the development of connected devices (such as home automation), the security of electronic systems has become increasingly important. In particular, it is crucial to ensure that the boot instructions contained in memory and executed during system initialization correspond correctly to the intended instructions, rather than instructions modified by malicious third parties.

[0005] In fact, secure boot instructions enable the establishment and maintenance of a chain of trust throughout the entire process of executing software instructions on a product.

[0006] Furthermore, secure boot instructions serve as a root of trust, verifying the authenticity and integrity of a user's application using cryptographic features before execution. Therefore, there is a need to improve the protection of electronic systems such as microcontrollers, particularly enhancing the security of boot instructions, especially when they are incorporated into connected objects. Summary of the Invention

[0007] According to one implementation and embodiment, it is proposed that once the application is booted, the boot instructions of the microcontroller, or at least a portion of those instructions corresponding to the most critical services, be made unavailable in order to prevent malware from reusing the coded services in the boot instructions in an unauthorized manner aimed at compromising the overall security of the product (e.g., a connected object containing such a microcontroller).

[0008] Based on one aspect, a method for protecting systems such as microcontrollers is proposed.

[0009] The system includes a processing unit, such as a processor core, and a memory that stores at least one first set of instructions (e.g., boot instructions) and a second set of instructions (e.g., application programs), which can be executed by the processing unit.

[0010] The method includes: the processing unit sequentially fetching instructions from a first set of memories and instructions from a second set of memories for execution.

[0011] In addition, the method includes comparing the storage address of each extraction instruction with protection criteria.

[0012] Furthermore, if the storage address meets the protection criteria, the method provides the triggering of a protection mechanism, which includes at least one prohibition of the processing unit from re-executing at least a portion of the instructions of the first group during the execution of the instructions of the second group.

[0013] The system may include a communication bus and at least one master device connected to the bus, such as a direct memory access (DMA) circuit, and the protection mechanism also advantageously includes prohibiting at least one master device from accessing at least a portion of the instructions of the first group during the execution of the instructions of the second group.

[0014] Therefore, the protection criteria are advantageously designed to protect at least a portion of the first set of directives.

[0015] As long as the protection criteria are not met, the first set of instructions (i.e., the boot instructions) can be executed normally. However, once the instructions fetched from memory meet the protection criteria, then for any other sequence initiated by the application or the master device on the bus and during its execution, access to at least a portion of the boot instructions is locked, optionally access to the set of boot instructions is locked, and optionally access to certain sensitive data stored in memory is locked.

[0016] Furthermore, the comparison between the address of the extracted instruction and the protection criteria is advantageously performed automatically. Similarly, once the protection criteria are met by implementing, for example, hardware circuitry (including, for example, hard-wired logic, without necessarily using specific logic instructions), this triggering of the protection mechanism is advantageously performed automatically.

[0017] There are multiple possible solutions for defining protection criteria, and when the criteria are met, the solution can trigger the protection mechanism.

[0018] Therefore, the protection criterion can be the address of the first instruction in the second set of instructions or the address of the last instruction in the first set of instructions. In this case, if the address of the instruction fetched from memory is the address of the first instruction in the second set of instructions or the address of the last instruction in the first set of instructions, then the instruction fetched from memory satisfies the protection criterion.

[0019] Alternatively, the protection criteria may include a first address range, and in that case, if the address of the instruction is outside the first address range, the instruction satisfies the protection criteria.

[0020] The first address range is, for example, the address range of instructions in the first group of instructions.

[0021] According to one implementation, the protection mechanism may include at least one prohibition on the processing unit re-executing all (but not a portion) of the instructions in the first group of instructions during the execution of the instructions in the second group and / or prohibition on at least one master device accessing all (but not a portion) of the instructions in the first group of instructions during the execution of the instructions in the second group.

[0022] In other words, in this implementation, access to all boot instructions, that is, access to all services contained in these boot instructions, is locked.

[0023] As previously stated, the protection mechanism includes at least one prohibition on the processing unit re-execution of at least a portion of the instructions in the first group of instructions during the execution of the instructions in the second group, and / or prohibition on at least one master device accessing at least a portion of the instructions in the first group during the execution of the instructions in the second group.

[0024] Furthermore, according to one embodiment, such prohibition of instructions newly executed by the processing unit, or of instructions accessed by at least one master device, includes: detecting a new request from the processing unit or at least one master device to fetch the instruction from memory; and performing an action to prevent the new request to fetch the instruction from being provided.

[0025] In other words, to determine whether the protection criteria are met, observe the address of the instruction fetched from memory. This time, it is to prohibit the processing unit from executing a new instruction or to prohibit the master device from accessing the instruction. Observe the request to fetch the instruction (i.e., before fetching the instruction from memory), and then execute an action to prevent the new fetch request from being provided, that is, an action designed to prevent the new requested instruction from being fetched from memory.

[0026] This helps improve the security of the first set of instructions, such as the security of the boot instructions.

[0027] As an example, the execution of this action may include resetting the system.

[0028] Alternatively, the execution of the action may include delivering a reference instruction to a processing unit or to at least one master device, rather than delivering a requested instruction.

[0029] The baseline instruction may be, for example, but not limited to, no-operation (NOP) instructions known to those skilled in the art.

[0030] According to one implementation, at least a portion of the instructions in the first group of instructions of interest to the protection mechanism may be stored at a memory address belonging to at least one second address range. In this case, the detection of a new request to retrieve instructions includes a comparison between the address of the requested instruction and at least one second address range.

[0031] If it is desired to prohibit access to all instructions in the first set of instructions, the second address range may be the address range of the instruction set in the first set. Alternatively, if it is desired to prohibit only certain coded services in the boot instructions and authorize applications to access other services contained in the boot instructions (e.g., access to the bootloader's version number), the second address range may be a more restricted address range than the address range of the instructions in the first set.

[0032] As previously described, according to one embodiment, the protection mechanism may further include prohibiting the processing unit and / or at least one master device from accessing at least one piece of data stored in memory during the execution of the second set of instructions, and generally prohibiting access to multiple pieces of data stored in memory.

[0033] The data that is to be protected can be stored in the same memory as the memory that stores the instructions of the first set or in a different memory, such as static random access memory (SRAM).

[0034] This data can be processed by boot instructions. Typically, this data is erased by boot instructions while it is stored in random access memory, but if this is not the case, protection mechanisms ensure that this potentially sensitive data cannot be accessed.

[0035] In this case, according to one implementation, prohibiting access to data includes: detecting a request from the processing unit or at least one master device to retrieve the data from memory, and performing an action to prevent the new request to retrieve the data from being provided.

[0036] Similarly, the execution of this action may include the execution of the system, or the delivery of baseline data (e.g., zero data) to the processing unit or at least one master device, instead of delivering the requested data.

[0037] According to one implementation, at least one piece of data of interest to the protection mechanism is stored at a storage address belonging to at least one third address range, and in this case, detecting a request to retrieve data includes a comparison between the address of the requested data and at least one third address range.

[0038] According to another aspect, a system is proposed, comprising:

[0039] -Processing unit,

[0040] - A memory intended to store at least a first set of instructions and a second set of instructions executable by a processing unit, the processing unit being configured to sequentially fetch the first set of instructions and the second set of instructions from the memory for execution, and

[0041] - A controller, comprising: a first auxiliary memory intended to store protection criteria; a comparator configured to advantageously automatically compare the storage address of each fetch instruction with the protection criteria; and control circuitry configured to advantageously automatically trigger a protection mechanism if the storage address satisfies the protection criteria, the protection mechanism comprising at least one prohibition of the processing unit from re-executing at least a portion of the instructions of the first group during the execution of the instructions of the second group.

[0042] According to one embodiment, the system includes a communication bus and at least one master device connected to the bus, and the protection mechanism further includes prohibiting the at least one master device from accessing at least a portion of the instructions of the first group during the execution of the instructions of the second group.

[0043] According to one embodiment, the protection criterion is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions, and if the address of the instruction is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions, then the instruction satisfies the protection criterion.

[0044] According to one embodiment, the protection criteria include a first address range, and if the address of the instruction is outside the first address range, the instruction satisfies the protection criteria.

[0045] According to one embodiment, the first address range is the address range of the instructions in the first group.

[0046] According to one embodiment, the control circuit is configured to: at least prevent the processing unit from re-executing all instructions in the first group of instructions during the execution of the instructions in the second group, and / or at least prevent at least one master device from accessing all instructions in the first group of instructions during the execution of the instructions in the second group.

[0047] According to one embodiment, in order to prevent the processing unit from newly executing instructions for that part or to prevent at least one master device from accessing instructions for that part, the control circuit is configured to: detect a new request from the processing unit or at least one master device to fetch the instruction from memory; and perform an action to prevent the new request to fetch the instruction from being provided.

[0048] According to one embodiment, the control circuit is configured to execute actions by resetting the system.

[0049] According to one embodiment, the control circuit is configured to execute an action by delivering a reference instruction to a processing unit or at least one master device instead of a requested instruction.

[0050] According to one embodiment, at least a portion of the instructions of the first group of instructions of concern to the protection mechanism are stored at a storage address belonging to at least one second address range, the control circuitry includes a second auxiliary memory intended to store at least one second address range, and the control circuitry is configured to detect a new request for the fetch instruction by comparing the address of the request instruction with at least one second address range.

[0051] According to one embodiment, the protection mechanism further includes: prohibiting the processing unit and / or at least one master device from accessing at least one piece of data stored in memory during the execution of the second set of instructions.

[0052] According to one embodiment, in order to implement access denial, the control circuit is configured to: detect a request from a processing unit or at least one master device to retrieve the data from memory; and perform an action to prevent new requests to retrieve the data from being provided.

[0053] According to one embodiment, the control circuit is configured to execute actions by resetting the system.

[0054] According to one embodiment, the control circuit is configured to execute an action by delivering reference data instead of requested data to a processing unit or at least one master device.

[0055] According to one embodiment, at least one piece of data of interest to the protection mechanism is stored at a storage address belonging to at least one third address range, the control circuitry includes a third auxiliary memory intended to store at least one third address range, and the control circuitry is configured to detect a request to extract data by comparing the address of the requested data with at least one third address range.

[0056] According to one embodiment, the protection criteria, as well as the second and third address ranges, are stored in a protected manner.

[0057] According to one embodiment, the system is a microcontroller, the first set of instructions includes boot instructions and the second set of instructions includes instructions for the application program.

[0058] From another perspective, a connection object containing systems such as those defined above is proposed. Attached Figure Description

[0059] Other advantages and features of the invention will become apparent upon examination of the detailed description of the non-limiting embodiments and examples, as well as the accompanying drawings, wherein:

[0060] Figure 1 The illustration shows a system, for example, a microcontroller, which is contained within a device, for example, a connected object;

[0061] Figure 2The diagram illustrates the operation of the protection mechanism, where the protection criterion is the application's first address;

[0062] Figure 3 The diagram illustrates the operation of the protection mechanism, where the protection criterion is the last address of the boot instruction program;

[0063] Figure 4 The diagram illustrates the operation of the protection mechanism, where the protection criterion is the address range of the boot instruction program;

[0064] Figure 5 The diagram illustrates the execution of application program instructions by the processing unit, where the control circuitry resets the microcontroller.

[0065] Figure 6 The diagram shows... Figure 5 The operation involves the control circuit optionally delivering a reference command to the processing unit;

[0066] Figure 7 The diagram illustrates the protection of only a portion of the bootloader's instructions;

[0067] Figure 8 The diagram illustrates a protection mechanism that safeguards data access during application execution, where a control circuit resets the microcontroller.

[0068] Figure 9 The diagram shows... Figure 8 The operation, wherein the control circuit alternatively delivers a reference command to the processing unit; and

[0069] Figure 10 The protection procedure is applied to each of the protection criterion parameter, the first address range parameter, and the second address range parameter, wherein the protection procedure may be the same or different for each of the parameters. Detailed Implementation

[0070] exist Figure 1 In the accompanying drawings, the reference MCU indicates a system such as a microcontroller, which is included here within a device such as an APP that connects to the object.

[0071] A microcontroller (MCU) is a microcontroller that seeks to protect instructions (such as boot instructions) in particular from modification or unauthorized access, that is, from being executed outside the execution context of the bootloader.

[0072] The microcontroller (MCU) includes, for example, a processing unit (UT) with a processor core, and includes memory, in this example, a first memory (MM1) and a second memory (MM2).

[0073] The first memory MM1 can be a rewritable non-volatile memory, such as flash memory. The second memory MM2 can be a volatile memory, such as static random access memory (SRAM).

[0074] The microcontroller (MCU) also includes other components such as direct memory access (DMA) circuitry and peripheral devices, which are not shown here for simplicity. Some of these components can be master components and other slave resources.

[0075] The various components of a microcontroller are interconnected via a communication bus (BS), which typically includes an instruction bus, a data bus, and a system bus. These buses are, for example, of the AMBA (Advanced Microcontroller Bus Architecture) type.

[0076] Both the instruction bus and the data bus specifically include an address thread for transmitting addresses and a data thread for transmitting instructions (if this involves the instruction bus) or data (if this involves the data bus).

[0077] The processing unit UT can therefore fetch instructions for their execution, or fetch data located in memory MM1 and / or MM2.

[0078] In this example, memory MM1 specifically stores the first set of instructions GR1, which is typically the system's boot or initialization instructions, and stores the second set of instructions GR2, which is typically the application's instructions.

[0079] In this example, assume that memory MM2 also stores data D, as will be seen below, which is the data to be protected.

[0080] Of course, at least some of the data to be protected can also be stored in memory MM1.

[0081] A boot instruction refers to the instruction itself and, optionally, the data required to execute it. Boot instructions are executed by the processing unit (UT). Preferably, the boot instruction originates from the first instruction executed during system startup.

[0082] The boot instructions include, for example, parameters for initializing one or more components of the microcontroller, such as memory protection units (which authorize or deauthorize access to various memory portions for various peripheral devices and various programs), watchdog circuits, and non-volatile protection circuits.

[0083] During the initial programming of the system, boot instructions are written into memory MM1. These boot instructions are not intended to be modified outside of a complete reprogramming of the system, which would mean a complete erasure of memory MM1.

[0084] This reprogramming will be considered a new initial programming of the system. Therefore, modification of the boot instructions implies an attempt to bypass the security mechanisms of the microcontroller (MCU) and / or to access unauthorized services by hackers.

[0085] The second set of GR2 instructions (usually application instructions) is executed after the first set of instructions, especially if the bootloader has verified the authenticity and integrity of the second set of instructions.

[0086] The microcontroller (MCU) also includes a controller SBI, which, as will be seen in more detail below, is configured to: ensure protection of at least a portion of the instructions of the first group GR1 during the execution of the application, optionally protect all such instructions, and optionally protect the data D.

[0087] As will be seen in more detail below, the protection mechanism in this example includes: prohibiting the processing unit UT from executing at least some or all of the instructions of the first group GR1 again during the execution of the instructions of the second group GR2, and prohibiting the processing unit UT from accessing sensitive data D contained in memory MM2 during the execution of the instructions of the second group.

[0088] However, the protection mechanism also advantageously includes: prohibiting each master device (especially the DMA circuitry) from accessing at least a portion or all of the instructions in the first group GR1 during the execution of the instructions in the second group GR2 (e.g., copying the instructions instead of executing them), and prohibiting each master device from accessing sensitive data D contained in memory MM2 and / or memory MM1 during the execution of the instructions in the second group.

[0089] For the sake of simplicity, the protection mechanism applicable to the processing unit is described below; it should be remembered that it also applies to each master device.

[0090] When the processing unit UT wants to fetch an instruction from memory MM1, it transmits the address @ of the instruction on the instruction thread of the instruction bus and receives the corresponding instruction INS on the data thread of the instruction bus.

[0091] Similarly, when a processing unit wants to access data contained in memory MM2, it issues an access (or fetch) request by transmitting the address of the data on the address thread of the data bus, and receives the data on the data thread of the data bus.

[0092] The controller SBI includes a comparator CMP, which is configured to compare the address @ of the instruction INS fetched from memory MM1 with the protection criteria CP contained in the first auxiliary memory MMX1 (e.g., one or more registers).

[0093] We will describe the content of this protection guideline CP in more detail below.

[0094] If the address of the extracted instruction INS satisfies the protection criterion CP, then the comparator CMP is configured to deliver the trigger signal SDL to the control circuit CTRL, which will implement the protection mechanism described in more detail below.

[0095] However, it can now be pointed out that this protection mechanism, implemented by the control circuit CTRL, provides a comparison between address @1 contained in the request for fetching instructions or the request for accessing data and the contents of the second auxiliary memory MMX2 or the third auxiliary memory MMX3, which we will describe in more detail below.

[0096] Furthermore, in the event of an attempt to deny access to instructions or data, the control circuit CTRL is configured to: perform an action that prevents the processing unit from re-executing the requested instruction or accessing the requested data.

[0097] In this regard, as will be seen in more detail below, the action may include resetting the microcontroller MCU by delivering a reset signal RST on the microcontroller's reset pin by delivering a reference instruction (e.g., an "operation-free" type instruction) contained in register RG1 instead of delivering the requested instruction, or by delivering reference data (e.g., zero data) contained in the second register RG2 instead of delivering the requested data.

[0098] It should also be noted that the controller SBI is only hardware. In particular, the control circuit CTRL includes hardwired logic.

[0099] Based on this hardware aspect of the controller SBI, the controller SBI automatically verifies whether the protection criteria are met, so as to automatically trigger the protection mechanism and execute it when applicable.

[0100] Now for reference Figure 2 The following describes embodiments of the protection method according to the present invention.

[0101] In this example, such as Figure 2 As shown, it is assumed that the instruction INSi (i.e., the boot instruction) of the first group GR1 is stored in the address range @0…@N, while the instruction INSi (i.e., the application instruction) of the second group GR2 is stored in the address range @P…@R.

[0102] P can be equal to N+1, but not necessarily.

[0103] Then, the processing unit UT will begin to sequentially fetch the instruction INSi of the first set of instructions GR1 from memory MM1.

[0104] Therefore, as shown in step ST20, the request to extract the instruction INSi of the first group GR1 causes the processing unit UT to issue the address @i of the instruction on the instruction bus.

[0105] The instruction INSi is fetched from memory MM1 (step ST21), and furthermore, in step ST22, the address @i of the instruction INSi is compared with the address @P, which is the address of the first instruction of the application.

[0106] In this implementation example, the address @P forms the protection principle CP mentioned above.

[0107] If address @i is not equal to address @P, the trigger signal SDL takes the first logic value, such as 0 (step ST23), and the protection mechanism is not triggered. Furthermore, instruction INSi is executed in step ST24, and we return to step ST20 to perform the subsequent instructions of the first group of instructions.

[0108] Therefore, as long as the address of the extracted instruction is not equal to address @P, that is, as long as it does not meet the protection criterion CP, everything will proceed normally and the protection mechanism will not be triggered.

[0109] However, once the address @i of the extracted instruction INSi equals the address @P, the trigger signal SDL takes a logic value of 1 (step ST25), which triggers the protection mechanism in step ST26. Furthermore, this instruction is executed in step ST24.

[0110] At the moment corresponding to the start of application execution, the processing unit will continue to issue requests to extract instructions INSi from the second set of instructions, so that they can be extracted sequentially and the application can be executed. If no hacking attack occurs, everything will proceed normally, and although the protection mechanism is activated, no specific protective action will be taken.

[0111] However, if, for example, after a hacker has compromised the application, the processing unit attempts to extract instruction INSi from the first set of instructions during the application's execution without permission, then a specific protection action will be delivered by a protection mechanism, as will be explained in more detail below.

[0112] However, in Figure 2 In the example, the protection rule CP is the first address @P of the application (second set of instructions GR2), which may be, as Figure 3 As shown, the protection rule CP is the last address @N of the first group of instructions GR1, which is the last address of the boot instruction program.

[0113] In this case, if the address @i of the fetched instruction is not equal to the last address @N, we proceed to step ST23 as explained above. Furthermore, if the address @i is equal to the last address @N, we proceed to step ST25 as mentioned above.

[0114] It is also possible that, such as Figure 4 As shown, the protection rule CP is the address range @0…@N of the first group of GR1 instructions.

[0115] In this case, as long as the address @i of the extracted instruction belongs to the address range @0…@N, we proceed to step ST23 (without triggering the protection mechanism).

[0116] However, once the address @i is not in the range @0…@N, we proceed to step ST25 by triggering the protection mechanism.

[0117] Compared to Figure 2 and Figure 3 This implementation method provides enhanced security. In fact, for example, in... Figure 2 In this implementation, a malicious third party could modify the software so that the processing unit never extracts the application's first address, which would not trigger the protection mechanism. The application might then run incorrectly, but this could allow a third party to access certain information contained in the bootloader.

[0118] However, this is in Figure 4 The previous implementation is no longer possible because all addresses of the application's instructions are outside the bootloader's address range @0…@N. Therefore, at least one fetch of one instruction from the application's instructions will trigger the protection mechanism.

[0119] Now for reference Figure 5 And the following text will explain in Figure 2 The implementation of the protection mechanism PRT triggered in step ST26.

[0120] like Figure 5 As shown, in this stage, the processing unit UT executes the instructions of the application (second group GR2) (step ST5).

[0121] In step ST50, the processing unit UT issues a request to retrieve the instruction located at address @1 in memory MM1.

[0122] Therefore, address @1 is delivered on the address thread for the instruction bus and controlled by the control circuit CTRL. Figure 1 ).

[0123] In this example, it is assumed that the second auxiliary memory MMX2 contains the entire address range @0…@N of the boot instructions. In other words, it is expected that new access to all bootloaders will be prohibited.

[0124] In step ST51, the control circuit then verifies whether address @1 belongs to the address range @0…@N.

[0125] If address @1 does not belong to the address range, the corresponding instruction can be fetched from memory MM1 (step ST52) and then executed (step ST53).

[0126] However, if address @1 is found to belong to the address range @0…@N in step ST51, the control circuit will prevent the new execution of the instruction. In this example, this prohibition causes the microcontroller's (MCU) control circuit to reset by, for example, setting the reset signal RST to 0 (step ST54).

[0127] Therefore, it can be seen here that the instruction, which is the request body of the processing unit, is not delivered on the instruction bus.

[0128] Alternative locations, such as Figure 6 As shown, step ST64 can be performed instead of step ST54, wherein the control circuit delivers the base instruction (in this case, the NOP instruction) contained in register RG1 to the processing unit on the instruction bus.

[0129] Similarly, the instruction stored at address @1 and requested by the processing unit UT was not delivered to the processing unit UT.

[0130] like Figure 7 As shown, it may be desirable to protect only a portion of the bootloader's instructions so that users can still access certain coded services within the bootloader during application execution.

[0131] Therefore, in this case, such as Figure 7 As shown, only the address subrange @0…@J is stored in the second auxiliary memory MMX2.

[0132] Furthermore, in step ST71, the control circuit CTRL verifies whether the address @1 of the instruction requested by the processing unit belongs to the address subrange @0…@G. If it does not belong to the subrange, then execution is performed. Figure 5 Steps ST52 and ST53.

[0133] However, if address @1 is a protected address, i.e., belongs to the subrange @0…@J, then execution is performed. Figure 5 or Figure 6 Step ST54 or step ST64.

[0134] Now, for more specific reference Figure 8 and Figure 9 To illustrate one implementation, a protection mechanism PRT protects access to data D during the execution of an application.

[0135] This execution is by Figure 8 The steps are illustrated in ST8.

[0136] In this example, it is assumed that the data D to be protected (which is not expected to be accessible by the processing unit UT during the execution of the application) is stored in the address range @K…@L in the third auxiliary memory MMX3.

[0137] When the processing unit UT issues a request to access data D in step ST80, it delivers the address @1 of the requested data on the address thread of the data bus.

[0138] Then, the control circuit verifies whether the address @1 belongs to the address range stored in the third auxiliary memory MMX3.

[0139] If this is not the case, the requested data is read effectively (step ST82).

[0140] However, if address @1 belongs to the data range @K…@L, then reading that data is again prohibited.

[0141] At this point, the control circuit CTRL can reset the microcontroller MCU as shown in step ST84.

[0142] Alternative locations, such as Figure 9 As shown, instead of resetting the microcontroller MCU, the control circuit CTRL can deliver the reference data DO (e.g., zero data) contained in register RG2, instead of delivering the requested data D (step ST94).

[0143] As previously seen, the protection criteria CP, address range PAD2, and address range PAD3 are stored in the auxiliary memories MMX1, MMX2, and MMX3 respectively.

[0144] To improve security, such as Figure 10 As shown, the protection procedure ST100 can be applied to each of these parameters CP, PAD2, and PAD3. The protection procedure ST100 can be the same or different for each of the parameters.

[0145] Such protection processes may include, for example, scrambling the bits of these parameters, or actually adding a CRC ("checksum") type control word to the various parameters, or may also include encryption processes, or actually a combination of at least some of these processes.

[0146] These protected parameters are then stored in the first auxiliary memory MMX1 (step ST101), the second auxiliary memory MMX2 (step ST102), and the third auxiliary memory (step ST103), respectively.

[0147] Of course, during the reading of auxiliary memory, the control circuit will apply a reverse protection process to find the original parameters.

Claims

1. A method for protecting a system, the system comprising a processing unit and a memory, the memory storing at least one first set of instructions and a second set of instructions executable by the processing unit, the method comprising: The processing unit sequentially retrieves the instructions of the first group of instructions and the instructions of the second group of instructions from the memory for execution; The storage address of each extracted instruction is compared with the protection criteria; as well as In response to the comparison of the memory address satisfying the protection criteria, a protection mechanism is triggered, the protection mechanism including at least one prohibition of the processing unit from re-executing at least a portion of the instructions of the first set of instructions during the execution of the instructions of the second set of instructions. The protection criterion is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions. When the address of the protected instruction is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions, the protected instruction satisfies the protection criterion. Alternatively, the protection criterion includes a first address range. When the address of the protected instruction is outside the first address range, the protected instruction satisfies the protection criterion.

2. The method of claim 1, wherein the system further comprises a communication bus and at least one master device connected to the bus, and the protection mechanism further comprises prohibiting the at least one master device from accessing at least a portion of the instructions of the extracted first set of instructions during execution of the instructions of the extracted second set of instructions.

3. The method according to claim 1, wherein the first address range is the address range of the extracted first group of instructions.

4. The method of claim 1, wherein the protection mechanism includes prohibiting the processing unit from re-executing all instructions in the instructions of the extracted first set of instructions during the execution of the instructions of the extracted second set of instructions, or includes prohibiting the at least one master device from accessing all instructions in the instructions of the extracted first set of instructions during the execution of the instructions of the extracted second set of instructions.

5. The method of claim 2, wherein the prohibition of re-execution of the protected instruction of the portion by the processing unit, or the prohibition of access to the protected instruction of the portion by the at least one master device, comprises: Detect a new request issued by the processing unit or by the at least one master device to retrieve the protected instruction from the memory; as well as Perform an action to prevent the new request to extract the protected instruction from being provided.

6. The method of claim 5, wherein performing the action includes resetting the system.

7. The method of claim 6, wherein performing the action comprises: Instead of delivering the protected instruction, the reference instruction is delivered to the processing unit or to the at least one master device.

8. The method of claim 5, wherein at least a portion of the extracted instructions of the first set of instructions protected by the protection mechanism is stored at a storage address belonging to at least one second address range, and detecting the new request to extract the protected instructions comprises: The address of the protected instruction is compared with the at least one second address range.

9. The method according to claim 2, wherein the protection mechanism further comprises: During the execution of the second set of instructions, the processing unit or the at least one master device is prohibited from accessing at least one protected data stored in the memory.

10. The method of claim 9, wherein the access prohibition includes: Detect a new request issued by the processing unit or by the at least one master device to retrieve the protected data from the memory; as well as Perform actions to prevent the new request to extract the protected data from being provided.

11. The method of claim 10, wherein performing the action includes resetting the system.

12. The method of claim 10, wherein performing the action comprises: Instead of delivering the protected data, the reference data is delivered to the processing unit or to the at least one master device.

13. The method of claim 10, wherein the at least one protected data protected by the protection mechanism is stored at a storage address belonging to at least one third address range, and detecting the new request to retrieve the protected data comprises: The address of the protected data is compared with the at least one third address range.

14. The method of claim 1, wherein the system is a microcontroller, the first set of instructions includes boot instructions, and the second set of instructions includes instructions for the application program.

15. An electronic system comprising: Processing unit; The memory is configured to store at least one first set of instructions and a second set of instructions executable by the processing unit, wherein the processing unit is configured to sequentially fetch instructions from the memory of the first set of instructions and instructions from the second set of instructions for execution. as well as The controller includes: The first auxiliary storage is configured to store protection criteria; A comparator is configured to compare the storage address of each fetched instruction with the protection criteria; and The control circuit is configured to: in response to the storage address satisfying the protection criterion, trigger a protection mechanism, the protection mechanism including at least one prohibition of the processing unit from re-executing at least a portion of the instructions of the first set of instructions during the execution of the instructions of the second set of instructions; The protection criterion is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions, and the protected instruction satisfies the protection criterion when the address of the protected instruction is the address of the first instruction of the second group of instructions or the address of the last instruction of the first group of instructions; or the protection criterion includes a first address range, and the protected instruction satisfies the protection criterion when the address of the protected instruction is outside the first address range.

16. The system of claim 15, further comprising a communication bus and at least one master device connected to the bus, wherein the protection mechanism further comprises prohibiting the at least one master device from accessing at least a portion of the instructions of the extracted first set of instructions during execution of the instructions of the extracted second set of instructions.

17. The system of claim 15, wherein the first address range is the address range of the instructions of the extracted first group of instructions.

18. The system of claim 15, wherein the control circuit is configured to: at least prevent the processing unit from executing all instructions in the instructions of the extracted first set of instructions again during the execution of instructions of the extracted second set of instructions, or at least prevent the at least one master device from accessing all instructions in the instructions of the extracted first set of instructions during the execution of instructions of the extracted second set of instructions.

19. The system of claim 16, wherein, in order to prevent the processing unit from executing the protected instructions of the portion again or to prevent the at least one master device from accessing the protected instructions of the portion, the control circuit is configured to: Detecting a new request from the processing unit or the at least one master device to retrieve the protected instruction from the memory; and Perform an action to prevent the new request to extract the protected instruction from being provided.

20. The system of claim 19, wherein the control circuitry is configured to perform the action by resetting the system.

21. The system of claim 19, wherein the control circuitry is configured to perform the action by delivering a reference instruction to the processing unit or to the at least one master device, rather than delivering the protected instruction.

22. The system of claim 19, wherein at least a portion of the instructions of the extracted first set of instructions protected by the protection mechanism is stored at a storage address belonging to at least one second address range, the control circuitry includes a second auxiliary memory configured to store at least one second address range, and the control circuitry is configured to detect the new request to extract the protected instructions by comparing the address of the protected instructions with the at least one second address range.

23. The system of claim 22, wherein the protection mechanism further comprises: During the execution of the second set of instructions, the processing unit or the at least one master device is prohibited from accessing at least one protected data stored in the memory.

24. The system of claim 23, wherein the access prohibition includes: The control circuit is configured to: Detect a new request issued by the processing unit or by the at least one master device to retrieve the protected data from the memory; as well as Perform actions to prevent the new request to extract the protected data from being provided.

25. The system of claim 24, wherein the control circuitry is configured to perform the action by resetting the system.

26. The system of claim 24, wherein the control circuitry is configured to perform the action by delivering reference data to the processing unit or to the at least one master device, rather than delivering the protected data.

27. The system of claim 23, wherein the at least one protected data protected by the protection mechanism is stored at a storage address belonging to at least one third address range, the control circuitry includes a third auxiliary memory configured to store the at least one third address range, and the control circuitry is configured to detect a new request to retrieve the protected data by comparing the address of the protected data with the at least one third address range.

28. The system of claim 27, wherein the protection criteria and the second address range and the third address range are stored in a protected manner.

29. The system of claim 15, wherein the system is a microcontroller, the first set of instructions includes boot instructions, and the second set of instructions includes instructions for the application program.

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