Anti-fuse storage device, storage array and programming method of anti-fuse storage device

Abstract

The present invention discloses an anti-fuse storage device, a storage array and a programming method of the anti-fuse storage device. When the driving circuit of the anti-fuse storage device programs the selected anti-fuse memory cell, by floating the unselected anti-fuse control line or applying a second control line voltage to the unselected anti-fuse control line, the voltage difference between the unselected bit line and the unselected anti-fuse control line will be eliminated or reduced to an acceptable value. The leakage current flowing from the unselected bit line through the broken anti-fuse transistor to the unselected anti-fuse control line will be reduced or eliminated, thereby avoiding programming interference.

Description

Technical Field

[0001] The present invention relates to an anti-fuse storage device and a control method thereof, in particular to an anti-fuse storage device capable of preventing leakage current and programming interference and a control method thereof. Background Art

[0002] Non-volatile memory (NVM) devices can retain stored data even after the power is turned off, and thus have become a type of storage device widely used in personal computers and electronic devices.

[0003] Anti-fuse memory devices are a type of one-time programming (OTP) non-volatile memory widely used in electronic devices. By applying voltage, current flows through the junction of the oxide layer and moves the dopants, so that the oxide layer of the anti-fuse transistor is broken (also called "ruptured"), thereby forming a conductive path. However, in a memory array formed by anti-fuse transistors, the oxide layer of programmed and unselected memory cells may rupture, causing leakage current during the programming operation of adjacent selected memory cells, resulting in the problem of program disturbance. Summary of the invention

[0004] An embodiment of the present invention discloses an anti-fuse memory device, which includes a plurality of anti-fuse control lines, a plurality of word lines, a plurality of bit lines, and a plurality of anti-fuse memory cells. The plurality of anti-fuse control lines include a first anti-fuse control line, the plurality of word lines include a first word line, and the plurality of bit lines include a first bit line. Each anti-fuse memory cell is coupled to a corresponding anti-fuse control line, a corresponding word line, and a corresponding bit line. When one of the anti-fuse memory cells is selected during a programming operation of the anti-fuse memory device, the first anti-fuse control line coupled to the selected anti-fuse memory cell is used to receive a first control line voltage, the first word line coupled to the selected anti-fuse memory cell is used to receive a first word line voltage, the first bit line coupled to the selected anti-fuse memory cell is used to receive a first bit line voltage, the other bit lines except the first bit line are used to receive a second bit line voltage higher than the first bit line voltage, and the other anti-fuse control lines except the first anti-fuse control line are in a floating state, or are used to receive a second control line voltage higher than the first bit line voltage. The second control line voltage is equal to or lower than the second bit line voltage and higher than the ground voltage.

[0005] Another embodiment of the present invention discloses a memory array, which includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. When the memory array performs a programming operation and the first memory cell is selected: a first control line coupled to the first memory cell and the second memory cell is used to receive a first control line voltage; a first word line coupled to the first memory cell and the second memory cell is used to receive a first word line voltage; a first bit line coupled to the first memory cell and the third memory cell is configured to receive a first bit line voltage; a second control line coupled to the third memory cell and the fourth memory cell is configured to be in a floating state or receive a second control line voltage; a second word line coupled to the third memory cell and the fourth memory cell is used to receive a second word line voltage; and a second bit line coupled to the second memory cell and the fourth memory cell is used to receive a second bit line voltage. The first control line voltage is higher than the second control line voltage, the first word line voltage is higher than the second word line voltage, and the first bit line voltage is lower than the second bit line voltage. The second control line voltage is higher than a ground voltage and lower than or equal to the second bit line voltage.

[0006] Another embodiment of the present invention discloses a programming method for an anti-fuse storage device, wherein the anti-fuse storage device includes multiple anti-fuse control lines, multiple word lines, multiple bit lines, multiple anti-fuse memory cells and a driving circuit, each anti-fuse memory cell is coupled to a corresponding anti-fuse control line, a corresponding word line and a corresponding bit line, and the driving circuit is used to control the operation of the anti-fuse memory cell through the anti-fuse control line, the word line and the bit line. The programming method includes: a driving circuit applies a first control line voltage to an anti-fuse control line coupled to a selected anti-fuse memory cell, applies a first word line voltage to a word line coupled to the selected anti-fuse memory cell, and applies a first bit line voltage to a bit line coupled to the selected anti-fuse memory cell to program the selected anti-fuse memory cell; when the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a second bit line voltage greater than the first bit line voltage to the remaining bit lines; and when the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a second control line voltage to the remaining anti-fuse control lines, or drives the remaining anti-fuse control lines to a floating state, wherein the second control line voltage is equal to or lower than the second bit line voltage and higher than a ground voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An anti-fuse memory device according to an embodiment of the present invention is illustrated.

[0008] Figure 2 Draws Figure 1 Several anti-fuse memory cells of the anti-fuse storage device.

[0009] Figure 3 and Figure 4Other anti-fuse memory devices according to different embodiments of the present invention are shown.

[0010] The reference numerals are described as follows:

[0011] 1, 1B, 1C: Antifuse storage device

[0012] 10: Storage Array

[0013] 20, 20C: Driving circuit

[0014] 22, 22C: Control unit

[0015] 30: Pseudo-ground circuit

[0016] 100, A11 to A33: Anti-fuse memory cells

[0017] AF1 to AFn: Anti-fuse control lines

[0018] BL1 to BLm: bit lines

[0019] GND: Second power supply terminal

[0020] FL1, FL2, FL3: follow the gate line

[0021] N1: The first N-type transistor

[0022] N2: Second N-type transistor

[0023] P1: The first P-type transistor

[0024] P2: Second P-type transistor

[0025] PVSS: Second control line voltage

[0026] Q1: P-type transistor

[0027] Q2: N-type transistor

[0028] Rp: rupture point

[0029] S1 to Sn: Select signal

[0030] SW: Switch

[0031] T1: Anti-fuse transistor

[0032] T2: Follower gate transistor

[0033] T3: Select transistor

[0034] VAF: First control line voltage

[0035] VDD2: First power supply terminal

[0036] WL1, WL2, WL3: word lines

[0037] ZEN: Operation signal DETAILED DESCRIPTION

[0038] Figure 1 An anti-fuse storage device 1 according to an embodiment of the present invention is shown. Figure 2 Draws Figure 1 The anti-fuse memory device 1 includes a plurality of anti-fuse memory cells A11 to A33. The anti-fuse memory device 1 includes a memory array 10 and a drive circuit 20. The memory array 10 includes a plurality of anti-fuse control lines AF1 to AFn, a plurality of word lines (e.g., Figure 2 The memory array 10 includes anti-fuse cells 100, a plurality of anti-fuse cells 100, a plurality of bit lines BL1 to BLm, and a plurality of anti-fuse cells 100. The anti-fuse cells 100 of the memory array 10 are arranged in m rows and n columns, where m and n are integers greater than 1. Each anti-fuse cell 100 is coupled to a corresponding anti-fuse control line, a corresponding word line, and a corresponding bit line. For example, the anti-fuse cell A21 is coupled to the anti-fuse control line AF2, the word line WL2, and the bit line BL1. The anti-fuse cell A13 is coupled to the anti-fuse control line AF1, the word line WL1, and the bit line BL3. Figure 2 The anti-fuse memory cells A11 to A33 shown in FIG. 1 are exemplarily selected from Figure 1 The anti-fuse memory cell 100 of the memory array 10 is shown in FIG.

[0039] In one embodiment of the present invention, each anti-fuse memory cell 100 includes an anti-fuse transistor T1 and a selection transistor T3. The anti-fuse transistor T1 has a thin oxide layer with a lower breakdown voltage and is coupled to a corresponding anti-fuse control line (e.g., AF1, AF2, or AF3). The selection transistor T3 is coupled to a corresponding word line (e.g., WL1, WL2, or WL3) and a corresponding bit line (e.g., BL1, BL2, or BL3). In another embodiment, each anti-fuse memory cell 100 may further include a follower gate transistor T2, which is coupled to a corresponding follower gate line (e.g., FL1, FL2, or FL3) and is coupled between the anti-fuse transistor T1 and the selection transistor T3. In other words, in some embodiments of the present invention, the follower gate transistor T2 is a selective component, and the anti-fuse transistor T1 may be directly coupled to the selection transistor T3. It is worth noting that the anti-fuse transistor T1 may be implemented by other types of transistors whose oxide layers may be easily broken down or ruptured.

[0040] During the programming operation of the anti-fuse memory device 1, one of the anti-fuse memory cells will be selected, and the relevant voltage will be applied to each anti-fuse memory cell 100 via the anti-fuse control lines AF1 to AFn, the word lines (e.g., WL1 to WL3), and the bit lines BL1 to BLm. For example, when the anti-fuse memory cell A31 is selected by the driving circuit 20 for programming, the voltage applied from the driving circuit 20 to the anti-fuse control lines AF1 to AF3, the word lines WL1 to WL3, the follower gate lines FL1 to FL3, and the bit lines BL1 to BL3 can be as shown in the following Table 1.

[0041]

[0042] (Table 1)

[0043] When the driving circuit 20 programs the selected anti-fuse memory cell A31, the anti-fuse control line AF3 coupled to the selected anti-fuse memory cell A31 is applied with a first control line voltage of 6 volts, the follower gate line FL3 coupled to the selected anti-fuse memory cell A31 is applied with a first follower gate line voltage of 2.2 volts, the word line WL3 coupled to the selected anti-fuse memory cell A31 is applied with a first word line voltage of 1.5 volts, and the bit line BL1 coupled to the selected anti-fuse memory cell A31 is applied with a first bit line voltage of 0 volts. In addition, when the driving circuit 20 programs the selected anti-fuse memory cell A31, the remaining anti-fuse control lines AF1 and AF2 are in a floating state or are applied with a second control line voltage of 0.5 to 1.5 volts, the remaining follower gate lines FL1 and FL2 are applied with a second follower gate line voltage of 0 volts, the remaining word lines WL1 and WL2 are applied with a second word line voltage of 0 volts, and the remaining bit lines BL2 and BL3 are applied with a second bit line voltage of 1.5 volts.

[0044] In this embodiment, the first control line voltage is higher than the first follower gate line voltage. The first follower gate line voltage is higher than the first word line voltage. The second bit line voltage is higher than the first word line voltage, or substantially equal to the first word line voltage, to ensure that the transistor T3 in each unselected storage cell (e.g., A32 and A33) can be turned off. In this embodiment, since the second control line voltage is 0.5 to 1.5 volts and the second bit line voltage is 1.5 volts, the second control line voltage is equal to or less than the second bit line voltage.

[0045] By following the magnitude relationship of the voltage values ​​of the above-mentioned voltages, the voltages of the present invention may not be limited to the voltage values ​​mentioned above.

[0046] In the present embodiment, the anti-fuse memory cell A12 has been programmed. In other words, the anti-fuse transistor T1 of the anti-fuse transistor A12 has been broken, and a rupture Rp with low resistance is formed. Therefore, leakage current may flow from the bit line BL2 to the anti-fuse control line AF1 through the broken anti-fuse transistor T1. However, since the anti-fuse control line AF1 is in a floating state or a second control line voltage of 0.5 to 1.5 volts is applied, when the driving circuit 20 programs the selected anti-fuse memory cell A31, the voltage difference between the bit line BL2 and the anti-fuse control line AF1 has been eliminated or reduced to an acceptable value. Therefore, the leakage current flowing from the bit line BL2 to the anti-fuse control line AF1 through the broken anti-fuse transistor T1 will be reduced or eliminated. Due to the reduction or elimination of leakage current, the voltage level of the bit line BL2 will remain stable (for example, the voltage level of the bit line BL2 remains at 1.5V), so that the anti-fuse transistor T1 of the anti-fuse memory cell A32 adjacent to the selected anti-fuse memory cell A31 and coupled to the selected anti-fuse control line AF3 is protected from program disturbance.

[0047] As mentioned above, the follower gate transistor T2 is an optional component in some embodiments of the present invention.

[0048] For these embodiments, the aforementioned Table 1 can be simplified into the following Table 2.

[0049]

[0050] (Table 2)

[0051] In one embodiment of the present invention, the driving circuit 20 may include a plurality of control units 22. Each control unit 22 is used to output a first control line voltage (e.g., 6 volts) or a second control line voltage (e.g., 0.5 to 1.5 volts) to an anti-fuse control line (e.g., AF1, ..., or AFn) coupled to the control unit 22 according to a selection signal (e.g., S1, ..., or Sn). Each control unit 22 may include a P-type transistor Q1 and an N-type transistor Q2. The P-type transistor Q1 has a first end to which the first control line voltage (i.e., VAF) is applied, a second end coupled to the corresponding anti-fuse control line (e.g., AF1, ..., or AFn), and a control end for receiving a selection signal (e.g., S1, ..., or Sn). The N-type transistor Q2 has a first end coupled to the corresponding anti-fuse control line (e.g., AF1, ..., or AFn), a second end to which the second control line voltage (i.e., PVSS) is applied, and a control end for receiving a selection signal (e.g., S1, ..., or Sn). The selection signals S1 to Sn are used to control the corresponding control unit 22. For example, when the selection signal S1 is at a high voltage level, the anti-fuse control line AF1 is applied with a second control line voltage PVSS (e.g., 0.5 volts to 1.5 volts). When the selection signal S1 is at a low voltage level, the anti-fuse control line AF1 is applied with a first control line voltage VAF (e.g., 6 volts). In one embodiment of the present invention, the anti-fuse memory device 1 may further include a pseudo-ground circuit 30. The pseudo-ground circuit 30 is used to output the second control line voltage PVSS, and may include a first P-type transistor P1, a second P-type transistor P2, and a first N-type transistor N1. The first-type transistor P1 has a first terminal coupled to the first power supply terminal VDD2, and a control terminal for receiving the operation signal ZEN. The second P-type transistor P2 has a first terminal coupled to the second terminal of the first P-type transistor P1, a second terminal coupled to the output terminal of the pseudo-ground circuit 30, and a control terminal for receiving the operation signal ZEN. The first N-type transistor N1 has a first terminal coupled to the output terminal of the virtual ground circuit 30 , a second terminal coupled to the second power terminal GND, and a control terminal coupled to the output terminal of the virtual ground circuit 30 .

[0052] The operation signal ZEN is used to control the anti-fuse memory device 1 to perform a programming operation or a reading operation. When the voltage level of the operation signal ZEN is at a low level, the anti-fuse memory device 1 performs a programming operation, and the pseudo ground circuit 30 outputs the second control line voltage PVSS to the driving circuit 20. When the anti-fuse memory device 1 performs a programming operation, since the second terminal of the first N-type transistor N1 is grounded and the first N-type transistor N1 is turned on, the second control line voltage PVSS outputted by the output terminal of the pseudo ground circuit 30 may be equal to the threshold voltage (e.g., 0.5 volts) of the first N-type transistor N1.

[0053] In one embodiment of the present invention, the pseudo ground circuit 30 may further include a second N-type transistor N2 having a first terminal coupled to the output terminal of the pseudo ground circuit 30, a second terminal coupled to the second power terminal GND, and a control terminal for receiving the operation signal ZEN. When the anti-fuse memory device 1 performs a read operation, the voltage level of the operation signal ZEN is at a high level to turn on the second N-type transistor N2, thereby coupling the output terminal of the pseudo ground circuit 30 to the second power terminal GND. Therefore, when the anti-fuse memory device 1 performs a read operation, the voltage level of the output terminal of the pseudo ground circuit 30 may be 0 volts.

[0054] In some embodiments, the first N-type transistor N1 may have better / stronger driving capability (eg, stronger than the driving capability of the P-type transistors P1 and P2) to drive the output of the pseudo ground circuit 30 to the ground voltage when the anti-fuse memory device 1 performs a programming operation.

[0055] although Figure 1 The structure of the pseudo ground circuit 30 is shown, but the present invention is not limited thereto. For example, in some other embodiments, the second P-type transistor P2 may be omitted, and the second end of the first P-type transistor P1 may be coupled to the output end of the pseudo ground circuit 30. In some other embodiments, the first P-type transistor P1 and the second P-type transistor P2 may be connected in series or in parallel with more transistors. In some other embodiments, the first N-type transistor N1 may be connected in series or in parallel with more transistors according to the required circuit specifications. For example, when the second N-type transistor N2 is connected between the first N-type transistor N1 and the second power supply terminal GND, the first end and the control end of the first N-type transistor N1 are connected to the output end of the pseudo ground circuit 30, the second end of the first N-type transistor N1 is connected to the control end and the first end of the second N-type transistor N2, and the second end of the second N-type transistor N2 is connected to the second power supply terminal GND, then the second control line voltage PVSS will be equal to the sum of the critical voltage of the first N-type transistor N1 and the critical voltage of the second N-type transistor N2.

[0056] Due to the limitation of the cross-voltages of the transistor, when the second control line voltage PVSS replaces the voltage of the second power terminal GND (e.g., the ground voltage), the first control line voltage VAF can be a higher voltage (e.g., a voltage greater than 6 volts). In this way, when the anti-fuse memory device 1 performs a programming operation, the voltage difference between the bit line coupled to the selected anti-fuse memory cell 100 and the anti-fuse control line will increase, thereby improving the programming efficiency of the anti-fuse memory device 1.

[0057] In this specification, the anti-fuse control line coupled to the selected anti-fuse memory may be referred to as the "selected anti-fuse control line", and the remaining anti-fuse control lines except the selected anti-fuse control line may be referred to as the "unselected anti-fuse control line". The above description can be analogized to the follower gate line, word line and bit line. According to such a definition, when the anti-fuse memory cell A31 is selected for programming, the anti-fuse control line AF3 is the selected anti-fuse control line, the follower gate line FL3 is the selected follower gate line, the word line WL3 is the selected word line, the bit line BL1 is the selected bit line, the anti-fuse control lines AF1 and AF2 are unselected anti-fuse control lines, the follower gate lines FL1 and FL2 are unselected follower gate lines, the word lines WL1 and WL2 are unselected word lines, and the bit lines BL2 and BL3 are unselected bit lines.

[0058] Figure 3 An anti-fuse memory device 1B according to another embodiment of the present invention is shown. The main differences between the anti-fuse memory devices 1 and 1B are as follows: the anti-fuse memory device 1B further includes a switch SW coupled between the driving circuit 20 and the pseudo ground circuit 30. The opening and closing of the switch SW is related to the operation of the memory array 10. For example, when the operation signal ZEN is at a low level and the switch SW is opened, the unselected anti-fuse control line (e.g., AF1, ... or AFn) coupled to the unselected anti-fuse memory cell 100 will receive the second control line voltage PVSS. When the switch SW is closed, the anti-fuse control line coupled to the unselected anti-fuse memory cell 100 will be in a floating state.

[0059] Figure 4 An anti-fuse memory device 1C according to another embodiment of the present invention is shown. The main differences between the anti-fuse memory devices 1 and 1C are as follows: Figure 1 The driving circuit 20 of the anti-fuse memory device 1 is shown Figure 4 The anti-fuse memory device 1C shown is replaced by a driving circuit 20C. The driving circuit 20C includes a plurality of control units 22C. Figure 4 The control unit 22C in Figure 1 The control unit 22C is similar to the control unit 22 in FIG. 1 , and the main difference between the control unit 22C and the control unit 22 is that each control unit 22C further includes a switch SW coupled between the output terminal of the pseudo ground circuit 30 and the second terminal of the N-type transistor Q2. The switch SW can be opened and closed during the operation of the memory array 10. For example, when the operation signal ZEN is at a high level and the switch SW is opened, the anti-fuse control line (e.g., AF1, ... or AFn) coupled to the opened switch SW will receive the second control line voltage PVSS. When the switch SW is closed, the anti-fuse control line coupled to the closed switch SW is in a floating state.

[0060] In summary, when the driver circuit programs the selected anti-fuse memory cell, by floating the unselected anti-fuse control line or applying the second control line voltage to the unselected anti-fuse control line, the voltage difference between the unselected bit line and the unselected anti-fuse control line will be eliminated or reduced to an acceptable value. Therefore, the leakage current flowing from the unselected bit line to the unselected anti-fuse control line through the broken anti-fuse transistor will be reduced or eliminated. Due to the reduction or elimination of the leakage current, the voltage level of the remaining unselected bit lines will remain stable, thereby protecting the anti-fuse transistor coupled to the selected anti-fuse control line from programming disturbance. In addition, due to the limitation of the cross-voltages of the transistor, by receiving the second control line voltage PVSS instead of receiving the ground voltage, the first control line voltage VAF can have a larger voltage level (for example, greater than 6 volts). As a result, when the anti-fuse memory device performs a programming operation, the voltage difference between the bit line coupled to the selected anti-fuse memory cell and the anti-fuse control line will increase, thereby improving the programming efficiency of the anti-fuse memory device.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An anti-fuse storage device, characterized in that: The anti-fuse storage device comprises: a plurality of anti-fuse control lines, including a first anti-fuse control line; A plurality of word lines, including a first word line; a plurality of bit lines, including a first bit line; A plurality of anti-fuse memory cells, each anti-fuse memory cell is coupled to a corresponding anti-fuse control line, a corresponding word line and a corresponding bit line; as well as A pseudo grounding circuit, used for outputting a second control line voltage; When an anti-fuse memory cell among the anti-fuse memory cells is selected during a programming operation of the anti-fuse storage device: The first anti-fuse control line coupled to the selected anti-fuse memory cell is used to receive a first control line voltage; The first word line coupled to the selected anti-fuse memory cell is used to receive a first word line voltage; The first bit line coupled to the selected anti-fuse memory cell is used to receive a first bit line voltage; The other bit lines except the first bit line are used to receive a second bit line voltage higher than the first bit line voltage; and The other anti-fuse control lines except the first anti-fuse control line are in a floating state or are used to receive the second control line voltage higher than the first bit line voltage, wherein the second control line voltage is equal to or lower than the second bit line voltage and higher than a ground voltage.

2. The anti-fuse storage device according to claim 1, wherein: During the programming operation, other word lines except the first word line are used to receive a second word line voltage lower than the first word line voltage.

3. The anti-fuse storage device according to claim 1, wherein: Each anti-fuse memory cell comprises: an anti-fuse transistor coupled to the corresponding anti-fuse control line; and The select transistor is coupled to the corresponding word line and the corresponding bit line.

4. The anti-fuse storage device according to claim 3, characterized in that: The anti-fuse storage device further comprises: Multiple follower gate lines; Wherein, each anti-fuse memory cell further comprises: The follower gate transistor is coupled to a corresponding follower gate line and is coupled between the anti-fuse transistor and the selection transistor.

5. The anti-fuse storage device according to claim 4, wherein: During this programming operation: A first follower gate line among the follower gate lines coupled to the selected anti-fuse memory cell is used to receive a first follower gate line voltage; and The other follower gate lines except the first follower gate line are used to receive a second follower gate line voltage which is lower than the first follower gate line voltage.

6. The anti-fuse memory device according to claim 1, wherein: The anti-fuse storage device further comprises: The driving circuit includes a plurality of control units, each of which is used to output the first control line voltage or the second control line voltage to an anti-fuse control line among the anti-fuse control lines according to a selection signal, wherein each of the control units includes: P-type transistor, with: a first terminal to which the first control line voltage is applied; a second end coupled to the anti-fuse control line coupled to each control unit; as well as a control terminal for receiving the selection signal; and N-type transistor, with: a first end coupled to the anti-fuse control line coupled to each control unit; a second terminal to which the second control line voltage is applied; and A control terminal is used to receive the selection signal.

7. The anti-fuse memory device according to claim 1, wherein: The pseudo ground circuit includes: The first P-type transistor has a first terminal coupled to a first power source, a second terminal coupled to an output terminal of the pseudo ground circuit, and a control terminal for receiving an operation signal; as well as The first N-type transistor has a first terminal, a control terminal coupled to the output terminal of the pseudo ground circuit, and a second terminal coupled to a second power terminal.

8. The anti-fuse memory device according to claim 7, wherein: The pseudo ground circuit further includes: a second N-type transistor having a first end coupled to the output end of the pseudo ground circuit, a second end coupled to the second power end, and a control end for receiving the operation signal.

9. The anti-fuse memory device according to claim 1, wherein: The anti-fuse memory device further comprises a switch coupled to the anti-fuse control lines and used for floating the other anti-fuse control lines except the first anti-fuse control line during the programming operation.

10. A storage array, characterized in that: The storage array includes: First memory cell; Second memory cell; The third memory cell; as well as Fourth memory cell; When the storage array performs a programming operation and the first memory cell is selected: A first control line coupled to the first memory cell and the second memory cell for receiving a first control line voltage; A first word line coupled to the first memory cell and the second memory cell for receiving a first word line voltage; A first bit line coupled to the first memory cell and the third memory cell is configured to receive a first bit line voltage; A second control line coupled to the third memory cell and the fourth memory cell is configured to be in a floating state or to receive a second control line voltage output by a pseudo ground circuit; A second word line coupled to the third memory cell and the fourth memory cell for receiving a second word line voltage; and A second bit line coupled to the second memory cell and the fourth memory cell for receiving a second bit line voltage; wherein the first control line voltage is higher than the second control line voltage, the first word line voltage is higher than the second word line voltage, and the first bit line voltage is lower than the second bit line voltage; and The second control line voltage is higher than a ground voltage and lower than or equal to the second bit line voltage.

11. The storage array according to claim 10, wherein: The first word line voltage is lower than or equal to the second bit line voltage.

12. A method for programming an anti-fuse storage device, characterized in that: The anti-fuse storage device includes a plurality of anti-fuse control lines, a plurality of word lines, a plurality of bit lines, a plurality of anti-fuse memory cells, a pseudo ground circuit and a driving circuit. The pseudo ground circuit is used to output a second control line voltage. Each anti-fuse memory cell is coupled to a corresponding anti-fuse control line, a corresponding word line and a corresponding bit line. The driving circuit is used to control the operations of the anti-fuse memory cells through the anti-fuse control lines, the word lines and the bit lines. The programming method includes: The driving circuit applies a first control line voltage to an anti-fuse control line coupled to a selected anti-fuse memory cell, applies a first word line voltage to a word line coupled to the selected anti-fuse memory cell, and applies a first bit line voltage to a bit line coupled to the selected anti-fuse memory cell, so as to program the selected anti-fuse memory cell; When the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a second bit line voltage greater than the first bit line voltage to the remaining bit lines; as well as When the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies the second control line voltage to the remaining anti-fuse control lines, or drives the remaining anti-fuse control lines to a floating state, wherein the second control line voltage is equal to or lower than the second bit line voltage and higher than a ground voltage.

13. The programming method according to claim 12, characterized in that: The programming method also includes: When the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a second word line voltage which is lower than the first word line voltage to the remaining word lines.

14. The programming method according to claim 12, characterized in that: Each anti-fuse memory cell includes: an anti-fuse transistor coupled to a corresponding anti-fuse control line; and The select transistor is coupled to a corresponding word line and a corresponding bit line.

15. The programming method according to claim 14, characterized in that: The anti-fuse storage device further comprises: a plurality of follower gate lines; Wherein, each anti-fuse memory cell further comprises: The follower gate transistor is coupled to a corresponding follower gate line and is coupled between the anti-fuse transistor and the selection transistor.

16. The programming method according to claim 15, characterized in that: The programming method also includes: When the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a first follower gate line voltage to the corresponding follower gate line; as well as When the driving circuit programs the selected anti-fuse memory cell, the driving circuit applies a second following gate line voltage lower than the first following gate line voltage to the remaining following gate lines.

17. The programming method according to claim 12, characterized in that: The driving circuit includes a plurality of control units, and each control unit is used for outputting the first control line voltage or the second control line voltage to an anti-fuse control line coupled to the control unit according to a selection signal.

18. The programming method according to claim 12, characterized in that: The pseudo ground circuit includes: The first P-type transistor has a first terminal coupled to a first power source and a control terminal for receiving an operation signal; A second P-type transistor having a first end coupled to a second end of the first P-type transistor, a second end coupled to an output end of the pseudo ground circuit, and a control end for receiving an operation signal; as well as The first N-type transistor has a first terminal, a second terminal coupled to a second power terminal, and a control terminal coupled to the output terminal of the pseudo ground circuit.

19. The programming method according to claim 18, characterized in that: The pseudo ground circuit further comprises: The second N-type transistor has a first end coupled to the output end of the pseudo ground circuit, a second end coupled to the second power end, and a control end for receiving the operation signal.

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