Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: temporarily bonding a qualified chip with a second carrier through a second bonding adhesive layer, a protective layer on a first surface of the chip being in contact with the second bonding adhesive layer; planarizing a side of the chip away from the second carrier to expose a bonding interface layer on a second surface of the chip; bonding the chip with a target wafer through the bonding interface layer on the second surface; removing the second carrier, a part of the second bonding adhesive layer remaining on the protective layer of the first surface; and planarizing a side of the chip away from the target wafer to remove the remaining second bonding adhesive layer and the protective layer on the first surface and expose the bonding interface layer on the first surface to obtain a bonding structure. The technical scheme of the application can prevent the mixed bonding interface from being in direct contact with the bonding adhesive, ensure that the surface of the bonding interface layer has high cleanliness, and avoid abnormal mixed bonding process between the chip and the target wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor device manufacturing method. BACKGROUND

[0002] Chip-wafer stacking technology is favored by global semiconductor giants because it is not limited by chip size matching, and its KGD (Known Good Die) scheme can greatly improve yield. At present, the mass production scheme of chip-wafer stacking technology mainly uses micro bump packaging technology, and the minimum pitch size (connection unit size) is about 40 μm. Moreover, the underfill between the micro bumps is not conducive to heat dissipation, so the research and development direction is developing towards a bumpless process with a smaller pitch size.

[0003] The main feature of the bumpless process is to realize metal-metal direct bonding on the bonding interface by using hybrid bonding technology, and the pitch size can be less than 10 μm, thereby realizing higher I / O connection density, and there is no underfill, so the heat dissipation performance is better. In the bumpless process, temporary bonding will be used. Specifically, the chips to be bonded and the carrier are temporarily bonded using bonding glue, and then the temporary bonding is removed, and the bonding glue is cleaned and removed using a glue removal solution. Then, the chips to be bonded and the target wafer are hybrid bonded. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can prevent the hybrid bonding interface from being directly contacted with the bonding glue, ensure that the surface of the bonding interface layer has very high cleanliness, and avoid abnormal hybrid bonding process between the chips and the target wafer.

[0005] To achieve the above purpose, the present application provides a semiconductor device manufacturing method, comprising:

[0006] Step S1, forming a plurality of test qualified chips, each chip has two opposite first and second surfaces, and a bonding interface layer and a protective layer are sequentially formed on each surface;

[0007] Step S2, providing a second carrier formed with a second bonding glue layer, temporarily bonding the chips to the second carrier through the second bonding glue layer, the protective layer on the first surface of the chip is in contact with the second bonding glue layer, and the adjacent chips have a gap therebetween;

[0008] Step S3, covering a medium layer on the chips, and the medium layer fills the gap;

[0009] Step S4, planarizing a side of the chip away from the second carrier until a bonding interface layer on the second side of the chip is exposed;

[0010] Step S5, bonding the chip to a target wafer through the bonding interface layer on the second side;

[0011] Step S6, performing a debonding process to remove the second carrier, leaving a portion of the second bonding adhesive layer on the protective layer of the first side; and,

[0012] Step S7, planarizing a side of the chip away from the target wafer to remove the remaining second bonding adhesive layer and the protective layer on the first side, and expose the bonding interface layer on the first side, to obtain a bonding structure.

[0013] Optionally, the step S1 comprises:

[0014] providing a device wafer;

[0015] forming a first bonding interface layer and a first protective layer on a front side of the device wafer in sequence;

[0016] providing a first carrier with a first bonding adhesive layer, temporarily bonding the device wafer to the first carrier through the first bonding adhesive layer, the first protective layer being in contact with the first bonding adhesive layer;

[0017] forming a second bonding interface layer and a second protective layer on a back side of the device wafer in sequence, the front side and the back side being opposite sides;

[0018] performing a debonding process to remove the first carrier; and,

[0019] performing a cutting process on the device wafer to obtain a chip that passes the test, a portion of the first bonding adhesive layer being left on the first protective layer of the chip.

[0020] Optionally, after temporarily bonding the device wafer to the first carrier through the first bonding adhesive layer and before forming the second bonding interface layer on the back side of the device wafer, the semiconductor device manufacturing method further comprises:

[0021] thinning the back side of the device wafer; and,

[0022] forming a conductive via structure on the back side of the device wafer.

[0023] Optionally, after forming the second bonding interface layer on the back side of the device wafer and before forming the second protective layer on the back side of the device wafer, the semiconductor device manufacturing method further comprises:

[0024] Testing the chips on the device wafer and marking the chips that pass the test.

[0025] Optionally, the first surface of the chip is the front surface of the device wafer, and the second surface of the chip is the back surface of the device wafer; in the step S4, the side of the chip away from the second carrier is planarized to remove the second protective layer.

[0026] Alternatively, the first surface of the chip is the back surface of the device wafer, and the second surface of the chip is the front surface of the device wafer; in the step S4, the side of the chip away from the second carrier is planarized to remove the residual first bonding glue layer and the first protective layer.

[0027] Optionally, the step S3 comprises:

[0028] forming a third bonding glue layer in the gap, the top surface of the third bonding glue layer being lower than the top surface of the chip; and,

[0029] covering an oxidation layer on the chip and the third bonding glue layer, the third bonding glue layer and the oxidation layer constituting the dielectric layer.

[0030] Optionally, after the step S4 and before the step S5 and / or after the step S7, a plasma process is performed to activate the bonding interface layer on the second surface of the chip and the bonding interface layer on the first surface of the chip.

[0031] Optionally, the second carrier is a light-transmitting substrate; the step S6 comprises: irradiating the second carrier and the second bonding glue layer with a laser to decompose the second bonding glue layer, thereby removing the second carrier and part of the second bonding glue layer.

[0032] Optionally, the method for manufacturing a semiconductor device further comprises:

[0033] The steps S1 to S7 are repeatedly executed in cycles, and the bonding structure obtained by the previous execution of the steps S1 to S7 is taken as the target wafer in the subsequent execution of the steps S1 to S7.

[0034] The present application also provides a semiconductor device, comprising:

[0035] a first chip;

[0036] a second chip having two opposite first and second surfaces, at least the first surface being provided with a bonding interface layer, the second chip being bonded to the first chip through the bonding interface layer on the first surface.

[0037] an oxidation layer covering the sidewall of a part of the height of the second chip; and

[0038] a bonding glue layer covering the sidewall of another part of the height of the second chip.

[0039] Optionally, the first chip is bonded with at least two layers of the second chip, and the bonding interface layer on the second face of the second chip close to the first chip is bonded with the bonding interface layer on the first face or the second face of the second chip away from the first chip.

[0040] Optionally, the first face is the front face of the second chip, and the second face is the back face of the chip; or, the first face is the back face of the second chip, and the second face is the front face of the chip.

[0041] Optionally, the oxidation layer covers the sidewall of a part of the height of the second chip close to the first chip; and the bonding glue layer covers the sidewall of another part of the height of the second chip away from the first chip.

[0042] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0043] 1. The manufacturing method of the semiconductor device of the present application forms a protective layer on the bonding interface layer of the chip that passes the test, so that the chip can avoid the contact between the bonding interface layer and the bonding glue layer when temporarily bonded with the carrier; and before the chip is mixedly bonded with the target wafer, the bonding glue layer and the protective layer remaining on the protective layer are removed by the planarization process, so that the mixed bonding interface can be prevented from directly contacting the bonding glue, the surface of the bonding interface layer has high cleanliness, and the abnormality of the mixed bonding process between the chip and the target wafer is avoided.

[0044] 2. The semiconductor device of the present application has the bonding interface layer on at least the first face of the second chip, the second chip is bonded with the first chip through the bonding interface layer on the first face, the bonding interface layer has high cleanliness, the abnormality of the mixed bonding between the second chip and the first chip is avoided, and the reliability of the semiconductor device is further avoided from being reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 is a flow chart of the manufacturing method of the semiconductor device of an embodiment of the present application;

[0046] Figures 2a-2r is Figure 1 the device schematic diagram of an embodiment in the manufacturing method of the semiconductor device shown in the figure;

[0047] Figures 3a-3i is Figure 1Device schematic diagram of another embodiment of the manufacturing method of the semiconductor device shown.

[0048] Figures 4a-4b Structure schematic diagram of the semiconductor device of an embodiment of the present application;

[0049] Figures 5a-5b Structure schematic diagram of the semiconductor device of another embodiment of the present application.

[0050] Wherein, the Figures 1-5b The reference signs in the drawings are explained as follows:

[0051] 11 - device wafer; 111 - first bonding interface layer; 112 - first protective layer; 113 - second bonding interface layer; 114 - second protective layer; 12 - first carrier; 121 - first bonding adhesive layer; 13 - blue film; 21 - chip; 22 - second carrier; 221 - second bonding adhesive layer; 23 - gap; 241 - third bonding adhesive layer; 242 - oxidation layer; 25 - target wafer; 30 - first chip; 311 - first bonding interface layer; 312 - second bonding interface layer; 31 - second chip; 32 - oxidation layer; 33 - bonding adhesive layer. DETAILED DESCRIPTION

[0052] In order to make the purpose, advantages and characteristics of the present application clearer, the semiconductor device and the manufacturing method thereof proposed by the present application are further described in detail below in combination with the drawings. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, which are only used to facilitate and clearly assist the purpose of describing the embodiments of the present application.

[0053] An embodiment of the present application provides a manufacturing method of a semiconductor device, referring to Figure 1 , Figure 1 Flow chart of the manufacturing method of the semiconductor device of an embodiment of the present application, the manufacturing method of the semiconductor device comprises:

[0054] Step S1, forming a plurality of qualified chips, a bonding interface layer and a protective layer are sequentially formed on two opposite first and second surfaces of each chip;

[0055] Step S2, providing a second carrier formed with a second bonding adhesive layer, temporarily bonding the chips with the second carrier through the second bonding adhesive layer, the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and the gap is provided between adjacent chips;

[0056] Step S3, covering a medium layer on the chips, the medium layer fills the gap;

[0057] Step S4, planarizing a side of the chip away from the second carrier until exposing the bonding interface layer on the second face of the chip;

[0058] Step S5, bonding the chip with a target wafer through the bonding interface layer on the second face;

[0059] Step S6, performing a debonding process to remove the second carrier, leaving part of the second bonding glue layer on the protective layer of the first face;

[0060] Step S7, planarizing a side of the chip away from the target wafer to remove the remaining second bonding glue layer and the protective layer on the first face, and exposing the bonding interface layer on the first face to obtain a bonding structure.

[0061] Reference will now be made to Figures 2a-3i the manufacturing method of the semiconductor device provided by the embodiment will be described in detail, Figure 2i is a top view of a semiconductor device, Figures 2a-2h , Figures 2j-2r , Figures 3a-3i is a longitudinal sectional view of a semiconductor device. Among them, Figures 2a-2r is an embodiment of the present application, Figures 2a-2i and Figures 3a-3i is another embodiment of the present application.

[0062] According to step S1, a plurality of qualified chips are formed, and a bonding interface layer and a protective layer are formed on two opposite first and second faces of each chip in sequence.

[0063] The step S1 includes: first, as shown in Figure 2a , a device wafer 11 is provided, which includes a substrate (not shown) and a device structure (not shown) formed on the substrate, and the device structure includes gate structure, metal interconnection structure, etc.; then, as shown in Figure 2a and Figure 2b , a first bonding interface layer 111 and a first protective layer 112 are formed on the front surface of the device wafer 11 in sequence; then, as shown in Figure 2c , a first carrier 12 is provided, and a first bonding glue layer 121 is formed, and the device wafer 11 is temporarily bonded to the first carrier 12 through the first bonding glue layer 121, and the first protective layer 112 is in contact with the first bonding glue layer 121; then, as shown in Figure 2d , the back surface of the device wafer 11 is thinned, that is, the substrate on the back surface of the device wafer 11 is thinned, and the front surface and the back surface are opposite surfaces; then, a conductive via structure (not shown) is formed on the back surface of the device wafer 11; then, as shown in Figure 2eAs shown, a second bonding interface layer 113 is formed on the back of the device wafer 11; then, the chips on the device wafer 11 are tested, and the chips that pass the test are marked, ready to be picked out after cutting, wherein testing the chips after forming the second bonding interface layer 113 instead of testing on the front side can prevent failure of the back process, so that the damaged chips are not identified; then, as shown, Figure 2f As shown, a second protective layer 114 is formed on the second bonding interface layer 113 on the back of the device wafer 11; then, as shown, Figure 2g As shown, a support film, such as a blue film 13 or a UV film (hereinafter, the blue film is taken as an example), is attached to the side of the second protective layer 114 away from the device wafer 11; then, as shown, Figure 2h As shown, a debonding process is performed to remove the first carrier 12, and the first bonding glue layer 121 remains on the first protective layer 112, so that the chip surface is protected from damage during the subsequent cutting process, and the particulate impurities caused by cutting will not fall on the chip surface; then, the device wafer 11 is subjected to a cutting process, and the first bonding glue layer 121 is removed by cleaning with a stripping solution, but since the stripping solution cannot completely remove the first bonding glue layer 121, part of the first bonding glue layer 121 remains on the first protective layer 112; then, the blue film 13 is expanded, so that the spacing between adjacent chips increases, facilitating the subsequent picking out of the chips 21 that pass the test for subsequent processes.

[0064] The first bonding interface layer 111 and the second bonding interface layer 113 each include an insulating medium layer (not shown) and a metal layer (not shown) in the insulating medium layer. The first protective layer 112 and the second protective layer 114 can be made of silicon oxide, silicon oxynitride, or silicon nitride, etc.

[0065] The front side of the device wafer 11 is formed with a device structure, and the back side of the device wafer 11 is a substrate. The first side of the chip 21 is the front side of the device wafer 11, and the second side of the chip 21 is the back side of the device wafer 11, so that the first bonding interface layer 111 and the first protective layer 112 are formed on the first side of the chip 21, and the second bonding interface layer 113 and the second protective layer 114 are formed on the second side of the chip 21; or, the first side of the chip 21 is the back side of the device wafer 11, and the second side of the chip 21 is the front side of the device wafer 11, so that the second bonding interface layer 113 and the second protective layer 114 are formed on the first side of the chip 21, and the first bonding interface layer 111 and the first protective layer 112 are formed on the second side of the chip 21.

[0066] According to step S2, referring to Figure 2i , Figure 2j and Figure 3a , a second carrier 22 is provided with a second bonding glue layer 221, the chip 21 is temporarily bonded to the second carrier 22 through the second bonding glue layer 221, the protective layer on the first surface of the chip 21 is in contact with the second bonding glue layer 221, and the gap 23 is between adjacent chips 21. Wherein, Figure 2i is Figure 2j and Figure 3a top view schematic diagram, Figure 3a the previous process steps refer to Figures 2a-2h .

[0067] As shown in Figure 2j , the first surface of the chip 21 is the back surface of the device wafer 11, and the second protective layer 114 is in contact with the second bonding glue layer 221; as shown in Figure 3a , the first surface of the chip 21 is the front surface of the device wafer 11, and the first protective layer 112 and the residual first bonding glue layer 121 are in contact with the second bonding glue layer 221.

[0068] The second carrier 22 can be a light-transmitting substrate to facilitate subsequent debonding process by laser. The material of the light-transmitting substrate can be glass, ceramic, plastic, etc.

[0069] According to step S3, a medium layer is covered on the chip 21, and the medium layer fills the gap 23.

[0070] Referring to Figure 2k and Figure 3b , the step S3 includes: first, forming a third bonding glue layer 241 in the gap 23, the top surface of the third bonding glue layer 241 is lower than the top surface of the chip 21, wherein the third bonding glue layer 241 can be formed by the steps of coating bonding glue, curing bonding glue and removing excess bonding glue, when the depth of the gap 23 is very deep, the speed of filling the gap 23 by coating bonding glue is very fast, which can save cost compared with filling the gap 23 by depositing silicon oxide and other materials; then, covering an oxide layer 242 on the chip 21 and the third bonding glue layer 241, the oxide layer 242 fills the gap 23, in Figure 2k , the oxide layer 242 buries the residual first bonding glue layer 121 inside, and in Figure 3b , the oxide layer 242 buries the second protective layer 114 inside, and the third bonding glue layer 241 and the oxide layer 242 constitute the medium layer.

[0071] Alternatively, the oxide layer 242 can also be replaced by other materials, such as silicon nitride, silicon oxynitride, etc.

[0072] Before forming the third bonding adhesive layer 241 in the gap 23, another oxide layer (not shown) can be formed on the sidewall and bottom wall of the gap 23. Since the bonding adhesive is fluid when the third bonding adhesive layer 241 is coated, the other oxide layer can fix the chip 21 in order to prevent the flowing bonding adhesive from knocking over or displacing the chip 21. The other oxide layer can also serve as a buffer layer between the second bonding adhesive layer 221 and the third bonding adhesive layer 241.

[0073] Following step S4, the side of the chip 21 away from the second carrier 22 is planarized until the bonding interface layer on the second surface of the chip 21 is exposed. Planarization is performed using a chemical mechanical polishing process.

[0074] like Figure 2l As shown, the side of the chip 21 away from the second carrier 22 is planarized, which is the side where the second surface of the chip 21 (i.e., the front surface of the device wafer 11) is located, in order to remove the residual first bonding adhesive layer 121 and the first protective layer 112, and expose the first bonding interface layer 111; or, as Figure 3c As shown, the side of the chip 21 away from the second carrier 22 is planarized, which is the side where the second surface of the chip 21 (i.e. the back side of the device wafer 11) is located, in order to remove the second protective layer 114 and expose the second bonding interface layer 113.

[0075] After step S4 and before step S5, a plasma process is performed to activate the bonding interface layer on the second surface of the chip 21, i.e. Figure 2l The first bonding interface layer 111 shown and Figure 3c The second bonding interface layer 113 shown makes the subsequent bonding with the target wafer more robust.

[0076] According to step S5, the chip 21 is bonded to a target wafer 25 through the bonding interface layer on the second surface.

[0077] The chip 21 can be pre-bonded to the target wafer 25 before annealing to enhance the bonding force between the chip 21 and the target wafer 25.

[0078] like Figure 2m As shown, the bonding interface layer on the second surface is the first bonding interface layer 111, and the chip 21 is bonded to the target wafer 25 through the first bonding interface layer 111; as Figure 3dAs shown, the bonding interface layer on the second surface is the second bonding interface layer 113, and the chip 21 is bonded to the target wafer 25 through the second bonding interface layer 113.

[0079] The target wafer 25 can include a device structure, and a bonding interface layer can also be formed on the surface of the target wafer 25 that is bonded to the chip 21.

[0080] According to step S6, a debonding process is performed to remove the second carrier 22, and part of the second bonding adhesive layer 221 remains on the protective layer of the first surface.

[0081] Since the second carrier 22 is a light-transmitting substrate, a laser can be used to irradiate the second carrier 22 and the second bonding adhesive layer 221, so that the second bonding adhesive layer 221 decomposes, the second carrier 22 and the second bonding adhesive layer 221 are separated, and then the second carrier 22 and part of the second bonding adhesive layer 221 are removed.

[0082] After the debonding process is performed, the surface where the remaining second bonding adhesive layer 221 is located can be further cleaned, but neither the debonding process nor the further cleaning can completely remove the second bonding adhesive layer 221.

[0083] As shown in Figure 2n As shown in Figure 3e As shown in

[0084] In addition, when the laser is used to irradiate the second carrier 22, the laser can also penetrate through the second carrier 22 to irradiate the third bonding adhesive layer 241 in the gap 23. If the third bonding adhesive layer 241 also partially decomposes and is partially removed, bonding adhesive can be continuously filled in the gap 23 to fill the gap 23.

[0085] According to step S7, the side of the chip 21 away from the target wafer 25 is planarized to remove the remaining second bonding adhesive layer 221 and the protective layer on the first surface, and to expose the bonding interface layer on the first surface, thereby obtaining a bonding structure. A chemical mechanical polishing process is used for planarization.

[0086] As shown in Figure 2oAs shown, the side of the chip 21 far away from the target wafer 25 is planarized, i.e. the side where the first surface of the chip 21 (i.e. the back surface of the device wafer 11) is located, to remove the residual second bonding glue layer 221 and the second protective layer 114, and expose the second bonding interface layer 113; as shown in Figure 3f As shown, the side of the chip 21 far away from the target wafer 25 is planarized, i.e. the side where the first surface of the chip 21 (i.e. the front surface of the device wafer 11) is located, to remove the residual second bonding glue layer 221, the residual first bonding glue layer 121 and the first protective layer 112, and expose the first bonding interface layer 111.

[0087] After the step S7, a plasma process is performed to activate the bonding interface layer on the first surface of the chip 21, i.e. Figure 2o the second bonding interface layer 113 as shown, and Figure 3f the first bonding interface layer 111 as shown, so that the subsequent bonding with other chips is more firm.

[0088] Then, after the above steps S1 to S7, in the bonding structure, the target wafer 25 is bonded with one layer of the plurality of test qualified chips 21.

[0089] The method for manufacturing the semiconductor device further comprises:

[0090] The steps S1 to S7 are repeatedly performed in cycles, and the bonding structure obtained by the previous execution of the steps S1 to S7 is taken as the target wafer 25 in the subsequent execution of the steps S1 to S7, to realize the bonding between chips and chips, so that in the new bonding structure obtained, the target wafer 25 is bonded with at least two layers of the plurality of test qualified chips 21.

[0091] Taking the bonding of two layers of the plurality of test qualified chips 21 on the target wafer 25 as an example, referring to Figures 2p-2i and Figures 3g-3i The steps include: first, the steps S1 to S7 are performed to obtain the bonding structure, in which the target wafer 25 is bonded with one layer of the plurality of test qualified chips 21, and the bonding structure is taken as the new target wafer in the next execution of the step S5, wherein the surface to be bonded in the bonding structure can be the second bonding interface layer 113 (as shown in Figure 2o ) or the first bonding interface layer 111 (as shown in Figure 3f ); then, as shown in Figure 2p and Figure 3gAs shown, the step S1 to the step S5 are continuously executed, the bonding interface layer on the chip 21 on the newly made second carrier 22 is bonded with the bonding interface layer on the new target wafer (i.e. the bonding structure), wherein the bonding interface layer on the chip 21 on the newly made second carrier 22 can be the first bonding interface layer 111 or the second bonding interface layer 113, then, the second bonding interface layer 113 or the first bonding interface layer 111 in the bonding structure can be bonded with the first bonding interface layer 111 on the chip 21 on the newly made second carrier 22, or, the second bonding interface layer 113 or the first bonding interface layer 111 in the bonding structure can be bonded with the second bonding interface layer 113 on the chip 21 on the newly made second carrier 22; then, as shown in Figure 2q and Figure 3h As shown, the step S6 is continuously executed, the debonding process is executed to remove the second carrier 22, and part of the second bonding adhesive layer 221 remains on the protective layer on the first surface; then, as shown in Figure 2r and Figure 3i The step S7 is continuously executed, the side of the chip 21 away from the bonding structure is planarized to remove the remaining second bonding adhesive layer 221 and the protective layer on the first surface, and the bonding interface layer on the first surface is exposed, thereby obtaining a new bonding structure, and two layers of the plurality of qualified chips 21 are bonded on the target wafer 25 in the new bonding structure.

[0092] In addition, for the qualified chip 21, only the protective layer can be formed on the first surface without forming the bonding interface layer, and the bonding interface layer and the protective layer can be sequentially formed on the second surface, then, the semiconductor device manufacturing method (not shown) can comprise: first, a second carrier is provided, the second bonding adhesive layer is formed, the chip is temporarily bonded with the second carrier through the second bonding adhesive layer, the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and the gap is provided between the adjacent chips; then, the medium layer is covered on the chip, and the gap is filled with the medium layer; then, the side of the chip away from the second carrier is planarized until the bonding interface layer on the second surface of the chip is exposed; then, the chip is bonded with a target wafer through the bonding interface layer on the second surface; then, the debonding process is executed to remove the second carrier, and part of the second bonding adhesive layer remains on the protective layer on the first surface; then, the side of the chip away from the target wafer is planarized to remove the remaining second bonding adhesive layer, and the protective layer on the first surface can be optionally removed, and the first surface of the chip is exposed.

[0093] In addition, after the above steps, the bonding structure can be cut to obtain a chip stack structure having at least one layer of the chip 21.

[0094] In summary, by forming a protective layer on the bonding interface layer of the qualified chip, the chip can avoid contact between the bonding interface layer and the bonding adhesive layer when temporarily bonded with the carrier. Before the chip is mixedly bonded with the target wafer, the residual bonding adhesive layer and the protective layer on the protective layer are removed by a planarization process, so that direct contact between the mixed bonding interface and the bonding adhesive can be prevented, the surface of the bonding interface layer has high cleanliness, and abnormal mixed bonding process between the chip and the target wafer (for example, voids or impurities at the interface after mixed bonding) can be avoided.

[0095] An embodiment of the present application provides a semiconductor device, referring to Figures 4a-4b and Figures 5a-5b The semiconductor device includes a first chip 30, a second chip 31, an oxide layer 32, and a bonding adhesive layer 33. The second chip 31 is bonded on the first chip 30, and the first chip 30 can be bonded with at least one layer of the second chip 31. Figures 4a-4b As shown in the figure, the first chip 30 is bonded with one layer of the second chip 31, Figures 5a-5b As shown in the figure, the first chip 30 is bonded with two layers of the second chip 31.

[0096] The semiconductor device provided by the embodiment is described in detail below with reference to Figures 4a-4b and Figures 5a-5b .

[0097] The first chip 30 and the second chip 31 can have a substrate (not shown) and a device structure (not shown).

[0098] The second chip 31 has two opposite first and second surfaces, and at least the first surface is formed with a bonding interface layer. The second chip 31 is bonded with the first chip 30 through the bonding interface layer on the first surface. The bonding interface layer of the second chip 31 has high cleanliness, which meets the requirements of the bonding process between adjacent layers of chips.

[0099] The front surface of the second chip 31 can be formed with a first bonding interface layer 311, and / or the back surface of the second chip 31 can be formed with a second bonding interface layer 312, the front and back surfaces of the second chip 31 being opposite surfaces, and the front surface side of the second chip 31 being formed with a device structure, and the back surface side of the second chip 31 being a substrate. The first bonding interface layer 311 and the second bonding interface layer 312 each include an insulating medium layer (not shown) and a metal layer (not shown) in the insulating medium layer.

[0100] The first surface is the front surface of the second chip 31, and the second surface is the back surface of the second chip 31, in which case the second chip 31 is bonded to the first chip 30 through the first bonding interface layer 311 (as shown in FIG. 2A); or the first surface is the back surface of the second chip 31, and the second surface is the front surface of the second chip 31, in which case the second chip 31 is bonded to the first chip 30 through the second bonding interface layer 312 (as shown in FIG. 2B). Figure 4a Figure 5a The first surface is the front surface of the second chip 31, and the second surface is the back surface of the second chip 31, in which case the second chip 31 is bonded to the first chip 30 through the first bonding interface layer 311 (as shown in FIG. 2A); or the first surface is the back surface of the second chip 31, and the second surface is the front surface of the second chip 31, in which case the second chip 31 is bonded to the first chip 30 through the second bonding interface layer 312 (as shown in FIG. 2B).

[0101] The oxide layer 32 covers a portion of the height of the sidewall of the second chip 31, as shown in FIGS. 2A and 2B. Figure 4a Figure 5a The bonding glue layer 33 covers another portion of the height of the sidewall of the second chip 31, as shown in FIGS. 2A and 2B. Figure 4a Figure 5a The bonding glue layer 33 covers another portion of the height of the sidewall of the second chip 31 away from the first chip 30.

[0102] In addition, another oxide layer (not shown) can be interposed between the sidewall of the second chip 31 and the oxide layer 32 and the bonding glue layer 33.

[0103] If the first chip 30 is bonded with at least two layers of the second chip 31, the bonding interface layer on the second surface of the second chip 31 close to the first chip 30 is bonded to the bonding interface layer on the first surface or the second surface of the second chip 31 away from the first chip 30.

[0104] The second surface is the back surface of the second chip 31, in which case the second bonding interface layer 312 on the second surface of the second chip 31 close to the first chip 30 is bonded to the first bonding interface layer 311 on the first surface of the second chip 31 away from the first chip 30 (as shown in FIG. 2A). Figure 4b ​​​As shown, the first bonding interface layer 311 on the second surface of the second chip 31 close to the first chip 30 is bonded with the second bonding interface layer 312 on the second surface of the second chip 31 away from the first chip 30 (i.e. the back surface of the second chip 31 close to the first chip 30 is bonded with the front surface of the second chip 31 away from the first chip 30), or, the first bonding interface layer 311 on the second surface of the second chip 31 away from the first chip 30 can be bonded with the first bonding interface layer 311 on the first surface of the second chip 31 away from the first chip 30 (i.e. the front surface of the second chip 31 close to the first chip 30 is bonded with the back surface of the second chip 31 away from the first chip 30). Figure 5b As shown, the first bonding interface layer 311 on the second surface of the second chip 31 close to the first chip 30 is bonded with the second bonding interface layer 312 on the second surface of the second chip 31 away from the first chip 30 (i.e. the back surface of the second chip 31 close to the first chip 30 is bonded with the front surface of the second chip 31 away from the first chip 30), or, the first bonding interface layer 311 on the second surface of the second chip 31 away from the first chip 30 can be bonded with the first bonding interface layer 311 on the first surface of the second chip 31 away from the first chip 30 (i.e. the front surface of the second chip 31 close to the first chip 30 is bonded with the back surface of the second chip 31 away from the first chip 30).

[0105] In addition, the semiconductor device described above can also be manufactured by the method for manufacturing the semiconductor device. Figures 4a-4b and Figures 5a-5b correspond to the partial structure in Figures 2a-3i , specifically, the first chip 30 is obtained after cutting the target wafer 25, the second chip 31 is the chip 21, the oxide layer 32 is the oxide layer 242, the bonding glue layer 33 is the third bonding glue layer 241, the first bonding interface layer 311 is the first bonding interface layer 111, and the second bonding interface layer 312 is the second bonding interface layer 113.

[0106] By using the method for manufacturing the semiconductor device, the surface of the bonding interface layer on the second chip has high cleanliness, which avoids abnormal mixed bonding between the second chip and the first chip (for example, there are gaps or impurities at the interface after mixed bonding), thereby avoiding reducing the reliability of the semiconductor device.

[0107] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application. Any modification or modification made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: S1, forming a plurality of qualified chips, each chip has two opposite first and second surfaces, and a bonding interface layer and a protective layer are sequentially formed on each of the two surfaces; S2, providing a second carrier wafer, forming a second bonding adhesive layer, temporarily bonding the chip to the second carrier wafer through the second bonding adhesive layer, the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and the gap between adjacent chips is provided; S3, covering a medium layer on the chip, and the medium layer fills the gap; S4, planarizing the side of the chip away from the second carrier wafer until the bonding interface layer on the second surface of the chip is exposed; S5, bonding the chip to a target wafer through the bonding interface layer on the second surface; S6, performing a debonding process to remove the second carrier wafer, and part of the second bonding adhesive layer remains on the protective layer of the first surface; And, S7, planarizing the side of the chip away from the target wafer to remove the remaining second bonding adhesive layer and the protective layer on the first surface, and exposing the bonding interface layer on the first surface to obtain a bonding structure.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein The step S1 comprises: providing a device wafer; sequentially forming a first bonding interface layer and a first protective layer on the front surface of the device wafer; providing a first carrier wafer, forming a first bonding adhesive layer, temporarily bonding the device wafer to the first carrier wafer through the first bonding adhesive layer, and the first protective layer is in contact with the first bonding adhesive layer; sequentially forming a second bonding interface layer and a second protective layer on the back surface of the device wafer, the front surface and the back surface being opposite surfaces; performing a debonding process to remove the first carrier wafer; and performing a cutting process on the device wafer to obtain qualified chips, and part of the first bonding adhesive layer remains on the first protective layer of the chip.

3. The method of manufacturing a semiconductor device according to Claim 2, wherein After temporarily bonding the device wafer to the first carrier wafer through the first bonding adhesive layer and before forming the second bonding interface layer on the back surface of the device wafer, the method for manufacturing the semiconductor device further comprises: thinning the back surface of the device wafer; and forming a conductive via structure on the back surface of the device wafer.

4. The method of manufacturing a semiconductor device according to Claim 2, wherein After forming the second bonding interface layer on the back surface of the device wafer and before forming the second protective layer on the back surface of the device wafer, the method for manufacturing the semiconductor device further comprises: testing the chips on the device wafer and marking the qualified chips.

5. The method of manufacturing a semiconductor device according to Claim 2, wherein The first surface of the chip is the front surface of the device wafer, and the second surface of the chip is the back surface of the device wafer; in the step S4, the side of the chip away from the second carrier wafer is planarized to remove the second protective layer; Or, the first surface of the chip is the back surface of the device wafer, and the second surface of the chip is the front surface of the device wafer; in the step S4, the side of the chip away from the second carrier wafer is planarized to remove the remaining first bonding adhesive layer and the first protective layer.

6. The method of manufacturing a semiconductor device according to Claim 1, wherein The step S3 comprises: forming a third bonding glue layer in the gap, a top surface of the third bonding glue layer being lower than a top surface of the chip; and covering an oxidation layer on the chip and the third bonding glue layer, the third bonding glue layer and the oxidation layer constituting the dielectric layer.

7. The method of manufacturing a semiconductor device according to Claim 1, wherein After the step S4 and before the step S5 and / or after the step S7, a plasma process is performed to activate the bonding interface layer on the second face of the chip and the bonding interface layer on the first face of the chip.

8. The method of manufacturing a semiconductor device according to Claim 1, wherein The second carrier is a light-transmitting substrate; the step S6 comprises: irradiating the second carrier and the second bonding glue layer with a laser to decompose the second bonding glue layer, thereby removing the second carrier and part of the second bonding glue layer.

9. The method of manufacturing a semiconductor device according to any one of Claims 1 to 8, wherein The method for manufacturing the semiconductor device further comprises: The steps S1 to S7 are repeatedly performed in cycles, and a bonding structure obtained by performing the steps S1 to S7 in a previous cycle is taken as a target wafer in a current cycle.

10. A semiconductor device, characterized by comprising: The semiconductor device is obtained after cutting, and the semiconductor device comprises: a first chip; a second chip having two opposite first and second faces, at least the first face of the second chip being provided with a bonding interface layer, the second chip being bonded to the first chip through the bonding interface layer on the first face; an oxidation layer covering a part of the sidewall of the second chip; and a bonding glue layer covering another part of the sidewall of the second chip.

11. The semiconductor device of claim 10, wherein the first and second semiconductor layers are formed of a same material. The first chip is bonded to at least two layers of the second chip, the bonding interface layer on the second face of the second chip close to the first chip being bonded to the bonding interface layer on the first or second face of the second chip away from the first chip.

12. The semiconductor device according to claim 10 or 11, wherein The first face is a front face of the second chip, and the second face is a back face of the chip; or, the first face is a back face of the second chip, and the second face is a front face of the chip.

13. The semiconductor device of claim 10, wherein, The oxidation layer covers a part of the sidewall of the second chip close to the first chip, and the bonding glue layer covers another part of the sidewall of the second chip away from the first chip. The oxidation layer covers a part of the sidewall of the second chip close to the first chip, and the bonding glue layer covers another part of the sidewall of the second chip away from the first chip.

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