Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

Embodiments of the present disclosure relate to methods of manufacturing semiconductor devices and corresponding semiconductor devices. A semiconductor die is mounted at a first surface of a leadframe, and an insulating encapsulation is formed over the leadframe. An etch mask is applied at a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts and connecting bars electrically coupling the electrical contacts between the two adjacent rows. The second surface is then etched through the etch mask to remove leadframe material at the second surface and define the electrical contacts and the connecting bars. The electrical contacts include distal surfaces and sides that are left uncovered by the insulating encapsulation. The etch mask is then removed, and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surfaces and the sides of the electrical contacts. The connecting bars are then removed between the two adjacent rows during device singulation.

Description

[0001] Priority requirements

[0002] This patent application claims priority to Italian application No. 102020000031541, filed on December 18, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This description relates to semiconductor devices.

[0004] One or more embodiments can be applied to semiconductor devices such as, for example, integrated circuits (ICs). Background Technology

[0005] The Quad Flat No-Lead (QFN) package, which has peripheral pads on the bottom of the package to provide electrical connections to a substrate such as a printed circuit board (PCB), is an example of a semiconductor device that may include contacts pre-plated only on its bottom side (e.g., referred to in the art as a pre-plated frame (PPF)).

[0006] Metal oxides (such as copper) on the sides of the contacts hinder solderability. Furthermore, PPF contact metallization is adversely affected by prolonged exposure to the atmosphere (leading to nickel migration and discoloration), which negatively impacts bonding performance.

[0007] It should be noted that the reliability of a solder joint is directly proportional to its cross-section, which in turn is directly proportional to the weldable area.

[0008] Increasing the contact width affects the contact pitch (fewer available I / O pins), increases the solder joint cross-section, i.e., the solderable area, which may increase migration risk and also cause creepage distance issues.

[0009] It should also be noted that conventional chemical plating of contacts (e.g., via chemical tin plating) can achieve a tin thickness of 1.5-2.0 μm, which is much smaller than the nearly 10 μm required in industries such as the automotive industry. Summary of the Invention

[0010] There is a need in this field to provide improved solutions that overcome the shortcomings of the aforementioned existing technical solutions.

[0011] According to one or more embodiments, such an objective can be achieved via a method having the features set forth in the claims below.

[0012] One or more embodiments can be used to design corresponding semiconductor devices.

[0013] The claims are an integral part of the technology disclosed herein in conjunction with the embodiments.

[0014] One or more embodiments provide a process for forming wettable sides (e.g., in a multi-row QFN) in which leadframe etching is performed via a mask and contact bars are formed to electrically connect leads in the leadframe; this facilitates the removal (sacrificing) of the contact bars by sawing before individual chip cutting to fully tin-plat the leads.

[0015] One or more embodiments can simplify leadframe design and manufacturing processes, eliminate bottom-side pre-plating, and thus reduce leadframe costs.

[0016] In one or more embodiments, masking process steps can be associated with standard etching processes to fabricate contact pads.

[0017] One or more embodiments facilitate, for example, electroplating contact pads (including sides) using a tin layer with a thickness greater than 5 micrometers via an electroplating process.

[0018] In one or more embodiments, the sacrificial tie rod can be removed during the final single-bead cutting by a (second) sawing step. For example, a (first) saw blade can perform the single-bead cutting, and another saw blade can be used for tie rod removal. These two sawing steps can be performed at least partially simultaneously. Attached Figure Description

[0019] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0020] Figure 1A It is a flowchart illustrating the conventional process flow for manufacturing semiconductor equipment;

[0021] Figure 1B It is a flowchart illustrating the process flow in manufacturing a semiconductor device including embodiments according to the present description;

[0022] Figures 2 to 4 These are illustrations of contact electroplating and welding embodiments according to the present description. Figure 4 It is along Figure 3 The cross-sectional view obtained from line IV-IV; and

[0023] Figure 5 , Figure 6 and Figure 7 The illustrations depict various steps in the process according to embodiments of this description.

[0024] It should be understood that, for clarity and ease of understanding, the various figures may not be drawn at the same scale. Detailed Implementation

[0025] In the following description, various specific details are illustrated to provide a thorough understanding of various examples of the embodiments according to the description. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so as not to obscure various aspects of the embodiments.

[0026] Within the framework of this description, references to "embodiment" or "an embodiment" are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., that may appear at various points in this description do not necessarily refer precisely to the same embodiment. Furthermore, specific conformations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0027] The headings / references used herein are for convenience only and therefore do not limit the extent of protection or the scope of the embodiments.

[0028] Furthermore, throughout the accompanying drawings, the same parts or elements are denoted by the same reference numerals, and for the sake of brevity, the descriptions corresponding to each drawing will not be repeated.

[0029] Standards across various industries (such as the automotive industry) are increasingly shifting towards semiconductor device packaging, such as pre-tinned contacts in Quad Flat No-Lead Multi-Row (QFN-MR) packages.

[0030] As mentioned above, in conventional semiconductor device packaging, the metal oxide (e.g., copper) pre-plated only on the bottom side of the contacts hinders solderability. In fact, the solder joint cross-section and solder pitch are based on the solderable area (e.g., proportional to the solderable area). Solder joint reliability depends on the solder joint cross-section, solder pitch, and stress distribution (primarily tangential).

[0031] Due to environmental storage conditions, pre-plated frames (“PPF”) that are plated only on the bottom side may have undesirable discoloration issues (copper oxidation and migration on the nickel and gold layers).

[0032] Methods to improve solder joint reliability (e.g., in QFN mr packages) may involve increasing the contact area.

[0033] At least in principle, such growth can be achieved in different ways.

[0034] For example, the contact width and pitch between contacts can be increased: as a result, the number of I / O contacts for the same package size is reduced.

[0035] Alternatively, the contact width can be increased without changing the pitch: as a result, the spacing between contacts decreases, which carries the risk of migration.

[0036] Another approach may involve increasing the contact length: this would affect the creepage distance between the contact and the central exposed pad, or the size of the die pad.

[0037] One or more embodiments can address the problems discussed above via process steps that can be easily integrated into conventional processes for manufacturing semiconductor devices, such as QFN-MR packages.

[0038] Figure 1 illustrates this conventional process in its functional flowchart.

[0039] exist Figure 1A In the process shown, in step 1001, the lead frame represented by box 1000 has been applied (connected) to one or more semiconductor chips or dies represented by box 2000.

[0040] The currently used term lead frame (or lead frame) (see, for example, the USPC Uniform Terminology) refers to a metal frame that provides support for a semiconductor chip or die, and electrical leads that couple the semiconductor chip or die to other electrical components or contacts.

[0041] Essentially, a leadframe comprises an array of conductive structures (leads) extending inward from a peripheral location along the direction of the semiconductor chip or die, thereby forming a conductive structure array from die pads on which at least one semiconductor chip or die is attached. This can be die attachment via an adhesive (e.g., die attachment film or DAF).

[0042] Electrical coupling between the leads in the lead frame and the semiconductor chip or die can be achieved via wires that form a wire bonding pattern around the chip or die.

[0043] like Figure 1A This indicates that such a chip or die 2000 can be obtained from semiconductor wafer 2000A via “mounting” and dicing steps (as indicated by frames 2000B and 2000C).

[0044] As indicated by box 1001, after attaching the lead core to the lead frame, as... Figure 1A The processes exemplified may include:

[0045] Plasma cleaning (box 1002)

[0046] Wire bonding (box 1003)

[0047] Plasma cleaning (frame 1004)

[0048] Encapsulation of a molding compound (e.g., epoxy resin) is molded onto a lead frame and one or more semiconductor chips attached thereto (box 1005).

[0049] Rear etching (frame 1006)

[0050] Water spray cleaning (frame 1007)

[0051] Laser marking (box 1008), and

[0052] Cut individual pieces to provide a single device (box 1009).

[0053] This process is conventional in the art and therefore does not require a more detailed description herein; however, those skilled in the art will recognize that similar conventional processes, such as... Figure 1A Some of the steps illustrated may be omitted or replaced by other steps, or additional steps may be added. Furthermore, one or more steps in the process may differ from... Figure 1A The examples in the middle are executed sequentially.

[0054] One or more embodiments may be conceived Figure 1A process along Figure 1B The changes in the lines. These changes include:

[0055] The masking step, indicated by box 3000, between the molding step of box 1005 and the rear etching of box 1006;

[0056] The mask removal step indicated by box 3001, and the electroplating step between the water spray cleaning in box 1007 and the laser marking in box 1008, also indicated by box 3001; and

[0057] The single-piece cutting process of frame 1009 includes the tie rod sawing action, such as by... Figure 1B The sub-frame 1009A in the text represents this.

[0058] Also note that, through Figure 1A and Figure 1B The comparative illustrations based on the embodiments in this specification are for simplicity and ease of explanation only.

[0059] result, Figure 1B Some of the steps illustrated in the figure are used Figure 1A The fact that the same reference numerals appear in the figures (and therefore, for the sake of brevity, the corresponding descriptions will not be repeated) does not mean that... Figure 1B Some steps illustrated in the diagram must be in accordance with... Figure 1A The steps corresponding to those shown in the diagram are executed in the same manner as 1A.

[0060] In addition, with Figure 1A The process illustrated is the same. Figure 1B Some steps in the illustrated process may be omitted or replaced by other steps, and additional steps may be added. Furthermore, one or more steps in the process may differ from... Figure 1B The examples in the middle are executed sequentially.

[0061] Figure 2 and Figure 3 This is an illustration of a semiconductor device 10 (e.g., a QFN-MR package), including leads 12 such as contacts in a lead frame, which are plated (e.g., tin-plated) on both the bottom (far end) surface and the sides, as shown at 12A.

[0062] For simplicity and ease of understanding, Figure 2 and Figure 3 Only a portion of the bottom or rear surface of device 10 is shown in the illustration.

[0063] Figure 2 and Figure 3 A pair of leads 12 are illustrated, protruding from an encapsulation 14 of an electrically insulating material (e.g., epoxy resin), which is molded or pre-molded onto a lead frame including the leads 12. Other possible features of the device 10 (such as wire bonding) are not shown for simplicity.

[0064] Figure 3 The illustration shows the steps of mounting device 10 onto a support substrate B (e.g., a printed circuit board or PCB), which can occur via solder mass block S.

[0065] The solder quality block S may include a material (such as tin) capable of “wetting” the lead 12 on the entire surface exposed by the molding compound 14, both on the bottom (far end) surface and the sides of the lead 12.

[0066] like Figure 3 As illustrated by the dashed line, lead 12 can also be wetted on its side by solder mass block S, resulting in an increase in the cross-section of the solder joint, which couples lead 12 (mechanically and electrically) to the support substrate B via solder mass block S.

[0067] This is due to Figure 4 Example of a cross-sectional view. This cross-sectional view, taken at an ideal plane IV-IV extending to the bottom (distal) surface of one of the leads 12, shows that, as a result of the surface tension effect associated with “wetting” the other (plated) side, the solder mass block S is coupled to the lead 12 in region 12S, which is significantly larger than the area of ​​the bottom (distal) surface of the lead 12.

[0068] As a result, the resulting solder mass block S will be significantly greater than the solder mass produced when lead 12 is plated only on its bottom side.

[0069] These larger solder mass blocks are better able to resist tensile / tangential stresses.

[0070] Figure 5 Examples of masking steps, such as Figure 1B Example at position 3000.

[0071] As illustrated, on the bottom or rear surface of device 10 (on Figure 5 and 6 Apply mask 300 to the surface opposite the top or front surface (on the middle surface). Figure 5 and 6 (face down), one or more of the semiconductor chips 2000 in Figure 1A and 1B The die is attached in step 1001, by the Figure 1A and 1B In molding step 1005, the molding compound is encapsulated thereon.

[0072] exist Figure 5 and Figure 6 In the image, the outline of this chip 2000 (attached to die pads 120 in the lead frame, including contacts or leads 120) is indicated by dashed lines.

[0073] As a result of 3000 masking steps, the rear etching in example 1006 will only affect those portions of the bottom or rear surface that are left exposed by (e.g., water-cleanable) mask 300.

[0074] In addition to the area where lead 12 is located, mask 300 also covers area 300A corresponding to the connecting rod, which is intended to electrically connect (basically as a busbar) lead 12 (and, if possible, exposed pads / baffles in the lead frame).

[0075] Masks such as 300 can be applied in ways known to those skilled in the art, for example via jet printing or grid printing.

[0076] In this embodiment, water-cleaning welding mask materials can be advantageously used, and Techspray at 8125 Cobb Center Drive, Kennesaw, GA 30152-USA has... (Inkjet printing) and (Grid printing) as a mask material, such as available materials.

[0077] like Figure 1B As exemplified at 1006, the rear etching applied to the bottom or rear surface of the device 10 using the mask 300 in step 3000 will cause the etching medium to remove metal (e.g., copper) from the bottom or rear surface of the device 10, except for the contacts (leads) 12 and the connecting rods 120, which remain in the area 300A protected by the mask 300.

[0078] like Figure 1B After etching as shown in example 1006, as Figure 1B The high-pressure (e.g., 250 bar) water spray cleaning example in section 1007 will also cause mask 300 to be removed. For clarity, this is in... Figure 1B The example is a different block 3001, even though it will involve a single cleaning step.

[0079] Figure 5 and Figure 6 (and Figure 7 The image shows at least one semiconductor chip or die 2000 disposed on a region or portion of a (first) surface of a lead frame having an insulating encapsulation 14 formed thereon, and at least one semiconductor chip or die 2000 disposed thereon, with two rows of leads 12 attached in the area surrounding the one or more semiconductor chips 2000.

[0080] Figure 5 and Figure 6 (and Figure 7 It also shows that the connecting rod 120 at region 300A extends between and connects to the two rows of leads 12 in the same lead frame portion, that is, the two rows of leads 12 in the same multi-row (two-row) array of leads 12 around the region where one or more semiconductor chips 2000 are connected.

[0081] This contrasts with arrangements where such rods are provided only as connectors between adjacent lead frame sections.

[0082] As a result, the plating step exemplified at 3002 (e.g., tin plating) will... Figure 7 The example structure is implemented such that the contact (lead) 12 is electrically connected via the rod 120.

[0083] Therefore, a plating layer will be electrodeposited on contact 12 (in a manner known to those skilled in the art, such as by ED). Figure 6 (as shown in the example).

[0084] This deposition will be included on the sides of the contact 12 in both rows (i.e., the inner row and the outer row), such as Figure 2 As exemplified at location 12A, bar 120 facilitates all contacts (leads, such as 12 and exposed pads / baffles in the lead frame) to act as anodes in the electrodeposition process.

[0085] For example, electroplating can help plate contacts, such as 12, on the entire exposed surface (the far bottom surface plus the sides), where the plating thickness is close to 10 μm, as required in the automotive industry.

[0086] The tie rod 120 can be removed (sacrificed) by sawing (possibly in combination with separation).

[0087] like Figure 1B The examples at locations 1009 and 1009A may involve two steps performed using two saw blades.

[0088] like Figure 7 The example shown illustrates the first cutting action using a first saw blade S1 (e.g., 200 micrometers wide). Figure 1B 1009A (of which), is specifically designed to remove the connecting rod 120 in order to restore the insulation of the contact 12 as needed.

[0089] The second cutting action using a second saw blade (e.g., 350 micrometers wide) Figure 1B The 1009 in the formula can be used to cut single pieces.

[0090] It is important to note that this distinction does not imply that these cutting actions should be performed in sequence.

[0091] For example, one or more embodiments may advantageously involve:

[0092] The first cutting step involves using a first saw blade (e.g., 200 micrometers wide) to remove half of the tie rod (east / south side of the module); and

[0093] In the second cutting step, the other half of the tie rod (west / north side of the module) is still removed using the first saw blade, and the second saw blade performs single-piece cutting of a single device.

[0094] For example, such as Figures 5 to 7 As shown, the connecting rod 120 at region 300A extends between and connects to the two rows of leads 12 in the same lead frame portion, namely the two rows of leads 12 in the same multi-row (multi-row) array of leads 12 around the region where one or more semiconductor chips 2000 are attached.

[0095] Therefore, even after removing the sacrificial rod 120, via the cross-sectional weld point ( Figure 3 The presence of a wettable / solderable (e.g., tin) plating on the sides of two rows of leads (both in the model) or contacts (such as 12) can also be easily detected. Similarly, this will allow for the measurement of the plating thickness on the sides (e.g., tin) and the grain size indicating the nature of the plating process.

[0096] In short, methods such as those exemplified in this article can include:

[0097] At least one semiconductor chip or die (e.g., 2000) is disposed (e.g., 1001) on a first surface of a lead frame (e.g., 1000), wherein the lead frame has a second surface opposite to the first surface;

[0098] An insulating encapsulation (e.g., 14) is formed or provided (e.g., 1005) on a lead frame having at least one semiconductor chip or die disposed on a first surface of the lead frame;

[0099] An etching (e.g., 1006) is applied to the second surface of the lead frame to provide an electrical contact (e.g., 12) for at least one semiconductor chip or die, wherein the electrical contact has a distal surface and an uncovered side left by an insulating encapsulation, wherein the etching at the second surface of the lead frame is performed via an etching mask (e.g., 300) covering the electrical contact and at least one (sacrificial) connecting rod (e.g., 120) electrically coupling a plurality of the electrical contacts;

[0100] Remove (e.g., 3001) the etch mask, where electrical contacts and at least one connecting rod are exposed;

[0101] The distal surface and sides of the electrical contact are electroplated (e.g., 3002) using an electrical contact and at least one connecting rod as electroplating electrodes (e.g., as the anode ED in an electroplating process); and

[0102] Remove (e.g., 1009, 1009A) at least one connecting rod.

[0103] Methods exemplified in this article may include removing (e.g., 1009A) at least one connecting rod while applying a single-cut (e.g., 1009) cut to the lead frame to separate multiple semiconductor chips or dies disposed thereon from each other.

[0104] The methods exemplified in this article may include applying the etched mask via jet printing or mesh printing.

[0105] In methods such as those exemplified herein, removing the etch mask may include water cleaning of the etch mask.

[0106] In the method exemplified herein, the electroplating may include tin plating on the distal surface and the sides of the electrical contact.

[0107] In the method exemplified herein, the electroplating may include electroplating the distal surface and sides of the electrical contacts using an electroplating layer having a thickness of about 9.1 to 9.8 micrometers.

[0108] As used in this article, the term “approximately” refers to technical features produced within the technical tolerances of the manufacturing method.

[0109] Methods exemplified herein may include mounting a leadframe to a substrate (e.g., a printed circuit board, such as B), wherein an insulating encapsulation is formed on the leadframe, and at least one semiconductor chip or die is disposed thereon, wherein the mounting is performed by wetting (both) the distal surfaces of the electroplated leads and the sides of the electrical contacts via a solder mass block (e.g., S).

[0110] Semiconductor devices (e.g., 10) as exemplified in this document may include:

[0111] At least one semiconductor chip or die (e.g., 2000) is disposed on a first surface of a lead frame (e.g., 1000), wherein the lead frame has a second surface opposite to the first surface;

[0112] An insulating encapsulation (e.g., 14) is formed (provided) onto a lead frame, on which at least one semiconductor chip or die is disposed at a first surface of the lead frame; and

[0113] Electrical contacts (e.g., 12) for etching (e.g., at 1006) at a second surface of a lead frame at least one semiconductor chip or die, wherein the electrical contacts have a distal surface and an uncovered side surface left by an insulating encapsulation, wherein the distal surface and the side surface have a plating (e.g., 12A) plated thereon (e.g., at 3002).

[0114] In devices such as those exemplified herein, the plating may include tin plating on the distal surface and the sides of the electrical contacts (both).

[0115] In devices such as those exemplified in this article, the coating may include an electroplated layer having a thickness of about 9.1 to 9.8 micrometers.

[0116] Here, as used in this article, the term “approximately” means a technical feature produced within the technical tolerance range of the method used to manufacture the technical feature.

[0117] Without affecting the basic principles, the details and embodiments may vary, even significantly, only without departing from the scope of the embodiments as described by example.

[0118] The extent of protection is determined by the appended claims.

Claims

1. A method comprising: A semiconductor chip or die is disposed on a first surface of a lead frame, wherein the lead frame has a second surface opposite to the first surface; An insulating encapsulation is formed on the lead frame and the semiconductor chip or die disposed thereon; An etching mask is applied to cover the second surface of the lead frame at a location including multiple electrical contacts and at least one connecting rod electrically coupled to the multiple electrical contacts; The second surface of the lead frame is etched using the etching mask to define the electrical contact and the at least one connecting rod, wherein the electrical contact has a distal surface and a side surface that are not covered by the insulating encapsulation. Remove the etch mask to expose the plurality of electrical contacts and the at least one connecting rod; While using the electrical contact and the at least one connecting rod as electroplating electrodes, the distal surface and the side surface of the electrical contact are electroplated; as well as Remove at least one connecting rod to electrically isolate the electrical contacts.

2. The method of claim 1, wherein at least one connecting rod is removed while applying a single-chip cut to the lead frame, so as to separate the plurality of semiconductor chips or dies disposed on the lead frame from each other.

3. The method of claim 1, wherein the etch mask is applied using either jet printing or mesh printing.

4. The method of claim 1, wherein removing the etched mask comprises cleaning with water to remove the etched mask.

5. The method of claim 1, wherein electroplating includes tin-plating the distal surface and the side surface of the electrical contact using a plating layer.

6. The method of claim 5, wherein the coating has a thickness of 9.1 micrometers to 9.8 micrometers.

7. The method of claim 1, further comprising mounting the lead frame having the insulating encapsulation onto the substrate by wetting the electroplated distal surface of the electrical contacts and the solder mass block on the side surface.

8. The method of claim 1, wherein the plurality of electrical contacts are arranged in two adjacent rows, and wherein at least one connecting rod is positioned between the two adjacent rows and configured to electrically couple the electrical contacts of the two adjacent rows to each other.

9. The method of claim 8, wherein removing the at least one connecting rod electrically disconnects the electrical contacts of the two adjacent rows from each other.

10. A semiconductor device, comprising: At least one semiconductor chip or die is disposed on a first surface of a lead frame, wherein the lead frame has a second surface opposite to the first surface; A semiconductor chip or die is disposed on the first surface of the lead frame; An insulating encapsulation is formed on the lead frame; Electrical contacts for at least one semiconductor chip or die at the second surface of the lead frame, wherein the electrical contacts have a distal surface and sides uncovered by the insulating encapsulation. as well as A coating is electroplated on the distal surface and the side surface, wherein the coating has a thickness of 9.1 micrometers to 9.8 micrometers.

11. The semiconductor device of claim 10, wherein the plating comprises tin plated on the distal surface and the side surface of the electrical contact.

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