display module

Abstract

A display module includes a display panel in which a plurality of pixels each including a plurality of sub-pixels are disposed on a plurality of row lines, and a driver. The driver is configured to set PWM data voltages to the plurality of sub-pixels included in the plurality of row lines in a row line order, to apply a sweep signal to the sub-pixels included in at least some consecutive row lines among the plurality of row lines in the row line order, the sweep signal being a voltage signal swept between two different voltages, and to drive the display panel such that the sub-pixels included in the at least some consecutive row lines emit light in the row line order based on the PWM data voltages.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display module. More particularly, the disclosure relates to a display module in which a self-emissive device forms a sub-pixel. BACKGROUND

[0002] In a related art display panel in which inorganic light emitting elements such as a red light emitting diode (LED), a green LED, and a blue LED (hereinafter, LED refers to an inorganic light emitting element) are driven by a sub-pixel, the gray scale of the sub-pixel is represented by a pulse amplitude modulation (PAM) driving method.

[0003] In this case, depending on the amplitude of the driving current, the wavelength and the gray scale of the emitted light can vary, resulting in a decrease in color reproducibility of an image. FIG. 1A 、 FIG. 1B and FIG. 1C It is shown that the wavelength varies depending on the amplitude of the driving current flowing through a blue LED, a green LED, and a red LED. SUMMARY

[0004] TECHNICAL PROBLEM

[0005] An object of the disclosure is to provide a display module and a driving method thereof, which provide improved color reproducibility for an input image signal.

[0006] Another object of the disclosure is to provide a display module and a driving method thereof, which include a sub-pixel circuit and a driving circuit capable of efficiently and stably driving an inorganic light emitting element constituting a sub-pixel.

[0007] SOLUTION TO PROBLEM

[0008] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the description, or can be learned by practice of the embodiments presented throughout the disclosure.

[0009] An embodiment of the disclosure provides a display module including a display panel in which a plurality of pixels each including a plurality of sub-pixels are disposed on a plurality of row lines, and a driver configured to: set a pulse width modulation (PWM) data voltage to the sub-pixels included in the plurality of row lines in a row line order; apply a sweep signal to the sub-pixels included in at least some consecutive row lines among the plurality of row lines in a row line order, the sweep signal being a voltage signal swept between two different voltages; and drive the display panel such that the sub-pixels included in the at least some consecutive row lines emit light in a row line order based on the set PWM data voltage.

[0010] The driver can be further configured to: apply the plurality of first control signals to the sub-pixels included in the one of the plurality of row lines and set a PWM data voltage to the sub-pixels included in the one of the plurality of row lines during a data setting period of the one of the plurality of row lines; apply the plurality of second control signals and the sweep signal to the sub-pixels included in the one of the plurality of row lines during a light emission period of the one of the plurality of row lines; and drive the display panel such that the sub-pixels included in the one of the plurality of row lines emit light during a time corresponding to the PWM data voltage.

[0011] The driver can be further configured to: apply the plurality of second control signals and the sweep signal to the sub-pixels included in the one of the plurality of row lines in each of a plurality of light emission periods of the one of the plurality of row lines, a first light emission period of the plurality of light emission periods can be consecutive in time with the data setting period, and each of the plurality of light emission periods can include a pre-emptive time interval.

[0012] The driver can be further configured to: apply a plurality of consecutive sweep signals to the sub-pixels included in the one of the plurality of row lines in one light emission period of the one of the plurality of row lines, and the data setting period can be consecutive in time with the one light emission period.

[0013] The driver can include: a first driver circuit configured to generate at least one of the plurality of first control signals; and a second driver circuit configured to generate the sweep signal and at least one of the plurality of second control signals.

[0014] The second driver circuit can include: a first circuit to generate one of the at least one of the plurality of second control signals; and a second circuit connected to the first circuit and configured to generate the sweep signal based on the one of the at least one of the plurality of second control signals generated in the first circuit.

[0015] The first circuit can include a first output to output the one of the at least one of the plurality of second control signals to the sub-pixels included in the one of the plurality of row lines, the second circuit can include a transistor having a gate terminal connected to the first output, the transistor can be configured to select and output, as an input signal, the sweep signal to be applied to the sub-pixels included in the one of the plurality of row lines based on the one of the at least one of the plurality of second control signals input through the gate terminal, and the input signal can include the sweep signal repeatedly consecutively.

[0016] The first driver circuit and the second driver circuit can be provided for each of the plurality of row lines, each of the second driver circuits can include a corresponding second circuit, and input signals to the corresponding second circuits of the second driver circuits corresponding to two consecutive row lines of the plurality of row lines can be the same signal having phases different from each other.

[0017] Each of the plurality of sub-pixels can include an inorganic light emitting element, and a sub-pixel circuit configured to control a light emitting time of the inorganic light emitting element according to driving of the driver, the sub-pixel circuit can include a constant current generator circuit configured to supply a constant current to the inorganic light emitting element during a light emitting period, and a PWM circuit for controlling an amount of time for which the constant current flows in the inorganic light emitting element based on PWM data and a sweep signal.

[0018] The constant current generator circuit can include a first driving transistor, and can be further configured to supply the constant current to the inorganic light emitting element while the first driving transistor is turned on in the light emitting period, and the PWM circuit can include a second driving transistor, and can be further configured to set a PWM data voltage to a gate terminal of the second driving transistor according to a plurality of first control signals, and turn off the first driving transistor based on the second driving transistor being turned on due to a change in voltage of the gate terminal of the second driving transistor due to the sweep signal.

[0019] Advantages of the Invention

[0020] According to various embodiments, it is possible to prevent a wavelength of light emitted by the inorganic light emitting element from varying according to a gray scale.

[0021] It is possible to easily correct a stain or a color that can occur on an image displayed on the display panel due to a deviation between the sub-pixel circuits. Even when a large size display panel is formed by combining display panels in a module form, it is possible to correct a difference in brightness or color between each display panel module.

[0022] It is possible to design a more optimized driving circuit, and to stably and efficiently drive the inorganic light emitting element. In particular, it is possible to reduce power consumption in the display panel. Also, it is possible to miniaturize and lighten the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] FIG. 1A 、 FIG. 1B and FIG. 1C is a graph showing a change in wavelength according to a size of a driving current flowing through a blue light emitting diode (LED), a green LED, and a red LED;

[0025] FIG. 2 shows a pixel structure of a display module according to an embodiment;

[0026] FIG. 3Ais a conceptual diagram illustrating a driving method of a related art display panel;

[0027] FIG. 3B is a conceptual diagram illustrating a driving method of a display panel according to an embodiment;

[0028] FIG. 3C is a conceptual diagram illustrating a driving method of a display panel according to an embodiment;

[0029] FIG. 3D is a conceptual diagram illustrating a driving method of a display panel according to an embodiment;

[0030] FIG. 4 is a block diagram of a display module according to an embodiment;

[0031] FIG. 5 is a detailed block diagram of a display module 300 according to an embodiment;

[0032] FIG. 6A is a driving method of a display panel for a plurality of image frames according to an embodiment;

[0033] FIG. 6B is more detailed FIG. 6A the second frame shown;

[0034] FIG. 6C is a configuration diagram of a sub-pixel circuit according to an embodiment;

[0035] FIG. 6D is a detailed circuit diagram of a sub-pixel circuit according to an embodiment;

[0036] FIG. 6E is a timing diagram of gate signals described above FIG. 6D in the above

[0037] FIG. 6F is a timing diagram of various signals for driving a display panel during one image frame period according to an embodiment;

[0038] FIG. 7A is a block diagram of a display module according to an embodiment;

[0039] FIG. 7B is a timing diagram of gate signals output from a gate driver when a scan signal and various clock signals are input during a frame time according to an embodiment;

[0040] FIG. 8A is a circuit diagram of a scan driver according to an embodiment;

[0041] FIG. 8B is a connection relationship between scan drivers according to an embodiment;

[0042] FIG. 8C is a timing chart of various signals for driving the scan driver according to an embodiment;

[0043] FIG. 9A is a circuit diagram of the emission driver according to an embodiment;

[0044] FIG. 9B shows a connection relationship between the emission drivers according to an embodiment;

[0045] FIG. 9C is a timing chart of various signals for driving the emission driver according to an embodiment;

[0046] FIG. 10A is a circuit diagram of the scan driver according to an embodiment;

[0047] FIG. 10B shows a connection relationship between the scan drivers according to an embodiment;

[0048] FIG. 10C is a timing chart of various signals for driving the scan driver according to an embodiment;

[0049] FIG. 11A is a circuit diagram of the scan / scan driver according to an embodiment;

[0050] FIG. 11B shows a connection relationship between the scan / scan drivers according to an embodiment;

[0051] FIG. 11C is a timing chart of various signals for driving the scan / scan driver according to an embodiment;

[0052] FIG. 12A is a circuit diagram of the scan / emission driver according to an embodiment;

[0053] FIG. 12B shows a connection relationship between the scan / emission drivers according to an embodiment;

[0054] FIG. 12C is a timing chart of various signals for driving the scan / emission driver according to an embodiment;

[0055] FIG. 13 is a detailed circuit diagram of the sub-pixel circuit according to an embodiment;

[0056] FIG. 14A shows the concept of driving the display panel in the same manner as FIG. 3B during two image frame periods;

[0057] FIG. 14B is for driving FIG. 14A in the same manner as FIG. 13a timing diagram of various control signals of the sub-pixel circuit shown;

[0058] FIG. 15A a concept of driving the display panel in the same manner as FIG. 3C during two image frame periods is illustrated;

[0059] FIG. 15B is a circuit diagram of a gate driver according to an embodiment; FIG. 15A FIG. 13 a timing diagram of various control signals of the sub-pixel circuit shown;

[0060] FIG. 16A is a circuit diagram of a gate driver according to an embodiment;

[0061] FIG. 16B is a timing diagram of an input scan signal and an emission signal;

[0062] FIG. 17A is a cross-sectional view of a display module according to an embodiment;

[0063] FIG. 17B is a cross-sectional view of a display module according to another embodiment of the disclosure;

[0064] FIG. 17C is a plan view of a thin film transistor (TFT) layer according to an embodiment; and

[0065] FIG. 18 is a configuration diagram of a display apparatus according to an embodiment. DETAILED DESCRIPTION

[0066] In describing the present disclosure, detailed descriptions of related technologies will be omitted when it is determined that such descriptions can unnecessarily obscure the gist of the present disclosure. Further, descriptions of the same configurations will be omitted.

[0067] The suffix "part" of the components used in the description of the present disclosure is added or used in consideration of the convenience of the specification, and is not intended to have a different meaning or role from each other.

[0068] The terms used in the present disclosure are used to describe the embodiments, and are not intended to restrict and / or limit the present disclosure. Unless the context clearly indicates otherwise, the singular expression includes the plural expression.

[0069] In the present disclosure, the term "have", "may have", "include", or "may include" indicates the presence of a corresponding feature (e.g., numerical value, function, operation, or constituent element such as a component), but does not exclude the presence of additional features.

[0070] ​In the disclosure, the terms "first", "second", and the like can be used to describe various elements, regardless of their order and / or importance, and to distinguish one element from other elements, without being limited to the corresponding elements.

[0071] If it is described that one element (for example, a first element) is "operatively or communicatively coupled to" or "connected to" another element (for example, a second element), it can be understood that the one element can be directly connected to the other element, or the one element is connected to the other element through still another element (for example, a third element).

[0072] When it is mentioned that one element (for example, a first element) is "directly coupled to" or "directly connected to" another element (for example, a second element), it can be understood that there is no element (for example, a third element) between the one element and the other element.

[0073] Unless otherwise defined, the terms used in the embodiments of the disclosure can be interpreted in the meanings well known to one of ordinary skill in the art.

[0074] Various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0075] FIG. 2 A pixel structure of a display module according to an embodiment is illustrated.

[0076] Reference FIG. 2 The display panel 100 includes a plurality of pixels 10 disposed or arranged in a matrix form. The matrix form can include a plurality of row lines or a plurality of column lines.

[0077] The row line can also be referred to as a horizontal line, a scan line, or a gate line, and the column line can also be referred to as a vertical line or a data line.

[0078] Each pixel 10 included in the display panel 100 can include three types of sub-pixels including an R (red) sub-pixel 20-1, a G (green) sub-pixel 20-2, and a B (blue) sub-pixel 20-3.

[0079] Each sub-pixel 20-1 to 20-3 can include an inorganic light emitting element corresponding to the type of the sub-pixel, and a sub-pixel circuit for controlling a light emitting time of the inorganic light emitting element.

[0080] Respectively, the R sub-pixel 20-1 can include an R inorganic light emitting element, and a sub-pixel circuit for controlling a light emitting time of the R inorganic light emitting element, the G sub-pixel 20-2 can include a G inorganic light emitting element, and a sub-pixel circuit for controlling a light emitting time of the G inorganic light emitting element, and the B sub-pixel 20-3 can include a B inorganic light emitting element, and a sub-pixel circuit for controlling a light emitting time of the B inorganic light emitting element.

[0081] Each sub-pixel circuit can express the gray scale of each sub-pixel by controlling the light emission time of the corresponding inorganic light emitting element based on an applied pulse width modulation (PWM) data voltage.

[0082] The sub-pixels included in each row line of the display panel 100 can be driven in the order of "PWM data voltage setting (or programming)" and "light emission based on the set PWM data voltage". In this regard, according to an embodiment, the sub-pixels included in each row line of the display panel 100 can be driven in the order of the row lines.

[0083] The PWM data voltage setting and light emission operation of the sub-pixels included in one row line (e.g., the first row line) and the PWM data voltage setting and light emission operation of the sub-pixels included in the next row line (e.g., the second row line) can be sequentially performed in the order of the row lines.

[0084] Sequentially performing does not mean that the operation associated with the next row line should start after all the operations associated with one row line have been completed. In the above example, the PWM data voltage can be set to the sub-pixels included in the second row line after the PWM data voltage is set to the sub-pixels included in the first row line, without the need to set the PWM data voltage to the sub-pixels included in the second row line after the light emission operation of the sub-pixels included in the first row line is completed.

[0085] FIG. 3A is a conceptual diagram illustrating a driving method of a related art display panel; FIG. 3B to FIG. 3D is a conceptual diagram illustrating a driving method of a display panel according to an embodiment.

[0086] FIG. 3A to FIG. 3D Various ways of driving a display panel during one image frame time are illustrated. Referring to FIG. 3A to FIG. 3D , the vertical axis represents row lines, and the horizontal axis represents time. The data setting period represents a driving period of the display panel 100 set by applying the PWM data voltage to the sub-pixels included in each row line, and the light emission period represents a driving period of the display panel 100 in which the sub-pixels emit light during a time corresponding to the PWM data voltage within the period.

[0087] Referring to FIG. 3A , in the related art, the light emission period is collectively performed after the PWM data voltage setting to the entire row lines of the display panel is completed in the order of the row lines.

[0088] In this embodiment, the entire row line of the display panel emits light at the same time during the light emission period, requiring a high peak current, and thus there is a problem of an increase in the peak power consumption required for the product. When the peak power consumption increases, the capacity of a power supply device such as a switch mode power supply (SMPS) installed in the product increases, resulting in an increase in cost and volume, thereby causing a design limitation.

[0089] In contrast, according to an embodiment of the present disclosure, there is only a difference in whether the PWM data voltage setting (S1) is completed for the entire row line during one image frame time, or whether the light emission period of all row lines is completely performed (S2) during one image frame time, or whether there are a plurality of light emission periods (S3) for each row line during one image frame time, and the PWM data voltage setting period and the light emission period of each row line are sequentially performed in row line order. FIG. 3B to FIG. 3D FIG. 3B FIG. 3C FIG. 3D

[0090] As described above, when the light emission period of each row line is sequentially driven in row line order according to various embodiments, the number of row lines that emit light at the same time can be reduced, and thus, compared to the related art, the required peak current amount can be reduced, and thus, the peak power consumption can be reduced.

[0091] According to various embodiments, it is possible to prevent the phenomenon in which the wavelength of light emitted from the inorganic light emitting element varies according to the gray scale by PWM driving the inorganic light emitting element in an active matrix (AM) method. By driving the display panel 100 such that the sub-pixels sequentially emit light in row line order, it is possible to reduce the instantaneous peak power consumption.

[0092] Referring to FIG. 2 , the sub-pixels 20-1 to 20-3 are arranged in an L shape in which the left and right of the sub-pixels 20-1 to 20-3 are different in one pixel area. However, embodiments are not limited thereto, and the R sub-pixel 20-1, the G sub-pixel 20-2, and the B sub-pixel 20-3 can be arranged in a linear shape in the pixel area, and can also be arranged in various shapes according to embodiments.

[0093] Referring to FIG. 2 , as an example, three sub-pixels can form one pixel. However, according to embodiments, four sub-pixels such as R, G, B, and white (W) can form one pixel, and any other number of sub-pixels can also form one pixel.

[0094] FIG. 4 is a block diagram illustrating a display module according to an embodiment. Referring to FIG. 4 , the display module 300 includes the display panel 100 and the driver 200.

[0095] ​​​​The driver 200 drives the display panel 100. The driver 200 can provide various control signals, data signals, driving voltages, etc. to the display panel 100 to drive the display panel 100.

[0096] The driver 200 can include at least one gate driver circuit for providing control signals to drive the panel of the display panel 100 in units of row lines.

[0097] The driver 200 can include a source driver circuit (or a data driver circuit) for providing a PWM data voltage to each pixel (or a sub-pixel) of the display panel 100.

[0098] The driver 200 can include a multiplexer (MUX) circuit for selecting each of a plurality of sub-pixels 20-1 to 20-3 included in one pixel 10.

[0099] The driver 200 can include a driving voltage providing circuit for providing driving voltages (e.g., a first driving voltage, a second driving voltage, a ground voltage, a test voltage, a Vset voltage, etc. to be described below), a constant current generator voltage, etc. to each sub-pixel circuit included in the display panel 100.

[0100] The driver 200 can include a clock signal providing circuit for providing various clock signals to a gate driver or a data driver circuit, and the driver 200 can include a sweep signal providing circuit for providing a sweep signal (or a sweep voltage) to be described below to a sub-pixel circuit.

[0101] At least some of the various circuits of the above-described driver 200 can be implemented in a form of a separate chip to be mounted on an external printed circuit board (PCB) together with a timing controller (TCON) and can be connected to a sub-pixel circuit formed on a thin film transistor (TFT) layer of the display panel 100 by a film on glass (FOG) wiring.

[0102] At least some of the various circuits of the above-described driver 200 can be implemented in a form of a separate chip and arranged on a film in a form of a chip on film (COF), and can be connected to a sub-pixel circuit formed on a TFT layer formed on the display panel 100 by a FOG wiring.

[0103] At least some of the various circuits of the above-described driver 200 can be implemented in a separate chip form, arranged in a COG form (i.e., arranged on a rear surface (a surface opposite to the surface on which the TFT layer is formed with respect to the glass substrate) of a glass substrate (described below) of the display panel 100), and can be connected to the sub-pixel circuits formed on the TFT layer of the display panel 100 through connection wirings.

[0104] At least some of the various circuits of the above-described driver 200 can be formed in the TFT layer together with the sub-pixel circuits in the TFT layer formed in the display panel 100, and can be connected to the sub-pixel circuits.

[0105] For example, among the various circuits of the above-described driver 200, the gate driver circuit, the scan signal providing circuit, and the MUX circuit can be formed in the TFT layer of the display panel 100, the data driver circuit can be arranged on the rear surface of the glass substrate of the display panel 100, and the driving voltage providing circuit, the clock signal providing circuit, and the TCON can be arranged on the external PCB, but are not limited thereto.

[0106] In particular, according to an embodiment, the driver 200 can set PWM data voltages to the sub-pixels included in each of the row lines of the display panel 100 in a row line order, apply scan signals to the sub-pixels included in at least some consecutive row lines among the plurality of row lines in a row line order, and drive the display panel 100 so that the sub-pixels included in the at least some consecutive row lines emit light based on the set PWM data voltages.

[0107] The at least some consecutive row lines can refer to all of the row lines of the display panel 100, or can refer to consecutive row lines belonging to each group when all of the row lines of the display panel 100 are divided into a plurality of groups each including some consecutive row lines.

[0108] Thus, as shown in FIG. 3B and FIG. 3C , the driver 200 can drive the display panel 100 so that the sub-pixels included in all of the row lines of the display panel 100 can emit light in a row line order.

[0109] As shown in FIG. 3D , the driver 200 can drive the display panel 100 so that, for each group including consecutive row lines, the sub-pixels included in the row lines belonging to each group emit light in a row line order.

[0110] FIG. 5 is a detailed block diagram illustrating a display module 300 according to an embodiment. In describing FIG. 5 , overlapping descriptions with FIG. 4 will be omitted.

[0111] Referring toFIG. 5 The display module 300 includes a display panel 100 including a sub-pixel circuit 110 and an inorganic light emitting element 120, and a driver 200.

[0112] The display panel 100 can have a structure in which the sub-pixel circuit 110 is formed on glass and the inorganic light emitting element 120 is disposed on the sub-pixel circuit 110. Referring to FIG. 5 For convenience, only a sub-pixel related structure included in the display panel 100 is illustrated, but the sub-pixel circuit 110 and the inorganic light emitting element 120 are provided for each sub-pixel of the above-described display panel 100.

[0113] The inorganic light emitting element 120 can be mounted on the sub-pixel circuit 110 to be electrically connected to the sub-pixel circuit 110, and can emit light based on a driving current provided from the sub-pixel circuit 110.

[0114] The inorganic light emitting element 120 can form sub-pixels 20-1 to 20-3 of the display panel 100, and depending on the color of the emitted light, there can be a variety of types. For example, the inorganic light emitting element 120 can include an R inorganic light emitting element that emits red light, a G inorganic light emitting element that emits green light, and a B inorganic light emitting element that emits blue light.

[0115] The type of the above-described sub-pixel can be determined according to the type of the inorganic light emitting element 120. The R inorganic light emitting element can form an R sub-pixel 20-1, the G inorganic light emitting element can form a G sub-pixel 20-2, and the B inorganic light emitting element can form a B sub-pixel 20-3.

[0116] The inorganic light emitting element 120 can refer to a light emitting element manufactured using an inorganic material, which is different from an organic light emitting diode (OLED) manufactured using an organic material.

[0117] According to an embodiment, the inorganic light emitting element 120 can be a micro light emitting diode (micro LED or μLED) having a size less than or equal to 100 micrometers (μm).

[0118] A display panel in which each sub-pixel is implemented with a micro LED is referred to as a micro LED display panel. The micro LED display panel is one of flat display panels, and can include a plurality of inorganic light emitting diodes each of which is less than or equal to 100 micrometers. The micro LED display panel can provide better contrast, response time, and energy efficiency compared to a liquid crystal display (LCD) panel that requires a backlight. An organic light emitting diode (OLED) and a micro LED have good energy efficiency, but the micro LED can provide better performance than the OLED in terms of brightness, light emitting efficiency, and lifespan.

[0119] Depending on the magnitude of the driving current provided from the sub-pixel circuit 110 or the pulse width of the driving current, the inorganic light emitting element 120 can represent a gray scale value of different brightness. The pulse width of the driving current can be referred to as a duty ratio of the driving current or a duration of the driving current.

[0120] For example, as the magnitude of the driving current increases, the inorganic light emitting element 120 can represent a brighter gray scale value. As the pulse width of the driving current increases (i.e., the duty ratio of the driving current increases or the duration of the driving current increases), the inorganic light emitting element 120 can represent a brighter gray scale.

[0121] The sub-pixel circuit 110 can provide the driving current to the inorganic light emitting element 120. The sub-pixel circuit 110 can provide the driving current having a controlled magnitude and duration to the inorganic light emitting element 120 based on a data voltage (e.g., a constant current generator voltage, a PWM data voltage), a driving voltage (e.g., a first driving voltage, a second driving voltage), and various control signals applied from the driver 200.

[0122] The sub-pixel circuit 110 can drive the inorganic light emitting element 120 by PAM and / or PWM driving to control the brightness of light emitted by the inorganic light emitting element 120.

[0123] The sub-pixel circuit 110 can include a constant current generator circuit 112 for providing a constant current having a magnitude corresponding to an applied constant current generator voltage to the inorganic light emitting element 120, and a PWM circuit 111 for providing the constant current to the inorganic light emitting element 120 for a time corresponding to a set PWM data voltage. The constant current provided to the inorganic light emitting element 120 becomes the above-described driving current.

[0124] According to an embodiment, the driver 200 can apply the same constant current generator voltage to all constant current generator circuits 112 of the display panel 100. Accordingly, since the same magnitude of driving current (i.e., constant current) is provided to each inorganic light emitting element 120 by each constant current generator circuit 112, the wavelength variation problem of the LED according to the driving current magnitude variation can be solved.

[0125] The driver 200 can apply a PWM data voltage corresponding to a gray scale value of each sub-pixel to each of the PWM circuits 111 of the display panel 100. Accordingly, the duration of the driving current (i.e., the duration of the constant current) provided to the inorganic light emitting element 120 of each sub-pixel can be controlled by the PWM circuit 111. Accordingly, a gray scale of an image can be expressed.

[0126] The same constant current generator voltage can be applied to one display module 300, and different constant current generator voltages can be applied to another display module 300. When a plurality of display modules are connected to each other to form a large display apparatus, luminance deviation or color deviation between the display modules can be compensated for by voltage adjustment of the constant current generator.

[0127] The display module 300 according to various embodiments can be applied to various electronic products, or electronic products requiring wearable devices, portable devices, handheld devices, and displays to be implemented in a single unit.

[0128] The display module 300 according to various embodiments can also be applied to small display apparatuses (e.g., monitors for personal computers, televisions (TVs)), or large display apparatuses (e.g., digital signage, electronic displays), etc.

[0129] Reference FIG. 6A to FIG. 6F The driving method of the display panel 100 will be described in detail. FIG. 3D The driving method of the display panel 100 will be described in detail.

[0130] FIG. 6A The driving method of a plurality of image frames of the display panel 100 according to an embodiment is illustrated. In each frame of FIG. 6A In each frame of

[0131] VST and SP can refer to control signals for a data setting operation applied by the driver 200 to the sub-pixels included in each row line, and SET, Emi_PWM, sweep, and Emi_PAM can refer to control signals for a light emission operation applied by the driver 200 to the sub-pixels included in each row line.

[0132] Reference FIG. 6A For each row line during an image frame duration, a data setting period (i.e., a period in which control signals VST and SP are applied) is performed once, and a light emission period (i.e., a period in which SET, Emi_PWM, Sweep, and Emi_PAM are applied) is performed a plurality of times.

[0133] According to an embodiment, during the data setting period of each row line, the driver 200 can set a PWM data voltage to the sub-pixels included in each row line, and during the plurality of light emission periods of each row line, the driver 200 can drive the display panel 100 such that the sub-pixels included in each row line emit light for a time corresponding to the set PWM data voltage.

[0134] FIG. 6B The driving method of a plurality of image frames of the display panel 100 according to an embodiment is illustrated. In FIG. 6AThe second frame is shown. In FIG. 6B In the second frame, the vertical axis can refer to a row line, and the horizontal axis can refer to time. In FIG. 6B In the second frame, for example, the display panel 100 is formed of 40 row lines for convenience.

[0135] Referring to FIG. 6B The driver 200 can apply a control signal (VST, SP) to the sub-pixels included in the first row line during a data setting period 61 of the first row line. Accordingly, the sub-pixels included in the first row line can be set (or programmed) with the PWM data voltage provided from the data driver.

[0136] The driver 200 can apply a control signal (e.g., SET, Emi_PWM, Sweep, Emi_PAM) to the sub-pixels included in the first row line during a first emission period 62 of the first row line. Accordingly, the sub-pixels included in the first row line can emit light for a time corresponding to the PWM data voltage in the first emission period 62.

[0137] Even during a second emission period 63 of the first row line, the driver 200 can apply a control signal (e.g., SET, Emi_PWM, Sweep, Emi_PAM) to the sub-pixels included in the first row line in the same manner as the first emission period 62. Even in the second emission period 63, the sub-pixels included in the first row line can emit light for a time corresponding to the PWM data voltage.

[0138] This is the same for a third emission period 64 and a fourth emission period 65 of the first row line.

[0139] Referring to FIG. 6B The driver 200 can sequentially perform the operations described above as being performed for the first row line in the same manner for the sub-pixels included in the remaining row lines (2nd row line to 40th row line) in row line order.

[0140] Referring to FIG. 6B Since only one frame period (i.e., the second frame period) is shown, it is shown that only three emission periods are performed for the 11th row line to the 20th row line, only two emission periods are performed for the 21st row line to the 30th row line, and only one emission period is performed for the 31st row line to the 40th row line. However, referring to the second frame period and the third frame period shown together in FIG. 6A It can be seen that even for the 11th row line to the 40th row line, the emission periods are performed four times, respectively.

[0141] According to FIG. 6BIn the example shown, a first light emission period 62 of the plurality of light emission periods of the first line can be continuous in time with the data setting period 61 of the first line, and the plurality of light emission periods 62 to 65 each have a predetermined time interval. This is the same for the remaining line.

[0142] According to the embodiment, the predetermined time interval between the light emission periods, and the number of light emission periods performed in each line of the line during one image frame period, can be set based on the size of the display panel 100 and / or the shutter speed of the camera, etc. However, the embodiment is not limited thereto.

[0143] Since the shutter speed of the camera is several times faster than one image frame time, if the display panel 100 is driven so that one light emission period is performed in the order of the line within one image frame time as shown in FIG. 3B or FIG. 3C the image captured in the camera and displayed on the display panel 100 can be distorted.

[0144] As shown in FIG. 3D , the display panel 100 can be driven so that a plurality of light emission periods are performed at predetermined time intervals during one image frame time, and by setting the predetermined time interval based on the speed of the camera, the image displayed on the display panel 100 is not distorted even if the display panel 100 is captured at any time.

[0145] FIG. 6B The data setting period and the light emission period shown in FIG. 6B are shown only to conceptually explain the data setting operation and the light emission operation performed in the order of the line. The detailed driving timing of the control signal (VST, SP) for data setting, the control signal (SET, Emi_PWM, Sweep, Emi_PAM) for the light emission operation is not limited to the embodiment shown in

[0146] FIG. 6C is a configuration diagram of a sub-pixel circuit 110 according to the embodiment. According to FIG. 6C , the sub-pixel circuit 110 includes a PWM circuit 111, a constant current generator circuit 112, a first switching transistor T10, and a second switching transistor T15.

[0147] The constant current generator circuit 112 includes a first drive transistor T8, and based on a voltage applied between the source terminal and the gate terminal of the first drive transistor T8, provides a constant current having a constant amplitude to the inorganic light emitting element 120.

[0148] When a constant current generator voltage is applied from the driver 200 in the data setting period, the constant current generator circuit 112 can apply a constant current generator voltage compensated for the threshold voltage of the first drive transistor T8 to the gate terminal B of the first drive transistor T8.

[0149] There can be a difference in threshold voltage between the first drive transistors T8 included in the sub-pixels of the display panel 100. In this example, even if the same constant current generator voltage is applied, the constant current generator circuit 112 of each sub-pixel can provide a driving current of a different magnitude through the difference in threshold voltage of the first drive transistor T8, resulting in a stain of the image, etc. Therefore, it is necessary to compensate for the threshold voltage deviation of the first drive transistor T8 included in the display panel 100.

[0150] To this end, the constant current generator circuit 112 includes an internal compensation unit 12. When a constant current generator voltage is applied, the constant current generator circuit 112 can provide, through the internal compensation unit 12, a first voltage based on the threshold voltage of the first drive transistor T8 and the constant current generator voltage to the gate terminal B of the first drive transistor T8.

[0151] Thereafter, in the light emission period, the constant current generator circuit 112 can provide a constant current of a magnitude based on the first drive voltage applied to the source terminal of the first drive transistor T8 and the first voltage applied to the gate terminal of the first drive transistor T8 to the inorganic light emitting element 120 through the turned-on first drive transistor T8.

[0152] Therefore, regardless of the threshold voltage of the first drive transistor T8, the constant current generator circuit 112 can provide a driving current of a magnitude corresponding to the applied constant current generator voltage to the inorganic light emitting element 120.

[0153] Meanwhile, referring to FIG. 6C , the source terminal of the first switch transistor T10 is connected to the drain terminal of the first drive transistor T8, and the drain terminal of the first switch transistor T10 is connected to the source terminal of the second switch transistor T15. The source terminal of the second switch transistor T15 can be connected to the drain terminal of the first switch transistor T10, and the drain terminal of the second switch transistor T15 can be connected to the anode terminal of the inorganic light emitting element 120. When the first switch transistor T10 and the second switch transistor T15 are turned on, a constant current can be provided to the inorganic light emitting element 120.

[0154] The PWM circuit 111 can include a second drive transistor T3, and control the time for which a constant current flows in the inorganic light emitting element 120 by controlling the turn-on / off operation of the first switch transistor T10.

[0155] When the PWM data voltage is applied from the driver 200 in the data setup period, the PWM circuit 111 can set the PWM data voltage in which the threshold voltage of the second driving transistor T3 is compensated on the gate terminal A of the second driving transistor T3.

[0156] For the second driving transistor T3, the threshold voltage deviation problem between the above-described first driving transistor T8 can also occur in the same manner, and the PWM circuit 111 can also include the internal compensation unit 11.

[0157] Upon application of the PWM data voltage, the PWM circuit 111 can set a second voltage based on the threshold voltage of the second driving transistor T3 and the PWM data voltage to the gate terminal A of the second driving transistor T3.

[0158] After the second driving transistor T3 is turned on based on the ramp signal applied in the emission period, the PWM circuit 111 can apply a second driving voltage to the gate terminal of the first switching transistor T10 to turn off the first switching transistor T10, and can control the time during which the constant current flows through the inorganic light emitting element 120. At this time, if the second voltage set to the gate terminal changes according to the ramp signal applied to the PWM circuit 111, the second driving transistor T3 can be turned on such that the voltage between the gate terminal and the source terminal becomes the threshold voltage of the second driving transistor T3.

[0159] The ramp signal is a voltage applied by the driver 200 to change the voltage of the gate terminal of the second driving transistor T3, and is a voltage signal that is ramped between two different voltages. For example, the ramp signal can be a linearly varying signal such as a triangular wave, but is not limited thereto.

[0160] The PWM circuit 111 can cause the constant current to flow through the inorganic light emitting element 120 only during a time corresponding to the applied PWM data voltage, regardless of the threshold voltage of the second driving transistor T3.

[0161] The PWM circuit 111 includes a reset unit 13. The reset unit 13 is configured to forcibly turn on the first switching transistor T10. As described above, it is necessary to turn on the first switching transistor T10 so that the constant current flows through the inorganic light emitting element 120 to cause the inorganic light emitting element 120 to emit light. Accordingly, the first switching transistor T10 can be turned on at the start point of each emission period by the operation of the reset unit 13.

[0162] The second switching transistor T15 can be turned on and off according to a control signal (Emi_PAM to be described below).

[0163] The first driving voltage is a driving voltage used when the constant current generator circuit 112 supplies a driving current (i.e., a constant current) to the inorganic light emitting element 120 in the light emission period, and the second driving voltage is a driving voltage used when a data voltage (e.g., a PWM data voltage, a constant current generator voltage) is set to the sub-pixel circuit 110 in the data setting period.

[0164] When the driving current flows through the inorganic light emitting element 120, an infrared (IR) voltage drop occurs, and thus, a voltage drop is generated in the first driving voltage. However, for accurate gray scale representation, it is necessary to set a precise data voltage to the sub-pixel circuit 110, and the driving voltage applied to the sub-pixel circuit 110 needs to be stable.

[0165] According to an embodiment, by applying the second driving voltage without an IR voltage drop even to the constant current generator circuit 112 that supplies the driving current as well as the PWM circuit 111 in the data setting period, stable setting of the data voltage (i.e., the PWM data voltage and the constant current generator voltage) to the sub-pixel circuit 110 is achievable.

[0166] FIG. 6D is a detailed circuit diagram of the sub-pixel circuit 110 according to an embodiment. Referring to FIG. 6D , the sub-pixel circuit 110 includes the PWM circuit 111, the constant current generator circuit 112, a first switching transistor T10, and a second switching transistor T15. As described above FIG. 6C , the PWM circuit 111 can include an internal compensation unit 11 and a reset unit 13, and the constant current generator circuit 112 can include an internal compensation unit 12.

[0167] The transistor T17 and the transistor T18 are circuits that apply the second driving voltage (VDD_PWM) to the constant current generator circuit 112 in the data setting period.

[0168] The transistor T13 is a circuit element that is turned on according to a test voltage, and is used to identify whether there is an abnormality in the sub-pixel circuit 110 before the inorganic light emitting element 120 is mounted on a TFT layer to be described and electrically connected to the sub-pixel circuit 110.

[0169] Referring to FIG. 6D , VDD_PAM denotes the first driving voltage (e.g., +10 [V]), VDD_PWM denotes the second driving voltage (e.g., +10 [V]), VSS denotes a ground voltage (e.g., 0 [V]), and Vset denotes a low voltage (e.g.,?3 [V]) for turning on the first switching transistor T10. VDD_PAM, VDD_PWM, VSS, Vset, and the test voltage can be applied from the above-described driving voltage supply circuit.

[0170] VST(n) denotes a signal of a voltage applied to the sub-pixel circuit 110 to initialize the A node (the gate terminal of the second drive transistor T3) and the B node (the gate terminal of the first drive transistor T8).

[0171] SP(n) denotes a signal applied to the sub-pixel circuit 110 to set a data voltage (i.e., a PWM data voltage, a constant current generator voltage).

[0172] SET(n) denotes a signal applied to the reset unit 13 of the PWM circuit 111 to turn on the first switch transistor T10.

[0173] Emi_PWM(n) denotes a signal for applying the second drive voltage (VDD_PWM) to the PWM circuit 111 by turning on the transistor T1 and the transistor T5, and applying the first drive voltage (VDD_PAM) to the constant current generator circuit 112 by turning on the transistor T6 and the transistor T16.

[0174] sweep(n) denotes a sweep signal. According to an embodiment, the sweep signal can be a linearly decreasing voltage, but is not limited thereto. For example, when the transistors included in the sub-pixel circuit 110 are implemented as NMOS transistors, a linearly increasing voltage can be used as the sweep signal. The sweep signal can be repeatedly applied in the same form for each light emission period.

[0175] Emi_PAM(n) denotes a signal for turning on the second switch transistor T15.

[0176] In the above signals, n denotes the nth line. As described above, the driver 200 drives the display panel 100 through the line (or sweep line or gate line), and the above-described control signals (VST(n), SP(n), SET(n), Emi_PWM(n), Sweep(n), and Emi_PAM(n)) can be applied to all of the sub-pixel circuits 110 included in the nth line in the same manner as FIG. 6E

[0177] Accordingly, the above-described control signals can be referred to as scan signals or gate signals, and can be applied by the above-described gate driver.

[0178] Vsig(m)_R / G / B denotes a PWM data voltage of each of the R, G, and B sub-pixels of the pixel included in the mth column line. Since the above-described gate signal is a signal for the nth line, the Vsig(m)_R / G / B shown in FIG. 6D indicates that the PWM data voltage of each of the R, G, and B sub-pixels of a specific pixel arranged at the intersection of the nth line and the mth column line is time-division multiplexed and applied.​

[0179] Vsig(m)_R / G / B can be applied by the above-described data driver. Also, Vsig(m)_R / G / B can use a voltage between +10 [V] (black) and +15 [V] (full white), for example, but is not limited thereto.

[0180] FIG. 6D The illustrated sub-pixel circuit 110 shows a sub-pixel circuit 110 corresponding to a sub-pixel (e.g., R sub-pixel) of any one of R, G, and B sub-pixels, such that only the PWM data voltage of the R sub-pixel can be selected and applied through a MUX circuit (not shown) among the time-division multiplexed PWM data voltages.

[0181] VPAM_R / G / B denotes a constant current generator voltage of each of R, G, and B sub-pixels included in the display panel 100. The same constant current generator voltage can be applied to the display panel 100.

[0182] However, the same constant current generator voltage means that the same constant current generator voltage is applied to the same type of sub-pixel included in the display panel 100, not that the same constant current generator voltage is applied to all different types of sub-pixels such as R, G, and B. The characteristics of R, G, and B sub-pixels are different depending on the type of the sub-pixel. Accordingly, the constant current generator voltage can vary according to the type of the sub-pixel.

[0183] In this example, the same constant current generator voltage is applied to the same type of sub-pixel regardless of the column line or the row line. According to an embodiment, unlike the PWM data voltage, the constant current generator voltage can be directly applied from the driving voltage supply circuit to each type of sub-pixel without using a data driver.

[0184] Since the same voltage is applied to the same type of sub-pixel regardless of the column line or the row line, a DC voltage can be used as the constant current generator voltage. For example, three DC voltages (e.g., +5.1 [V], +4.8 [V], +5.0 [V]) corresponding to each of R, G, and B sub-pixels can be separately applied from the driving voltage supply circuit to each of R, G, and B sub-pixel circuits of the display panel 100. In this example, a MUX circuit is not needed.

[0185] According to an embodiment, when the same constant current generator voltage exhibits better characteristics when used for different types of sub-pixels, the same constant current generator voltage can be applied to the different types of sub-pixels.

[0186] FIG. 6E is a timing chart of the gate signal described above in FIG. 6D .

[0187] FIG. 6E VST(n) and SP(n) (①) in the gate signals illustrated are associated with the data setting operation of the sub-pixel circuit 110, and can be referred to as a scan signal. In FIG. 6E In the gate signals illustrated, Emi_PWM(n), SET(n), Emi_PAM(n), and Sweep(n) (②) are associated with the light emission operation of the sub-pixel circuit 110, and can be referred to as an emission signal.

[0188] As described above, according to the embodiment, during one image frame period, for each line, the data setting period can be performed once, and the light emission period can be performed multiple times.

[0189] Therefore, the ① signal can be applied to each line of the display panel 100 once per image frame, and the ② signal can be applied to each line of the display panel 100 multiple times per image frame.

[0190] FIG. 6F is a timing chart of various signals for driving the display panel 100 during one image frame period according to the embodiment. Referring to FIG. 6F , the display panel 100 includes 270 lines.

[0191] Referring to reference numerals 1-①, 2-① to 270-①, the scan signal (VST(n), SP(n)) for the data setting operation can be applied to each line in line order once within one frame period.

[0192] Referring to reference numerals 1-②, 2-② to 270-②, the emission signal (Emi_PWM(n), SET(n), Emi_PAM(n), and Sweep(n)) for the light emission operation can be applied to each line multiple times.

[0193] According to the embodiment, in the light emission period performed in the entire lines of the display panel 100 during one image frame period, some light emission periods (for example, the upper light emission periods based on FIG. 6B the lines connecting the data setting periods) can be performed based on the data voltage applied during one image frame period, and the remaining light emission periods (for example, the lower light emission periods with respect to the lines connecting the data setting periods) can be performed based on the data voltage applied during the previous image frame period of one image frame period.

[0194] In FIG. 6F the light emission operation by the gate signals illustrated, the light emission operation by the emission signal of reference numeral 14 is a light emission operation based on the data voltage applied in the previous image frame period.

[0195] Referring toFIG. 7A to FIG. 13 An operation example of the driver 200 according to various embodiments of the gate signal illustrated in FIG. 1 will be described. FIG. 6D An operation example of the driver 200 according to various embodiments of the gate signal illustrated in FIG. 1 will be described.

[0196] FIG. 7A is a block diagram of a display module 300 according to an embodiment. As illustrated in FIG. 7A The display module 300 includes the display panel 100 and the driver 200.

[0197] The driver 200 can include a gate driver disposed in each of the row lines to provide the gate signals (e.g., VST(n), SP(n), Emi_PWM(n), SET(n), Emi_PAM(n), and Sweep(n)) to each of the row lines.

[0198] FIG. 7A A first gate driver 200-1 for providing the gate signals to a first row line and a second gate driver 200-2 for providing the gate signals to a second row line are illustrated.

[0199] According to FIG. 7A Each of the gate drivers 200-1 and 200-2 can receive a driving voltage signal (VDD, VSS), a clock signal (CLK1, CLK2...) for generating a scan signal, a clock signal (EM_CLK1...) for generating an emission signal, an input sweep signal (Sweep1, Sweep2, Sweep3...), and an enable signal (Vst1, Vst2, Vst3...) to generate the gate signals, and can provide the generated gate signals to the corresponding row line (specifically, a sub-pixel circuit included in the row line).

[0200] Each of the gate drivers 200-1 and 200-2 can be implemented by a combination of at least one scan driver and / or at least one emission driver. Detailed descriptions will be provided with reference to FIG. 8A to FIG. 13

[0201] FIG. 7B is a timing chart of the gate signals output from the gate drivers when the input sweep signal and various clock signals are input during a frame time according to an embodiment.

[0202] Referring to FIG. 7B To generate the scan signals (VST(n) and SP(n)), two-phase clock signals (CLK, CLKB) can be input to the gate drivers 200-1, 200-2.

[0203] ​To generate the emission signals (Emi_PWM(n), SET(n), Emi_PAM(n), and Sweet(n)), six-phase Emi_PWM clock signals (Emi_PWM_CLK1 to Emi_PWM_CLK6), four-phase Emi_PAM clock signals (Emi_PAM_CLK1 to Emi_PAM_CLK4), and six-phase input sweep signals (Sweep P1 to Sweep P6) can be input to the gate drivers 200-1, 200-2.

[0204] As shown in FIG. 1, FIG. 7B the gate drivers 200-1, 200-2 can apply the scan signals and the emission signals to each of the row lines in row line order.

[0205] FIG. 7B The number of different phases of the input sweep signals in FIG. 1, and the number of different phases of the various clock signals are exemplary only and can vary according to embodiments, and are not limited to the embodiments shown in FIG. 1. FIG. 7B

[0206] FIG. 8A to FIG. 8C is a diagram of an embodiment in which gate signals are generated using a scan driver.

[0207] FIG. 8A is a circuit diagram of a scan driver 81 according to an embodiment. As shown in FIG. 8, FIG. 8A the scan driver 81 can generate a scan signal SP(n).

[0208] The scan driver 81 can receive clock signals (CLK, CLKB) having opposite phases, drive voltage signals (VDD and VSS), and a scan signal SP(n-1) applied to a previous row line, and can output a scan signal SP(n).

[0209] FIG. 8B shows a connection relationship between scan drivers according to an embodiment. As described above, the scan signals SP(n) are applied to the display panel 100 in row line order. As shown in FIG. 9, FIG. 8B the scan drivers 81-1 to 81-n provided for each of the row lines can be connected to each other.

[0210] Referring to FIG. 8B the output signal SP(1) of the scan driver 81-1 of the first row line can be input to the scan driver 81-2 of the second row line (i.e., the next row line) as an enable signal of the scan driver 81-2. This applies to the scan driver 81-n of the nth row line. A separate enable signal (Vst) is applied to the scan driver 81-1 of the first row line.

[0211] Referring to FIG. 8B ​In the scan drivers 81-1 to 81-n of each row line, the clock signals CLK and CLKB are input in the opposite order to the previous row line for each row line. The CLK signal can be input to the CLK input terminal of the scan driver 81-1, and the CLKB signal can be input to the CLKB input terminal. The CLKB signal can be input to the CLK input terminal of the scan driver 81-2 of the next row line, and the CLK signal can be input to the CLKB input terminal. This is the same for the scan driver 81-n of the nth row line.

[0212] FIG. 8C is a timing chart of various signals for driving a scan driver according to an embodiment.

[0213] Referring to FIG. 8A and FIG. 8C The process of outputting the scan signal SP(n) is described. First, when the scan signal SP(n-1) is input to the scan driver 81, the Q(n) node voltage becomes low. Then, as the CLK signal becomes low, the Q(n) node voltage is boosted, and thus, the transistor T7 can be fully turned on to output the output signal, that is, SP(n). Those of ordinary skill in the art can easily understand other operations related to the signals applied to the circuit configuration, and thus a more detailed description will be omitted.

[0214] It has been described that the scan signal SP(n) is generated using the scan driver 81, but the same circuit and the same driving method described above can be applied to the generation of the scan signal VST(n) or the emission signal SET(n) as described above with reference to FIG. 8A to FIG. 8C .

[0215] FIG. 9A to FIG. 9C is a diagram for illustrating an embodiment for generating a gate signal using an emission driver. In FIG. 9A to FIG. 9C , according to an embodiment, the output signal Out(n) can correspond to any one of the emission signal Emi_PWM(n), the emission signal Emi_PAM(n), or the emission signal SET(n).

[0216] FIG. 9A is a circuit diagram of an emission driver 91 according to an embodiment. Referring to FIG. 9A , the emission driver 91 can generate the output signal Out(n). The emission driver 91 can receive clock signals (CLK, CLKB) having opposite phases, driving voltage signals (VGH, VGL), and an output signal Out(n-1) applied to the previous row line, to output the output signal Out(n).

[0217] FIG. 9BThe connection relationships between the emission drivers according to an embodiment are shown. As described above, since the emission periods occur in row-line sequence, the emission signals are also applied to the display panel 100 in row-line sequence. FIG. 9B As shown, the transmitter drivers 91-1 to 91-n provided for each row line can be connected to each other.

[0218] refer to FIG. 9B The output signal (Out(1)) of the first row transmitter driver 91-1 can be input to the transmitter driver 91-2 as the start signal of the second row (i.e., the next row). This is the same for the transmitter drivers 91-n up to the nth row. A separate start signal Vst is applied to the transmitter driver 91-1 of the first row.

[0219] refer to FIG. 9B In the transmit drivers 91-1 to 91-n for each row line, clock signals CLK and CLKB are input in the opposite direction to the previous row line. The CLK signal can be input to the CLK input of transmit driver 91-1, and the CLKB signal can be input to the CLKB input. However, the CLKB signal can be input to the CLK input of the transmit driver 91-2 for the next row line, and the CLK signal can be input to the CLKB input. This is the same for transmit drivers 91-n up to the nth row line.

[0220] FIG. 9C This is a timing diagram of various signals used to drive the transmit driver 91 according to an embodiment. For example... FIG. 9C As shown, the output signal Out(n-1) of the (n-1)th row and the output signal Out(n) of the nth row are generated sequentially in row order.

[0221] pass FIG. 9A Circuit configuration, FIG. 9B The connection relationships of the transmitter drivers 91-1 to 91-n shown, and FIG. 9C The timing diagram shown illustrates the more specific operation of the transmit driver 91, which will be obvious to those skilled in the art, and therefore its detailed description will be omitted.

[0222] FIG. 10A to FIG. 10C This is a diagram of another embodiment of generating gate signals using a scan driver.

[0223] FIG. 10A This is a circuit diagram of the scan driver 81 according to an embodiment. FIG. 10A The scan driver 81 has a similar function to FIG. 8A It has the same circuit configuration as the scan driver 81.

[0224] but, FIG. 10AScan driver 81 and FIG. 8A The difference of the scan driver 81 shown is that it outputs the transmit signal Emi_PWM(n) by receiving two clock signals with opposite phases out of six clock signals with different phases, and the transmit signal Emi-PWM(n-3) applied to the row lines before the three row lines.

[0225] FIG. 10B The connection relationships between scan drivers according to an embodiment are shown. Reference FIG. 10B ,and FIG. 8B The difference is that there are three dummy scan drivers 81′-1 to 81′-3. This is because the scan drivers 81′-1 to 81′-n for each row line need to receive the transmit signal Emi_PWM(n-3) of the row line applied to the three row lines as a start signal.

[0226] Therefore, as FIG. 10B As shown, the first dummy scan driver 81'-1 can receive clock signals CLK1 and CLK4, as well as a start signal Vst3, and can output an Emi_PWM(-3) signal. The output Emi_PWM(-3) signal is input as the start signal of the first row line scan driver 81-1.

[0227] The second dummy scan driver 81'-2 can receive clock signals CLK2 and CLK5, start signal Vst2, and output Emi_PWM(-2) signal. The output Emi_PWM(-2) signal can be input as the start signal of the second row scan driver (not shown).

[0228] The third dummy scan driver 81'-3 can receive clock signals CLK3 and CLK6, as well as a start signal Mst1, to output an Emi_PWM(-1) signal. The output Emi_PWM(-1) signal can be input as the start signal of the third row scan driver (unused).

[0229] For each row line scan driver 81-1 to 81-n, the same clock signal as that applied to the row lines preceding the three row lines is applied. For the first row line scan driver 81-1, the same clock signals CLK1 and CLK4 as those applied to the first dummy scan driver 81′-1 are applied. Although not shown in the figures, the same applies to the remaining scan drivers.

[0230] FIG. 10C This is a timing diagram of various signals used to drive the scan driver according to an embodiment.

[0231] refer to FIG. 10CThe six clock signals CLK1 to CLK6 have different phases. Clock signals CLK1 and CLK4 can have opposite phases, CLK1 and CLK5 can have opposite phases, and CLK3 and CLK6 can have opposite phases.

[0232] refer to FIG. 10C Since the transmitted signals Emi PWM(n-3) and Emi-PWM(n) are generated with time intervals of up to 3H, it is sufficient to predict that the transmitted signals Emi-PWM(n-1) and Emi_PWM(n) are generated in row-line order with time intervals of 1H (e.g., FIG. 9C Out(n-1) and out(n)).

[0233] Due to the passage FIG. 10A The circuit configuration shown FIG. 10B The connection relationships of scan drivers 81′-1 to 81′-3 and 81-1 to 81-n are shown, and FIG. 10C The timing diagram shown will allow those skilled in the art to understand the more detailed operation of the scan driver 81, therefore a more detailed description will be omitted.

[0234] The generation of the transmit signal Emi_PWM(n) using six clock signals with different phases and a scan driver 81 has been described, but... FIG. 10A to FIG. 10C The same circuit and the same driving method shown can be applied to the generation of the transmit signal Emi_PAM(n) or the transmit signal SET(n).

[0235] FIG. 11A to FIG. 11C This is a diagram showing the generation of sweep signals using a scan driver.

[0236] FIG. 11A This is a circuit diagram of a sweep / scan driver 800 according to an embodiment. FIG. 11A As shown, the sweep / scan driver 800 can generate a transmit signal Emi_PWM(n) and a transmit signal sweep(n) (i.e., the sweep signal).

[0237] The sweep / scan driver 800 includes a scan driver 81 and a sweep driver 82. For example... FIG. 11A As shown, scan driver 81 and sweep driver 82 can form a circuit.

[0238] The scanning actuator 81 can have the same as FIG. 10A It has the same circuit configuration as the scan driver 81, and can output the output signal Emi_PWM(n) through the first output terminal 5.

[0239] The sweep driver 82 can include two transistors T9 and T10 connected in series, and a capacitor C3, and can output a transmission signal Sweep(n) at the second output terminal 6, which is a node at which the two transistors T9 and T10 are connected to each other.

[0240] The gate terminal of the transistor T9 can be connected to the first output terminal 5 of the scan driver 81, the source terminal of the transistor T9 can receive an input sweep signal Sweep PN, which has a form in which a sweep signal that sweeps between two different voltages is continuously repeated, and the drain terminal of the transistor T9 is connected to the transistor T10. The input sweep signal (Sweep PN) is one of a plurality of input sweep signals (Sweep P1, Sweep P2, and Sweep P3) having different phases as illustrated in FIG. 8. FIG. 11B and FIG. 11C

[0241] FIG. 11B The connection relationship between the sweep / scan drivers according to the embodiment is illustrated. FIG. 11B The connection relationship between the sweep / scan drivers illustrated in FIG. 9 is similar to the connection relationship of the scan drivers illustrated in FIG. 8. However, FIG. 10B FIG. 11B The sweep / scan drivers of FIG. 9 additionally receive input sweep signals (Sweep P1 to Sweep P3) to output a transmission signal Sweep(n).

[0242] Referring to FIG. 9, FIG. 11B The output signal Emi_PWM(1) of the sweep / scan driver 800-1 of the first line can be input to a sweep / scan driver (not shown) of a second line (i.e., a next line) as a start signal of the sweep / scan driver (not shown), and this is the same for the sweep / scan drivers 800-n of the lines up to the nth line.

[0243] The first dummy sweep / scan driver 800'-1 can receive clock signals CLK1 and CLK4 having opposite phases, and a start signal Vst3, to output an Emi_PWM(-3) signal. The output Emi_PWM(-3) signal is input to the sweep / scan driver 800-1 of the first line as a start signal of the sweep / scan driver 800-1.

[0244] ​​The second dummy sweep / scan driver 800'-2 can receive clock signals CLK2 and CLK5 having opposite phases to each other, and a start signal Vst2, and output an Emi_PWM(-2) signal. The output Emi_PWM(-2) signal is input to a sweep / scan driver (not shown) of a second row line as a start signal of the sweep / scan driver (not shown).

[0245] The third dummy sweep / scan driver 800'-3 can receive clock signals CLK3 and CLK6 having opposite phases to each other, and a start signal Vst1 is input to output an Emi_PWM(-1) signal. The output Emi_PWM(-1) signal is input to a sweep / scan driver (not shown) of a third row line as a start signal of the sweep / scan driver (not shown).

[0246] For the sweep / scan drivers 800-1 to 800-n of each row line, the same clock signals as those applied to the row lines before three row lines can be applied thereto. Thus, for the sweep / scan driver 800-1 of the first row line, the same clock signals CLK1 and CLK4 as those applied to the first dummy sweep / scan driver 800'-1 can be applied thereto. Although not shown in the drawing, the clock signals are applied to the remaining sweep / scan drivers in the same manner.

[0247] For the sweep / scan drivers 800-1 to 800-n of each row line, three input sweep signals (Sweep P1, Sweep P2, and Sweep P3) having different phases can be alternately applied according to the row lines.

[0248] According to FIG. 11B , the input sweep signal Sweep P1 is applied to the sweep / scan driver 800-1 of the first row line, the input sweep signal Sweep P2 and the input sweep signal Sweep P3 are applied to the sweep / scan drivers (not shown) of the second and third row lines, respectively, and the input sweep signal Sweep P1 is applied again to the sweep / scan driver (not shown) of the fourth row line. Although not shown in the drawing, the input sweep signals are applied to the remaining sweep / scan drivers in this manner.

[0249] The sweep / scan drivers 800-1 to 800-n of each row line can output an emission signal Emi_PWM(n) and an emission signal sweep(n) of a corresponding line.

[0250] FIG. 11C is a timing diagram of various signals for driving a sweep / scan driver according to an embodiment.

[0251] AsFIG. 11C As shown, the clock signals CLK1 and CLK4 have opposite phases. Although not shown, as described above, the clock signals CLK2 and CLK5 can have opposite phases to each other, and the clock signals CLK3 and CLK6 can have opposite phases to each other.

[0252] As FIG. 11C shown, the three input sweep signals (Sweep P1, Sweep P2, Sweep P3) can have different phases.

[0253] Each input sweep signal can have a format in which a transmission signal sweep(n) (i.e., a sweep signal) output from a sweep / scan driver to which the corresponding input sweep signal is applied is sequentially repeated.

[0254] For example, the input sweep signal Sweep P3 input to the sweep / scan driver 800-n of the nth row line can have a format in which a transmission signal Sweep(n) output from the sweep / scan driver 800-n is sequentially repeated, and the input sweep signal Sweep P2 input to the sweep / scan driver (not shown) of the (n-1)th row line can have a format in which a transmission signal Sweep(n-1) output from the sweep / scan driver (not shown) of the (n-1)th row line is sequentially repeated.

[0255] This is because the transmission signal sweep(n) is a signal that is selectively output from the input sweep signal.

[0256] Referring to FIG. 11A and FIG. 11B , the scan driver 81 of the sweep / scan driver 800-n can receive a transmission signal Emi_PWM(n-3) output from the sweep / scan driver (not shown) of the previous row line of the three row lines, as well as the clock signals CLK3 and CLK6, and can output a transmission signal Emi_PWM(n) through the first output terminal 5.

[0257] The sweep driver 82 includes a transistor T9, a gate terminal of the transistor T9 is connected to the first output terminal 5, the sweep driver 82 receives the input sweep signal Sweep P3 through a source terminal of the transistor T9, and a drain terminal of the transistor T9 becomes the second output terminal 6.

[0258] The sweep driver 82 can select a transmission signal Sweep(n) from the input sweep signal Sweep P3 while the transmission signal Emi_PWM(n) is output from the scan driver 81, and output the transmission signal Sweep(n) through the second output terminal 6.

[0259] By FIG. 11BThe connection relationship of the sweep / scanning drivers 800'-1 to 800'-3, 800-1 to 800-n shown in the timing chart, and FIG. 11C From the timing chart shown, one of ordinary skill in the art can easily understand more specific operations of the sweep / scanning driver 800. Further description will be omitted.

[0260] It has been shown that the sweep / scanning driver 800 generates the emission signal Emi_PWM(n) and Sweep(n), but by applying the same circuit and the same driving method as described above through FIG. 11A to FIG. 11C the emission signal Emi_PAM(n) and Sweep(n) can be generated.

[0261] FIG. 12A to FIG. 12C is a diagram of an embodiment in which a sweep signal is generated using an emission driver.

[0262] FIG. 12A is a circuit diagram of a sweep / emission driver 900 according to another embodiment. As FIG. 12A shown, the sweep / emission driver 900 can generate the emission signal Emi_PWM(n), and the sweep / emission driver 900 can generate the emission signal Sweep(n) (i.e., a sweep signal).

[0263] The sweep / emission driver 900 can include an emission driver 91 and a sweep driver 92. As FIG. 12A shown, the emission driver 91 and the sweep driver 92 can be configured as one circuit.

[0264] The emission driver 91 has the same circuit configuration as the emission driver 91 shown in FIG. 9A , and can output the output signal Emi_PWM(n) through the first output terminal 7.

[0265] The sweep driver 92 can include two transistors M11 and M12 connected in series, and one capacitor C4, and can output the emission signal Sweep(n) at the second output terminal 8, which is a node at which the two transistors M11 and M12 connected in series are connected to each other.

[0266] The gate terminal of the transistor M11 can be connected to the first output terminal 7 of the emission driver 91, the source terminal of the transistor M11 can receive an input sweep signal Sweep PN having a form in which a sweep signal sweeping between two different voltages is continuously repeated, and the drain terminal of the transistor M11 is connected to the transistor M12. As FIG. 12B and FIG. 12CAs shown, the input sweep signal (Sweep PN) is one of a plurality of input sweep signals (Sweep P1, Sweep P2, Sweep P3) having different phases.

[0267] FIG. 12B The connection relationship between the sweep / emission drivers according to the embodiment is shown. FIG. 12B The connection relationship of the sweep / emission drivers shown is similar to FIG. 9B The connection relationship of the emission drivers shown. However, FIG. 12B The sweep / emission drivers of FIG. 1 can additionally output an emission signal Sweep(n) by receiving an input sweep signal (Sweep P1 to Sweep P3).

[0268] Referring to FIG. 2, FIG. 12B The output signal Emi_PWM(1) of the sweep / emission driver 900-1 of the first line can be input to the sweep / emission driver 900-2 of the second line as an enable signal of the sweep / emission driver 900-2, and this is the same for the sweep / emission drivers 900-n of the nth line. The sweep / emission driver 900-1 of the first line can receive a separate enable signal Vst.

[0269] Referring to FIG. 3, FIG. 12B The clock signals CLK and CLKB are input to the sweep / emission drivers 900-1 to 900-n for each line in the opposite direction to the previous line. For example, the CLK signal can be input to the CLK input terminal of the sweep / emission driver 900-1, and the CLKB signal can be input to the CLKB input terminal of the sweep / emission driver 900-1. However, the CLKB signal can be input to the CLK input terminal of the sweep / emission driver 900-2 of the next line, and the CLK signal can be input to the CLKB input terminal of the sweep / emission driver 900-2. This is the same for the sweep / emission drivers 900-n of the nth line.

[0270] Three input sweep signals (Sweep P1, Sweep P2, and Sweep P3) having different phases can be sequentially and alternately applied to the sweep / emission drivers 900-1 to 900-n along the lines.

[0271] Referring to FIG. 4, FIG. 12B, the input sweep signal Sweep P1 is applied to the sweep / emission driver 900-1 of the first row line, the input sweep signal Sweep P2 and the input sweep signal Sweep P3 are applied to the sweep / emission drivers 900-2 and 900-3 of the second and third row lines, respectively, and the input sweep signal Sweep P1 is applied again to the sweep / emission driver 900-4 of the fourth row line. Although not shown in the drawing, the input sweep signals are applied to the remaining sweep / emission drivers in the same manner.

[0272] Therefore, the sweep / emission drivers 900-1 to 900-n of each row line can output the emission signal Emi_PWM(n) and the emission signal Sweep(n) of the corresponding line.

[0273] FIG. 12C is a timing chart of various signals for driving the sweep / emission driver according to an embodiment.

[0274] As FIG. 12C indicated, the three input sweep signals (Sweep P1, Sweep P2, and Sweep P3) can have different phases.

[0275] Each input sweep signal can have a form in which the emission signal sweep(n) (i.e., the sweep signal) output from the sweep / emission driver is continuously repeated.

[0276] For example, the input sweep signal Sweep P2 input to the sweep / emission driver 900-n of the nth row line can have a form in which the emission signal sweep(n) output from the sweep / emission driver 900-n is continuously repeated, and the input sweep signal Sweep P1 input to the sweep / emission driver (not shown) of the (n-1)th row line can have a form in which the emission signal Sweep(n-1) output from the sweep / emission driver (not shown) of the (n-1)th row line is continuously repeated.

[0277] This is because the emission signal Sweep(n) is a signal that is selectively output from the input sweep signal.

[0278] Referring to FIG. 12A and FIG. 12B , the emission driver 91 of the sweep / emission driver 900-n can receive the emission signal Emi_PWM(n-1) output from the sweep / emission driver (not shown) of the previous row line, as well as the clock signals CLK and CLKB, and can output the emission signal Emi_PWM(n) through the first output terminal 7.

[0279] The sweep driver 92 includes a transistor M11, the gate terminal of which is connected to the first output terminal 7. The sweep driver 92 receives the input sweep signal Sweep P2 through the source terminal of the transistor M11, and the drain terminal of the transistor M11 becomes the second output terminal 8.

[0280] While outputting the transmit signal EMI_PWM(n) from the transmit driver, the sweep driver 92 can select the transmit signal sweep(n) from the input sweep signal sweep P2 and output the signal through the second output terminal 8.

[0281] pass FIG. 12A Circuit configuration, FIG. 12B The connection relationships between sweep / transmit drivers 900-1 to 900-n are shown, and FIG. 12C The timing diagram shown allows those skilled in the art to easily understand the more specific operation of the sweep / emit driver 900, therefore further description will be omitted.

[0282] The sweep / transmit driver 900 has already been described, generating transmit signals Emi_PWM(n) and sweep(n), but by applying and FIG. 12A to FIG. 12C The same circuitry and driving method described can generate the transmit signals Emi_PAM(n) and Sweep(n).

[0283] By combination FIG. 8A to FIG. 12C Various circuits can be used to implement gate drivers 200-1 or 200-2...

[0284] Various implementations of the driving method for the display panel 100, such as FIG. 3B As shown, and will refer to FIG. 13 to FIG. 16B To describe FIG. 3B .

[0285] FIG. 13 This is a detailed circuit diagram of a sub-pixel circuit according to another embodiment. FIG. 13 The sub-pixel circuit 110 shown can be configured as follows FIG. 3B or FIG. 3C The subpixels of the display panel 100 are driven by the driving method described in the document.

[0286] FIG. 13 The “partial” shown illustrates the display panel 100 as will be described below. FIG. 14A and FIG. 14B The driving scenario shown is as follows, that is... FIG. 13 The "partial" view shown illustrates the case where the corresponding signals are applied to the sub-pixel circuit 110 in row-line order. Meanwhile, FIG. 13 The “Global” view shown indicates the display panel 100 as will be described below.FIG. 15A and FIG. 15B driven as illustrated in FIG. 1A, i.e., FIG. 13 "global" illustrated in FIG. 1B shows a case where a corresponding signal is applied to all of the sub-pixel circuits 110 included in the display panel 100.

[0287] FIG. 14A illustrated in FIG. 1A is driven in the same manner as FIG. 3B illustrated in FIG. 1B. In each frame of FIG. 14A , the vertical axis represents a row line, and the horizontal axis represents time.

[0288] Referring to FIG. 14A , the VST scan represents driving of a control signal for an initialization operation of the sub-pixel circuit 110, the PWM scan represents driving of a control signal for setting a PWM data voltage, the PAM scan refers to driving of a control signal for setting a constant current generator voltage, and the emission scan refers to driving of a control signal for controlling a light emitting operation of the inorganic light emitting element 120 based on the set PWM data voltage and the constant current generator voltage.

[0289] Referring to FIG. 14A , "scan" indicated in each control signal can mean that the control signals are sequentially applied in row line order.

[0290] Referring to FIG. 14A , the driver 200 can apply data voltages (the PWM data voltage and the constant current generator voltage) to the sub-pixels included in each row line of the display panel 100 in row line order, and can drive the display panel 100 such that the sub-pixels included in each row line of the display panel 100 emit light in row line order based on the applied data voltages.

[0291] The driver 200 can drive the display panel 100 such that a data voltage setting operation for the entire row line is performed during the entire time of the image frame period. In this example, since the light emitting operation of the inorganic light emitting element 120 can be performed after the data voltage is set, as FIG. 14A illustrated, the light emitting operation of some row lines can be performed in the next image frame period.

[0292] FIG. 14B is a timing chart of various control signals for driving the sub-pixel circuit 110 illustrated in FIG. 1A in the same manner as FIG. 14A FIG. 13 According to an embodiment, the driver 200 can drive the sub-pixel circuit 110 included in each row line by driving as illustrated, and can drive the display panel 100 as

[0293] illustrated. FIG. 14B FIG. 14A FIG. 13 ​​The sub-pixel circuit 110 shown.

[0294] refer to FIG. 16A The PWM sweep signal indicates that the input to the signal to be swept is... FIG. 13 The input sweep signal of the gate driver described herein, not the input to the gate driver. FIG. 16A The Sweep_Scan(n) signal of the sub-pixel circuit 110 shown below. FIG. 16B and FIG. 15A Describe the Sweep_Scan(n) signal.

[0295] FIG. 3C It shows the time interval between two image frames with FIG. 15A The display panel 100 is driven in the same way as in [the previous method]. FIG. 15A In each frame, the vertical axis represents the line and the horizontal axis represents time.

[0296] refer to FIG. 14A ,and FIG. 15A The driving method shown is different; the control signals VST and PAM are not applied to the display panel 100 sequentially in row-line order, but simultaneously. Therefore, there is no description of "scanning".

[0297] according to FIG. 14A The driving method shown performs initialization and constant current generator voltage setting operations simultaneously at the entire sub-pixel circuit of the display panel 100.

[0298] Similar to FIG. 15A As shown, the PWM data voltage setting operation and the illumination operation can be executed sequentially in row line order. (Reference) FIG. 15A As shown in the example, driver 200 can apply PWM data voltage to the sub-pixels included in each row line of display panel 100, and can drive display panel 100 such that the sub-pixels included in each row line of display panel 100 emit light in row line order based on the applied data voltage.

[0299] Driver 200 can drive display panel 100, enabling data voltage setting and illumination operations for the entire row line to be completed within an image frame time. In this example, such as FIG. 15B As shown, the entire row line illumination operation can be completed within the corresponding image frame time.

[0300] FIG. 15A It is used for FIG. 13 Drive in the manner shown FIG. 15B The timing diagram of various control signals of the sub-pixel circuit 110 is shown.

[0301] refer to FIG. 14B ,andFIG. 15B Differently, the VST signal and the CCG Scan signal are input globally. The driver 200 can drive the sub-pixel circuit 110 included in each row line by FIG. 15A as shown. FIG. 13 as shown. FIG. 15B as shown.

[0302] FIG. 16A The PWM Sweep signal shown represents a sweep signal input to the gate driver described in FIG. 13 , not the Sweep_Scan(n) signal input to the sub-pixel circuit 110 shown. FIG. 16A

[0303] FIG. 16A is a circuit diagram of a gate driver according to an embodiment.

[0304] According to an embodiment, as shown in FIG. 16A , the gate driver 1300 of the scan signal SPWM(n), the emission signal EM(n), and the emission signal Sweep(n) in the output gate signal can be implemented using one Q(n) node 31 and two QB(n) nodes 32 and 33.

[0305] In order to output the scan signal SPWM(n) and the emission signal EM(n) respectively, the clock signals CLK, CLKB, and EM CLK are applied to the gate driver 1300.

[0306] FIG. 13 The scan signal SPWM(n) of the gate driver 1300 can correspond to any one of the VST(n), the CCG_Scan(n), or the PWM_Scan(n) described in FIG. 16A . In addition, FIG. 13 The emission signal EM(n) of the gate driver 1300 can correspond to the Emi_Scan(n) shown in ​ , and Figure 16A The emission signal Sweep(n) of the gate driver 1300 can correspond to the Sweep_Scan(n) described in Figure 13 .

[0307] As shown in Figure 16A , the gate driver 1300 includes a transistor T10, the node 35 outputting the emission signal EM(n) is connected to the gate terminal of the transistor T10, and the gate driver 1300 receives the input sweep signal PWM Sweep through the source terminal of the transistor T10.

[0308] ​The gate driver 1300 can select the emission signal Sweep(n) from the input sweep signal PWM Sweep while outputting the emission signal Emi_Scan(n), and can output through the drain terminal of the transistor T10.

[0309] Figure 16B The timing relationship between the input sweep signal PWM Sweep, the emission signal Emi_Scan(n), and the emission signal Sweep_Scan(n) is shown.

[0310] Referring to Figure 16B As described above, the emission signal Sweep_Scan(n) is selected from the input sweep signal PWM Sweep while the emission signal Emi_Scan(n) is output.

[0311] The Sweep_Scan(1) signal is selected and output from the input sweep signal PWM Sweep during the output of the Emi_Scan(1) signal, the Sweep_Scan(2) signal is selected and output from the input sweep signal PWM Sweep during the output of the Emi_Scan(2) signal, and the Sweep_Scan(3) signal is selected and output from the input sweep signal PWM Sweep during the output of the Emi_Scan(3) signal.

[0312] Referring to Figure 16B Unlike the emission signal Sweep(n) described with reference to Figures 6A to 12C A plurality of consecutive sweep signals are included in the emission signal Sweep_Scan(n), unlike the emission signal Sweep(n) described with reference to

[0313] According to an embodiment, the gate driver 1300 can apply a plurality of consecutive sweep signals to the sub-pixels included in one row line in one light emission period of the one row line.

[0314] Figure 17A FIG. 1 is a cross-sectional view of a display module according to an embodiment. Referring to Figure 17A , for convenience, one pixel included in the display module 300 is shown.

[0315] Referring to Figure 17A , the display module 300 includes a glass substrate 80, a thin film transistor (TFT) layer 70, and inorganic light emitting elements R, G, and B (120-R, 120-G, and 120-B). The sub-pixel circuit 110 described above can be implemented as a TFT, and can be included in the TFT layer 70 on the glass substrate 80.

[0316] Each of the inorganic light emitting elements R, G, and B (120-R, 120-G, and 120-B) can be mounted on the TFT layer 70 to be electrically connected to the corresponding sub-pixel circuit 110 to configure the above-described sub-pixel.

[0317] Although not shown, in the TFT layer 70, there is a sub-pixel circuit 110 that supplies a driving current to each of the inorganic light emitting elements (120-R, 120-G, 120-B), and each of the inorganic light emitting elements (120-R, 120-G, 120-B) can be mounted or placed on the TFT layer 70 to be electrically connected to the corresponding sub-pixel circuit 110, respectively.

[0318] Referring to Figure 17A , the inorganic light emitting elements R, G, and B (120-R, 120-G, 120-B) are micro-LEDs in a flip-chip type. Embodiments are not limited thereto, and according to embodiments, the inorganic light emitting elements R, G, and B (120-R, 120-G, 120-B) can be micro-LEDs of a lateral type or a vertical type.

[0319] Figure 17B is a cross-sectional view of a display module according to another embodiment of the disclosure.

[0320] Referring to Figure 17B , the display module 300 can include a TFT layer 70 formed on one surface of a glass substrate 80, inorganic light emitting elements R, G, and B (120-R, 120-G, 120-b) mounted on the TFT layer 70, a driver 200, and a connection line 90 formed on the TFT layer 70 to electrically connect the sub-pixel circuit 110 and the driver 200.

[0321] As described above in Figure 4 , according to embodiments, at least some of the various circuits of the driver 200 can be implemented in a separate chip form to be disposed on the rear surface of the glass substrate 80, and can be connected to the sub-pixel circuit 110 formed on the TFT layer 70 through the connection line 90.

[0322] Referring to Figure 17B , the sub-pixel circuit 110 included in the TFT layer 70 can be electrically connected to the driver 200 through the connection line 90 formed on the edge (or side surface) of the TFT panel (hereinafter, the combination of the TFT layer 70 and the glass substrate 80 is referred to as a TFT panel).

[0323] The reason that the connection line 90 is formed in the edge area of the display panel 100 to connect the sub-pixel circuit 110 included in the TFT layer 70 and the driver 200 is that, when the sub-pixel circuit 110 and the driver 200 are connected by forming a hole that penetrates the glass substrate 80, there can be a problem such as a crack in the glass substrate 80 due to a temperature difference between a manufacturing process of the TFT panel 70, 80 and a process of filling the hole with a conductive material.

[0324] As described above in Figure 4 , according to another embodiment, at least some of the various circuits of the driver 200 can be formed in the TFT layer having the sub-pixel circuit, and can be connected to the sub-pixel circuit, in which the sub-pixel circuit is formed in the TFT layer in the display panel 100. Figure 17C This embodiment is illustrated.

[0325] Figure 17C is a plan view of the TFT layer 70 according to the embodiment. Referring to Figure 17C , there is a remaining area 11 in addition to an area occupied by one pixel in the TFT layer 70 (in which area, there is a sub-pixel circuit 110 corresponding to each of the R, G, B sub-pixels included in the pixel 10).

[0326] In the TFT layer 70, there is the remaining area 11, and thus some of the various circuits of the driver 200 described above can be formed on the remaining area 11.

[0327] Figure 17C An example in which the gate driver 200-1, 200-2,..., or 1300 is implemented in the remaining area 11 of the TFT layer 70 is illustrated. Thus, the structure in which the gate driver 200-1, 200-2,..., or 1300 is formed inside the TFT layer 70 can be referred to as a gate-in-panel (GIP) structure, but the name is not limited thereto.

[0328] Figure 17C This is only one example, and the circuit that can be included in the remaining area 11 of the TFT layer 70 is not limited to the gate driver 200-1, 200-2,..., 1300. According to the embodiment, the TFT layer 70 can further include a multiplexer (MUX) circuit for selecting R, G, and B sub-pixels, an electrostatic discharge (ESD) protection circuit for protecting the sub-pixel circuit 110 from static electricity, and a sweep voltage providing circuit, etc.

[0329] Figure 18 is a configuration diagram of a display apparatus 1000 according to the embodiment.

[0330] Referring to Figure 18The display device 1000 includes a display panel 100, a driver 200, and a processor 902.

[0331] The display panel 100 includes a plurality of pixels each including a plurality of sub-pixels.

[0332] The display panel 100 can be formed in a matrix shape such that gate lines (G1 to Gx) and data lines (D1 to Dy) intersect each other, and each pixel can be formed in an area provided by the intersection.

[0333] As described above, each pixel can include three sub-pixels (e.g., R, G, and B), and each sub-pixel included in the display panel 100 can include an inorganic light emitting element 120 and a sub-pixel circuit 110 of a corresponding color.

[0334] The data lines (D1 to Dy) are lines for applying data voltages (especially, PWM data voltages) to each sub-pixel included in the display panel 100, and the gate lines (G1 to Gx) are lines for selecting pixels (or sub-pixels) included in the display panel 100 by lines. The data voltages applied through the data lines (D1 to Dy) can be applied to the pixels (or sub-pixels) of the selected row line by gate signals.

[0335] According to an embodiment, a data voltage to be applied to a pixel associated with each data line (D1 to Dy) can be applied to each data line (D1 to Dy). Since a single pixel includes a plurality of sub-pixels (e.g., R, G, B sub-pixels), data voltages (i.e., R data voltage, G data voltage, and B data voltage) to be applied to each of the R, G, B sub-pixels included in a single pixel can be time-divisioned and applied to each sub-pixel through one data line. The data voltages time-divisioned and applied through a single data line as described above can be applied to each sub-pixel through a MUX circuit.

[0336] According to an embodiment, a separate data line can be provided for each R, G, and B sub-pixel. In this example, R data voltages, G data voltages, and B data voltages need not be time-divisioned and applied, and a corresponding data voltage can be simultaneously applied to a corresponding sub-pixel through each data line.

[0337] Referring to Figure 18 For convenience of explanation, only one set of gate lines (e.g., G1 to Gx) is illustrated. However, the number of actual gate lines can vary according to a driving method of the sub-pixel circuit 110 included in the display panel 100.

[0338] The driver 200 can drive the display panel 100 according to the control of the processor 902, and can include a timing controller 210, a data driver 220, and gate drivers 200-1, 200-2... 1300, etc.

[0339] The timing controller 210 can receive an input signal (IS), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), a main clock signal (MCLK), etc. from the outside, generate an image data signal, a scan control signal, a data control signal, a light emission control signal, etc., and provide the same to the display panel 100, the data driver 220, the gate drivers 200-1, 200-2,..., or 1300, etc.

[0340] The timing controller 210 can be a control signal for selecting R, G, B sub-pixels, respectively, that is, a MUX signal for a MUX circuit (not shown). A plurality of sub-pixels included in a pixel of the display panel 100 can be selected by the MUX circuit (not shown), respectively.

[0341] The data driver 220 (or source driver) is a device that generates a data signal (particularly, a PWM data voltage), and can generate the data signal by forwarding image data of R / G / B components from the processor 902, etc. The data driver 220 can apply the generated data signal to each sub-pixel circuit 110 of the display panel 100 through a data line (D1 to Dy).

[0342] The gate drivers 200-1, 200-2,..., or 1300 can generate various gate signals (e.g., VST, SP, Emi_PWM, Emi_PAM, Sweep, SET, etc.) for selecting and driving pixels arranged in a row line unit in a matrix form, and can apply the generated gate signals to the display panel 100 through a gate line (G1 to Gx). According to an embodiment, the gate drivers 200-1, 200-2,..., or 1300 can sequentially apply the generated gate signals in a row line order.

[0343] Although not shown in the drawings, the driver 200 can further include a driving voltage providing circuit for providing various driving voltages (e.g., a first driving voltage (VDD_PAM), a second driving voltage (VDD_PWM), a ground voltage (VSS), a reset voltage (Vset), a test voltage (TEST), a constant current generator voltage (VPAM_R / G / B), etc.) to the sub-pixel circuit 110 included in the display panel 100, a clock signal providing circuit for providing a clock signal to the gate drivers 200-1, 200-2,..., or 1300 or the data driver 220, a MUX circuit, a sweep voltage providing circuit, an EST protection circuit, etc.

[0344] The processor 902 controls the overall operation of the display apparatus 1000. The processor 902 can drive the display panel 100 by controlling the driver 200.

[0345] The processor 902 can be implemented with at least one of a central processing unit (CPU), a microcontroller, an application processor (AP), a communication processor (CP), or an advanced reduced-instruction set computing (RISC) machine (ARM) processor.

[0346] Referring to Figure 18 The processor 902 and the timing controller 210 are described as separate components. However, according to an embodiment, only one of the components is included in the display device 1000, and an embodiment in which the included component performs the functions of the remaining components is possible.

[0347] According to various embodiments, it is possible to prevent the wavelength of light emitted by the inorganic light emitting element from varying according to a gray scale.

[0348] It is possible to easily correct a stain or color that can occur on an image displayed on the display panel due to a deviation between the sub-pixel circuits. Even when a large-size display panel is formed by combining display panel modules, it is possible to correct a difference in brightness or color between each display panel module.

[0349] It is possible to design a more optimized driving circuit, and it is possible to stably and efficiently drive the inorganic light emitting element. In particular, it is possible to reduce power consumption in the display panel. Also, it is possible to miniaturize and lighten the display panel.

[0350] For example, the sub-pixel circuit 110 is implemented as a P-type TFT, but the above-described embodiments can also be applied to an N-type TFT.

[0351] According to various embodiments, the TFTs forming the TFT layer (or TFT panel) are not limited to a specific structure or type. In other words, the TFTs set forth in various examples can be implemented as a low-temperature polysilicon (LTPS) TFT, an oxide TFT, a polysilicon or amorphous silicon TFT, an organic TFT, and a graphene TFT, etc., and can be applied to a P-type (or N-type) MOSFET in a Si wafer CMOS process.

[0352] It has been described that the sub-pixel circuit 110 is implemented in the TFT layer 70, but embodiments are not limited thereto. According to another embodiment, when the sub-pixel circuit 110 is implemented, a pixel circuit chip can be implemented in the form of a super-small microchip, and the chip can be mounted on the substrate 80 in the form of a sub-pixel unit or a pixel unit. The position where the sub-pixel chip is placed can be, for example, around the corresponding inorganic light emitting element 120, but is not limited thereto.

[0353] According to yet another embodiment, a driving circuit for driving micro-LEDs (e.g., various circuits of the sub-pixel circuit 110 and the driver 200 described above) can be arranged in a pixel area, and can be implemented by a micro-IC for controlling driving of at least 2n pixels. In this example, in a TFT layer (or backplane), only a channel layer connecting the micro-IC and each micro-LED (rather than a TFT device) can be formed.

[0354] The above description is merely illustrative of the technical concept of the present disclosure. It will be obvious to those ordinary skilled in the art that various modifications and changes can be made thereto without departing from the basic characteristics of the present disclosure. Furthermore, the embodiments according to the present disclosure are not intended to limit the technical spirit of the present disclosure, nor are they intended to limit the scope of the present disclosure to the technical personnel. Therefore, the scope of the present disclosure should be interpreted by the appended claims, and all technical concepts within the scope of the present disclosure should be interpreted as included in the scope of the present disclosure.

Claims

1. A display module, comprising: a display panel in which a plurality of pixels each including a plurality of sub-pixels are arranged on a plurality of row lines; and a driver configured to: set pulse width modulation (PWM) data voltages to the plurality of sub-pixels included in the plurality of row lines in a row line order; apply a sweep signal to sub-pixels included in at least some consecutive row lines among the plurality of row lines in the row line order, the sweep signal being a voltage signal swept between two different voltages; and drive the display panel such that the sub-pixels included in the at least some consecutive row lines emit light in the row line order based on the PWM data voltages, wherein one image frame period includes a data setting period and a plurality of light emission periods, and wherein, during the one image frame period, the driver is further configured to: apply a plurality of first control signals to sub-pixels included in one row line among the plurality of row lines and set the PWM data voltages to the sub-pixels included in the one row line during a data setting period of the one row line; select a sweep signal to be applied to the sub-pixels included in the one row line from among input signals including the sweep signal, the sweep signal being continuously repeated based on one second control signal among a plurality of second control signals, and apply the plurality of second control signals and the selected sweep signal to the sub-pixels included in the one row line such that the sub-pixels included in the one row line emit light a plurality of times during the one image frame period with a preset time interval between each of the plurality of light emission periods; and drive the display panel such that the sub-pixels included in the one row line emit light during a time corresponding to the PWM data voltages. The driver is further configured to apply the plurality of second control signals and the sweep signal to the sub-pixels included in the one row line in each of a plurality of light emission periods of the one row line, 2. The display module of claim 1, wherein, wherein a first light emission period among the plurality of light emission periods is continuous in time with the data setting period. The driver is further configured to apply a plurality of consecutive sweep signals to the sub-pixels included in the one row line in one light emission period of the one row line, and 3. The display module of claim 1, wherein, wherein the data setting period is continuous in time with the one light emission period. The driver includes:

4. The display module of claim 1, wherein, a first driver circuit configured to generate at least one first control signal among the plurality of first control signals; and a second driver circuit configured to generate the sweep signal and at least one second control signal among the plurality of second control signals. The second driver circuit includes:

5. The display module of claim 4, wherein, a first circuit to generate one second control signal among the at least one second control signal among the plurality of second control signals; and ​ A second circuit connected to the first circuit is configured to generate the sweep signal based on the one second control signal generated in the first circuit.

6. The display module of claim 5, wherein, The first circuit includes a first output terminal for outputting the one second control signal to the sub-pixel included in the one row line, The second circuit includes a transistor, and a gate terminal of the transistor is connected to the first output terminal, The transistor is configured to select and output the sweep signal from the input signal based on the one second control signal input through the gate terminal.

7. The display module of claim 6, wherein, The first driver circuit and the second driver circuit are provided for each of the plurality of row lines, Each second driver circuit includes a corresponding second circuit, and The input signals input to the corresponding second circuits of the second driver circuits corresponding to two consecutive row lines among the plurality of row lines are the same signals different in phase from each other.

8. The display module of claim 1, wherein, Each of the plurality of sub-pixels includes: An inorganic light emitting element; and A sub-pixel circuit configured to control a light emitting time of the inorganic light emitting element according to driving of the driver, The sub-pixel circuit includes: A constant current generator circuit configured to supply a constant current to the inorganic light emitting element during the light emitting period; and A PWM circuit for controlling an amount of time for which the constant current flows in the inorganic light emitting element based on the PWM data voltage and the sweep signal.

9. The display module of claim 8, wherein, The constant current generator circuit includes a first drive transistor, and is further configured to supply the constant current to the inorganic light emitting element while the first drive transistor is turned on in the light emitting period, and The PWM circuit includes a second drive transistor, and is further configured to: set the PWM data voltage to a gate terminal of the second drive transistor according to the plurality of first control signals, and turn off the first drive transistor based on the second drive transistor being turned on due to a change in voltage of the gate terminal of the second drive transistor caused by the sweep signal.

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