A method for rapid formulation of ADI based on free-form light sources

Abstract

The present invention provides a method for quickly formulating ADI based on a free-form light source, taking a light source file, wherein each sampling point records a light intensity value within a circle with a radius of 1, and each sampling point records its x coordinate, y coordinate and light intensity; decomposing the light intensity of each sampling point to obtain the first light intensity in the X direction and the second light intensity in the Y direction; then calculating the light intensity ratio of the first total light intensity to the second total light intensity; providing a layout, obtaining the first design value in the X direction and the second design value in the Y direction of the connecting hole in the layout, taking the sum of the deviation value after etching the connecting hole and the first design value as the first ADI value in the X direction, and taking the ratio of the first ADI value to the light intensity ratio as the second ADI value in the Y direction. The invention can reduce the number of ADI target value setting iterations for setting the ADI value and adding the average standard deviation to the original chip design layout, reduce the OPC debugging time, and speed up publication.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for quickly formulating ADI based on a free-form light source. Background Art

[0002] In the manufacturing of semiconductor chips at advanced nodes, OPC (optical proximity correction) will offset the designed chip layout according to the graphic target ADI (after development inspection) value when correcting the mask, thereby increasing the layout's lithography process window and reducing wafer defects.

[0003] At present, the initial value of the target ADI value of the layout is generally set based on the lithography process and existing experience, and multiple rounds of adjustments are made based on the results after running OPC. For traditional light sources, it is easy to set the appropriate ADI initial value based on sufficient experience, but for advanced node processes such as those below the 14nm node, the light source is a free-form light source generated by SMO (source mask collaborative optimization technology), and there is no experience to set the appropriate initial ADI value. This may require multiple rounds of adjustments to obtain the appropriate ADI value.

[0004] Therefore, a new ADI formulation method is needed to reduce the number of times the ADI value is adjusted, reduce the workload, speed up the publication of the mask, and gain more time for subsequent chip manufacturing processes. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, an object of the present invention is to provide a method for quickly formulating ADI based on a free-form light source, so as to solve the problem in the prior art that for advanced node processes such as below the 14nm node, the light source is a free-form light source generated by the light source mask collaborative optimization technology, and there is no experience in setting a suitable initial ADI value, which may require multiple rounds of adjustments to obtain a suitable ADI value.

[0006] To achieve the above objectives and other related objectives, the present invention provides a method for quickly formulating ADI based on a free-form light source, comprising:

[0007] Step 1, obtain a light source file, the light source file is a sampling point within a circle with a radius of 1, each of the sampling points records a light intensity value, which is used to form a light source readable by a lithography machine, and each of the sampling points records its x coordinate, y coordinate and light intensity;

[0008] Step 2: Decomposing the light intensity of each sampling point to obtain a first light intensity in the X direction and a second light intensity in the Y direction;

[0009] Step 3, summing up the first light intensity and the second light intensity at all the sampling points to obtain a first total light intensity and a second total light intensity, and then calculating a light intensity ratio of the first total light intensity to the second total light intensity;

[0010] Step 4: Provide a layout, obtain a first design value of the length of the connection hole in the X direction and a second design value of the length in the Y direction in the layout, use the sum of the deviation value of the connection hole after etching and the first design value as the first ADI value in the X direction, and use the ratio of the first ADI value to the light intensity ratio as the second ADI value in the Y direction.

[0011] Preferably, the method further comprises step five, setting the ADI value and adding the average standard deviation to the original chip design layout with the first ADI value and the second ADI value, and then running OPC to verify the wafer.

[0012] Preferably, the method further comprises step six, keeping the first ADI value unchanged, changing the second ADI value, and obtaining a lithography window under each of the second ADI values.

[0013] Preferably, the layout in step 4 includes hole-shaped graphics and strip-shaped graphics.

[0014] Preferably, the layout in step 4 includes a first layer, a second layer and a third layer for connecting the two.

[0015] Preferably, the third layer includes a plurality of the connecting holes.

[0016] Preferably, the length and width of the connecting hole in step 4 are both no greater than 50 nanometers.

[0017] Preferably, the light intensity ratio in step three is 0.871.

[0018] Preferably, the first design value in step 4 is 40 nanometers, the second design value is 50 nanometers, the first ADI value obtained by the sum of the deviation value and the first design value is 65 nanometers, and the second ADI value obtained by the ratio of the first ADI value to the light intensity ratio is 75 nanometers.

[0019] As described above, the method for quickly formulating ADI based on a free-form light source of the present invention has the following beneficial effects:

[0020] At the beginning of layout preparation, under the condition of existing light source, by substituting the light intensity ratio in the XY direction into the ADI target value setting, the number of ADI target value setting iterations for setting the ADI value and adding the average standard deviation to the original chip design layout can be reduced, the OPC debugging time can be reduced, and the publication can be accelerated. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic diagram of a light source file of the prior art;

[0022] Figure 2 A schematic diagram of a layout of the prior art is shown;

[0023] Figure 3 Shown is a schematic diagram of a connection hole bridge in the prior art;

[0024] Figure 4 Shown is a schematic diagram of a photolithography window of the present invention;

[0025] Figure 5 Shown is a schematic diagram of the photolithography window verification of the present invention;

[0026] Figure 6 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figure 6 The present invention provides a method for quickly formulating ADI based on a free-form light source, comprising:

[0029] Step 1, obtain the light source file. The light source file is a circle with a radius of 1. Each sampling point records a light intensity value, which is used to form a light source readable by the lithography machine. Each sampling point records its x coordinate, y coordinate and light intensity;

[0030] In an alternative embodiment, Figure 1 is the light source of the 14nm node. The light source value is (x, y, I), x and y are coordinates, and I is the light intensity at this location. The decomposition method for the light source in the x and Y directions is as follows:

[0031] 1. Assume that the light source value of the i-th sampling point is (xi,yi,Ii).

[0032] 2. The light intensity decomposition value in the X direction is Iix=Ii*xi / (xi2+yi2)1 / 2

[0033] 3. The light intensity decomposition value in the Y direction is Iiy=Ii*yi / (xi2+yi2)1 / 2

[0034] Step 2: A script may be used in a loop to decompose the light intensity at each sampling point to obtain a first light intensity in the X direction and a second light intensity in the Y direction;

[0035] Step 3, summing up all the first light intensities and all the second light intensities to obtain a first total light intensity and a second total light intensity, and then calculating the light intensity ratio of the first total light intensity to the second total light intensity, that is, the ratio of the light intensity in the X direction of the light source to the light intensity in the Y direction of the light source;

[0036] Step 4: Provide a layout. Usually, the layout design shape of the connection hole is a rectangle. Obtain the first design value of the length of the connection hole in the X direction and the second design value of the length in the Y direction in the layout. Use the sum of the deviation value after etching the connection hole and the first design value as the first ADI value in the X direction, and use the ratio of the first ADI value to the light intensity ratio as the second ADI value in the Y direction.

[0037] In an optional embodiment, the layout in step four includes hole-shaped graphics and strip-shaped graphics.

[0038] In an optional implementation, the layout in step 4 includes a first layer, a second layer, and a third layer for connecting the two.

[0039] In an alternative embodiment, see Figure 2 In the SRAM691 layout, the M0P layer is used to connect the PO and V0 layers. The layout type is relatively complex, so the light source obtained through SMO optimization is a free form. For this type of non-traditional light source, there is no unified experience in setting the ADI target value of the layout. Normally, the value after adding the etching deviation is set as the ADI value. Among the SRAM691 layout, the most difficult thing is that the size of the two holes of M0P S1 is only 50 nanometers, and it cannot be increased, so there is a great risk of bridging here (such as Figure 3 ), so the PVB of these two opposite sides needs to be considered when setting the ADI value.

[0040] See also Figure 4 PVB is the difference between the maximum value and the minimum value of the critical dimension under the optimal lithography conditions. The smaller the PVB value, the larger the lithography window.

[0041] In an optional embodiment, the third layer includes a plurality of connection holes.

[0042] In an optional embodiment, the length and width of the connection hole in step four are no greater than 50 nanometers.

[0043] In an optional embodiment, the light intensity ratio in step three is 0.871.

[0044] In an optional embodiment, the first design value in step four is 40 nanometers, the second design value is 50 nanometers, the first ADI value obtained by the sum of the deviation value and the first design value is 65 nanometers, and the second ADI value obtained by the ratio of the first ADI value to the light intensity ratio is 75 nanometers.

[0045] In an optional implementation scheme, the method also includes step five, after reading and correcting the original chip design layout, setting the ADI value and adding the average standard deviation to the original chip design layout with the first ADI value and the second ADI value. The formation of the chip layout pattern is mainly composed of two processes, photolithography and dry etching. In order to meet the photolithography process window, it is necessary to set a reasonable photolithography ADI. After photolithography, dry etching and other processes are used to achieve the final chip design wafer transfer. Then, based on the photolithography process model, the original chip design layout is corrected to generate a chip Mask layout file, and then OPC is run to verify the wafer.

[0046] In an optional embodiment, the method further includes step six, keeping the first ADI value unchanged, changing the second ADI value, and obtaining a lithography window under each second ADI value.

[0047] In an alternative embodiment, see Figure 5 , keeping the first ADI value (critical dimension in the X direction) at 65nm, changing the second ADI value (critical dimension in the Y direction), it is verified that the minimum value of PVB is obtained, at which time the lithography window is the largest.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] In summary, at the beginning of layout making, under the condition of existing light source, by substituting the light intensity ratio in the XY direction into the ADI target value setting, the number of ADI target value setting iterations for setting the ADI value and adding the average standard deviation to the original chip design layout can be reduced, the OPC debugging time can be reduced, and the publication can be accelerated. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for quickly formulating ADI based on a free-form light source, characterized in that: At least: Step 1, obtain a light source file, the light source file is a sampling point within a circle with a radius of 1, each of the sampling points records a light intensity value, which is used to form a light source readable by a lithography machine, and each of the sampling points records its x coordinate, y coordinate and light intensity; Step 2: Decomposing the light intensity of each sampling point to obtain a first light intensity in the X direction and a second light intensity in the Y direction; Step 3, summing up the first light intensity and the second light intensity at all the sampling points to obtain a first total light intensity and a second total light intensity, and then calculating a light intensity ratio of the first total light intensity to the second total light intensity; Step 4: Provide a layout, obtain a first design value of the length of the connection hole in the X direction and a second design value of the length in the Y direction in the layout, use the sum of the deviation value of the connection hole after etching and the first design value as the first ADI value in the X direction, and use the ratio of the first ADI value to the light intensity ratio as the second ADI value in the Y direction.

2. The method for rapidly formulating ADI based on a free-form light source according to claim 1, characterized in that: The method also includes step five, setting the ADI value and adding the average standard deviation to the original chip design layout with the first ADI value and the second ADI value, and then running OPC to verify the wafer.

3. The method for rapidly formulating ADI based on free-form light sources according to claim 1, characterized in that: The method further includes step six, maintaining the first ADI value unchanged, changing the second ADI value, and obtaining a lithography window under each of the second ADI values.

4. The method for rapidly formulating ADI based on free-form light sources according to claim 1, characterized in that: The layout in step 4 includes hole-shaped graphics and strip-shaped graphics.

5. The method for rapidly formulating ADI based on free-form light sources according to claim 1, characterized in that: The layout in step 4 includes a first layer, a second layer, and a third layer for connecting the two.

6. The method for rapidly formulating ADI based on a free-form light source according to claim 5, characterized in that: The third layer includes a plurality of the connection holes.

7. The method for rapidly formulating ADI based on free-form light sources according to claim 6, characterized in that: The length and width of the connection hole in step 4 are both no greater than 50 nanometers.

8. The method for rapidly formulating ADI based on free-form light sources according to claim 7, characterized in that: The light intensity ratio in step three is 0.

871.

9. The method for rapidly formulating ADI based on a free-form light source according to claim 8, characterized in that: The first design value in step 4 is 40 nanometers, the second design value is 50 nanometers, the first ADI value obtained by the sum of the deviation value and the first design value is 65 nanometers, and the second ADI value obtained by the ratio of the first ADI value to the light intensity ratio is 75 nanometers.

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