Data access method and system

Abstract

The present application provides a data access method and system, which are applied to a data access system, wherein the data access system includes a system on chip and a storage medium, wherein the system on chip includes at least two processors and a DMA controller, an arbitrator, and a memory controller for each processor. The method includes: the processor sends a request message, wherein the request message includes an operation type and an address, and the operation type includes a read operation or a write operation. When the request message is for local access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbitrator and memory controller according to the address to complete the processor's local memory access. When the request message is for non-local memory access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbitrator, memory controller, and DMA controller according to the address to complete the processor's non-local memory access. This can shorten data transfer time and improve data access efficiency.

Description

Technical Field

[0001] The present invention relates to the field of data access technology, and in particular to a data access method and system. Background Art

[0002] A system-on-a-chip (SoC) is an integrated circuit chip that includes one or more processor units, may include internal memory (e.g., static random access memory (SRAM)), or may communicate with an external memory device (e.g., dynamic random access memory (DRAM)) whose capacity is greater than that of the internal memory.

[0003] Currently, multiple processors on an SoC access memory via a bus, accessing the dynamic random access memory (DRAM) through a single memory controller. Multiple processor units on the SoC share a large memory pool, resulting in low data transmission efficiency and high latency when multiple processors need to transmit data. Summary of the Invention

[0004] In view of this, it is necessary to provide a data access method and system that can improve data transmission efficiency and reduce latency.

[0005] One embodiment of the present application provides a data access method, which is applied to a data access system. The data access system includes a system on chip and a storage medium. The system on chip and the storage medium communicate via a bus. The system on chip includes at least two processors and a transfer module for each processor. The transfer module includes a DMA controller, an arbitrator, and a memory controller. The data access method includes:

[0006] The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation;

[0007] When the request information is for local access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address to complete the local memory access of the processor; and

[0008] When the request information is for non-local memory access, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller and DMA controller to complete the non-local memory access of the processor.

[0009] According to some embodiments of the present application, when the request information is for local access, the processor performs a read operation or a write operation on the storage medium based on the address through its corresponding arbiter and memory controller to complete the local memory access of the processor, including:

[0010] When the request information is for local access, the operating mode of the processor is a memory control mode, and the processor sends a first control command to the corresponding memory controller, where the first control command is used to instruct the memory controller to obtain the request information;

[0011] The memory controller sends a bus request signal to the arbiter according to the request information, and the arbiter sends the bus use right to the memory controller;

[0012] The memory controller performs a read operation or a write operation on the storage medium according to the address.

[0013] According to some embodiments of the present application, the memory controller performing a read operation or a write operation on the storage medium according to the address includes:

[0014] When performing a read operation, the memory controller reads first data according to the address, and the processor receives the first data sent by the memory controller;

[0015] Alternatively, when performing a write operation, the memory controller writes the second data sent by the processor into the storage medium according to the address.

[0016] According to some embodiments of the present application, when the request information is for non-local memory access, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller, and DMA controller to complete the non-local memory access of the processor, including:

[0017] When the request information is for non-local memory access, the operating mode of the processor is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller, where the second control command is used to instruct the DMA controller to obtain the request information;

[0018] The DMA controller sends a bus request signal to the corresponding arbiter according to the request information, and the arbiter sends the bus use right to the DMA controller;

[0019] The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address.

[0020] According to some embodiments of the present application, the DMA controller performing a read operation or a write operation on the storage medium through the corresponding memory controller according to the address includes:

[0021] The DMA controller sends the address to the memory controller, and the memory controller performs a read operation or a write operation on the storage medium according to the address.

[0022] According to some embodiments of the present application, the DMA controller sends the address to the memory controller, and the memory controller performs a read operation or a write operation on the storage medium according to the address, including:

[0023] When performing a write operation, the DMA controller receives the third data sent by the processor and sends a bus request signal to the arbiter corresponding to the destination address in the address. After obtaining the right to use the bus, the DMA controller sends the third data to the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium;

[0024] Alternatively, when performing a read operation, the DMA controller sends a bus request signal to the corresponding arbitrator based on the source address in the address. After obtaining the right to use the bus, the DMA controller sends the source address to the second memory controller corresponding to the source address. The second memory controller reads the fourth data based on the source address. The DMA controller receives the fourth data, and the processor reads the fourth data through the DMA controller.

[0025] According to some embodiments of the present application, the processor includes one or more of the following: a central processing unit, a graphics processing unit, and a digital signal processor.

[0026] An embodiment of the present application provides a data access system, the data access system including a system on chip and a storage medium, wherein the system on chip and the storage medium communicate with each other via a bus, the system on chip including at least two processors and a respective transport module for each processor, the transport module including a DMA controller, an arbitrator, and a memory controller;

[0027] The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation;

[0028] The processor is configured to, when the request information is for local access, perform a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address to complete local memory access; and, when the request information is for non-local memory access, perform a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller, and DMA controller based on the address to complete non-local memory access.

[0029] According to some embodiments of the present application, the system on chip and the storage medium are connected via wafer stacking.

[0030] According to some embodiments of the present application, the storage medium is a dynamic random access memory.

[0031] The data access method and system provided by the embodiments of the present application perform data access via a memory controller during local access and via a DMA controller during non-local access. Thus, the data access method and system provided by the embodiments of the present application eliminate the need to wait for the bus to become idle, thereby shortening data transfer time and improving data access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a structural diagram of a data access system according to one embodiment of the present application.

[0033] Figure 2 and Figure 3 It is a schematic diagram of the workflow of the transport module according to one embodiment of the present application.

[0034] Figure 4 This is a flow chart of a data access method according to one embodiment of the present application.

[0035] Figure 5 yes Figure 4 Detailed flowchart of step S20.

[0036] Figure 6 yes Figure 4 Detailed flowchart of step S30.

[0037] Description of main component symbols

[0038]

[0039] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0041] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] See also Figure 1 , Figure 1 is a structural diagram of a data access system 100 according to an embodiment of the present application, as shown in FIG. Figure 1 As shown, the data access system 100 includes a system-on-a-chip (SoC) 10 and a storage medium 20. The system-on-chip 10 and the storage medium 20 communicate with each other via a bus, which is an extended peripheral component interconnect express (PCIe) bus.

[0043] In the embodiment of the present application, the data access system 100 solves the problem of insufficient bandwidth when accessing dynamic random access memory by a single memory controller 43, which causes reduced processing efficiency, and can improve the access speed of the processor 30 on the system on chip 10 to the storage medium 20.

[0044] In the embodiment of the present application, a corresponding memory address space is allocated to each processor 30 on the storage medium 20 .

[0045] In the embodiment of the present application, the system-on-chip 10 integrates a complete system on a single chip, including a central processing unit (CPU) 30, memory, and peripheral circuits. The system-on-chip 10 includes at least two processors 30 and a transfer module 40 for each processor 30. The transfer module 40 includes a DMA controller 41, an arbiter 42, and a memory controller 43.

[0046] In the embodiment of the present application, the processor 30 includes a central processing unit, a graphics processing unit or a digital signal processor.

[0047] In the implementation of this application, the storage medium 20 can be a non-volatile memory express (NVMe) solid state disk (SSD), or other types of storage media 20. In one possible implementation, the storage medium 20 is dynamic random access memory (DRAM).

[0048] In an embodiment of the present application, a direct memory access controller (DMA), namely a DMA controller 41, runs in each storage medium 20. The DMA controller 41 is used to directly move the data to be read from the storage medium to the memory corresponding to the processor, such as a double data rate synchronous dynamic random access memory.

[0049] In the embodiment of the present application, the memory controller 43 is an important component of the computer system that controls the memory and is responsible for data exchange between the memory and the central processing unit 30. Data is transmitted from the memory controller 43 to the central processing unit 30.

[0050] In an embodiment of the present application, multiple devices or modules in the system on chip 10 may apply for the right to use the bus at the same time. To avoid bus conflicts, the arbitrator 42 reasonably controls and manages the applicants who need to occupy the bus in the system. When multiple applicants make bus requests at the same time, the processor 30 that obtains the right to use the bus is arbitrated using a certain priority algorithm.

[0051] The processor 30 sends a request message, wherein the request message includes an operation type and an address, and the operation type includes a read operation or a write operation.

[0052] The processor 30 is used to perform a read operation or a write operation on the storage medium 20 based on the address through its corresponding arbitrator 42 and memory controller 43 to complete local memory access when the request information is for local access; and to perform a read operation or a write operation on the storage medium 20 based on the address through its corresponding arbitrator 42, memory controller 43 and DMA controller 41 to complete non-local memory access when the request information is for non-local memory access.

[0053] Please also refer to Figure 2 and Figure 3 , Figure 2 and Figure 31 is a schematic diagram of the workflow of the transfer module 40 according to one embodiment of the present application. When the request information is for local access, based on the address, the processor 30 performs a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42 and memory controller 43 to complete the local memory access of the processor 30. When the request information is for non-local memory access, based on the address, the processor 30 performs a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42, memory controller 43, and DMA controller 41 to complete the non-local memory access of the processor 30.

[0054] like Figure 2 As shown, taking the CPU 30 as an example, CPU 30 30 CPU1 and its corresponding transport module 40 have an arbiter A1, a memory controller B1, and a DMA controller C1. CPU2's transport module 40 has an arbiter A2, a memory controller B2, and a DMA controller C2. CPU 30 CPU3 and its corresponding transport module 40 have an arbiter A3, a memory controller B3, and a DMA controller C3. CPU 30 CPU4 and its corresponding transport module 40 have an arbiter A4, a memory controller B4, and a DMA controller C4. Each CPU has its own corresponding memory space address. When a CPU accesses its own memory space, it is considered a local access. When a CPU accesses the memory space of another CPU, it is considered a non-local access.

[0055] Please also refer to Figure 3 The workflow of the transport module 40 corresponding to each processor 30 is as follows:

[0056] When CPU1 intends to perform local access, it operates in memory controller mode and sends a first control command to memory controller B1, instructing memory controller B1 to obtain the request information. Based on the request information, memory controller B1 sends a bus request signal to arbiter A1. Arbiter A1 then sends bus usage rights to memory controller B1, which then reads or writes to storage medium 20 based on the address in the request information.

[0057] During a read operation, the memory controller B1 reads first data according to the address, and the CPU 1 receives the first data sent by the memory controller B1. During a write operation, the memory controller B1 writes second data sent by the CPU 1 to the storage medium 20 according to the address.

[0058] When CPU1 wants to perform non-local access, when CPU1 wants to transfer data with CPU2, the CPU1 working mode is DMA control mode, CPU1 sends a second control command to its corresponding DMA controller C1, and the second control command is used to instruct the DMA controller C1 to obtain the request information. The DMA controller C1 sends a bus request signal to the corresponding arbitrator A1 according to the request information, and the arbitrator A1 sends the bus usage right to the DMA controller C1. The DMA controller C1 performs a read operation or a write operation on the storage medium 20 through the corresponding memory controller 43 according to the address.

[0059] When performing a write operation, the DMA controller C1 receives the third data sent by the CPU1 and sends a bus request signal to the arbiter A2 corresponding to the destination address in the address. After obtaining the right to use the bus, the DMA controller C1 sends the third data to the first memory controller B2 corresponding to the destination address, so that the first memory controller B2 writes the third data to the storage medium 20 corresponding to the CPU2, that is, the destination address in the address.

[0060] When performing a read operation, the DMA controller C1 sends a bus request signal to the corresponding arbiter A2 according to the source address in the address. After obtaining the right to use the bus, the DMA controller C1 sends the source address to the second memory controller B2 corresponding to the source address. The second memory controller B2 reads the fourth data according to the memory corresponding to the source address, that is, CPU2. The DMA controller C1 receives the fourth data, and the CPU1 reads the fourth data through the DMA controller C1.

[0061] In an embodiment of the present application, when performing local access, each processor 30 uses its corresponding memory controller 43 to directly access the storage medium 20. When performing non-local access, each processor 30 uses its corresponding DMA controller 41 to move data between processors 30, thereby shortening the data transmission time and improving efficiency.

[0062] In one possible implementation, the system on chip 10 and the storage medium 20 are connected via wafer stacking.

[0063] In the embodiment of the present application, the IO signal lines of the system-on-chip (SoC) 10 wafer and the storage medium 20 wafer are connected together through a wafer-on-wafer method, which simplifies the number of IO pins. The IO port of the storage medium 20 does not need to have lead pins, thereby reducing latency and power consumption. In addition, due to the integration of the chip of the SoC 10 and the chip of the storage medium 20, the layout and area of ​​the printed circuit board (PCB) are reduced, thereby reducing the production cost and wiring difficulty of the PCB.

[0064] See also Figure 4 , Figure 4 1 is a flow chart of a data access method according to an embodiment of the present application. The method is applied to a data access system 100, which includes a system on chip 10 and a storage medium 20. The system on chip 10 and the storage medium 20 communicate with each other via a bus. The system on chip 10 includes at least two processors 30 and a transfer module 40 for each processor 30. The transfer module 40 includes a DMA controller 41, an arbitrator 42, and a memory controller 43. Figure 4 As shown, the data access method includes the following steps:

[0065] Step S10: The processor sends a request message, wherein the request message includes an operation type and an address, and the operation type includes a read operation or a write operation.

[0066] Step S20: When the request information is for local access, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller to complete the local memory access of the processor.

[0067] In the embodiment of the present application, when the processor 30 performs local access and needs to access data to its allocated memory, the corresponding memory controller 43 performs data movement, which can improve data access efficiency.

[0068] Please also refer to Figure 5 , which is a detailed flowchart of step S20. In at least one embodiment of the present invention, when the request information is for local access, based on the address, the processor 30 performs a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42 and memory controller 43 to complete the local memory access of the processor 30, including:

[0069] Step S201: When the request information is for local access, the processor operating mode is a memory control mode, and the processor sends a first control command to the corresponding memory controller, where the first control command is used to instruct the memory controller to obtain the request information.

[0070] Step S202: the memory controller sends a bus request signal to the arbiter according to the request information, and the arbiter sends the bus use right to the memory controller.

[0071] Step S203: the memory controller performs a read operation or a write operation on the storage medium according to the address.

[0072] In an embodiment of the present application, when the processor 30 wants to locally access the memory address space allocated to it, the processor 30 performs local access and moves data through the memory controller 43 corresponding to the processor 30 to implement read operations or write operations on its own memory.

[0073] In one possible implementation, the IMC Bus is used for communication during local access.

[0074] Furthermore, when performing a read operation, the memory controller 43 reads the first data according to the address, and the processor 30 receives the first data sent by the memory controller 43 .

[0075] Alternatively, when performing a write operation, the memory controller 43 writes the second data sent by the processor 30 into the storage medium 20 according to the address.

[0076] Step S30: When the request information is for non-local memory access, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller and DMA controller to complete the non-local memory access of the processor.

[0077] In one possible implementation, non-local access uses a Quick Path Interconnect (QPI) bus for communication.

[0078] Please also refer to Figure 6 , which is a detailed flowchart of step S30. In at least one embodiment of the present invention, when the request information is for non-local memory access, based on the address, the processor 30 performs a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42, memory controller 43, and DMA controller 41 to complete the non-local memory access of the processor 30, including:

[0079] Step S301: When the request information is for non-local memory access, the processor operating mode is the DMA control mode, and the processor sends a second control command to the corresponding DMA controller, where the second control command is used to instruct the DMA controller to obtain the request information.

[0080] Step S302: the DMA controller sends a bus request signal to the corresponding arbitrator according to the request information. The arbitrator sends the bus usage right to the DMA controller. The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address.

[0081] In one possible implementation, the DMA controller 41 sends the address to the memory controller 43 , and the memory controller 43 performs a read operation or a write operation on the storage medium 20 according to the address.

[0082] Furthermore, when performing a write operation, the DMA controller 41 receives the third data sent by the processor 30 and sends a bus request signal to the arbiter 42 corresponding to the destination address in the address. After obtaining the right to use the bus, the DMA controller 41 sends the third data to the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium 20.

[0083] Alternatively, when performing a read operation, the DMA controller 41 sends a bus request signal to the corresponding arbitrator 42 according to the source address in the address. After obtaining the right to use the bus, the DMA controller 41 sends the source address to the second memory controller corresponding to the source address. The second memory controller reads the fourth data according to the source address. The DMA controller 41 receives the fourth data, and the processor 30 reads the fourth data through the DMA controller 41.

[0084] In an embodiment of the present application, when the processor 30 wants to access the memory address space of other processors 30, it performs non-local access, and moves data through the DMA controller 41 corresponding to the processor 30, thereby increasing the rate at which the processor accesses the memory of other processors.

[0085] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments described above should be considered exemplary and non-restrictive in all respects, and the scope of the present application is defined by the appended claims rather than the foregoing description, and all variations that come within the meaning and range of equivalents of the claims are intended to be encompassed within the present application.

Claims

1. A data access method, characterized in that: The data access method is applied to a data access system, wherein the data access system includes a system on chip and a storage medium, wherein the system on chip and the storage medium communicate with each other via a bus, wherein the system on chip includes at least two processors and a respective transport module for each processor, wherein the transport module includes a DMA controller, an arbitrator, and a memory controller, and wherein the data access method includes: The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation; When the request information is for local access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address to complete the local memory access of the processor; and When the request information is for non-local memory access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller, and DMA controller based on the address, so as to complete the non-local memory access of the processor; When the request information is for non-local memory access, the operating mode of the processor is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller, where the second control command is used to instruct the DMA controller to obtain the request information; The DMA controller sends a bus request signal to the corresponding arbiter according to the request information, and the arbiter sends the bus use right to the DMA controller; The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address.

2. The data access method according to claim 1, wherein: When the request information is for local access, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address to complete the local memory access of the processor, including: When the request information is for local access, the operating mode of the processor is a memory control mode, and the processor sends a first control command to the corresponding memory controller, where the first control command is used to instruct the memory controller to obtain the request information; The memory controller sends a bus request signal to the arbiter according to the request information, and the arbiter sends the bus use right to the memory controller; The memory controller performs a read operation or a write operation on the storage medium according to the address.

3. The data access method according to claim 2, wherein: The memory controller performing a read operation or a write operation on the storage medium according to the address includes: When performing a read operation, the memory controller reads first data according to the address, and the processor receives the first data sent by the memory controller; Alternatively, when performing a write operation, the memory controller writes the second data sent by the processor into the storage medium according to the address.

4. The data access method according to claim 1, wherein: The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address, including: The DMA controller sends the address to the memory controller, and the memory controller performs a read operation or a write operation on the storage medium according to the address.

5. The data access method according to claim 4, wherein: The DMA controller sends the address to the memory controller, and the memory controller performs a read operation or a write operation on the storage medium according to the address, including: When performing a write operation, the DMA controller receives the third data sent by the processor and sends a bus request signal to the arbiter corresponding to the destination address in the address. After obtaining the right to use the bus, the DMA controller sends the third data to the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium; Alternatively, when performing a read operation, the DMA controller sends a bus request signal to the corresponding arbitrator based on the source address in the address. After obtaining the right to use the bus, the DMA controller sends the source address to the second memory controller corresponding to the source address. The second memory controller reads the fourth data based on the source address. The DMA controller receives the fourth data, and the processor reads the fourth data through the DMA controller.

6. The data access method according to any one of claims 1 to 5, wherein: The processor includes one or more of the following: a central processing unit, a graphics processing unit, and a digital signal processor.

7. A data access system, characterized in that: The data access system includes a system on chip and a storage medium, wherein the system on chip and the storage medium communicate with each other via a bus, the system on chip includes at least two processors and a respective transport module for each processor, and the transport module includes a DMA controller, an arbitrator, and a memory controller; The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation; The processor is configured to, when the request information is for local access, perform a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address to complete the local memory access; and, when the request information is for non-local memory access, perform a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller, and DMA controller based on the address to complete the non-local memory access; When the request information is for non-local memory access, the operating mode of the processor is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller, where the second control command is used to instruct the DMA controller to obtain the request information; The DMA controller sends a bus request signal to the corresponding arbiter according to the request information, and the arbiter sends the bus use right to the DMA controller; The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address.

8. The data access system according to claim 7, wherein: The system on chip and the storage medium are connected via wafer stacking.

9. The data access system according to claim 7, wherein: The storage medium is a dynamic random access memory.

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