Electrocardiosignal intelligent monitoring acceleration method based on programmable system on chip

Abstract

The application discloses an electrocardiosignal intelligent monitoring acceleration system and method based on a programmable system on chip, and belongs to the field of neural network algorithm implementation and hardware acceleration. The system comprises an analog-digital conversion module, a system on chip processor, a hardware acceleration module, a bus structure and an output display module. The operation of the feature extraction algorithm and the classification algorithm of the application is processed by software and the hardware acceleration circuit is specially designed. Compared with the existing pure software scheme, the processing speed is greatly optimized, the processing capacity is faster under the same power consumption, and the utilization rate of the programmable system on chip resources is improved. The result of electrocardiosignal classification is obtained from the system on chip processor, and other output contents can be directly provided by the analog-digital conversion module, so that the running load of the system on chip processor is reduced, the performance and real-time performance of the overall system are significantly improved, and the application has very important significance in the field of portable devices with high performance requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to an electrocardiosignal intelligent monitoring acceleration method based on a programmable system on chip, and belongs to the field of neural network algorithm implementation and hardware acceleration. BACKGROUND

[0002] Cardiovascular diseases have long been a threat to people's health, and they are sudden and accidental, so long-term real-time monitoring of electrocardio conditions is needed. In recent years, some electrocardio classification devices based on embedded microcontrollers have appeared on the market, realizing real-time monitoring and classification diagnosis, but due to the constraints of embedded microcontrollers in terms of computing power and power consumption, their identification accuracy, performance and real-time performance still do not meet professional requirements.

[0003] With the progress of microelectronic technology, programmable system on chips have attracted widespread attention from researchers. A typical programmable system on chip integrates microcontrollers, memories, programmable logic devices and other hardware circuits, as well as embedded software required by system functions. Compared with embedded microcontrollers, it can effectively improve real-time performance, improve performance, reduce size and improve portability. Based on this feature, some electrocardiosignal monitoring schemes based on programmable system on chips have appeared on the market, but the mainstream design idea is to develop hardware modules and software modules separately. Although the system can achieve the function, the performance is greatly affected by the running efficiency of the software. Generally, the working process of an intelligent electrocardio monitoring device is: sampling, filtering, feature extraction, classification and output result. The computational load of the entire system is mainly concentrated in the feature extraction and classification steps.

[0004] At present, the wavelet transform method is commonly used for feature extraction of the collected signals, but the existing technology requires the processor to perform complex convolution operations, causing delay in monitoring. Moreover, the classification of electrocardiosignals also involves a large number of operations, which hinders the running speed of the system. In addition, due to the dependence of the workflow, only the processor is working in the core operation step, and other modules are in an idle state, which will cause low efficiency, high delay and high power consumption of the system, which is not conducive to the development of wearable devices. SUMMARY

[0005] In order to solve the problems of poor real-time performance, low performance, high power consumption and complex devices caused by the existing electrocardiosignal monitoring process relying only on the processor to implement software algorithms, the present application provides an electrocardiosignal intelligent monitoring acceleration system and method based on a programmable system on chip.

[0006] The first object of the present application is to provide an electrocardiosignal intelligent monitoring system based on a programmable system on chip, which comprises an analog-to-digital conversion module, a system on chip processor, a hardware acceleration module, a bus structure and an output display module.

[0007] The analog-to-digital conversion module is configured to convert the electrocardio signal into a digital signal.

[0008] The system-on-chip processor is connected with the analog-to-digital conversion module and configured to process the digital electrocardio signal, including feature extraction and signal classification.

[0009] The hardware acceleration module is connected with the system-on-chip processor through a system bus and configured to perform hardware calculation on data of the system-on-chip processor.

[0010] The output display module is connected with the system-on-chip processor and configured to output and display related data of the electrocardio signal.

[0011] Optionally, the hardware acceleration module comprises a plurality of hardware calculation subunits, each of which comprises a plurality of multipliers and an adder, the plurality of multipliers are independent and connected in parallel, and the adder accumulates results obtained by the parallel multipliers.

[0012] Optionally, the system-on-chip processor extracts features of the digital electrocardio signal by using the Mallat algorithm, in the process of feature extraction, the Mallat algorithm represents the decomposition process of the input signal by using a feature matrix, and transmits repeated multiplication and addition operations in the feature matrix to the hardware acceleration module for hardware calculation.

[0013] The decomposition process of the input signal is represented by using the feature matrix, which comprises:

[0014] The filtering process of the Mallat algorithm is realized by using convolution operation, which comprises:

[0015]

[0016]

[0017] wherein, G1(n) is an output result of the input signal vector after passing through a first-layer digital low-pass filter, H1(n) is an output result of the input signal vector after passing through a first-layer digital high-pass filter, S(n) is the original input signal vector, and g(n) and h(n) represent the digital low-pass filter and the digital high-pass filter, respectively.

[0018] The above convolution formula is transformed into a matrix form, the length of the input signal S(n) is N, the length of the digital low-pass filter g(n) and the digital high-pass filter h(n) is K, and N>K, so the matrix form of the above formula is:

[0019]

[0020] The matrix composed of h(n) in the first layer is called a high-pass filter feature matrix F.h1 The matrix composed of the digital low-pass filter g(n) is called a low-pass filter feature matrix F g1 The two (K+N-1) x N matrices are subjected to the following regular transformation:

[0021] (1) Each removes the first (K / 2)-1 rows and the last (K / 2)-1 rows to form an (N+1) x N matrix;

[0022] (2) For the remaining N+1 rows, each extracts the even rows for point sampling;

[0023] (3) The two matrices extracted are spliced together to form an N x N matrix F1, where the matrix F1 is the feature matrix, and the decomposition layer is 1.

[0024] The following is a sequence of electrocardio signals, and the detail component sequence cD1 and the approximation component cA1 obtained after the first layer decomposition of the Mallat feature matrix.

[0025]

[0026] For the second layer decomposition, the input signal is the approximation component cA1 after the first layer decomposition, the high-pass filter feature matrix F h1 and the low-pass filter feature matrix F g1 Repeat the above steps (1), (2) and (3) to obtain the feature matrix F2 of At this time, let F2 perform matrix multiplication operation with cA1, and the detail component cD2 and the approximation component cA2 on the second layer decomposition can be obtained.

[0027] The wavelet decomposition process is expressed by a matrix as follows:

[0028]

[0029]

[0030] The subsequent decomposition layer is similar to the above steps.

[0031] Optionally, the system-on-chip processor classifies the electrocardio signal by using a BP neural network.

[0032] Optionally, the Mallat algorithm and the BP neural network are connected in a two-stage pipeline manner, and the operation process includes: first-stage pipeline calculation and second-stage pipeline calculation, and the calculation processes of the two-stage pipeline both include:

[0033] The system on chip processor first executes the Mallat algorithm, then transmits data to the hardware acceleration module for hardware calculation to obtain electrocardio feature data, and the electrocardio feature data is handed over to the BP neural network for classification calculation, and the final result is obtained after hardware operation of the hardware acceleration module.

[0034] When the Mallat algorithm of the first stage pipeline is completed and handed over to the hardware acceleration module for operation, the second stage pipeline starts to intervene, and the system on chip processor processes a new round of signals.

[0035] The second object of the application is to provide an electrocardio signal intelligent monitoring method based on a programmable system on chip, which comprises the following steps:

[0036] Step 1: acquiring original electrocardio signal data by using an analog-digital conversion module, and converting the original electrocardio signal data into digital electrocardio signal data;

[0037] Step 2: executing a feature extraction algorithm by using a system on chip processor to extract features from the digital electrocardio signal data;

[0038] Step 3: transmitting operation data of feature extraction from the system on chip processor to a hardware acceleration module through a system bus, performing hardware calculation, obtaining feature values of the digital electrocardio signal data, and caching the feature values in a storage module;

[0039] Step 4: reading the feature values of the electrocardio signal data from the storage module by using the system on chip processor, executing a classification algorithm, and classifying the electrocardio signal data according to the feature values;

[0040] Step 5: transmitting classification operation data to the hardware acceleration module through the system bus, performing hardware calculation, and obtaining a classification result;

[0041] Step 6: outputting the classification result and electrocardio signal waveform by using an output display module;

[0042] The hardware acceleration module is used for hardware operation on the process executed by the system on chip processor.

[0043] The storage module is used for caching results obtained by the hardware acceleration module, and the system on chip processor reads data from the storage module.

[0044] Optionally, the hardware acceleration module comprises a plurality of hardware calculation subunits, each hardware calculation subunit comprises a plurality of multipliers and an adder, the plurality of multipliers are independent and connected in parallel, and the adder accumulates results obtained by the plurality of parallel multipliers.

[0045] Optionally, the step 2 adopts the Mallat algorithm to perform feature extraction on the digital electrocardio signal, in the process of feature extraction, the decomposition process of the Mallat algorithm on the input signal is represented by a feature matrix, and repeated multiplication and addition operations in the feature matrix are transmitted to the hardware acceleration module for hardware calculation.

[0046] The decomposition process of the input signal is represented by a feature matrix, which includes:

[0047] The filtering process of the Mallat algorithm is realized by convolution operation, which is:

[0048]

[0049]

[0050] Wherein, G1(n) is the output result of the input signal vector after passing through the first layer of digital low-pass filter, H1(n) is the output result of the input signal vector after passing through the first layer of digital high-pass filter. S(n) is the original input signal vector, and g(n) and h(n) represent the digital low-pass and high-pass filters respectively.

[0051] The matrix transformation is performed on the above convolution formula, the length of the input signal S(n) is N, the length of the digital low-pass filter g(n) and the digital high-pass filter h(n) is K, and N>K, then the matrix form of the above formula is:

[0052]

[0053] The matrix composed of h(n) in the first layer is called high-pass filter feature matrix F h1 , and the matrix composed of digital low-pass filter g(n) is called low-pass filter feature matrix F g1 The two (K+N-1)×N matrices are transformed as follows:

[0054] (1) Each removes the first (K / 2)-1 row and the last (K / 2)-1 row to form an (N+1)×N matrix;

[0055] (2) Extract the even rows of the remaining N+1 rows for point sampling;

[0056] (3) The two matrices extracted are spliced together to form an N×N matrix F1, wherein the matrix F1 is the feature matrix, and the decomposition layer is 1.

[0057] The following is a group of electrocardio signal sequences, and the detail component sequence cD1 and the approximate component cA1 obtained after the first layer decomposition of the Mallat feature matrix.

[0058]

[0059] For the decomposition of the second layer, the input signal at this time is the approximate component cA1 after the first layer decomposition, and the high-pass filtering feature matrix F h1 and the low-pass filtering feature matrix F g1 The above steps (1), (2) and (3) will be repeated to obtain the feature matrix F2 of At this time, let F2 and cA1 perform matrix multiplication operation, and the detail component cD2 and the approximate component cA2 on the second layer decomposition can be obtained.

[0060] The wavelet decomposition process is expressed by a matrix as follows:

[0061]

[0062]

[0063] The subsequent decomposition layer is similar to the above steps.

[0064] Optionally, the step 4 uses a BP neural network to classify the electrocardio signal.

[0065] Optionally, the Mallat algorithm and the BP neural network classification algorithm are connected in a two-stage pipeline manner, and the operation process includes one-stage pipeline calculation and two-stage pipeline calculation, and the calculation process of the two-stage pipeline includes:

[0066] The system on chip processor first executes the Mallat algorithm, then transmits data to the hardware acceleration module for hardware calculation to obtain electrocardio feature data, and the electrocardio feature data is classified and calculated by the BP neural network, and then the hardware acceleration module is used for hardware operation to obtain the final result.

[0067] When the one-stage pipeline Mallat algorithm is completed and is handed over to the hardware acceleration module for operation, the two-stage pipeline starts to intervene, and the system on chip processor processes a new round of signal.

[0068] The present application has the following advantages:

[0069] The electrocardio signal intelligent detection acceleration system designed by the present application realizes the high integration of signal extraction, signal processing, signal output and other functions in the monitoring process by using the programmable system on chip structure and the software and hardware collaborative design, solves the problems of many components, large size and complex structure in the existing embedded scheme when realizing similar functions, and improves the portability.

[0070] The bus structure used by the system on chip in the application has high data transmission capacity, solves the defects of narrow data bandwidth and general processing performance of the existing embedded scheme, can provide faster processing capacity for electrocardiosignal processing, and thus improves real-time performance.

[0071] The electrocardiosignal output display module is designed in the application, main output content can be directly provided by an analog-digital conversion module, and only the result of electrocardiosignal classification is obtained from the system on chip processor, so that the running load of the system on chip processor can be greatly reduced, and the real-time performance of the system is improved.

[0072] The operation of the feature extraction algorithm and the classification algorithm in the application is processed through software and the special design of hardware acceleration circuit, compared with the existing pure software scheme, the processing speed is greatly optimized, under the same power consumption, more rapid processing capacity can be provided, the utilization rate of programmable system on chip resources is improved, and the performance and real-time performance of the overall system are significantly improved. This has very important significance in the field of portable devices with high power consumption requirements. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0074] Figure 1 The structural block diagram of the programmable system on chip in the application is shown.

[0075] Figure 2 The data communication schematic diagram of the electrocardiosignal classification algorithm hardware acceleration module and the system on chip processor in the application is shown.

[0076] Figure 3 The running block diagram of the Mallat algorithm in the application is shown.

[0077] Figure 4 The detailed structure of the hardware acceleration module in the application is shown.

[0078] Figure 5 The traditional connection mode of the Mallat algorithm and the BP neural network, and the pipeline connection mode used in the application are shown.

[0079] Figure 6 The BP neural network framework diagram is shown. DETAILED DESCRIPTION

[0080] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0081] Example 1:

[0082] This embodiment provides an intelligent ECG signal monitoring system based on a programmable system-on-a-chip, such as... Figure 1 As shown, the system includes: an analog-to-digital conversion module, an on-chip system processor, a hardware acceleration module, a bus structure, and an output display module; the analog-to-digital conversion module, the on-chip system processor, the bus structure, and the output display module are connected in sequence, and the hardware acceleration module is connected in parallel with the on-chip system.

[0083] The analog-to-digital conversion module is used to obtain the original electrocardiogram (ECG) signal data and convert it into a digital signal that the digital system can recognize and process. The on-chip system processor is used to process the ECG digital signal obtained by the digital-to-analog conversion module, run the core ECG signal feature extraction and classification algorithm, and transmit the calculated results to the output display module through the bus. The hardware acceleration module is connected to the on-chip system processor through the bus and can be used to perform hardware operations on specific arithmetic operations to accelerate the processor's operations.

[0084] Compared to existing pure software technologies, this invention, while ensuring portability, can significantly improve the system's processing performance and achieve reliable monitoring of the user's cardiovascular condition at all times.

[0085] The bus structure is a crucial data path for the programmable system-on-a-chip (SoC), enabling rapid data transfer between modules. The output display module outputs one HDMI video signal, which an external display device can directly display as video and audio. Specifically, the output display module can first utilize the SoC's bus structure to directly obtain the electrocardiogram (ECG) signal from the digital-to-analog converter (DAC) and output the corresponding waveform, thereby reducing the workload on the SoC's processor. Furthermore, the output display module obtains the ECG signal classification results from the SoC processor and outputs these results. The final output includes ECG waveforms, classification results, and other data. It can also output a warning audible signal when a potentially dangerous classification result is detected, providing users with a complete display of results, a user-friendly interface, and necessary alerts.

[0086] Example 2:

[0087] This embodiment provides an intelligent ECG signal monitoring system based on a programmable system-on-a-chip, such as... Figure 1 As shown, the system includes: an analog-to-digital conversion module, an on-chip system processor, a hardware acceleration module, a bus structure, and an output display module; the analog-to-digital conversion module, the on-chip system processor, the bus structure, and the output display module are connected in sequence, and the hardware acceleration module is connected in parallel with the on-chip system.

[0088] The analog-digital conversion module is configured to obtain original electrocardio signal data and convert the original electrocardio signal data into digital signals recognizable by a digital system; the system-on-chip processor is configured to process the electrocardio digital signals obtained by the analog-digital conversion module, run a core electrocardio signal feature extraction and classification algorithm, and transmit the running results obtained by calculation to the output display module through a bus; and the hardware acceleration module is connected to the system-on-chip processor through the bus, and can be configured to perform hardware operation on specific arithmetic to accelerate the operation of the processor.

[0089] The Mallat algorithm is configured to extract electrocardio signal features and run on the system-on-chip processor; the BP neural network is configured to process and classify electrocardio signals and also run on the system-on-chip processor; and the connection structure of the Mallat algorithm and the BP neural network is as shown in Figure 5 (b).

[0090] As shown in Figure 2 , the hardware acceleration module, the storage module and the bus structure constitute a whole hardware acceleration method, and all of them are connected to the system-on-chip processor. The Mallat algorithm is subjected to matrix transformation for electrocardio signal features, parallel calculation is performed by using a large number of adder and multiplier units of the system-on-chip, the classification process of the BP neural network is deployed on the core for operation, and the internal structure of the system-on-chip is used to perform two-stage pipeline optimization on the electrocardio intelligent classification system.

[0091] The system-on-chip processor runs the Mallat algorithm and communicates and cooperates with the hardware acceleration module and the storage module through the bus to realize speedup of operation;

[0092] The hardware acceleration module is as shown in Figure 4 , which is designed by using HDL language or HLS high-level synthesis tool for programmable logic gate array, and a large number of adder, multiplier and other combination logic circuits are called to perform hardware optimization for complex algorithms;

[0093] The storage module is an important link for algorithm running, which is a DDR memory in the embodiment and is configured to cache the results obtained by calculation of the hardware acceleration module, and the system-on-chip processor can also read data from the storage module;

[0094] The bus structure is responsible for transmitting data between modules in the system; the BP neural network is an electrocardio classification algorithm, which is trained according to the MIT_BIH database disclosed by Massachusetts Institute of Technology and Beth Israel Hospital, and is configured to further monitor and analyze the electrocardio signal feature values extracted by the Mallat algorithm.

[0095] The Mallat algorithm decomposes and reconstructs a signal layer by layer through high-pass and low-pass filters. Through the high-pass filter, the high-frequency part of the signal, also called the detail component cA, is obtained; through the low-pass filter, the low-frequency part of the signal, also called the approximation component cD, is obtained.

[0096] As shown in Figure 3 , let the length of the original input signal S be N, then after the first layer of decomposition:

[0097]

[0098] The second layer of decomposition is:

[0099]

[0100] The decomposition of the subsequent layers is an analogy of the above formula.

[0101] The filtering process of the Mallat algorithm is realized by convolution operation:

[0102]

[0103]

[0104] where G1(n) is the output result of the input signal vector after passing through the first layer of digital low-pass filter, H1(n) is the output result of the input signal vector after passing through the first layer of digital high-pass filter. S(n) is the original input signal vector, and g(n) and h(n) represent the digital low-pass and high-pass filters respectively.

[0105] The above convolution formula is transformed into a matrix form. The length of the input signal S(n) is N, the length of the digital low-pass filter g(n) and the digital high-pass filter h(n) is K, and N>K, then the matrix form of the above formula is:

[0106]

[0107] The matrix composed of h(n) in the first layer is called the high-pass filter characteristic matrix F h1 , and the matrix composed of the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F g1 The two (K+N-1) x N matrices are transformed as follows:

[0108] (1) Each removes the first (K / 2)-1 rows and the last (K / 2)-1 rows to form an (N+1) x N matrix;

[0109] (2) For the remaining N+1 rows, each extracts the even rows for point sampling;

[0110] (3) The two matrices after the extraction are spliced together to form an N x N matrix F1, wherein the matrix F1 is a characteristic matrix, and the number of decomposition layers is 1.

[0111] The following is a set of electrocardio signal sequences, and the detail component sequence cD1 and the approximate component cA1 obtained after the first layer decomposition of the Mallat characteristic matrix.

[0112]

[0113] For the second layer decomposition, the input signal is the approximate component cA1 after the first layer decomposition, the high-pass filtered characteristic matrix F h1 and the low-pass filtered characteristic matrix F g1 The above steps (1), (2) and (3) are repeated to obtain the characteristic matrix F2 of At this time, the F2 and the cA1 perform matrix multiplication operation, and the detail component cD2 and the approximate component cA2 on the second layer decomposition can be obtained.

[0114] The wavelet decomposition process is expressed by a matrix as follows:

[0115]

[0116]

[0117] The subsequent decomposition layer is similar to the above steps.

[0118] That is, the decomposition process of the Mallat algorithm on the input signal can be represented by the characteristic matrix, and the repeated multiplication and addition operations in the matrix can be completed by the adder and multiplier units in the hardware.

[0119] After the decomposition of the signal is completed, according to the amplitude-frequency characteristics of the P, QRS and T waves of the electrocardio signal, the positions of the P, QRS and T waves can be found on different decomposition layers, and the corresponding characteristic values can be obtained by subtraction operation. For example, three characteristic values such as the average interval of P-P wave, the average interval of T-T wave and the average existence period of QRS wave group are taken. The characteristic value data is temporarily stored in the storage unit of the hardware.

[0120] Then, the above three characteristic values can be taken as input values and sent into the trained BP neural network, and the electrocardio signal is classified according to the result to judge the electrocardio condition of the patient.

[0121] BP neural network is a kind of multilayer feedforward network trained by error back propagation algorithm, and is one of the most widely used neural network models. The MIT-BIH ECG abnormal database is used to train the parameters of the BP neural network, the correct weights obtained by training are brought into the network and deployed to the hardware, the ARM core is used to calculate the process of classifying ECG signals by the BP neural network, and the input values of the network are extracted from the hardware storage unit.

[0122] In order to optimize the system, the convolution operation in the Mallat algorithm is transformed in the form of matrix, and the hardware is specially structured, so that the multi-granularity optimization of the Mallat algorithm and the matrix operation of the BP neural network is realized. In this embodiment, the optimization of matrix operation can be divided into two kinds of granularities, namely fine-grained optimization and coarse-grained optimization. The fine-grained optimization refers to the optimization of the operation of a single element in the matrix. The coarse-grained optimization refers to the optimization of the operation between different elements in the matrix.

[0123] As shown in Figure 4 , in the system on chip processor, the input ECG signal data is first processed to obtain matrix data, which is denoted as operation matrix 1 and operation matrix 2 respectively. Next, the system on chip processor controls the data to be transmitted to the hardware acceleration module through the bus, as shown in Figure 2 .

[0124] After the data of the two operation matrices enters the hardware acceleration module shown in Figure 4 , they will enter the sub-units marked by the dashed boxes respectively. Each sub-unit includes a plurality of multipliers and adders. Since the multiplication operation in matrix operation has high independence and parallelism, the multipliers in the sub-unit are independent and parallel. After the multipliers complete the multiplication part of the matrix operation, the adders add the results obtained by the parallel multipliers to obtain one element M i,j of the result matrix, where M represents the result matrix of m rows and n columns, i represents the row number of the element, and j represents the column number of the element. By this method, fine-grained optimization of matrix operation is realized.

[0125] Since the result matrix includes a plurality of elements, and the operation between each element is not affected by each other, it has good independence and parallelism, so Figure 4 the sub-units marked by the dashed lines in the matrix operation module are parallel to each other and can independently operate at the same time to obtain the corresponding elements of the result matrix. Through such design, the embodiment can obtain all elements of the result matrix at the same time in one element calculation period, complete the operation of the entire result matrix, and realize coarse-grained optimization of matrix operation.

[0126] Through hardware acceleration in two granularities, the entire system can more efficiently and quickly operate on a large amount of data, which enables the speed of extracting the electrocardio characteristic value by using the Mallat algorithm to be further improved. Since the extraction of the electrocardio characteristic value has a core position in the system on chip involved in the embodiment, the performance and real-time performance of the entire system on chip can also be greatly improved, so that the intelligent monitoring of the electrocardio signal can be truly and effectively realized.

[0127] Embodiment three:

[0128] The embodiment provides an electrocardio signal intelligent monitoring method based on a programmable system on chip, and is realized by using the electrocardio signal intelligent monitoring system described in embodiment two. The method comprises the following steps:

[0129] Step 1: acquiring original electrocardio signal data by using an analog-digital conversion module, and converting the original electrocardio signal data into digital electrocardio signal data;

[0130] Step 2: performing a feature extraction algorithm by using a system on chip processor to extract features from the digital electrocardio signal data;

[0131] Step 3: transmitting operation data of feature extraction from the system on chip processor to a hardware acceleration module through a system bus, performing hardware calculation, obtaining the electrocardio signal feature value, and caching the electrocardio signal feature value in a storage module;

[0132] Step 4: reading the electrocardio signal feature value from the storage module by using the system on chip processor, performing a classification algorithm, and classifying the electrocardio signal data according to the electrocardio signal feature value;

[0133] Step 5: transmitting classification operation data to the hardware acceleration module through the system bus, performing hardware calculation, and obtaining a classification result;

[0134] Step 6: outputting the classification result and the electrocardio signal waveform by using an output display module.

[0135] As shown in Figure 5 , the Mallat algorithm and the BP neural network classification algorithm have a certain dependent relationship. The BP neural network classification algorithm needs to obtain the electrocardio signal feature information extracted by the Mallat algorithm to perform subsequent operation. The traditional connection mode of the two algorithms is simple series connection, that is, the two algorithms are realized in sequence in a software program.

[0136] As shown in Figure 5 (a), the traditional method first performs the Mallat algorithm, then obtains the electrocardio feature data by using hardware calculation, then the data is classified by using the BP neural network, and finally the last result is obtained by using hardware operation. After the above steps are completed, the same steps are performed again to realize real-time monitoring of the electrocardio signal.

[0137] However, in the present embodiment, the process of hardware operation can be processed by a hardware acceleration module other than the system on chip processor. If the traditional scheme shown in Figure 5 (a) is used, the system on chip processor will be in an idle state during the process run by the hardware acceleration module. Similarly, when the system on chip processor is in a working state, the hardware acceleration module will also be in an idle state.

[0138] In the present embodiment, the connection mode of the Mallat algorithm and the BP neural network classification algorithm is optimized by using a two-stage pipeline structure, so that the further acceleration of the intelligent monitoring of the electrocardio signal can be realized. The operation of each stage of the pipeline is consistent with the traditional method, that is, the Mallat algorithm is first executed, then the electrocardio feature data is obtained by hardware calculation, then the data is classified by the BP neural network, and then the final result is obtained by hardware operation. The acceleration method of the present embodiment is reflected in the alternate use of resources by the two-stage pipeline. As shown in Figure 5 (b), when the Mallat algorithm of the first stage pipeline is completed and is operated by the hardware acceleration module, the second stage pipeline starts to intervene, and the system on chip processor processes a new round of signal. When a stage of the pipeline is completed, it will continue to run according to the original steps to realize the real-time monitoring of the electrocardio signal.

[0139] Under the structure of the two-stage pipeline, the resource utilization rate of the system is further improved. Figure 5 In (b), the vertical dashed line indicates the same time. It can be seen that at the same time, the system on chip processor and the hardware acceleration module will be in a working state all the time under the two-stage pipeline, which reflects the full exploitation and utilization of resources; in contrast, in the traditional scheme shown in Figure 5 (a), one of the processor or the hardware acceleration module will be in an idle state in the working process, which will cause the waste of resources. In the two-stage pipeline method used in the present system, the functions of each stage of the pipeline are similar to those of the traditional scheme shown in Figure 5 (a), which ensures the reliability of the system operation and reduces the development difficulty. Through the implementation of the present embodiment, the system can further improve the utilization rate of the operation resources, and the operation speed can also be further improved.

[0140] As shown in ​As shown, the 8 steps required by the traditional scheme to complete the two-cycle ECG signal monitoring can be optimized to 5 steps by the two-stage pipeline method; and with the loop execution of the algorithm, the optimization of the pipeline will have more significant effect. In addition, under the pipeline structure, the ECG signal acquisition operation becomes more frequent, which also means that the present application improves the accuracy and real-time performance of the system in ECG signal monitoring. Through the implementation of the present embodiment, not only the utilization rate of the two algorithms is maximized, but also the resource utilization rate of the programmable system on chip is further improved, which significantly improves the working efficiency of the system, thereby truly and effectively realizing the further acceleration of the ECG signal intelligent monitoring.

[0141] Part of the steps in the embodiments of the present application can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0142] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A smart monitoring system for electrocardiogram signals based on a programmable system-on-a-chip, characterized in that, The system includes: an analog-to-digital conversion module, a system-on-a-chip processor, a hardware acceleration module, a bus structure, and an output display module; The analog-to-digital converter module is used to convert electrocardiogram signals into digital signals; The on-chip system processor is connected to the analog-to-digital converter module and is used to process digital electrocardiogram signals, including signal feature extraction and signal classification. The hardware acceleration module is connected to the on-chip system processor via a system bus and is used to perform hardware calculations on the data of the on-chip system processor. The output display module is connected to the system-on-chip processor and is used to output and display relevant data of the electrocardiogram signal; The hardware acceleration module includes multiple hardware computing sub-units, each of which includes several multipliers and adders. The multipliers are independent of each other and connected in parallel, and the adders accumulate the results obtained by the parallel multipliers. The on-chip system processor uses the Mallat algorithm to extract features from the digital electrocardiogram signal. During the feature extraction process, the Mallat algorithm represents the decomposition process of the input signal with a feature matrix and transmits the repeated multiplication and addition operations in the feature matrix to the hardware acceleration module for hardware calculation. The decomposition process of using feature matrices to characterize the input signal includes: The filtering process of Mallat's algorithm using convolution operations is as follows: Where G1(n) is the output of the input signal vector after passing through the first digital low-pass filter, H1(n) is the output of the input signal vector after passing through the first digital high-pass filter, S(n) is the original input signal vector, and g(n) and h(n) represent the digital low-pass and high-pass filters, respectively. Performing a matrix transformation on the above convolution formula, with the input signal S(n) having a length of N, and the digital low-pass filter g(n) and digital high-pass filter h(n) both having a length of K, and N>K, the matrix form of the above formula becomes: The matrix formed by h(n) in the first layer is called the high-pass filter feature matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1 The following rule transformation is applied to these two (K+N-1)×N matrices: (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix; (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals; (3) Concatenate the two extracted matrices together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer number is 1. The following is a set of electrocardiogram signal sequences, after which the detail component sequence cD1 and approximate component cA1 are obtained after the first level decomposition of the Mallat feature matrix; For the second layer of decomposition, the input signal is now the approximate component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain The characteristic matrix F2 is then multiplied with cA1 to obtain the detail component cD2 and the approximate component cA2 in the second decomposition. The wavelet decomposition process can be expressed using matrices as follows: Subsequent decomposition layers follow the same steps as described above.

2. The intelligent ECG signal monitoring system according to claim 1, characterized in that, The on-chip system processor uses a BP neural network to classify electrocardiogram signals.

3. The intelligent ECG signal monitoring system according to claim 2, characterized in that, The Mallat algorithm and the BP neural network are connected in a two-stage pipeline manner. The computation process includes: a first-stage pipeline computation and a second-stage pipeline computation. The computation process of both stages includes: The on-chip system processor first executes the Mallat algorithm, then transmits the data to the hardware acceleration module for hardware calculation to obtain ECG feature data. The ECG feature data is then passed to the BP neural network for classification calculation, and finally passed to the hardware acceleration module for hardware operation to obtain the final result. Once the Mallat algorithm in the first-stage pipeline is completed and handed over to the hardware acceleration module for computation, the second-stage pipeline begins to intervene, and the on-chip system processor performs a new round of signal processing.

4. A method for intelligent monitoring of electrocardiogram signals based on a programmable on-chip system, characterized in that, The method includes: Step 1: Use an analog-to-digital converter to acquire the raw ECG signal data and convert it into a digital ECG signal; Step 2: The on-chip system processor executes a feature extraction algorithm to extract features from the digital electrocardiogram signal; Step 3: The on-chip system processor transmits the feature extraction operation data to the hardware acceleration module through the system bus for hardware calculation to obtain the digital electrocardiogram signal feature values ​​and cache them in the storage module; Step 4: The on-chip system processor reads the ECG data feature values ​​from the storage module, executes a classification algorithm, and classifies the ECG data according to the ECG data feature values; Step 5: The classification calculation data is transmitted to the hardware acceleration module through the system bus for hardware calculation to obtain the classification result; Step 6: The output display module outputs the classification results and ECG signal waveforms; The hardware acceleration module is used to perform hardware calculations on the execution process of the on-chip system processor. The storage module is used to cache the results calculated by the hardware acceleration module, from which the on-chip system processor reads data. The hardware acceleration module includes multiple hardware computing sub-units, each of which includes several multipliers and adders. The multipliers are independent of each other and connected in parallel, and the adders accumulate the results obtained by the parallel multipliers. Step 2 uses the Mallat algorithm to extract features from the digital electrocardiogram signal. During the feature extraction process, the Mallat algorithm represents the decomposition process of the input signal with a feature matrix and transmits the repeated multiplication and addition operations in the feature matrix to the hardware acceleration module for hardware calculation. The decomposition process of using feature matrices to characterize the input signal includes: The filtering process of Mallat's algorithm using convolution operations is as follows: Where G1(n) is the output of the input signal vector after passing through the first digital low-pass filter, H1(n) is the output of the input signal vector after passing through the first digital high-pass filter, S(n) is the original input signal vector, and g(n) and h(n) represent the digital low-pass and high-pass filters, respectively. Performing a matrix transformation on the above convolution formula, with the input signal S(n) having a length of N, and the digital low-pass filter g(n) and digital high-pass filter h(n) both having a length of K, and N>K, the matrix form of the above formula becomes: The matrix formed by h(n) in the first layer is called the high-pass filter feature matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1 The following rule transformation is applied to these two (K+N-1)×N matrices: (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix; (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals; (3) Concatenate the two extracted matrices together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer number is 1. The following is a set of electrocardiogram signal sequences, after which the detail component sequence cD1 and approximate component cA1 are obtained after the first level decomposition of the Mallat feature matrix; For the second layer of decomposition, the input signal is now the approximate component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain The characteristic matrix F2 is then multiplied with cA1 to obtain the detail component cD2 and the approximate component cA2 in the second decomposition. The wavelet decomposition process can be expressed using matrices as follows: Subsequent decomposition layers follow the same steps as described above.

5. The intelligent electrocardiogram signal monitoring method according to claim 4, characterized in that, Step 4 uses a BP neural network to classify electrocardiogram signals.

6. The intelligent electrocardiogram signal monitoring method according to claim 5, characterized in that, The Mallat algorithm and the BP neural network classification algorithm are connected in a two-stage pipeline manner. The computation process includes a first-stage pipeline calculation and a second-stage pipeline calculation. The computation process of both stages includes: The on-chip system processor first executes the Mallat algorithm, then transmits the data to the hardware acceleration module for hardware calculation to obtain ECG feature data. The ECG feature data is then passed to the BP neural network for classification calculation, and finally passed to the hardware acceleration module for hardware operation to obtain the final result. Once the Mallat algorithm in the first-stage pipeline is completed and handed over to the hardware acceleration module for computation, the second-stage pipeline begins to intervene, and the on-chip system processor performs a new round of signal processing.

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