Test substrate, test circuit, display panel and test assembly

Abstract

The present application discloses a test substrate, a test circuit, a display panel and a test assembly, wherein a test pad is provided on the test substrate, and the test pad includes a power supply voltage pad and a negative voltage pad. The power supply voltage pad and the negative voltage pad are respectively used to be electrically connected to the detection pad of the detection area of ​​the panel to be tested, and the binding pad located in the binding area. The embodiment of the present application redesigns the structure of the test substrate and the test circuit structure, so that the test substrate is electrically connected to the detection pad on the panel to be tested, and is directly connected to the binding welding on the panel to be tested, thereby adding a new current path to reduce the current flowing through the GATE layer in the original current path, and ultimately avoid damage to the panel.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to a test substrate, a test circuit, a display panel and a test assembly. Background Art

[0002] With the development and advancement of display technology, electronic products have increasingly higher performance requirements for display panels, such as size requirements, pixel density requirements, etc.

[0003] Before forming the display panel, it is necessary to perform an ET (Electric Test) on the array substrate using a test substrate to detect whether the signal lines on the array substrate have problems such as defects. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a test substrate, a test circuit, a display panel and a test assembly, by configuring the test substrate to be directly electrically connected to the binding PAD on the panel to increase the current path during testing, reduce the current flowing through the GATE layer, and avoid damage to the panel.

[0005] In a first aspect, an embodiment of the present application provides a test substrate, on which a test pad is disposed, and the test pad includes a power supply voltage pad and a negative voltage pad.

[0006] The power supply voltage pad and the negative voltage pad are respectively used to be electrically connected to the detection pad in the detection area of ​​the panel to be detected and the binding pad in the binding area.

[0007] Optionally, in the test substrate provided in an embodiment of the present application, protrusions are arranged at corresponding positions of the power supply voltage pad and the negative voltage pad on the test substrate, so that the power supply voltage pad and the negative voltage pad extending to the protrusion are electrically connected to the binding pad in the binding area.

[0008] Optionally, in the test substrate provided in an embodiment of the present application, the protrusion includes a first protrusion corresponding to the power voltage pad, and a second protrusion corresponding to the negative voltage pad.

[0009] Optionally, in the test substrate provided in the embodiment of the present application, the power supply voltage pad is crimped to the power supply voltage pad of the detection area of ​​the panel to be detected, and the negative voltage pad is crimped to the negative voltage pad of the detection area of ​​the panel to be detected.

[0010] Optionally, in the test substrate provided in the embodiment of the present application, the power supply voltage pad is pressed against the power supply voltage pad of the binding area of ​​the panel to be tested and the negative voltage pad is pressed against the negative voltage pad of the binding area of ​​the panel to be tested.

[0011] In a second aspect, an embodiment of the present application provides a panel test circuit, the circuit comprising:

[0012] A detection module configured in the detection area on the panel to be detected, a binding module configured in the binding area, and a test module configured on the test substrate;

[0013] The testing module is electrically connected to the detecting module and the binding module respectively.

[0014] Optionally, in the test circuit provided in the embodiment of the present application, the test module includes a power supply voltage pad and a negative pole voltage pad; the detection module includes a power supply voltage pad and a negative pole voltage pad, and the power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the detection module; the negative pole voltage pad in the test module is electrically connected to the negative pole voltage pad in the detection module.

[0015] Optionally, in the test circuit provided in an embodiment of the present application, the binding module includes a power supply voltage pad and a negative voltage pad, and the power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the binding module; the negative voltage pad in the test module is electrically connected to the negative voltage pad in the binding module.

[0016] In a third aspect, an embodiment of the present application provides a display panel, on which a binding area and a detection area are configured, and the panel is detected using the test substrate as described in the first aspect.

[0017] In a fourth aspect, an embodiment of the present application provides a panel testing assembly, which includes the display panel as described in the third aspect, and the testing substrate as described in the first aspect.

[0018] In summary, the embodiments of the present application provide a test substrate, a test circuit, a display panel and a test assembly. By redesigning the structure of the test substrate and the test circuit structure, the test substrate is electrically connected to the detection pad on the panel to be tested, and is directly connected to the binding welding on the panel to be tested, thereby adding a new current path to reduce the current flowing through the GATE layer in the original current path, and ultimately avoiding damage to the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0020] Figure 1 It is a schematic diagram of the structure of the panel;

[0021] Figure 2 A schematic diagram of the structure of a panel test of the related technology;

[0022] Figure 3 A schematic diagram of the structure of a test substrate according to an embodiment of the present application;

[0023] Figure 4 This is a schematic diagram of the structure of the connection between the test substrate and the panel in an embodiment of the present application;

[0024] Figure 5 Schematic diagram of the structure of the test substrate in some other embodiments of the present application;

[0025] Figure 6 A schematic diagram of the test circuit structure of an embodiment of the present application;

[0026] Figure 7 Schematic diagram of the equivalent circuit structure of the panel test according to the embodiment of the present application.

[0027] 1-display panel; 2-binding area, 21-source voltage pad, 22-low voltage pad, 23-data signal pad, 3-detection area, 31-source voltage pad, 32-low voltage pad, 4-test substrate, 41-source voltage pad, 42-low voltage pad, 43-protrusion, 431-first protrusion, 432-second protrusion. DETAILED DESCRIPTION

[0028] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] It is understandable that Figure 1 As shown, the actual panel 1 generally includes a display area AA and a bonding area 2 around the display area. A bonding pad is configured in the bonding area. The configured bonding pad generally includes a power supply voltage (Voltage Drain Pad, VDD) pad 21, a negative voltage (Voltage Source Pad, VSS) pad 22 and a signal data (data line, gate line, etc.) pad 23.

[0031] It can also be understood that as the size of the panel gradually increases, such as the folding mobile phone screen has reached 8 inches, the size of the NB is 13-19 inches, etc., the number of binding pads in the panel increases accordingly, and accompanied by a high pixel density (PPI), a larger driving voltage and current are required.

[0032] It can also be understood that before forming the panel, it is necessary to perform an electric test (Electric Test, ET) on the array substrate in the panel to detect whether the signal lines on the array substrate have problems such as defects, or to perform an aging test on the array substrate.

[0033] Furthermore, in order to implement the test, in practice, a detection area 3 is also configured near the binding area 2 of the panel, and a detection pad (ET PAD) is configured in the detection area 3. Correspondingly, the detection pad may also include a power voltage pad 31, a negative voltage pad 32, etc., to implement a high current test of the panel to detect the performance of the panel circuit connection and aging.

[0034] It can be understood that the connection between the ET PAD and the panel is made by punching holes in two layers of different materials. The material at the ET PAD end is the source and drain metal (SD) layer with low resistance; the material at the panel end is the gate metal (GATE) layer with high resistance.

[0035] Based on the configuration of the above-mentioned binding area and test area, in the related art, when the packaged panel is tested, such as Figure 2 As shown, it is completed through the test substrate (ET FPC) provided by the outside. That is, by pressing the VSS Pad and VDD Pad on the test substrate with the ET Pad on the panel, the test current signal is input to the panel through the ET Pad to achieve detection. That is, after the test substrate is pressed with the ET PAD, an external power supply is applied to light up the panel to screen the quality of the screen.

[0036] When the panel is tested in the above-mentioned related technologies, the connection between the ET PAD and the panel has a source-drain metal (SD) layer with a smaller resistance and a gate metal (GATE) layer with a larger resistance. When the ET PAD is powered on for testing, the detection current will pass through the SD layer and the GATE layer. Since the test power supply voltage (ELVDD) and the test cathode voltage (ELVSS) of the large-size panel are relatively large, when a large current flows through the GATE layer with a large resistance, because its resistance is high, according to Q=I 2 Rt will generate higher heat at the GATE of the panel, thus burning the panel and eventually causing damage.

[0037] In an embodiment of the present application, in order to avoid the defect of burning loss to the panel caused by the large current generated during the test passing through the GATE layer, the circuit connection structure of the test substrate is redesigned. That is, the test substrate is connected to the panel through the ETPAD, and at the same time, it is directly connected to the binding PAD on the display panel to form a new test circuit structure, thereby increasing the current path, reducing the current flowing through the GATE layer, and ultimately avoiding damage to the panel.

[0038] For a better understanding, the test circuit and test substrate provided in the embodiment of the present application are described below. Figures 3 to 7 Elaborate in detail.

[0039] Figure 3 A schematic diagram of the structure of the test substrate provided in the embodiment of the present application, such as Figure 3 As shown:

[0040] The test substrate 4 is provided with test pads, which include a power supply voltage pad 41 and a negative voltage pad 42 .

[0041] The power supply voltage pad 41 and the negative voltage pad 42 are respectively used to be electrically connected to the detection pad of the detection area 3 of the panel 1 to be detected and the binding pad located in the binding area 2 .

[0042] Specifically, Figure 3 As shown, the test substrate 4 in the embodiment of the present application is provided with test pads including a power supply voltage pad 41 and a negative voltage pad 42 .

[0043] In order to achieve performance testing of the panel to be tested, the test pads on the test substrate 4 are electrically connected to the test pads in the test area 3 arranged on the panel to be tested 1, such as by crimping, so that the test substrate is connected to the circuit inside the panel through the test pads on the panel, thereby achieving performance testing of the internal circuit of the panel.

[0044] Furthermore, in an embodiment of the present application, in order to avoid heat loss to the panel when current passes through the connection between the detection pad of the detection area 3 and the panel 1 during the panel performance test, the test pad of the test substrate 4 is directly electrically connected to the binding pad in the panel binding area 2, so as to add a new current branch. After flowing out from the test substrate, this current branch will not pass through the detection pad on the panel, but will directly flow into the binding pad of the panel, thereby reducing the current flowing through the GATE layer and avoiding damage to the panel.

[0045] In practice, if Figure 3 and Figure 4 As shown, before the test, the VSS Pad and VDD Pad on the test substrate are crimped to the ET Pad (VSS Pad and VDD Pad) in the detection area 3 respectively, so that when the ET test is performed, the current provided by the external device flows out from the VDD Pad of the test substrate, passes through the VDD Pad of the ET Pad, passes through the SD layer, and then passes through the metal layer and the GATE layer in contact with the SD layer, and finally flows out from the VSS Pad of the ET Pad and returns to the VSS Pad of the test substrate.

[0046] Further, if Figure 4As shown, on the basis of this connection, in order to reduce the large current flowing through the metal layer and the GATE layer in contact with the SD layer and the GATE layer and avoid burning of the panel, the embodiment of the present application directly connects the VDD Pad on the test substrate to the VDD Pad in the binding area, and connects the VSS Pad on the test substrate to the VSS Pad in the binding area. As a result, when performing ET testing, a current path with a small resistance is added to the original current path, that is, after flowing out from the VDDPad of the test substrate, it directly flows through the VDD Pad and VSS Pad in the panel binding area, and finally returns to the VSS Pad of the test substrate.

[0047] It can be understood that since there is no large resistance in the newly added current path, that is, the resistance of the metal layer passed through is much smaller than the resistance of the metal layer and the GATE layer in contact with the SD layer in the first circuit path, the newly added current path can effectively divert the current on the original path during testing, ultimately protecting the safety of the display panel.

[0048] It can be understood that in order to achieve direct connection between the test substrate and the binding area, the mechanical structure of the test substrate can be redesigned.

[0049] For example, Figure 3 In some embodiments shown in the figure, in order to facilitate the effective electrical connection between the VSS Pad and the VDD Pad of the test substrate and the binding pads, one side of the test substrate can be widened to form a protrusion 43, that is, Figure 3 As shown, the corresponding positions of the power supply voltage pad and the negative voltage pad on the test substrate are configured as protrusions extending to the outside of the test substrate, so that the power supply voltage pad and the negative voltage pad extending to the protrusion are electrically connected to the binding pad in the binding area to achieve direct connection with the binding area on the panel.

[0050] For example, in some other embodiments, Figure 5 As shown, in order to facilitate the process, the VSSPad and VDD Pad of the test substrate are crimped with their corresponding binding pads, respectively, and the substrate size can be extended at the positions corresponding to the VSS Pad and the VDD Pad, respectively, to form a first protrusion 431 corresponding to the VDD Pad, and a second protrusion 432 corresponding to the VSS Pad, so that the test substrate can be directly connected to the VDDPad in the binding area on the panel with the help of the configured first protrusion 431, and can be directly connected to the VSS Pad in the binding area on the panel with the help of the configured first protrusion 432.

[0051] It can be understood that the specific mechanical structure setting of the test substrate can be flexibly set according to actual requirements to achieve direct electrical connection between the VSS Pad and VDD Pad on it and the VSS Pad and VDD Pad in the binding area. The embodiments of the present application do not limit its specific setting structure.

[0052] It can be understood that the test substrate provided in the above embodiment has formed a protrusion by extending the corresponding position dimensions of the VSS Pad and VDD Pad of the test substrate, so that the VSS Pad and VDD Pad of the test substrate can be directly connected to the binding pads in the binding area through the formed protrusion, providing a new low-resistance current branch for the test current, thereby effectively limiting the current flowing into the connection between the SD layer and the GATE layer, avoiding the heat generated here due to excessive current, that is, avoiding panel burning caused by severe heating of the panel during the test process, and effectively protecting the panel during the test process.

[0053] In addition, general panel settings such as Figure 1 and Figure 4 As shown, there is a cutting line between the binding area and the detection area. After the detection procedure is completed and there is no problem in the detection, when the independent display panel is cut, the detection area is cut away and not retained in the panel. That is, only the VSS Pad and VDD Pad in the panel need to be shared during the ET test.

[0054] In order to better understand the test substrate provided in the above embodiments, the protection of the panel during the actual test is as follows. Figure 6 and Figure 7 The corresponding circuit structure when the panel test is performed using the provided test substrate is described in detail.

[0055] Figure 6 FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the present invention. Figure 6 As shown, the test circuit specifically includes:

[0056] A detection module is configured in the detection area of ​​the panel to be tested, a binding module is configured in the binding area, and a test module is configured on the test substrate.

[0057] The testing module is electrically connected to the detecting module and the binding module respectively.

[0058] Specifically, Figure 1 As shown, a display area AA, a binding area 2 located outside the display area, and a detection area 3 located near the binding area are arranged on the panel to be tested 1 .

[0059] The binding area is provided with a binding module, that is, it may include a power supply voltage pad and a negative voltage pad.

[0060] A detection module is disposed in the detection area, and the detection module may also include a power supply voltage pad and a negative voltage pad.

[0061] In addition, the test module configured on the test substrate may also include a power supply voltage pad and a negative voltage pad.

[0062] Correspondingly, the power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the detection module; the negative voltage pad in the test module is electrically connected to the negative voltage pad in the detection module.

[0063] The power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the binding module; the cathode voltage pad in the test module is electrically connected to the cathode voltage pad in the binding module.

[0064] In addition, the power supply voltage pad and the negative voltage pad configured in the detection area 3 are connected to the panel by punching, that is, one end is overlapped with the SD layer of the panel, and the other end is overlapped with the gate layer of the panel, so that the pads on the detection area 3 can be used to achieve electrical connection with the circuit in the panel.

[0065] In practice, combined Figure 4 On the one hand, the VDD pad and the VSS pad on the test substrate are respectively overlapped with the VDD pad and the VSS pad in the detection area 3 to form a circuit connected to the inside of the panel; on the other hand, the VDD pad and the VSS pad on the test substrate are directly overlapped with the VDD pad and the VSS pad in the panel binding area 2 to form a new current path.

[0066] It can be understood that the above circuit structure, in actual testing, Figure 7 The equivalent circuit structure diagram is shown as follows:

[0067] Figure 7 R1 is the resistor corresponding to the connection between the SD layer and the GATE layer, R2 is the resistor corresponding to the GATE layer, and R3 is the resistor corresponding to the connection line between the VDD pad and the VSS pad on the test substrate and the binding pad.

[0068] Combination Figure 7 When the external device is connected to the test substrate and a large current is input to the test substrate, the current flows to the VDD pad and VSS pad of the test substrate, and there are two current branches at the same time:

[0069] The first branch: The current output by the external device flows from the VDD pad of the test substrate, through the crimping with the detection pad of the panel detection area, into the VDD pad of the detection area, and then through the SD layer of the panel, the connection between the SD layer and the GATE layer, and then into the GATE layer, and enter the circuit inside the panel. For example, it can enter the VDD pad of the panel binding area, and then flow into the VSS pad of the panel binding area, and then pass through the GATE layer, the connection between the SD layer and the GATE layer, the SD layer and the VSS pad of the detection area, and finally flow out from the VSS pad of the test substrate to complete a test loop.

[0070] The second branch: After the current output by the external device flows out from the VDD pad of the test substrate, it directly flows into the VDD pad of the panel binding area due to the direct connection with the binding pad of the binding area, and then flows out directly to the VSS pad of the test substrate after passing through the VSS pad of the panel binding area.

[0071] It is understandable that Figure 6 and Figure 7 The two current branches provided in the circuit structure shown above, for the first circuit path, need to pass through the connection between the SD layer and the GATE layer and the GATE layer. In general, the connection between the SD layer and the GATE layer is a metal layer with a relatively large resistance, such as metal molybdenum. The second branch, that is, the test substrate is directly overlapped with the binding area on the panel, and there is no large resistance.

[0072] Under the premise that there is a large resistance in the first current branch, most of the large current input from the external device to the test substrate will choose to enter the second current branch, which greatly reduces the current entering the first current branch, thereby effectively limiting the current flowing into the connection between the SD layer and the GATE layer, avoiding the heat generated here due to excessive current, that is, avoiding panel burns caused by severe heating of the panel during the test, and effectively protecting the panel during the test.

[0073] On the other hand, an embodiment of the present application further provides a display panel, on which a binding area and a detection area are configured, and the panel is tested using the test substrate described in the above embodiments.

[0074] On the other hand, an embodiment of the present application further provides a panel testing assembly, which includes the display panel and the testing substrate as described in the above embodiment.

[0075] To summarize, the test substrate, test circuit, display panel and test assembly provided in the embodiments of the present application redesign the structure of the test substrate and the test circuit structure so that the test substrate is electrically connected to the detection pads on the panel to be tested and directly connected to the binding welding on the panel to be tested, thereby adding a new current path to reduce the current flowing through the GATE layer in the original current path, ultimately avoiding damage to the panel.

[0076] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the concept of the invention. For example, the above features are replaced with the technical features with similar functions disclosed in the present application (but not limited to) by each other.

Claims

1. A test substrate, characterized in that: The test substrate is provided with a test pad, and the test pad includes a power supply voltage pad and a negative voltage pad; The power supply voltage pad and the negative pole voltage pad are respectively used to be electrically connected to the detection pad of the detection area of ​​the panel to be detected, and the binding pad located in the binding area; the resistance of the newly added current path is less than the resistance of the original current path, the newly added current path is a current path formed by the electrical connection between the power supply voltage pad and the negative pole voltage pad and the binding pad in the binding area, and the original current path is a current path formed by the electrical connection between the power supply voltage pad and the negative pole voltage pad and the detection pad of the detection area; Protrusions are arranged at corresponding positions of the power supply voltage pad and the negative voltage pad on the test substrate, so that the power supply voltage pad and the negative voltage pad extending onto the protrusions are electrically connected to the binding pads in the binding area.

2. The test substrate according to claim 1, characterized in that: The protrusions include a first protrusion corresponding to the power voltage pad and a second protrusion corresponding to the negative voltage pad.

3. The test substrate according to any one of claims 1 to 2, characterized in that: The power supply voltage pad is pressed against the power supply voltage pad of the detection area of ​​the panel to be detected, and the negative electrode voltage pad is pressed against the negative electrode voltage pad of the detection area of ​​the panel to be detected.

4. The test substrate according to any one of claims 1 to 2, characterized in that: The power supply voltage pad is pressed against a power supply voltage pad of a binding area between a panel to be detected and the panel to be detected, and the negative voltage pad is pressed against a negative voltage pad of a binding area between the panel to be detected.

5. A test circuit, characterized in that: The circuit comprises: A detection module configured in the detection area of ​​the panel to be detected, a binding module configured in the binding area, and a test module configured on the test substrate; the test module includes a power supply voltage pad and a negative voltage pad, the detection module includes a detection pad, and the binding module includes a binding pad, The power supply voltage pad and the negative voltage pad in the test module are electrically connected to the detection pad in the detection module and the binding pad in the binding module, respectively; the resistance of the newly added current path is less than the resistance of the original current path, the newly added current path is a current path formed by the electrical connection between the power supply voltage pad and the negative voltage pad and the binding pad in the binding area, and the original current path is a current path formed by the electrical connection between the power supply voltage pad and the negative voltage pad and the detection pad in the detection area; Protrusions are arranged at corresponding positions of the power supply voltage pad and the negative voltage pad on the test substrate, so that the power supply voltage pad and the negative voltage pad extending onto the protrusions are electrically connected to the binding pads in the binding area.

6. The test circuit according to claim 5, characterized in that: The detection module includes a power supply voltage pad and a negative voltage pad, and the power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the detection module; the negative voltage pad in the test module is electrically connected to the negative voltage pad in the detection module.

7. The test circuit according to claim 6, characterized in that: The binding module includes a power supply voltage pad and a negative voltage pad, and the power supply voltage pad in the test module is electrically connected to the power supply voltage pad in the binding module; the negative voltage pad in the test module is electrically connected to the negative voltage pad in the binding module.

8. A display panel, characterized in that: The display panel is provided with a binding area and a detection area, and the panel is detected using the test substrate according to any one of claims 1-4.

9. A panel test assembly, characterized in that: The panel testing assembly comprises the display panel as claimed in claim 8 and the testing substrate as claimed in any one of claims 1 to 4.

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