Gate drive circuit and electroluminescent display device using the same

Abstract

An electroluminescent display device is provided. The electroluminescent display device includes a pixel circuit implemented by multiple transistors, and a gate drive circuit that provides a scan signal, an initialization signal, and a light-emission signal to the pixel circuit. The gate drive circuit includes: a scan signal generation circuit that provides a scan signal to the gate electrode of at least one of the multiple transistors; an initialization signal generation circuit that provides an initialization signal to the source electrode or drain electrode of at least one of the multiple transistors; and a light-emission signal generation circuit that provides a light-emission signal to the gate electrode of at least one of the multiple transistors. The initialization signal generation circuit receives the output signal of the scan signal generation circuit and the output signal of the light-emission signal generation circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to Korean Patent Application No. 10-2020-0181933, filed in Korea on December 23, 2020, which is hereby expressly incorporated by reference into this application in its entirety. Technical Field

[0003] The present disclosure relates to a simplified gate driving circuit and an electroluminescent display device using the same. Background Art

[0004] With the development of information technology, the market for display devices, which serve as a medium connecting users to information, continues to grow. Accordingly, the use of different types of display devices, such as electroluminescent display devices, liquid crystal display devices, organic light-emitting display devices, and quantum dot display devices, is also increasing.

[0005] Among them, electroluminescent display devices have the advantages of fast response speed, high luminous efficiency, and wide viewing angle. Typically, electroluminescent display devices use a transistor that is turned on by a scan signal to apply a data voltage to the gate electrode of a drive transistor. The data voltage applied to the drive transistor is then stored in a storage capacitor. The data voltage stored in the storage capacitor is then output using a light-emitting signal to cause the light-emitting element to emit light. Light-emitting elements can include organic light-emitting elements, inorganic light-emitting elements, and quantum dot elements.

[0006] In an electroluminescent display device, pixels each including a light emitting element are arranged in a matrix form, and the brightness of the pixels is adjusted in accordance with the grayscale of video data.

[0007] Each pixel includes a light emitting element, a driving transistor for controlling a driving current flowing through the light emitting element according to a gate-source voltage, and at least one switching transistor for programming the gate-source voltage of the driving transistor.

[0008] As an electroluminescent display device is continuously driven, a hysteresis phenomenon occurs, in which the threshold voltage Vth of the drive transistor changes. To mitigate this hysteresis phenomenon, it is necessary to apply an on-bias stress to the drive transistor. To apply the on-bias stress to the drive transistor, it is necessary to adjust the voltage level of the initialization signal even within a single frame.

[0009] Accordingly, the gate drive circuit should include a separate initialization signal generating circuit for swinging the initialization signal. Accordingly, since the electroluminescent display device includes a separate circuit for applying on-bias stress in the gate drive circuit, the frame will increase and the driving power consumption will increase. Summary of the Invention

[0010] An electroluminescent display device includes a display panel, which is the smallest device for displaying an image, and a pixel array disposed within the display panel to display the image. The display panel can be divided into a display area, which displays the image, and a non-display area, which does not. The pixel array can be disposed in the display area, and a gate driver circuit for providing at least one luminous signal and a scanning signal to the pixel array can be disposed in the non-display area.

[0011] The gate drive circuit is attached to the display panel in the form of a chip on film or a chip on glass, or the gate drive circuit can be implemented in the form of a gate within a panel (hereinafter referred to as a GIP) by combining thin film transistors in the border area of ​​the non-display area of ​​the display panel. The gate drive circuit in the form of a GIP includes a gate signal generating circuit corresponding to the number of gate lines, and each gate signal generating circuit outputs a gate pulse one-to-one to provide to the gate line corresponding thereto. The gate line provides a gate signal to the pixel array provided in the display area so that the light-emitting element can emit light. Accordingly, as the number of gate signals provided to the pixel array increases, the configuration of the gate drive circuit will be complicated and have a large area, thereby increasing the border of the display panel.

[0012] Also, as described above, in order to apply the on-bias stress to the pixel array, the configuration of the gate driving circuit may be complicated and the bezel may be increased.

[0013] Accordingly, an object of the present disclosure is to provide a gate driving circuit capable of applying on-bias stress to a driving transistor while allowing a non-display area of ​​a display panel to be reduced, and an electroluminescent display device using the same.

[0014] The objectives of the present disclosure are not limited to the above objectives, and those skilled in the art can clearly understand other objectives not mentioned above from the following description.

[0015] According to an exemplary embodiment of the present disclosure, an electroluminescent display device includes: a pixel circuit implemented by a plurality of transistors, and a gate drive circuit for providing a scan signal, an initialization signal, and a light-emitting signal to the pixel circuit, wherein the gate drive circuit includes: a scan signal generating circuit for providing a scan signal to the gate electrode of at least one transistor among the plurality of transistors; an initialization signal generating circuit for providing an initialization signal to the source electrode or drain electrode of at least one transistor among the plurality of transistors; and a light-emitting signal generating circuit for providing a light-emitting signal to the gate electrode of at least one transistor among the plurality of transistors, wherein the initialization signal generating circuit receives an output signal of the scan signal generating circuit and an output signal of the light-emitting signal generating circuit, wherein the initialization signal generating circuit and the light-emitting signal generating circuit include an n-type transistor and a p-type transistor. Accordingly, by simplifying the gate drive circuit, the border of the electroluminescent display device can be reduced.

[0016] According to an exemplary embodiment of the present disclosure, a gate drive circuit includes: a first pull-down unit controlled by a Q node; a first pull-up unit controlled by a QB node; a second pull-up unit controlled by a Q' node; a second pull-down unit controlled by a QB' node; a Q-node inverter electrically connected to the Q node and the QB node to apply an inverted voltage of the Q node to the QB node; a Q'-node inverter electrically connected to the Q' node and the QB' node to apply an inverted voltage of the Q' node to the QB' node; and a light-emitting signal inverter electrically connected to the Q' node to apply a scan signal or a voltage inverted from a light-emitting signal to the Q' node, wherein the first pull-down unit and the first pull-up unit output the light-emitting signal, and the second pull-up unit and the second pull-down unit output initialization signals. Accordingly, the gate drive circuit can be simplified, thereby allowing a reduction in the area in which the gate drive circuit is disposed.

[0017] Additional details regarding illustrative embodiments are included in the detailed description and accompanying drawings.

[0018] According to an exemplary embodiment of the present disclosure, by using a light emitting signal generating circuit that generates a light emitting signal instead of including a separate generating circuit that swings an initialization signal to apply a turn-on bias stress, a gate driving circuit can be simplified and a bezel of an electroluminescent display device can be reduced.

[0019] Furthermore, according to exemplary embodiments of the present disclosure, by implementing a gate driving circuit including both an n-type transistor and a p-type transistor, the gate driving circuit can be simplified and the bezel of the electroluminescent display device can be reduced.

[0020] Furthermore, according to exemplary embodiments of the present disclosure, a light emitting signal generating circuit and an initialization signal generating circuit are implemented using a Q node or a Q' node or a light emitting signal inverter, thereby simplifying a gate driving circuit and reducing a bezel of an electroluminescent display device.

[0021] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram of an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 2A is a block diagram illustrating a gate driving circuit provided on the left side of an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0024] Figure 2B is a block diagram illustrating a gate driving circuit provided on the right side of an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0025] Figure 3 is a circuit diagram illustrating a pixel circuit of an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0026] Figure 4 is provided to Figure 3 Waveform diagram of the signal of the pixel circuit.

[0027] Figure 5 is a circuit diagram illustrating a gate driving circuit of an electroluminescent display device according to an exemplary embodiment of the present disclosure.

[0028] Figure 6 is provided to Figure 5 The waveform diagram of the signal of the gate drive circuit.

[0029] Figure 7A According to an exemplary embodiment of the present disclosure, Figure 6 Circuit diagram of the gate drive circuit for time periods ①, ⑤, and ⑦.

[0030] Figure 7B According to an exemplary embodiment of the present disclosure, Figure 6 Circuit diagram of the gate drive circuit for time periods ②, ④, and ⑥.

[0031] Figure 7C According to an exemplary embodiment of the present disclosure, Figure 6 Circuit diagram of the gate drive circuit in period ③. DETAILED DESCRIPTION

[0032] The advantages and features of the present disclosure and methods for achieving these advantages and features will be illustrated by the following exemplary embodiments described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various forms. These exemplary embodiments are provided only as examples to enable those skilled in the art to fully understand the disclosure and scope of the present disclosure.

[0033] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals always represent the same elements. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies will be omitted so as not to unnecessarily confuse the subject matter of the present disclosure. Unless used with the term "only", terms such as "including", "having" and "comprising" used herein should generally allow for the addition of other components. Unless expressly stated otherwise, any reference to the singular may include the plural.

[0034] Even if not explicitly stated, components are interpreted as including a normal margin of error.

[0035] When terms such as "on," "above," "below," or "after" are used to describe the positional relationship between two parts, unless these terms are used together with the terms "immediately" or "directly," one or more parts may be placed between the two parts.

[0036] When an element or layer is referred to as being “on” another element or layer, the other layer or element may be directly interposed on or between the other element.

[0037] Although terms such as "first" and "second" are used to describe different components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may also be the second component.

[0038] In the description, like reference numerals generally refer to like elements throughout.

[0039] The size and thickness of each element shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the elements shown in the drawings.

[0040] The features of different embodiments of the present disclosure may be partially or completely dependent on or combined with each other, may be technically interlocked and operated in different ways, and these embodiments may be implemented in an independent manner or in an interrelated manner.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a block diagram of an electroluminescent display device 100 according to an exemplary embodiment of the present disclosure.

[0043] refer to Figure 1 In an electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, a plurality of data lines DL and a plurality of gate lines GL are provided, and the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure may include: a display panel 110 provided with a plurality of sub-pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL; and a driving circuit providing a driving signal to the display panel 110.

[0044] Although the sub-pixels PX are illustrated as being arranged in a matrix to form a pixel array, the present disclosure is not limited thereto, and the sub-pixels PX may be arranged in various forms.

[0045] The driving circuit may include a data driving circuit 120 that provides data signals to the plurality of data lines DL, a gate driving circuit GD that provides gate signals to the plurality of gate lines GL, and a controller 130 that controls the data driving circuit 120 and the gate driving circuit GD.

[0046] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA outside the display area DA. A plurality of sub-pixels PX may be disposed in the display area DA. Data lines DL for supplying data signals to the plurality of sub-pixels PX and gate lines GL for supplying gate signals may be disposed in the plurality of sub-pixels.

[0047] The plurality of data lines DL provided in the display area DA may extend to the non-display area NDA and may be electrically connected to the data driving circuit 120. The data line DL electrically connects the sub-pixels PX and the data driving circuit 120 and may be implemented as a single line or may be implemented by connecting a plurality of lines via contact holes using connection lines.

[0048] The plurality of gate lines GL provided in the display area DA may extend to the non-display area NDA and may be electrically connected to the gate drive circuit GD. The gate lines GL electrically connect the sub-pixels PX and the gate drive circuit GD. In addition, gate drive-related circuits required for the gate drive circuit GD to generate or drive gate signals may be provided in the non-display area NDA. For example, the gate drive-related circuits may include one or more high-level gate voltage lines for providing a high-level gate voltage to the gate drive circuit GD, one or more low-level gate voltage lines for providing a low-level gate voltage to the gate drive circuit GD, multiple clock lines for providing a plurality of clock signals to the gate drive circuit GD, and one or more start lines for providing one or more start signals to the gate drive circuit GD, and the like.

[0049] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL are provided in the subpixels PX. As an example, each of the plurality of data lines DL and the plurality of gate lines GL may be arranged in rows or columns. For ease of explanation, it is assumed that the plurality of data lines DL are arranged in columns, and the plurality of gate lines GL are arranged in rows.

[0050] The controller 130 starts scanning according to the timing implemented in each frame, converts input image data input from the outside to match the data signal format used by the data driving circuit 120, outputs the converted image data, and controls data driving at an appropriate time according to the scanning.

[0051] The controller 130 receives timing signals including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal, as well as an input image signal from the outside. The controller 130 generates and outputs control signals for controlling the data driving circuit 120 and the gate driving circuit GD.

[0052] For example, the controller 130 outputs various data control signals, including a source start pulse, a source sampling clock, and a source output enable signal, to control the data driver circuit 120. The source start pulse controls the data sampling start timing of one or more data signal generating circuits that comprise the data driver circuit 120. The source sampling clock is a clock signal that controls the data sampling timing of each data signal generating circuit. The source output enable signal controls the output timing of the data driver circuit 120.

[0053] In addition, the controller 130 outputs gate control signals including a gate start pulse, a gate shift clock, a gate output enable signal, and the like to control the gate drive circuit GD. The gate start pulse controls the operation start timing of one or more gate signal generating circuits constituting the gate drive circuit GD. The gate shift clock is a clock signal commonly input to one or more gate signal generating circuits and controls the shift timing of the scan signal (or gate pulse). The gate output enable signal specifies the timing information of one or more gate signal generating circuits.

[0054] The controller 130 may be a timing controller used in typical display device technology, or may be a control device that includes a timing controller and can further perform other control functions.

[0055] The controller 130 may be implemented as a component separate from the data driving circuit 120 or may be implemented as a single integrated circuit by being integrated with the data driving circuit 120 .

[0056] The data driving circuit 120 may include one or more data signal generating circuits. The data signal generating circuits may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, etc. In some cases, the data signal generating circuit may further include an analog-to-digital converter.

[0057] The data signal generating circuit may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method, be directly provided on the display panel 110, or be integrated and provided on the display panel 110. In addition, a plurality of data signal generating circuits may be implemented by a chip on film (COF) method by being mounted on a source circuit film connected to the display panel 110.

[0058] The gate driving circuit GD sequentially provides scanning signals to the plurality of gate lines GL, thereby driving the sub-pixels PX connected to the plurality of gate lines GL. The gate driving circuit GD may include a shift register, a level shifter, and the like.

[0059] The gate driver circuit GD may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method, or may be implemented as a GIP type and provided so as to be integrated in the display panel 110. Furthermore, a plurality of gate signal generating circuits may be implemented by a chip on film (COF) method by being mounted on a gate circuit film connected to the display panel 110. For ease of explanation, an example is hereinafter given in which the gate driver circuit GD includes a plurality of gate signal generating circuits, and the plurality of gate signal generating circuits are implemented as a GIP type and provided in the non-display area NDA of the display panel 110.

[0060] The gate driving circuit GD sequentially supplies scan signals of a transistor-on voltage or a transistor-off voltage to the plurality of gate lines GL according to the control of the controller 130. When a specific gate line is turned on by the gate driving circuit GD, the data driving circuit 120 converts image data received from the controller 130 into a data signal in an analog format and supplies the data signal to the plurality of data lines DL.

[0061] The data driving circuit 120 may be located on one side of the display panel 110. For example, the data driving circuit 120 may be located on the upper side, lower side, left side, or right side of the display panel 110. Furthermore, depending on a driving method and a panel design method, etc., the data driving circuit 120 may be located on both sides of the display panel 110. For example, the data driving circuit 120 may be located on both the upper side and the lower side or on both the left side and the right side of the display panel 110.

[0062] The gate driving circuit GD may be located on one side of the display panel 110. For example, the gate driving circuit GD may be located on the upper side, lower side, left side, or right side of the display panel 110. Furthermore, depending on the driving method and panel design method, etc., the data driving circuit 120 may be located on both sides of the display panel 110. For example, the data driving circuit 120 may be located on both the upper side and the lower side of the display panel 110, or on both the left side and the right side of the display panel 110.

[0063] The following description uses as an example a case where the data driver circuit 120 is located on the upper side of the display panel 110 and the gate driver circuit GD is located on the left and right sides of the display panel 110. In this case, in the display panel 110, the gate driver circuit GD includes a first gate driver circuit GDL located on the left side of the display panel 110 and a second gate driver circuit GDR located on the right side of the display panel 110. The width of the area occupied by the first gate driver circuit GDL can be referred to as a first width WL, and the width of the area occupied by the second gate driver circuit GDR can be referred to as a second width WR. The size of the frame of the electroluminescent display device 100 can be changed according to the corresponding widths WL and WR of the first gate driver circuit GDL and the second gate driver circuit GDR. Since the aesthetic effect of the electroluminescent display device 100 is improved as the frame becomes smaller, it is advantageous to simplify the gate driver circuit GD to reduce the frame.

[0064] The plurality of gate lines GL provided on the display panel 110 may include a plurality of scan lines and a plurality of emission signal lines, etc. The plurality of scan lines and the plurality of emission signal lines are lines that transmit different types of gate signals to corresponding gate nodes of different transistors.

[0065] Accordingly, the gate driving circuit GD includes a plurality of scanning driving circuits for outputting scanning signals to a plurality of scanning lines as one type of gate lines GL, and a plurality of light emitting driving circuits for outputting light emitting signals to a plurality of light emitting signal lines as another type of gate lines GL.

[0066] Figure 2A is a block diagram illustrating a first gate driving circuit GDL disposed on the left side of the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure. Figure 2B is a block diagram illustrating a second gate driving circuit GDR disposed on the right side of the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure.

[0067] The display area DA includes a plurality of sub-pixels PX, and displays an image based on the grayscale displayed by each sub-pixel PX. Each sub-pixel PX is connected to a data line DL arranged along a column line and to a gate line GL arranged along a pixel row. In this case, the sub-pixels PX located on the same row line are referred to as pixel rows PG, and the sub-pixels PX located on the same pixel row share the same gate line GL and receive gate signals at the same time. Accordingly, the sub-pixel PX connected to the first gate line may be referred to as the first pixel row, and the sub-pixel PX connected to the n-th gate line may be referred to as the n-th pixel row PG(n). When the number of pixel rows set in the display area DA is n, the first pixel row to the n-th pixel row are driven sequentially in synchronization with the gate signal generating circuit. In this case, the gate drive circuit GD is composed of gate signal generating circuits corresponding to the number of pixel rows.

[0068] As described above, the display panel 110 includes a display area DA where an image is displayed based on the sub-pixels PX, and a non-display area NDA where signal lines, a driver, and the like are located where an image is not displayed.

[0069] The subpixel PX includes a light-emitting element and a pixel circuit for controlling the amount of current applied to the anode of the light-emitting element. The pixel circuit may include a drive transistor for controlling the amount of current so that a predetermined current flows through the light-emitting element. The light-emitting element emits light during a light-emitting period and does not emit light during periods outside of the light-emitting period. During periods outside of the light-emitting period, the pixel circuit may be initialized, a scan signal may be input to the pixel circuit, and a programming period and a pixel circuit compensation period may be implemented. For example, pixel circuit compensation may include threshold voltage compensation for the drive transistor. During periods outside of the light-emitting period, the light-emitting element should not emit light because a current sufficient to emit light at a specific brightness is not constantly supplied. For example, in a method for disabling light-emitting elements, a light-emission control transistor may be connected between the anode of the light-emitting element and the drive transistor. The light-emission control transistor is connected to a light-emission signal line and is controlled by a light-emission signal output by a light-emission signal generation circuit. During the light-emission period, the light-emission signal may be an on-voltage, and during periods outside of the light-emission period, the light-emission signal may be an off-voltage.

[0070] The gate signals used to drive the subpixels PX included in the display panel 110 include scan signals and emission signals. Accordingly, the gate drive circuit GD may separately include a scan drive circuit that provides scan signals and a emission drive circuit that provides emission signals. The scan signals are applied to the pixel rows PG via scan lines, and the emission signals are applied to the pixel rows PG via emission signal lines.

[0071] As described above, in order to apply a conduction bias stress to reduce the hysteresis of the drive transistor of the electroluminescent display device 100, the initialization signal can be increased from a low level to a high level within a frame. Therefore, in some embodiments, the gate drive circuit GD may include a separate gate signal generation circuit for swinging the initialization signal. In this case, the gate drive circuit GD includes a separate gate signal generation circuit for swinging the initialization signal to apply a conduction bias stress to the pixel circuit. As a result, the gate drive circuit GD may be complex and the bezel of the electroluminescent display device 100 may be increased.

[0072] However, in the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, the bezel may be reduced by simplifying a separate gate signal generating circuit.

[0073] Accordingly, if Figure 2A and 2B As shown, the first gate driving circuit GDL that provides a gate signal to the nth pixel row PG(n) and is arranged on the left side of the display area DA may include an odd-numbered second scanning signal generating circuit SDC2O(n), an even-numbered second scanning signal generating circuit SDC2E(n) and a light-emitting signal generating circuit EDC(n).

[0074] The second gate driving circuit GDR, which provides gate signals to the nth pixel row PG(n) and is arranged on the right side of the display area DA, may include an odd-numbered second scan signal generating circuit SDC2O(n), an even-numbered second scan signal generating circuit SDC2E(n) and a first scan signal generating circuit SDC1(n).

[0075] By using the output signal of the light-emitting signal generating circuit EDC(n) to implement the initialization signal generating circuit VDC(n) for swinging the initialization signal provided to the pixel circuit, the first gate driver circuit GDL can be simplified. In this case, the first width WL of the first gate driver circuit GDL can be reduced by tens of micrometers.

[0076] The third scanning signal and the first scanning signal are provided to the reference Figure 3 The pixel circuit described above is implemented by using the output signal of the first scan signal generating circuit SDC1(n) to implement the third scan signal generating circuit SDC3(n), thereby simplifying the second gate driving circuit GDR. In this case, the second width WR of the second gate driving circuit GDR can be reduced by tens of micrometers.

[0077] Accordingly, since the respective widths of the first gate driving circuit GDL and the second gate driving circuit GDR are reduced by tens of micrometers, the bezel width of the electroluminescent display device 100 can be reduced by tens to hundreds of micrometers.

[0078] Figure 3 is a circuit diagram illustrating a pixel circuit of the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure. Figure 4 is provided to Figure 3 The waveform diagram of the signal of the pixel circuit is shown in FIG. The sub-pixel PX arranged on the n-th pixel row PG(n) is used as an example to illustrate Figure 3 The pixel circuit shown.

[0079] Each sub-pixel PX includes a light emitting element EL and a pixel circuit, and the pixel circuit includes a driving transistor T1 , second to seventh transistors T2 to T7 , and a storage capacitor Cst.

[0080] The light-emitting element EL emits light by the driving current provided from the driving transistor T1. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the light-emitting element EL. The organic compound layer may include at least one hole transport layer and an electron transport layer and a light-emitting layer. Here, the hole transport layer is a layer that injects or transports holes to the light-emitting layer, and as an example, it can be a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, the electron transport layer is a layer that injects or transports electrons to the light-emitting layer, and as an example, it can be an electron transport layer, an electron injection layer, and a hole blocking layer. The anode electrode of the light-emitting element EL is connected to the fourth node N4, and the cathode electrode of the light-emitting element EL is connected to a line that provides a low-potential driving voltage VSS.

[0081] The driving transistor T1 controls the driving current applied to the light-emitting element EL according to the source-gate voltage Vsg. The driving transistor T1 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. Furthermore, the source electrode of the driving transistor T1 is connected to a first node N1, the gate electrode of the driving transistor T1 is connected to a second node N2, and the drain electrode of the driving transistor T1 is connected to a third node N3. The driving transistor T1 may be referred to as a first transistor.

[0082] The second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor T1. The second transistor T2 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The second transistor T2 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to a second scan signal line that transmits a second scan signal Scan2(n). Accordingly, the second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor T1, in response to the second scan signal Scan2(n) of a low level (on-state voltage).

[0083] The third transistor T3 is connected to the gate electrode and drain electrode of the driving transistor T1 in a diode manner. The third transistor T3 can be an n-type MOSFET (NMOS) and can be implemented as an oxide thin film transistor to minimize leakage current during the off period. The third transistor T3 includes a drain electrode or a source electrode connected to the third node N3, a source electrode or a drain electrode connected to the second node N2, and a gate electrode connected to the first scan signal line that transmits the first scan signal Scan1(n). Accordingly, the third transistor T3 is connected to the gate electrode and the drain electrode of the driving transistor T1 in a diode manner in response to the first scan signal Scan1(n) of a high level (on-state voltage).

[0084] The fourth transistor T4 applies an initialization signal Vini(n) to the third node N3, which serves as the drain electrode of the driving transistor T1. The fourth transistor T4 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The fourth transistor T4 includes a source electrode connected to an initialization signal line that transmits the initialization signal Vini(n), a drain electrode connected to the third node N3, and a gate electrode connected to a third scan signal line that transmits the third scan signal Scan3(n). Accordingly, the fourth transistor T4 applies the initialization signal Vini(n) to the third node N3, which serves as the drain electrode of the driving transistor T1, in response to the third scan signal Scan3(n) of a low level (on-state voltage).

[0085] The fifth transistor T5 applies a high-potential driving voltage VDD to the first node N1, which serves as the source electrode of the driving transistor T1. The fifth transistor T5 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The fifth transistor T5 includes a source electrode connected to a high-potential driving voltage line that transmits the high-potential driving voltage VDD, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line that transmits the light-emitting signal EM(n). Accordingly, the fifth transistor T5 applies the high-potential driving voltage VDD to the first node N1, which serves as the source electrode of the driving transistor T1, in response to the low-level (on-state voltage) light-emitting signal EM(n).

[0086] The sixth transistor T6 forms a current path between the driving transistor T1 and the light-emitting element EL. The sixth transistor T6 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The sixth transistor T6 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light-emitting signal line that transmits the light-emitting signal EM(n). In response to the light-emitting signal EM(n), the sixth transistor T6 forms a current path between the third node N3, which serves as the source electrode of the sixth transistor T6, and the fourth node N4, which serves as the drain electrode of the sixth transistor T6. Accordingly, the sixth transistor T6 forms a current path between the driving transistor T1 and the light-emitting element EL in response to the light-emitting signal EM(n) at a low level (on-state voltage).

[0087] The seventh transistor T7 applies a reset voltage VAR to the fourth node N4, which serves as the anode electrode of the light-emitting element EL. The seventh transistor T7 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The seventh transistor T7 includes a source electrode connected to a reset voltage line that transmits the reset voltage VAR, a drain electrode connected to the fourth node N4, and a gate electrode connected to a third scan signal line that transmits the third scan signal Scan3(n+1). Accordingly, the seventh transistor T7 applies the reset voltage VAR to the fourth node N4, which serves as the anode electrode of the light-emitting element EL, in response to the third scan signal Scan3(n+1) provided to the (n+1)th pixel row and having a low level (on-level).

[0088] The storage capacitor Cst maintains the data voltage Vdata stored in each subpixel PX during one frame. The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to a high-potential driving voltage line that transmits the high-potential driving voltage VDD. In other words, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor T1, and the other electrode of the storage capacitor Cst is connected to the high-potential driving voltage line that transmits the high-potential driving voltage VDD.

[0089] The following will refer to Figure 3 and 4 Driving of the sub-pixel PX of the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure will be described.

[0090] The electroluminescent display device 100 can be driven separately in a refresh frame and an anode reset frame. In the refresh frame, the data voltage Vdata is programmed in each subpixel PX, and the light-emitting element EL emits light. The anode reset frame can be a vertical blank frame, and the anode electrode of the light-emitting element EL is reset in the anode reset frame.

[0091] In the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, the refresh frame and the anode reset frame may include a plurality of on-bias stress periods OBS (hereinafter referred to as stress periods). The stress period OBS is a period in which bias stress is applied to the third node N3, which is the drain electrode of the driving transistor T1. Figure 4 As shown, in the stress period OBS of the refresh frame and the anode reset frame, the initialization signal Vini(n) is at a high level, and the third scan signal Scan3(n) is at a low level as a turn-on voltage.

[0092] In the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, a refresh frame can be divided into an initialization period Initial, a sampling period Sampling, and a light emission period Emission. The initialization period Initial is a period for initializing the voltage of the third node N3, which is the drain electrode of the driving transistor T1. The sampling period Sampling is a period for sampling the threshold voltage Vth of the driving transistor T1 and programming the data voltage Vdata. The light emission period Emission is a period for the light emitting element EL to emit light according to the driving current generated by the programmed source-gate voltage Vsg of the driving transistor T1. And, as Figure 4 As shown in FIG, in the initialization period of the refresh frame, the initialization signal Vini(n) is at a low level, and the third scan signal Scan3(n) is also at a low level as a turn-on voltage. In addition, in the sampling period, the initialization signal Vini(n) is at a high level, and the third scan signal Scan3(n) is at a high level as a turn-off voltage. In the light-emitting period, the initialization signal Vini(n) is at a low level, and the third scan signal Scan3(n) is at a high level as a turn-off voltage.

[0093] In particular, refer to Figure 3 and Figure 4 During the stress period OBS of the refresh frame and the anode reset frame, the third scan signal Scan3(n) is at a low level, serving as a turn-on voltage. During the refresh frame and the anode reset frame that include multiple stress periods OBS, the third scan signal Scan3(n) may have a waveform including multiple pulses. Furthermore, during the multiple stress periods OBS, the bias stress of the drive transistor T1 can be reduced by switching the initialization signal Vini(n) from a low level to a high level and providing the initialization signal Vini(n) to the third node N3, serving as the drain electrode of the drive transistor T1. The high-level initialization signal Vini(n) can be selected within a voltage range sufficiently higher than the operating voltage of the light-emitting element EL and can be set to a voltage equal to or lower than the high-potential drive voltage VDD. That is, during the stress period OBS, a turn-on bias stress can be applied to the third node N3, serving as the drain electrode of the drive transistor T1, thereby reducing the source-drain voltage Vsd of the drive transistor T1. Accordingly, during the stress period OBS, the influence of hysteresis can be reduced by reducing the charge characteristics of the channel portion of the driving transistor T1 to the same voltage. In this case, during the stress period OBS, the voltage applied to the drain electrode of the driving transistor T1 is the same voltage.

[0094] In the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, the anode reset frame may include an anode reset period. During the anode reset period, the seventh transistor T7 is turned on by the (n+1)th third scan signal Scan3(n+1) and applies a reset voltage VAR to the fourth node N4. That is, the anode electrode of the light-emitting element EL is reset to the reset voltage VAR. In this case, the reset voltage VAR is a voltage equal to or lower than the low-potential drive voltage VSS, and the light-emitting element EL can maintain the same luminous characteristics in the refresh frame and the anode reset frame and prevent screen flickering. The anode reset period may also be included in the refresh frame.

[0095] Furthermore, during the anode reset frame, the initialization signal Vini(n) may be at a high level. The high-level third scan signal Scan3(n) is applied to the gate electrode of the fourth transistor T4, and the high-level initialization signal Vini(n) is applied to the source electrode of the fourth transistor T4. This reduces the potential difference between the gate electrode and the source electrode of the fourth transistor T4. Accordingly, during the anode reset frame, the leakage current of the fourth transistor T4 may be reduced or minimized.

[0096] In the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, during the initialization period Initial of a refresh frame, the first scan signal Scan1(n) is at a high level, which is a turn-on voltage, and the third scan signal Scan3(n) is at a low level, which is a turn-on voltage. Accordingly, the third transistor T3 and the fourth transistor T4 are turned on and apply the initialization signal Vini(n) to the third node N3 and the second node N2. As a result, the gate electrode and the drain electrode of the driving transistor T1 are initialized by the initialization signal Vini(n). During the initialization period Initial of the refresh frame, a low-level initialization signal Vini(n) can be selected within a voltage range sufficiently lower than the operating voltage of the light-emitting element EL, and the low-level initialization signal Vini(n) can be set to a voltage equal to or lower than the low-potential driving voltage VSS.

[0097] Subsequently, in a sampling period Sampling of a refresh frame, the first scan signal Scan1(n) is at a high level as a turn-on voltage, and the second scan signal Scan2(n) is at a low level as a turn-on voltage. In a sampling period Sampling of a refresh frame, the first scan signal Scan1(n) is at a high level as a turn-on voltage, the odd-numbered second scan signal Scan2O(n) is at a low level as a turn-on voltage, and the even-numbered second scan signal Scan2E(n) is at a low level as a turn-on voltage.

[0098] Accordingly, during the sampling period (Sampling), the second transistor T2 is turned on, and the data voltage Vdata is applied to the first node N1. Furthermore, since the third transistor T3 is also turned on, the driving transistor T1 is diode-connected, with the gate and drain electrodes of the driving transistor T1 short-circuited, causing the driving transistor T1 to operate like a diode. During the sampling period (Sampling), the driving transistor T1 is turned on, and a current Ids flows between the source and drain electrodes. Since the gate and drain electrodes of the driving transistor T1 are in a diode-connected state, the voltage at the second node N2 rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage Vgs of the driving transistor T1 reaches the threshold voltage Vth. During the sampling period (Sampling), the voltage at the second node N2 is charged to a voltage Vdata-|Vth| corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving transistor T1.

[0099] Subsequently, during the emission period Emission of the refresh frame, the emission signal EM(n) is at a low level, serving as a turn-on voltage. Accordingly, the fifth transistor T5 is turned on, and the high-potential drive voltage VDD is applied to the first node N1. Furthermore, the sixth transistor T6 is also turned on, thereby forming a current path between the third node N3 and the fourth node N4. As a result, the drive current Ioled generated by the source and drain electrodes of the drive transistor T1 is applied to the light-emitting element EL. During the emission period Emission, the drive current Ioled flowing through the light-emitting element EL is expressed as follows [Equation 1].

[0100] [Equation 1] Ioled = k / 2(Vgs + |Vth|) 2 =k / 2(Vdata-VDD) 2

[0101] In [Equation 1], k / 2 represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor T1.

[0102] As shown in [Equation 1], the threshold voltage Vth component of the driving transistor T1 is removed from the relationship between the driving current Ioled. This means that in the display device according to the present disclosure, even if the threshold voltage Vth changes, the driving current Ioled does not change. As described above, regardless of the amount of change in the threshold voltage Vth, the display device according to the present disclosure can program the data voltage during the sampling period.

[0103] As described above, in the anode reset frame and the refresh frame, the anode electrode of the light emitting element EL is reset to the reset voltage VAR.

[0104] As a result, in the electroluminescent display device 100 according to the exemplary embodiment of the present disclosure, the anode electrode of the light-emitting element EL can be periodically reset in the refresh frame and the anode reset frame. Accordingly, even when driven at a low frequency, the voltage of the anode electrode of the light-emitting element EL can be prevented from continuously increasing due to leakage current, so that the anode electrode of the light-emitting element EL can maintain a constant voltage level. Accordingly, even when the driving frequency is switched to a low frequency, the brightness variation of the electroluminescent display device 100 is minimized, thereby improving image quality.

[0105] Figure 5 is a circuit diagram illustrating a gate driving circuit of the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure.

[0106] In order to apply an on-bias stress to the driving transistor of the electroluminescent display device 100 and raise the initialization signal from a low level to a high level during a frame, the electroluminescent display device 100 may include a gate drive circuit GD composed of a separate gate signal generation circuit for swinging the initialization signal. In this case, the width of the gate drive circuit GD may increase due to the additional circuit, but to prevent this, a light emitting signal generation circuit may be used.

[0107] Accordingly, a lighting signal generating circuit EDC(n) that provides the lighting signal EM(n) and an initialization signal generating circuit VDC(n) that provides the initialization signal Vini(n) using the lighting signal generating circuit EDC(n) will be described below.

[0108] refer to Figure 5 The light emitting signal generating circuit EDC(n) includes a first pull-down unit PDE, a first pull-up unit PUE, a Q-node holding unit QS, a Q2-node controller Q2C, and a Q-node inverter QI.

[0109] The first pull-down unit PDE outputs a light-emission signal EM(n) as a turn-on voltage in response to the voltage of the Q node, and the first pull-up unit PUE outputs a light-emission signal EM(n) as a turn-off voltage in response to the voltage of the QB node. Furthermore, the light-emission signal EM(n) determined by the first pull-down unit PDE and the first pull-up unit PUE is applied to the n-th pixel row PG(n).

[0110] The Q-node holding unit QS is connected between the Q-node and the Q2-node and acts as a buffer to prevent sudden changes in the voltage applied to the Q-node. The Q-node holding unit QS continuously electrically connects the Q-node and the Q2-node. Accordingly, the voltage of the Q2-node is kept at the same level as the voltage of the Q-node.

[0111] The Q2 node controller Q2C is a component for charging or discharging the Q2 node and uses the start signal EVST to apply an on-voltage or off-voltage to the Q2 node. When n is a natural number greater than or equal to 2, the Q2 node controller Q2C can use the output signal EM(n-1) of the (n-1)th emission signal generating circuit EDC(n-1) as the start signal.

[0112] The Q node inverter QI applies an inverted voltage of the Q node to the QB node according to the Q2 node voltage applied by the Q2 node controller Q2C. Here, the inverted voltage of the Q node is a voltage with a phase opposite to that of the voltage of the Q node.

[0113] The initialization signal generating circuit VDC(n) includes a second pull-up unit PUV, a second pull-down unit PDV, a QB′ node holding unit QB′S, a light emitting signal inverter EI, and a Q′ node inverter Q′I.

[0114] The second pull-up unit PUV outputs an initialization signal Vini(n) of a high level voltage in response to the voltage of the Q' node, and the second pull-down unit PDV outputs an initialization signal Vini(n) of a low level voltage in response to the voltage of the QB' node. Furthermore, the initialization signal Vini(n) determined by the second pull-up unit PUV and the second pull-down unit PDV is applied to the n-th pixel row PG(n).

[0115] The QB' node holding unit QB'S is connected between the QB' node and the QB'2 node and acts as a buffer to prevent sudden changes in the voltage applied to the QB' node. The QB' node holding unit QB'S continuously electrically connects the QB' node and the QB'2 node. Accordingly, the voltage of the QB'2 node is maintained at the same level as the voltage of the QB' node.

[0116] The lighting signal inverter EI applies the first scan signal Scan1 (n) or a voltage inverted from the lighting signal EM(n) to the Q' node according to the lighting signal EM(n) output by the lighting signal generating circuit EDC(n).

[0117] The Q' node inverter Q'I applies an inverted voltage of the Q' node to the QB'2 node according to the voltage of the Q' node applied by the light emitting signal inverter EI. Here, the inverted voltage of the Q' node is a voltage with a phase opposite to that of the voltage of the Q' node.

[0118] At the same time, the aforementioned turn-off voltage can be changed according to the type of transistor to which the turn-off voltage is applied. For p-type transistors, the turn-off voltage is at a high level, and for n-type transistors, the turn-off voltage is at a low level. In addition, for p-type transistors, the turn-on voltage is at a low level, and for n-type transistors, the turn-on voltage is at a high level. According to the illustrated embodiment of the present disclosure, the gate signal generating circuit includes an n-type transistor and a p-type transistor. The luminous signal EM(n) and the initialization signal Vini(n) as the output signals of the gate signal generating circuit are provided to the pixel circuit included in the n-th pixel row PG(n). The specific circuit structure and operation of the gate signal generating circuit will be described below.

[0119] Figure 6 is provided to Figure 5 The waveform diagram of the signal of the gate drive circuit. Figure 7A According to an exemplary embodiment of the present disclosure Figure 6 Circuit diagram of the gate drive circuit for time periods ①, ⑤, and ⑦. Figure 7B According to an exemplary embodiment of the present disclosure Figure 6 Circuit diagram of the gate drive circuit for time periods ②, ④, and ⑥. Figure 7C According to an exemplary embodiment of the present disclosure Figure 6 FIG. 1 is a circuit diagram of a gate drive circuit during period ③ in FIG. In this example, the gate drive circuit specifically refers to a gate signal generating circuit.

[0120] As described above, the electroluminescent display device 100 according to the exemplary embodiment of the present disclosure can be driven separately in the refresh frame and the anode reset frame. In the description of driving the light emitting signal generating circuit EDC(n) and the initialization signal generating circuit VDC(n), the refresh frame can be divided into periods ①, ②, ③, ④, and ⑤, and the anode reset frame can be divided into periods ⑤, ⑥, and ⑦.

[0121] Figure 5 、 6 7A and 7B show the driving of the emission signal generating circuit EDC(n) and the initialization signal generating circuit VDC(n) in the periods ①, ⑤, and ⑦ when the light emitting element EL emits light. In the periods ①, ⑤, and ⑦, the emission signal generating circuit EDC(n) outputs the emission signal EM(n) of low level, and the initialization signal generating circuit VDC(n) outputs the initialization signal Vini(n) of low level.

[0122] In the refresh frame and the anode reset frame periods ①, ⑤ and ⑦, the Q2 node controller Q2C provides a low-level voltage to the Q2 node. The Q2 node controller Q2C is controlled by the clock signal ECLK and provides the start signal EVST or the light-emitting signal EM(n-1) of the previous row to the Q2 node. The Q2 node controller Q2C can be implemented as a first transistor T1. The first transistor T1 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. In this case, since the start signal EVST and the clock signal ECLK are at a low level, the Q2 node controller Q2C is turned on and the low level is transmitted to the Q2 node. Moreover, even if the clock signal ECLK is switched to a high level, the Q2 node will remain at a low level.

[0123] During the refresh frame and the anode reset frame periods ①, ⑤, and ⑦, the Q node holding unit QS electrically connects the Q node and the Q2 node. The Q node holding unit QS is controlled by the first low voltage VGL1 and electrically connects the Q node and the Q2 node. The Q node holding unit QS can be implemented as a second transistor T2. The second transistor T2 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. Since the first low voltage VGL1 is applied to the gate electrode of the second transistor T2, the second transistor T2 always remains in an on state and electrically connects the Q node and the Q2 node.

[0124] In the time periods ①, ⑤ and ⑦ of the refresh frame and the anode reset frame, the first pull-down unit PDE applies the first low voltage VGL1 to the first output node EV. The first pull-down unit PDE is controlled by the Q node and provides the first low voltage VGL1 to the first output node EV. The first pull-down unit PDE can be implemented as a fifth transistor T5 and a Q-node capacitor CQ. The fifth transistor T5 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The Q-node capacitor CQ is connected to the gate electrode and the drain electrode of the fifth transistor T5. The Q-node capacitor CQ quickly applies the first low voltage VGL1 to the first output node EV through the bootstrap effect. Since the first output node EV is connected to the line that provides the light-emitting signal EM(n), the light-emitting signal EM(n) is the first low voltage VGL1 in the time periods ①, ⑤ and ⑦.

[0125] At the same time, in the periods ①, ⑤ and ⑦ of the refresh frame and the anode reset frame, the Q node inverter QI provides the inverted voltage of the Q node to the QB node to make the QB node become a high level state. The Q node inverter QI includes a third transistor T3 and a fourth transistor T4. The third transistor T3 can be an n-type MOSFET (NMOS) and can be implemented as an oxide thin film transistor, and the fourth transistor T4 can be a p-type MOSFET (PMOS) and can be implemented as a low temperature polycrystalline silicon (LTPS) thin film transistor. The third transistor T3 is turned off by the low level of the Q node, and the fourth transistor T4 is turned on by the low level of the Q2 node. The turned-on fourth transistor T4 applies the first high voltage VGH1 to the QB node. That is, in the periods ①, ⑤ and ⑦, the Q node is at a low level, and the QB node is at a high level due to the Q node inverter QI.

[0126] In the periods ①, ⑤ and ⑦ of the refresh frame and the anode reset frame, the first pull-up unit PUE is controlled by the QB node and prevents the first high voltage VGH1 from being output to the first output node EV. The first pull-up unit PUE can be implemented as a sixth transistor T6 and a QB node capacitor CQB. The sixth transistor T6 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The QB node capacitor CQB is connected to the gate electrode and the source electrode of the sixth transistor T6. The first pull-up unit PUE is turned off by the first high voltage VGH1 of the QB node, and the first high voltage VGH1 is not applied to the first output node EV.

[0127] During the refresh frame and the anode reset frame, the light signal inverter EI is controlled by the light signal EM(n) and provides a voltage that is opposite to the light signal EM(n) to the Q' node. The light signal inverter EI can be implemented as a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 can be an n-type MOSFET (NMOS) and can be implemented as an oxide thin film transistor, and the eighth transistor T8 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin film transistor. The seventh transistor T7 is controlled by the light signal EM(n) and provides the first scan signal Scan1(n) to the Q' node. The eighth transistor T8 is controlled by the light signal EM(n) and provides the first high voltage VGH1 to the Q' node. During the periods 1, 5, and 7, the light signal EM(n) is the first low voltage VGL1, and the first scan signal Scan1(n) is at a low level, thereby turning off the seventh transistor T7 and turning on the eighth transistor T8. Accordingly, the light emitting signal inverter EI provides the first high voltage VGH1 inverted to the light emitting signal EM(n) of the first low voltage VGL1 to the Q' node.

[0128] In the periods ①, ⑤ and ⑦ of the refresh frame and the anode reset frame, the second pull-up unit PUV is controlled by the Q' node and prevents the second high voltage VGH2 from being output to the second output node DV. The second pull-up unit PUV can be implemented as a twelfth transistor T12 and a Q' node capacitor CQ'. The twelfth transistor T12 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The Q' node capacitor CQ' is connected to the gate electrode and the source electrode of the twelfth transistor T12. The second pull-up unit PUV is turned off by the first high voltage VGH1 of the Q' node, and the second high voltage VGH2 is not applied to the second output node DV.

[0129] In the refresh frame and the anode reset frame, during the periods ①, ⑤, and ⑦, the Q' node inverter Q'I provides the inverted voltage of the Q' node to the QB'2 node, so the QB'2 node becomes a low-level state. The Q' node inverter Q'I includes a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polysilicon (LTPS) thin-film transistor, and the tenth transistor T10 can be an n-type MOSFET (NMOS) and can be implemented as an oxide thin-film transistor. The ninth transistor T9 is turned off by the first high voltage VGH1 of the Q' node, and the tenth transistor T10 is turned on by the first high voltage VGH1 of the Q' node. The turned-on tenth transistor T10 applies the first low voltage VGL1 to the QB'2 node. That is, in the periods ①, ⑤, and ⑦, the Q' node is at a high level (or the first high voltage VGH1), and the QB'2 node is at a low level (or the first low voltage VGL1) due to the Q' node inverter Q'I.

[0130] In the refresh frame and the anode reset frame periods ①, ⑤ and ⑦, the QB' node holding unit QB'S electrically connects the QB' node and the QB'2 node. The QB' node holding unit QB'S is controlled by the first low voltage VGL1 and electrically connects the QB' node and the QB'2 node. The QB' node holding unit QB'S can be implemented as an eleventh transistor T11. The eleventh transistor T11 can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polysilicon (LTPS) thin-film transistor. Since the first low voltage VGL1 is provided to the gate electrode of the eleventh transistor T11, the eleventh transistor T11 always remains in the on state and electrically connects the QB' node and the QB'2 node. Since the QB'2 node is in the state of the first low voltage VGL1 due to the Q' node inverter Q'I in the periods ①, ⑤ and ⑦, the QB' node also becomes the first low voltage VGL1 due to the QB' node holding unit QB'S.

[0131] In the periods ①, ⑤ and ⑦ of the refresh frame and the anode reset frame, the second pull-down unit PDV applies the second low voltage VGL2 to the second output node DV. The second pull-down unit PDV is controlled by the QB' node and provides the second low voltage VGL2 to the second output node DV. The second pull-down unit PDV can be implemented as a thirteenth transistor T13 and a QB' node capacitor CQB'. The thirteenth transistor T13 can be a p-type MOSFET (PMOS) and implemented as a low-temperature polysilicon (LTPS) thin-film transistor. The QB' node capacitor CQB' is connected to the gate electrode and the drain electrode of the thirteenth transistor T13. The QB' node capacitor CQB' quickly applies the second low voltage VGL2 to the second output node DV through the bootstrap effect. Since the second output node DV is connected to the line that provides the initialization signal Vini(n), the initialization signal Vini(n) is the second low voltage VGL2 in the periods ①, ⑤ and ⑦.

[0132] The first low voltage VGL1 and the first high voltage VGH1 are used as driving voltages for driving the gate drive circuit, respectively, and can be referred to as a low level and a high level. On the other hand, the second low voltage VGL2 and the second high voltage VGH2 are voltages different from the first low voltage VGL1 and the first high voltage VGH1, respectively, and are used as voltages for implementing the initialization signal Vini(n). Accordingly, the second high voltage VGH2 is lower than the first high voltage VGH1 and is a voltage similar to the level of the black voltage so as to affect the on-state bias stress of the transistor. In addition, the second low voltage VGL2 is higher than the first low voltage VGL1 and is a voltage similar to the level of the low potential drive voltage VSS.

[0133] Figure 5 、 6 7B and 7C show the driving of the emission signal generating circuit EDC(n) and the initialization signal generating circuit VDC(n) in periods 2, 4, and 6. In periods 2, 4, and 6, the on-bias voltage is applied to the drive transistor. In periods 2, 4, and 6, the emission signal generating circuit EDC(n) outputs a high-level emission signal EM(n), and the initialization signal generating circuit VDC(n) outputs a high-level initialization signal Vini(n).

[0134] During the refresh frame and anode reset frame periods ②, ④, and ⑥, the Q2 node controller Q2C provides a high-level voltage to the Q2 node. The Q2 node controller Q2C is controlled by the clock signal ECLK and provides the start signal EVST or the previous row's emission signal EM(n-1) to the Q2 node. In this case, since the clock signal ECLK is at a low level and the start signal EVST is at a high level, the Q2 node controller Q2C is turned on and transmits a high level to the Q2 node.

[0135] Even in periods ②, ④, and ⑥ of the refresh frame and the anode reset frame, the Q-node holding unit QS electrically connects the Q-node and the Q2-node.

[0136] In the refresh frame and the anode reset frame, the first pull-down unit PDE is controlled by the Q node and blocks the first low voltage VGL1 from being output. The first pull-down unit PDE is turned off by the high voltage of the Q node and does not apply the first low voltage VGL1 to the first output node EV.

[0137] At the same time, during periods ②, ④, and ⑥ of the refresh frame and the anode reset frame, since the Q-node inverter QI provides the inverted voltage of the Q-node to the QB node, the QB node becomes a low-level state. The third transistor T3 constituting the Q-node inverter QI is turned on by the high level of the Q-node, and the fourth transistor T4 is turned off by the high level of the Q2 node. The turned-on third transistor T3 applies the first low voltage VGL1 to the QB node. That is, during periods ②, ④, and ⑥, the Q-node is at a high level, and the QB node becomes a low level due to the Q-node inverter QI.

[0138] In the refresh frame and the anode reset frame, the first pull-up unit PUE is controlled by the QB node and transmits the first high voltage VGH1 to the first output node EV. The sixth transistor T6 constituting the first pull-up unit PUE is turned on by the first low voltage VGL1 of the QB node and applies the first high voltage VGH1 to the first output node EV. The QB node capacitor CQB quickly applies the first high voltage VGH1 to the first output node EV through the bootstrap effect and maintains the voltage of the QB node at the first low voltage VGL1. Since the first output node EV is connected to the line that provides the light-emitting signal EM(n), the light-emitting signal EM(n) is the first high voltage VGH1 in the periods ②, ④, and ⑥.

[0139] During periods ②, ④, and ⑥ of the refresh frame and the anode reset frame, the luminescence signal inverter EI is controlled by the luminescence signal EM(n) and provides the first scan signal Scan1(n) to the Q' node. The seventh transistor T7 constituting the luminescence signal inverter EI is turned on by the first high voltage VGH1 of the luminescence signal EM(n) and provides the first scan signal Scan1(n) to the Q' node. The eighth transistor T8 is turned off by the first high voltage VGH1 of the luminescence signal EM(n). Since the first scan signal Scan1(n) is a low-level voltage during periods ②, ④, and ⑥, the luminescence signal inverter EI provides the low-level first scan signal Scan1(n) to the Q' node.

[0140] In the periods ②, ④ and ⑥ of the refresh frame and the anode reset frame, the second pull-up unit PUV is controlled by the Q' node and transmits the second high voltage VGH2 to the second output node DV. The twelfth transistor T12 constituting the second pull-up unit PUV is turned on by the low-level voltage of the Q' node and applies the second high voltage VGH2 to the second output node DV. The Q' node capacitor CQ' can quickly apply the second high voltage VGH2 to the second output node DV through the bootstrap effect, and can maintain the voltage of the Q' node at a low-level voltage. Since the second output node DV is connected to the line that provides the initialization signal Vini(n), the initialization signal Vini(n) is the second high voltage VGH2 in the periods ②, ④ and ⑥.

[0141] During periods ②, ④, and ⑥ of the refresh frame and the anode reset frame, the Q' node inverter Q'I provides the inverted voltage of the Q' node to the QB'2 node, so the QB'2 node becomes a high-level state. The ninth transistor T9 constituting the Q' node inverter Q'I is turned on by the low-level voltage of the Q' node and applies the second high voltage VGH2 to the QB'2 node. The tenth transistor T10 is turned off by the low-level voltage of the Q' node. That is, during periods ②, ④, and ⑥, the Q' node is at a low level, and the QB'2 node becomes the second high voltage VGH2 due to the Q' node inverter Q'I.

[0142] Even in the refresh frame and the anode reset frame periods ②, ④, and ⑥, the QB' node holding unit QB'S electrically connects the QB' node and the QB'2 node. Since the QB'2 node is at the second high voltage VGH2 through the Q' node inverter Q'I, the QB' node also becomes the second high voltage VGH2 through the QB' node holding unit QB'S.

[0143] The second pull-down unit PDV blocks the second low voltage VGL2 from being outputted. The thirteenth transistor T13 constituting the second pull-down unit PDV is turned off by the second high voltage VGH2 of the QB' node and does not apply the second low voltage VGL2 to the second output node DV.

[0144] Figure 5 、 6 7C shows the driving of the light emission signal generating circuit EDC(n) and the initialization signal generating circuit VDC(n) in the period ③ for initializing the gate electrode and the drain electrode of the driving transistor. In the period ③, the light emission signal generating circuit EDC(n) outputs a high-level light emission signal EM(n), and the initialization signal generating circuit VDC(n) outputs a low-level initialization signal Vini(n).

[0145] In the refresh frame and the anode reset frame, the Q2 node controller Q2C maintains the high voltage applied to the Q2 node in the period 2. Since the Q node holding unit QS electrically connects the Q node and the Q2 node, the Q2 node is also at a high level.

[0146] In the period ③ of the refresh frame and the anode reset frame, the first pull-down unit PDE is turned off by the high-level voltage of the Q node and does not apply the first low voltage VGL1 to the first output node EV.

[0147] During the refresh frame and the anode reset frame, during period ③, the Q node inverter QI provides the inverted voltage of the Q node to the QB node, and therefore, the QB node becomes a low level state. The third transistor T3 constituting the Q node inverter QI is turned on by the high level of the Q node, and the fourth transistor T4 is turned off by the high level of the Q2 node. The turned-on third transistor T3 applies the first low voltage VGL1 to the QB node. That is, during period ③, the Q node is at a high level, and the QB node becomes a low level due to the Q node inverter QI.

[0148] During the refresh frame and the anode reset frame (3), the first pull-up unit PUE is controlled by the QB node and transmits the first high voltage VGH1 to the first output node EV. The sixth transistor T6 constituting the first pull-up unit PUE is turned on by the first low voltage VGL1 of the QB node and applies the first high voltage VGH1 to the first output node EV. The QB node capacitor CQB maintains the QB node at the first low voltage VGL1 and continuously applies the first high voltage VGH1 to the first output node EV. Since the first output node EV is connected to the line that provides the emission signal EM(n), the emission signal EM(n) is the first high voltage VGH1 during the 3 period.

[0149] During period ③ of the refresh frame and the anode reset frame, the luminescence signal inverter EI is controlled by the luminescence signal EM(n) and provides the first scan signal Scan1(n) to the Q' node. The seventh transistor T7 constituting the luminescence signal inverter EI is turned on by the first high voltage VGH1 of the luminescence signal EM(n) and provides the first scan signal Scan1(n) to the Q' node. The eighth transistor T8 is turned off by the first high voltage VGH1 of the luminescence signal EM(n). During period ③, since the luminescence signal EM(n) is the first high voltage VGH1, the seventh transistor T7 is turned on and the eighth transistor T8 is turned off. Furthermore, the first scan signal Scan1(n) is at a high level. Accordingly, the luminescence signal inverter EI provides the high-level first scan signal Scan1(n) to the Q' node.

[0150] During the refresh frame and the anode reset frame (3), the second pull-up unit PUV is controlled by the Q' node and blocks the second high voltage VGH2 from being output to the second output node DV. The twelfth transistor T12 constituting the second pull-up unit PUV is turned off by the high-level voltage of the Q' node and does not apply the second high voltage VGH2 to the second output node DV.

[0151] During the refresh frame and the anode reset frame, during period ③, the Q' node inverter Q'I provides the inverted voltage of the Q' node to the QB'2 node, and therefore, the QB'2 node becomes a low-level state. The ninth transistor T9 constituting the Q' node inverter Q'I is turned off by the high-level voltage of the Q' node, and the tenth transistor T10 is turned on by the high-level voltage of the Q' node. The turned-on tenth transistor T10 applies the first low voltage VGL1 to the QB'2 node. That is, during period ③, the Q' node is at a high level, and the QB'2 node becomes the first low voltage VGL1 due to the Q' node inverter Q'I.

[0152] Even in the refresh frame and the anode reset frame period ③, the QB' node holding unit QB'S electrically connects the QB' node and the QB'2 node. Since the QB'2 node is in the first low voltage VGL1 state through the Q' node inverter Q'I in period ③, the QB' node also becomes the first low voltage VGL1 due to the QB' node holding unit QB'S.

[0153] During the refresh frame and the anode reset frame period ③, the second pull-down unit PDV applies the second low voltage VGL2 to the second output node DV. The second pull-down unit PDV is controlled by the QB' node and provides the second low voltage VGL2 to the second output node DV. The thirteenth transistor T13 constituting the second pull-down unit PDV is turned on and provides the second low voltage VGL2 to the second output node DV. In addition, the QB' node capacitor CQB' quickly applies the second low voltage VGL2 to the second output node DV through the bootstrap effect, and maintains the voltage of the QB' node at the first low voltage VGL1. Since the second output node DV is connected to the line that provides the initialization signal Vini(n), the initialization signal Vini(n) is the second low voltage VGL2 in period ③.

[0154] The embodiments of the present disclosure may also be described as follows:

[0155] According to one aspect of the present disclosure, an electroluminescent display device is provided. The electroluminescent display device includes a pixel circuit implemented by multiple transistors, and a gate drive circuit that provides a scan signal, an initialization signal, and a light-emitting signal to the pixel circuit. The gate drive circuit includes: a scan signal generation circuit that provides the scan signal to the gate electrode of at least one transistor among the multiple transistors; an initialization signal generation circuit that provides the initialization signal to the source electrode or drain electrode of at least one transistor among the multiple transistors; and a light-emitting signal generation circuit that provides the light-emitting signal to the gate electrode of at least one transistor among the multiple transistors. The initialization signal generation circuit receives the output signal of the scan signal generation circuit and the output signal of the light-emitting signal generation circuit. The initialization signal generation circuit and the light-emitting signal generation circuit include n-type transistors and p-type transistors.

[0156] The light emitting signal generating circuit may include a first pull-down unit controlled by a Q node and a first pull-up unit controlled by a QB node. The QB node may be coupled to a Q node inverter that provides an inverted voltage of the Q node to the QB node.

[0157] The initialization signal generating circuit may include a second pull-up unit controlled by the Q' node and a second pull-down unit controlled by the QB' node. The QB' node is coupled to a Q' node inverter, and the Q' node inverter provides an inverted voltage of the Q' node to the QB' node. The Q' node inverter is coupled to a light emitting signal inverter, and the light emitting signal inverter provides an output signal of the scan signal generating circuit or a voltage inverted from the output signal of the light emitting signal generating circuit to the Q' node.

[0158] The plurality of transistors may include at least one n-type transistor and at least one p-type transistor.

[0159] The scan signal generating circuit may be coupled to a gate electrode of the at least one n-type transistor.

[0160] The light emitting signal generating circuit may be coupled to a gate electrode of the at least one p-type transistor.

[0161] The initialization signal generating circuit may be coupled to a source electrode or a drain electrode of a p-type transistor other than the p-type transistor coupled to the light emitting signal generating circuit.

[0162] The initialization signal may be a signal that swings between a high level and a low level within one frame.

[0163] The electroluminescent display device may further include a plurality of pixel rows, each pixel row including a plurality of pixel circuits. The gate drive circuit may include a first gate drive circuit and a second gate drive circuit. The first gate drive circuit may include: a first scan signal generating circuit providing a scan signal for sampling the threshold voltage of the drive transistor; a second scan signal generating circuit providing a scan signal for controlling the data voltage applied to the pixel circuit; and a third scan signal generating circuit providing a scan signal for controlling the initialization signal provided to the pixel circuit. The second gate drive circuit may include: the luminous signal generating circuit; the second scan signal generating circuit; and the initialization signal generating circuit. The first gate drive circuit and the second gate drive circuit may share the second scan signal generating circuit coupled to the odd-numbered pixel circuits in a pixel row and the second scan signal generating circuit coupled to the even-numbered pixel circuits in a pixel row.

[0164] According to another aspect of the present disclosure, a gate drive circuit is provided. The gate drive circuit includes: a first pull-down unit controlled by the Q node; a first pull-up unit controlled by the QB node; a second pull-up unit controlled by the Q' node; a second pull-down unit controlled by the QB' node; a Q node inverter electrically connected to the Q node and the QB node to provide an inverted voltage of the Q node to the QB node; a Q' node inverter electrically connected to the Q' node and the QB' node to provide an inverted voltage of the Q' node to the QB' node; and a light-emitting signal inverter electrically connected to the Q' node to provide a scan signal or a voltage inverted with respect to the light-emitting signal to the Q' node. The first pull-down unit and the first pull-up unit output the light-emitting signal. The second pull-up unit and the second pull-down unit output an initialization signal.

[0165] The first pull-down unit may be coupled to a circuit providing a first low voltage. The first pull-up unit may be coupled to a circuit providing a first high voltage. The second pull-up unit may be coupled to a circuit providing a second high voltage. The second pull-down unit may be coupled to a circuit providing a second low voltage.

[0166] The gate driving circuit may further include a Q-node holding unit electrically connecting the Q-node inverter to the Q-node.

[0167] The Q-node holding unit may be controlled by the first low voltage provided by the line coupled to the first pull-down unit and electrically connect the Q-node and the Q2 node. The Q-node inverter may include an n-type transistor controlled by the Q-node and a p-type transistor controlled by the Q2 node.

[0168] The gate driving circuit may further include a Q2 node controller coupled to the Q2 node, the Q2 node controller may be controlled by a clock signal, and may provide a start signal or a light emitting signal output from a previous row to the Q2 node.

[0169] The gate driving circuit may further include a QB′ node holding unit electrically connecting the Q′ node inverter to the QB′ node.

[0170] The Q' node inverter may be controlled by the Q' node and may include an n-type transistor and a p-type transistor coupled to the QB'2 node. The n-type transistor may be coupled to a line providing the first low voltage, and the p-type transistor may be coupled to a line providing the second high voltage.

[0171] The QB′ node holding unit may be controlled by the first low voltage provided by a line coupled to the n-type transistor, and may electrically connect the QB′ node and the QB′ 2 node.

[0172] The gate driving circuit may further include a scanning signal generating circuit for outputting the scanning signal. The light emitting signal inverter may include an n-type transistor and a p-type transistor controlled by the light emitting signal.

[0173] Each of the first pull-down unit, the first pull-up unit, the second pull-up unit, and the second pull-down unit may include a p-type transistor and a capacitor coupling a gate electrode of the p-type transistor and a drain electrode or a source electrode of the p-type transistor.

[0174] The second high voltage may be lower than the first high voltage.The second low voltage may be higher than the first low voltage.

[0175] Although the exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should be understood that the above exemplary embodiments are exemplary in all aspects and do not constitute a limitation on the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be understood to fall within the scope of protection of the present invention.

Claims

1. An electroluminescent display device comprising: A pixel circuit implemented by a plurality of transistors and a gate driving circuit for providing a scanning signal, an initialization signal and a light emitting signal to the pixel circuit, The gate drive circuit includes: a scanning signal generating circuit for providing the scanning signal to a gate electrode of at least one transistor among the plurality of transistors; an initialization signal generating circuit that provides the initialization signal to a source electrode or a drain electrode of at least one transistor among the plurality of transistors; and a light emission signal generating circuit for providing the light emission signal to a gate electrode of at least one transistor among the plurality of transistors; wherein the initialization signal generating circuit is electrically and directly coupled to the scanning signal generating circuit and the light emitting signal generating circuit, wherein the initialization signal generating circuit receives the scan signal of the scan signal generating circuit and the light emitting signal of the light emitting signal generating circuit, and provides the initialization signal based on the scan signal of the scan signal generating circuit and the light emitting signal of the light emitting signal generating circuit, The initialization signal generating circuit and the light emitting signal generating circuit include an n-type transistor and a p-type transistor.

2. The electroluminescent display device according to claim 1 , wherein the light emitting signal generating circuit comprises a first pull-down unit controlled by the Q node and a first pull-up unit controlled by the QB node, The QB node is coupled to a Q-node inverter, and the Q-node inverter provides an inverted voltage of the Q-node to the QB node.

3. The electroluminescent display device according to claim 1 , wherein the initialization signal generating circuit comprises a second pull-up unit controlled by the Q′ node and a second pull-down unit controlled by the QB′ node, wherein the QB' node is coupled to a Q' node inverter, and the Q' node inverter provides an inverted voltage of the Q' node to the QB' node, The Q' node inverter is coupled to a light emitting signal inverter, and the light emitting signal inverter provides an output signal of the scan signal generating circuit or a voltage inverted from the output signal of the light emitting signal generating circuit to the Q' node. 4 . The electroluminescent display device of claim 1 , wherein the plurality of transistors include at least one n-type transistor and at least one p-type transistor. 5 . The electroluminescent display device according to claim 4 , wherein the scan signal generating circuit is coupled to a gate electrode of the at least one n-type transistor. 6 . The electroluminescent display device according to claim 4 , wherein the light emission signal generating circuit is coupled to a gate electrode of the at least one p-type transistor. 7 . The electroluminescent display device according to claim 4 , wherein the initialization signal generating circuit is coupled to a source electrode or a drain electrode of a p-type transistor other than the p-type transistor coupled to the light emitting signal generating circuit.

8. The electroluminescent display device according to claim 1, wherein the initialization signal is a signal that swings between a high level and a low level within one frame.

9. The electroluminescent display device according to claim 1, further comprising: A plurality of pixel rows, each pixel row including a plurality of pixel circuits, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit includes: a first scanning signal generating circuit, providing a scanning signal for sampling a threshold voltage of the driving transistor; a second scanning signal generating circuit, providing a scanning signal for controlling a data voltage applied to the pixel circuit; and a third scanning signal generating circuit, providing a scanning signal for controlling the initialization signal provided to the pixel circuit; The second gate driving circuit includes: The luminous signal generating circuit; the second scanning signal generating circuit; and The initialization signal generating circuit, The first gate driving circuit and the second gate driving circuit share the second scanning signal generating circuit coupled to the odd-numbered pixel circuits in a pixel row and the second scanning signal generating circuit coupled to the even-numbered pixel circuits in a pixel row.

10. A gate drive circuit comprising: A first pull-down unit controlled by the Q node; a first pull-up unit controlled by the QB node; a second pull-up unit controlled by the Q' node; a second pull-down unit controlled by the QB' node; a Q-node inverter electrically connected to the Q-node and the QB-node to provide an inverted voltage of the Q-node to the QB-node; a Q' node inverter electrically connected to the Q' node and the QB' node to provide an inverted voltage of the Q' node to the QB' node; as well as a light emitting signal inverter electrically connected to the Q' node to provide a scan signal or a voltage inverted with the light emitting signal to the Q' node; wherein the first pull-down unit and the first pull-up unit output the light emitting signal, The second pull-up unit and the second pull-down unit output initialization signals.

11. The gate driving circuit according to claim 10 , wherein the first pull-down unit is coupled to a line providing a first low voltage, wherein the first pull-up unit is coupled to a circuit providing a first high voltage, wherein the second pull-up unit is coupled to a circuit providing a second high voltage, The second pull-down unit is coupled to a circuit providing a second low voltage.

12. The gate driving circuit according to claim 11, further comprising: A Q-node holding unit electrically connects the Q-node inverter to the Q-node.

13. The gate driving circuit of claim 12 , wherein the Q-node holding unit is controlled by the first low voltage provided by a line coupled to the first pull-down unit and electrically connects the Q-node and the Q2-node, The Q-node inverter includes an n-type transistor controlled by the Q-node and a p-type transistor controlled by the Q2 node.

14. The gate driving circuit according to claim 13, further comprising: a Q2 node controller coupled to the Q2 node, The Q2 node controller is controlled by a clock signal and provides a start signal or a light emission signal output from a previous row to the Q2 node.

15. The gate driving circuit according to claim 11, further comprising: A QB' node holding unit electrically connects the Q' node inverter to the QB' node.

16. The gate driving circuit according to claim 15, The Q' node inverter is controlled by the Q' node and includes an n-type transistor and a p-type transistor coupled to the QB'2 node. The n-type transistor is coupled to a circuit providing the first low voltage, and the p-type transistor is coupled to a circuit providing the second high voltage. 17 . The gate driving circuit of claim 16 , wherein the QB′ node holding unit is controlled by the first low voltage provided by a line coupled to the n-type transistor and electrically connects the QB′ node and the QB′2 node.

18. The gate driving circuit according to claim 10, further comprising: a scanning signal generating circuit for outputting the scanning signal, The light emitting signal inverter includes an n-type transistor and a p-type transistor controlled by the light emitting signal.

19. The gate driving circuit of claim 10, wherein each of the first pull-down unit, the first pull-up unit, the second pull-up unit, and the second pull-down unit comprises a p-type transistor and a capacitor coupling a gate electrode of the p-type transistor and a drain electrode or a source electrode of the p-type transistor. 20 . The gate driving circuit of claim 11 , wherein the second high voltage is lower than the first high voltage, and the second low voltage is higher than the first low voltage.

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