An SOT-MRAM memory cell, memory array, memory and method of operation

Abstract

The present disclosure provides a SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer on the bottom electrode; an orbit Hall effect layer on the magnetic tunnel junction layer; a first transistor having a drain connected to the orbit Hall effect layer; and a second transistor having a drain connected to the bottom electrode. The present disclosure also provides a SOT-MRAM memory, an operating method, and a SOT-MRAM memory array.

Description

Technical Field

[0001] This disclosure relates to the field of magnetic random access memory technology, specifically to a SOT-MRAM memory cell, memory array, memory, and operation method. Background Technology

[0002] SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory), as a new generation of magnetic random access memory, has attracted widespread attention from academia and industry due to its sub-nanosecond write speed, high data retention time, high durability, low power consumption, radiation resistance, and unique three-terminal device structure with separate read and write operations. It overcomes the bottlenecks in information write speed and reliability of the previous generation STT-MRAM and is expected to become the next generation of general-purpose non-volatile memory.

[0003] However, SOT-MRAM faces unresolved technical challenges. For vertically anisotropic (PMA) SOT-MRAM, data writing requires an external in-plane magnetic field along the current direction, limiting its integration, miniaturization, and large-scale application. Existing data writing methods without external magnetic field assistance, such as those using structural asymmetry or introducing built-in in-plane fields through exchange bias / interlayer exchange coupling, suffer from difficulties in miniaturization and poor compatibility with CMOS processes. Furthermore, current SOT-MRAM technologies heavily utilize expensive heavy metal materials as spin-orbit coupling layers, hindering further cost reduction. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a SOT-MRAM memory cell, memory array, memory and operation method, which aims to combine the orbital Hall effect, the spin-orbit precession effect of ferromagnetic materials or the planar Hall effect, and the competing spin current to realize an SOT-MRAM memory cell without external magnetic field assistance.

[0005] The first aspect of this disclosure provides a SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunneling junction layer on the bottom electrode; an orbital Hall effect layer on the magnetic tunneling junction layer; a first transistor whose drain is connected to the orbital Hall effect layer; and a second transistor whose drain is connected to the bottom electrode.

[0006] Furthermore, the storage unit also includes a heavy metal layer located between the magnetic tunnel junction layer and the orbital Hall effect layer.

[0007] Furthermore, the orbital Hall effect layer and the heavy metal layer are configured to transmit the write current; wherein, the orbital Hall effect layer is used to convert the write current into an orbitally polarized orbital current through the orbital Hall effect; and the heavy metal layer is used to convert the write current into a spin-polarized spin current through spin-orbit coupling.

[0008] Furthermore, the orbital flow that diffuses into the heavy metal layer is transformed into a spin flow under the strong spin-orbit coupling effect of the heavy metal layer.

[0009] Furthermore, the spin current generated by the heavy metal layer has opposite polarity to the spin current formed by the conversion of the orbital current, forming a competing spin current, which is used to achieve deterministic magnetization reversal assisted by an external magnetic field.

[0010] Furthermore, the magnetic tunneling layer comprises, from bottom to top, a ferromagnetic reference layer, a nonmagnetic barrier layer, and a ferromagnetic free layer.

[0011] Furthermore, the ferromagnetic reference layer adopts a pinned structure, including: an antiferromagnetic structure layer from bottom to top, a second space layer, and a reference layer.

[0012] Furthermore, the antiferromagnetic structure layer has an RKKY function, including: a second ferromagnetic layer, a first space layer, and a first ferromagnetic layer from bottom to top, wherein the first space layer is used to form antiferromagnetic coupling between the first ferromagnetic layer and the second ferromagnetic layer.

[0013] Furthermore, the structure formed by the first ferromagnetic layer and the second ferromagnetic layer is a synthetic ferromagnetic structure composed of periodic Co / Pt or Co / Pd.

[0014] Furthermore, it also includes: a source line and a bit line; wherein the source line is connected to the orbital Hall effect layer; and the bit line is connected to the source of the first transistor and the second transistor, respectively.

[0015] Furthermore, the heavy metal layer is one or more of Pt, Ta, W, and Gd.

[0016] Furthermore, the ferromagnetic reference layer is any one of Co, CoFeB, Co / Pt, and includes a synthetic antiferromagnetic structure; the bottom electrode is composed of one or more materials of Pt, Ta, and W; the nonmagnetic barrier layer is composed of MgO or Al2O3; the ferromagnetic free layer is any one of Co, CoFe, and CoFeB; and the orbital Hall effect layer is composed of Cu or Cr.

[0017] The second aspect of this disclosure provides a SOT-MRAM memory, comprising: the SOT-MRAM memory cell provided in the first aspect of this disclosure.

[0018] A third aspect of this disclosure provides a method for operating a SOT-MRAM memory, characterized by comprising: controlling voltage bias applied to a first transistor and a second transistor in the SOT-MRAM memory, and performing data writing and reading operations on the SOT-MRAM memory respectively.

[0019] Furthermore, data reading operations are performed on the SOT-MRAM memory, including: controlling the first transistor to be off and the second transistor to be on, and reading the stored data in the SOT-MRAM memory through the tunnel magnetoresistance effect.

[0020] Furthermore, the data writing operation of the SOT-MRAM memory includes: controlling the first transistor to turn on and the second transistor to turn off, and realizing the data writing of the SOT-MRAM memory by forming a competing spin current through the orbital Hall effect and the spin Hall effect.

[0021] A fourth aspect of this disclosure provides a SOT-MRAM memory array comprising: a plurality of SOT-MRAM memory cells as provided in the first aspect of this disclosure, wherein each SOT-MRAM memory cell is arranged periodically.

[0022] A fifth aspect of this disclosure provides a SOT-MRAM memory, comprising: an SOT-MRAM memory array as provided in the fourth aspect of this disclosure.

[0023] The embodiments of this disclosure provide a SOT-MRAM memory cell, memory array, and memory. This memory cell achieves fully electrically controlled deterministic magnetization reversal without external magnetic field assistance by configuring an orbital Hall effect layer to convert write current into orbital-polarized orbital current, and setting a spin-orbit coupling layer to convert write current and orbital current diffused into the layer into spin currents with opposite spin polarization, forming competing spin currents. Furthermore, this SOT-MRAM device has a simple structure, reduces the use of expensive heavy metal materials, and its material system is compatible with CMOS processes, which is beneficial for the large-scale fabrication and practical application of this SOT-MRAM device. Attached Figure Description

[0024] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 This illustration schematically shows the evolution of the research background of SOT-MRAM according to embodiments of the present disclosure;

[0026] Figure 2 A schematic diagram of the structure of an SOT-MRAM memory cell according to an embodiment of the present disclosure is shown.

[0027] Figure 3A schematic diagram of the structure of a magnetic tunnel junction according to an embodiment of the present disclosure is shown.

[0028] Figure 4 Schematic illustration Figure 2 The diagram shows a deterministic magnetization flipping mechanism for a SOT-MRAM memory cell without the aid of an external magnetic field.

[0029] Figure 5 A schematic diagram illustrating the structure of a SOT-MRAM memory cell according to another embodiment of the present disclosure is shown.

[0030] Figure 6 Schematic illustration Figure 5 The diagram shows a deterministic magnetization reversal of a SOT-MRAM memory cell without the aid of an external magnetic field. Detailed Implementation

[0031] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0033] In describing the embodiments of this disclosure in detail, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] Figure 1This illustration schematically depicts the evolution of the research background of SOT-MRAM according to embodiments of this disclosure. This disclosure primarily addresses the miniaturization issues of existing SOT-MRAM structures without external magnetic field-assisted magnetization reversal, compatibility with CMOS, and the problem of using expensive heavy metal materials as spin-orbit coupling layers in existing SOT-MRAMs. Existing mechanisms for magnetization reversal without external magnetic field assistance mainly include four types: structural asymmetry (e.g., wedge-shaped barrier layers, ferromagnetic layers, heavy metal layers, etc.), built-in bias fields (e.g., ferromagnetic / antiferromagnetic exchange bias, interlayer coupling, etc.), hybrid mechanisms (e.g., STT and SOT synergy, based on domain wall motion, etc.), and spin flow configurations (e.g., gradient spin flow, competing spin flow, out-of-plane polarized spin flow, etc.).

[0035] Heavy metals are widely used as the spin-orbit coupling layer in SOT-MRAMs due to their strong spin-orbit coupling. However, heavy metals also suffer from high cost and high resistivity. Since 2018, researchers have proposed the orbital Hall effect, which allows orbital currents to be converted into spin currents through spin-orbit coupling, thus enhancing the spin current conversion efficiency. Furthermore, in light metals (such as Cu) / ferromagnetic materials, the combination of the orbital Hall effect and spin-orbit coupling can achieve spin current conversion efficiencies comparable to those of heavy metals. This disclosure aims to invent an SOT-MRAM that combines the orbital Hall effect, the spin-orbit precession effect or planar Hall effect of ferromagnetic materials, and competing spin currents to achieve an external magnetic field-free SOT-MRAM.

[0036] To address the problems existing in the prior art, this disclosure provides a SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor whose drain is connected to the orbital Hall effect layer; and a second transistor whose drain is connected to the bottom electrode.

[0037] The SOT-MRAM memory cell provided in this disclosure achieves fully electrically controlled deterministic magnetization reversal without external magnetic field assistance by configuring the orbital Hall effect layer to convert the write current into an orbitally polarized orbital current, and setting the spin-orbit coupling layer to convert the write current and the orbital current diffused into the layer into a spin current with opposite spin polarization, forming a competing spin current. The SOT-MRAM device provided in this disclosure has a simple structure, reduces the use of expensive heavy metal materials, and its material system is compatible with CMOS processes, which is beneficial for the large-scale fabrication and practical application of this SOT-MRAM device.

[0038] The technical solution of this disclosure will be described in detail below with reference to the structure of the SOT-MRAM memory cell in specific embodiments. It should be understood that... Figures 2-5The material layers, shapes, and structures of the various parts of the SOT-MRAM memory cell shown are merely exemplary to help those skilled in the art understand the technical solutions of this disclosure, and are not intended to limit the scope of protection of this disclosure.

[0039] Figure 2 A schematic diagram of the structure of an SOT-MRAM memory cell according to an embodiment of the present disclosure is shown.

[0040] like Figure 2 As shown, an embodiment of the SOT-MRAM memory cell disclosed herein includes, from bottom to top, a bottom electrode 10, a magnetic tunnel junction layer 20, a heavy metal layer 30, an orbital Hall effect layer 40, a first transistor 50, and a second transistor 60. The drain of the first transistor 50 is connected to the top of the orbital Hall effect layer 40, and the drain of the second transistor 60 is connected to the top of the bottom electrode 10. The magnetic tunnel junction layer 20 is a spin-orbit-moment magnetic tunnel junction (SOT-MTJ).

[0041] In embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the magnetic tunneling layer 20 includes, from bottom to top, a ferromagnetic reference layer 201, a nonmagnetic barrier layer 202, and a ferromagnetic free layer 203. The ferromagnetic reference layer 201 adopts a pinned structure, which specifically includes, from bottom to top, an antiferromagnetic structure layer 2011, a second space layer 2012, and a reference layer 2013.

[0042] Specifically, such as Figure 3 As shown, the antiferromagnetic structure layer 2011 exhibits RKKY interaction and specifically comprises, from bottom to top, a second ferromagnetic layer 201I, a first space layer 201II, and a first ferromagnetic layer 201III. The first space layer 201II is used to form antiferromagnetic coupling between the first ferromagnetic layer 201III and the second ferromagnetic layer 201I. The second ferromagnetic layer 201I, the first space layer 201II, and the first ferromagnetic layer 201III form a synthetic antiferromagnetic structure (SAF) through RKKY interaction.

[0043] Furthermore, the structure formed by the first ferromagnetic layer 201III and the second ferromagnetic layer 201I is specifically a synthetic ferromagnetic structure composed of periodic Co / Pt or Co / Pd.

[0044] According to embodiments of this disclosure, the SOT-MRAM memory cell further includes a source line SL and a bit line BL. The source line SL is connected to the track Hall effect layer 40, and the bit line BL is connected to the sources of the first transistor 50 and the second transistor 60, respectively. The gates of the first transistor 50 and the second transistor 60 are respectively used to apply bias voltages for writing and reading.

[0045] In this embodiment, the orbital Hall effect layer 40 and the heavy metal layer 30 are configured to carry a write current. Wherein, as... Figure 4 As shown, the orbital Hall effect layer 40 is used to convert the write current into an orbital magnetic moment (L) polarized orbital current through the orbital Hall effect, and this orbital current can diffuse into the heavy metal layer 30. The heavy metal layer 30 is used to convert the write current into a spin (S) polarized spin current through spin-orbit coupling, and simultaneously, the orbital current diffused into the heavy metal layer 30 is converted into a spin current under the strong spin-orbit coupling effect of the heavy metal layer 30. Its spin polarization direction is determined by the spin-orbit coupling polarity of the heavy metal.

[0046] like Figure 4 As shown, the intrinsic spin current and the spin current converted from orbital current at the interface of heavy metal layer 30 and ferromagnetic free layer 203 have opposite polarization directions, forming a competing spin current, thus achieving deterministic magnetization reversal without the assistance of an external magnetic field.

[0047] In the embodiments of this disclosure, the heavy metal layer 30 is one or more of Pt, Ta, W and Gd, and its thickness can be set according to actual application requirements. The embodiments of this disclosure do not limit this.

[0048] Specifically, the ferromagnetic reference layer 201 is any one of Co, CoFeB, Co / Pt, and materials containing a synthetic antiferromagnetic structure. The bottom electrode 10 is composed of one or more materials selected from Pt, Ta, and W. The nonmagnetic barrier layer 202 can be composed of MgO or Al2O3. The ferromagnetic free layer 203 is any one of Co, CoFe, and CoFeB. The orbital Hall effect layer 40 can be composed of Cu or Cr. It should be noted that the selection of these materials is only illustrative and can be replaced with other materials in practical applications.

[0049] Figure 5 A schematic diagram of the structure of a SOT-MRAM memory cell according to another embodiment of the present disclosure is shown.

[0050] like Figure 5 As shown, the structure of this SOT-MRAM memory cell is as follows: Figure 2 The structural difference of the SOT-MRAM memory cell shown is that it does not contain a heavy metal layer 30. Other material layers are as follows: Figure 2 The material layers shown are consistent.

[0051] In this embodiment, as Figure 6As shown, the orbital Hall effect layer 40 and the ferromagnetic free layer 203 (i.e., the ferromagnetic spin-orbit coupling layer) are configured to transmit a write current. The orbital Hall effect layer 40 converts the write current into an orbital magnetic moment (L) polarized orbital current through the orbital Hall effect, which can diffuse into the ferromagnetic free layer 203. The ferromagnetic free layer 203 converts the write current into a spin-polarized (S) spin current through the spin-orbit precession effect or the planar Hall effect, and simultaneously converts the orbital current diffused into the ferromagnetic free layer 203 into a spin current through spin-orbit coupling, the spin polarization direction of which is determined by the spin-orbit coupling polarity of the ferromagnetic layer.

[0052] like Figure 6 As shown, at the interface between the orbital Hall effect layer 40 and the ferromagnetic free layer 203, the intrinsic spin current and the spin current converted from the orbital current have opposite polarization directions, forming a competing spin current, thereby achieving deterministic magnetization reversal without the assistance of an external magnetic field.

[0053] In the embodiments of this disclosure, the coupling polarity of the orbital Hall effect and the spin Hall effect in the orbital Hall effect layer, heavy metal layer, and ferromagnetic layer system is described below with reference to Table 1.

[0054] Table 1. Coupling polarity of orbital Hall effect and spin Hall effect

[0055]

[0056] As shown in Table 1 above, the polarity of the spin current converted from the orbital Hall effect and the spin current generated by the spin Hall effect are determined by the spin-orbit coupling polarity of the ferromagnetic layer and the heavy metal layer. By configuring heavy metal layer and ferromagnetic layer materials, the orbital Hall effect can enhance or compete with the spin Hall effect.

[0057] It should be noted that the thickness of each material layer of the storage unit provided in this disclosure embodiment is set according to actual application requirements and can be achieved in the manufacturing process. The embodiments of this disclosure do not limit the thickness of each material layer.

[0058] In another aspect, this disclosure also provides an SOT-MRAM memory, which includes: an SOT-MRAM memory cell as shown in the above embodiments.

[0059] In this embodiment, by controlling the bias voltage of the transistors on the SOT-MRAM memory, read and write operations of memory data can be realized respectively. This control process can also be implemented by a logic control unit. Specifically, the logic control unit can set the word lines, bit lines, and applied gate voltage bias to realize data read and write operations respectively. The embodiments disclosed herein are not limited in this respect.

[0060] In yet another exemplary embodiment of this disclosure, an operation method for a SOT-MRAM memory as described above is provided, comprising: controlling voltage bias applied to a first transistor and a second transistor in the SOT-MRAM memory, and performing data write and read operations on the SOT-MRAM memory respectively. This operation method includes a data read operation method and a data write operation method, wherein there is no fixed execution order between the data read operation method and the data write operation method.

[0061] Specifically, such as Figure 2 As shown in Figure 5, the data reading operation of the SOT-MRAM memory includes: controlling the first transistor 50 to be turned off and the second transistor 60 to be turned on, forming a current path from bit line BL-magnetic tunnel junction (MTJ)-source line SL-ground, and reading the stored data in the SOT-MRAM memory through the tunnel magnetoresistance effect.

[0062] Specifically, such as Figure 2 As shown in Figure 5, the data writing operation of the SOT-MRAM memory includes: controlling the first transistor to be turned on 50 and the second transistor to be turned off, forming a current path from the bit line BL to the orbital Hall effect layer / heavy metal layer, and realizing the data writing of the SOT-MRAM memory by forming a competing spin current through the orbital Hall effect and the spin Hall effect.

[0063] In yet another exemplary embodiment of this disclosure, a memory array comprising a plurality of SOT-MRAM memory cells as described above is provided, wherein each SOT-MRAM memory cell is arranged periodically.

[0064] Specifically, periodically arranged SOT-MRAM memory cells can share word lines, bit lines, source lines, etc., to achieve high integration of the device.

[0065] In another exemplary embodiment of this disclosure, another SOT-MRAM memory is also provided, including: an SOT-MRAM memory array as described above.

[0066] Specifically, the selection of word lines and bit lines in the memory and the setting of applied voltage bias can be achieved through the logic control unit, thereby realizing data reading and writing operations respectively.

[0067] As can be seen from the above description, the embodiments of this disclosure achieve at least the following technical effects:

[0068] (1) The SOT-MRAM storage unit provided in this disclosure can realize data writing without the assistance of an external magnetic field, which is conducive to the large-scale integration of SOT-MRAM.

[0069] (2) The SOT-MRAM memory cell can reduce the use of expensive heavy metal materials, thereby reducing the manufacturing cost of SOT-MRAM.

[0070] (3) The competitive spin current method used in the SOT-MRAM provided in this disclosure to achieve field-free writing does not require the introduction of structural asymmetry, antiferromagnetic materials, etc., which improves the compatibility with CMOS process and is conducive to the large-scale preparation and practical application of SOT-MRAM.

[0071] Although the present disclosure has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions should be considered illustrative or exemplary rather than limiting.

[0072] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0073] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A SOT-MRAM memory cell, characterized in that, include: Bottom electrode; A magnetic tunneling layer is located on the bottom electrode; An orbital Hall effect layer is located on the magnetic tunneling layer; A heavy metal layer is located between the magnetic tunneling layer and the orbital Hall effect layer; The first transistor has its drain connected to the orbital Hall effect layer; as well as The drain of the second transistor is connected to the bottom electrode; The orbital Hall effect layer and the heavy metal layer are configured to allow writing current to pass through them. The orbital Hall effect layer is used to convert the writing current into an orbitally polarized orbital current through the orbital Hall effect. The heavy metal layer is used to convert the writing current into a spin-polarized spin current through spin-orbit coupling. The orbital current diffused into the heavy metal layer is converted into a spin current under the strong spin-orbit coupling of the heavy metal layer. The spin current generated by the heavy metal layer has the opposite polarity to the spin current formed by the conversion of the orbital current, forming a competing spin current. This competing spin current is used to achieve deterministic magnetization reversal without the assistance of an external magnetic field.

2. The SOT-MRAM memory cell according to claim 1, characterized in that, The magnetic tunnel layer comprises, from bottom to top, a ferromagnetic reference layer, a nonmagnetic barrier layer, and a ferromagnetic free layer.

3. The SOT-MRAM memory cell according to claim 2, characterized in that, The ferromagnetic reference layer adopts a pinned structure, including: an antiferromagnetic structure layer, a second spatial layer, and a reference layer from bottom to top.

4. The SOT-MRAM memory cell according to claim 3, characterized in that, The antiferromagnetic structure layer has an RKKY function and includes: a second ferromagnetic layer, a first space layer, and a first ferromagnetic layer from bottom to top. The first space layer is used to form antiferromagnetic coupling between the first ferromagnetic layer and the second ferromagnetic layer.

5. The SOT-MRAM memory cell according to claim 4, characterized in that, The structure formed by the first ferromagnetic layer and the second ferromagnetic layer is a periodic composite ferromagnetic structure composed of Co / Pt or Co / Pd.

6. The SOT-MRAM memory cell according to claim 1, characterized in that, Also includes: Source line and bit line; among which, The source line is connected to the orbital Hall effect layer; The bit lines are respectively connected to the sources of the first transistor and the second transistor.

7. The SOT-MRAM memory cell according to claim 1, characterized in that, The heavy metal layer is one or more of Pt, Ta, W and Gd.

8. The SOT-MRAM memory cell according to claim 2, characterized in that, The ferromagnetic reference layer is any one of Co, CoFeB, Co / Pt, and synthetic antiferromagnetic structures. The bottom electrode is made of one or more materials selected from Pt, Ta, and W; The non-magnetic barrier layer is composed of MgO or Al2O3; The ferromagnetic free layer is any one of Co, CoFe, and CoFeB; The orbital Hall effect layer is composed of Cu or Cr.

9. A SOT-MRAM memory, characterized in that, include: The SOT-MRAM memory cell as described in any one of claims 1 to 8.

10. A method for operating a SOT-MRAM memory as described in claim 9, characterized in that, include: The voltage bias applied to the first and second transistors in the SOT-MRAM memory is controlled to perform data writing and reading operations on the SOT-MRAM memory respectively.

11. The operating method according to claim 10, characterized in that, The data reading operation of the SOT-MRAM memory includes: By controlling the first transistor to be turned off and the second transistor to be turned on, the stored data in the SOT-MRAM memory is read through the tunnel magnetoresistive effect.

12. The operating method according to claim 10, characterized in that, The data writing operation to the SOT-MRAM memory includes: By controlling the first transistor to turn on and the second transistor to turn off, data writing to the SOT-MRAM memory is achieved by forming a competing spin current through the orbital Hall effect and the spin Hall effect.

13. A SOT-MRAM memory array, characterized in that, include: A plurality of SOT-MRAM memory cells as described in any one of claims 1 to 8, wherein each SOT-MRAM memory cell is arranged periodically.

14. A SOT-MRAM memory, characterized in that, include: The SOT-MRAM storage array as described in claim 13.

Images