Hardware circuit implementation method of PageRank algorithm based on memristor array

Abstract

The present invention provides a hardware circuit implementation method for the PageRank algorithm based on a memristor array. The method includes: setting the conductance value of each memristor unit in the memristor array, writing a state transition matrix corresponding to a website link jump into the memristor array; inputting an initial PageRank value vector (representing the popularity of a webpage) into the column signal input of the memristor array in the form of a voltage, and obtaining the result of a first matrix-vector product operation at the row signal output of the memristor array; and connecting the row signal output of the memristor array back to the array input after current-voltage conversion. The PR value calculation result is the stable distribution of the output row signal. In addition, because the present invention uses in-memory calculation in the analog domain, it can improve calculation speed while reducing energy consumption.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a method for implementing a PageRank algorithm hardware circuit based on a memristor array. Background Art

[0002] The PageRank algorithm is a search engine's method for ranking web pages in search results. It uses the number and quality of hyperlinks between web pages as key variables and can be used to analyze the importance of web pages. In the PageRank algorithm, each web page has a variable called a PageRank (PR) value, which measures its recommendation level. Based on existing user behavior data, a state transition matrix between web pages can be obtained. The updated PageRank value vector is obtained by multiplying the initial PageRank value vector by this state transition matrix. Mathematically, it can be proven that such iterations can achieve a stationary distribution of PageRank values, effectively determining the relative importance of each web page. The PageRank algorithm is applicable not only to search engine optimization but also to other problems that can be mathematically abstracted into graphs and networks, such as those in bibliometrics, information network analysis, and protein network analysis.

[0003] In 1971, Professor Cai Shaotang first theoretically proposed the concept of a memristor, arguing it as a fourth basic passive device, characterizing the relationship between charge and magnetic flux. The resistance of a memristor is determined by the charge flowing through it, meaning it possesses adjustable conductance. Numerous experimental studies have demonstrated that nano-memristor devices offer high speed, low power consumption, ease of integration, and non-volatility, leading to extensive research and application in areas such as in-memory computing, non-volatile storage, and neural networks.

[0004] With the development of big data, artificial intelligence, and cloud computing, the amount of data that needs to be stored and processed is increasing rapidly. However, the "memory wall" problem stemming from the traditional von Neumann computing architecture remains unresolved, and the speed at which data can be transferred between memory and the processor hinders further increases in computing power. In this context, memristors, due to their unique electrical properties, are expected to play a central role in establishing new computing architectures. Due to their tunable resistance and non-volatility, memristors can be used in conjunction with hardware circuit design to leverage circuit theorems to implement in-situ storage and matrix operations in the analog domain. This avoids frequent digital-to-analog conversion and data exchange, significantly improving computing speed while reducing energy consumption. Summary of the Invention

[0005] The purpose of this invention is to solve the shortcoming of the O(n^2) time complexity of solving the PR value in the PageRank algorithm by traditional von Neumann architecture computers, and propose a hardware circuit implementation method of the PageRank algorithm based on a memristor array to improve the algorithm's large-scale parallel computing capabilities.

[0006] In order to achieve the above objectives, the present invention proposes a method for implementing the PageRank algorithm hardware circuit based on a memristor array, as shown in the schematic diagram. Figure 1 The method is implemented by a resistance control circuit, a memristor array, and peripheral circuits, and includes the following steps:

[0007] Step 1: Use a resistance control circuit to set the conductance value of the memristor array, and write the state transition matrix of the website link jump into the memristor array;

[0008] Step 2: inputting the initial PR value signal into the column signal input terminal of the set memristor array to complete the first matrix-vector product operation;

[0009] Step 3: Connect the row signal output end of the memristor array back to the column input end of the array through current-voltage conversion, and the stable distribution of the output row signal is the PR value calculation result.

[0010] Furthermore, the resistance control circuit input voltage signal represents the size of the corresponding element of the state transition matrix, which can change the conductance value of the memristor unit at the corresponding position of the memristor array. The resistance control circuit includes control signals for row selection and column selection of the memristor array.

[0011] Furthermore, the memristor array adopts Figure 2 The cross structure integration shown in the figure does not impose any special restrictions on the memristor material and unit structure in the present invention.

[0012] Furthermore, the hardware circuit of the solution can be controlled to enter step three from step two by switching an analog switch.

[0013] Furthermore, the memristor array output signal obtained in step 3 is converted into an input signal and then input into the array, which can adopt a sampling and holding circuit or a proportional amplification circuit composed of an operational amplifier; the output voltage stable distribution can be converted into a digital value by an analog-to-digital converter for storage.

[0014] Overall, the technical solution conceived by this invention achieves the limiting distribution of single matrix-vector products and vector-matrix power products in the analog domain. This can be applied to solving for the eigenvectors corresponding to matrices with an eigenvalue of 1. More specifically, this solution can be used to determine the PageRank value vector, which represents the popularity of web pages in the PageRank algorithm. Compared to existing technologies, this solution enables in-memory computation in the analog domain, breaking through the "memory wall" barrier, thereby increasing computation speed and reducing energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0016] Figure 1 Schematic diagram of the hardware circuit implementation of the PageRank algorithm based on a memristor array.

[0017] Figure 2 Schematic diagram of the cross-shaped structure of the memristor array.

[0018] Figure 3 A circuit diagram of a resistance control circuit provided in at least one embodiment of the present disclosure.

[0019] Figure 4 This is a simulation waveform diagram of regulating the resistance of a memristor during operation of a resistance regulation circuit provided by at least one embodiment of the present disclosure.

[0020] Figure 5 A schematic diagram of a vector and matrix multiplication operation provided in at least one embodiment of the present disclosure.

[0021] Figure 6 A schematic diagram of a vector and matrix power multiplication operation provided in at least one embodiment of the present disclosure.

[0022] Figure 7 A schematic diagram of a sample-and-hold circuit according to at least one embodiment of the present disclosure.

[0023] Figure 8 A complete circuit diagram for calculating the PR value vector in the PageRank algorithm provided by at least one embodiment of the present disclosure.

[0024] Figure 9 This is a circuit simulation result for calculating the PR value vector in the PageRank algorithm provided by at least one embodiment of the present disclosure.

[0025] Figure 10 This is a circuit simulation waveform diagram for calculating the PR value vector in the PageRank algorithm provided by at least one embodiment of the present disclosure.

[0026] Figure 11 A physical diagram of a PCB provided for at least one embodiment of the present disclosure.

[0027] Figure 12 This is a waveform diagram of the PCB physical circuit output provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Examples of the embodiments are shown in the accompanying drawings. The specific embodiments described in the following embodiments of the present invention are only exemplary illustrations of the specific embodiments of the present invention and are intended to be used to explain the present invention, but are not intended to limit the present invention.

[0029] Step 1: Use a resistance control circuit to set the conductance value of the memristor array, and write the state transition matrix of the website link jump into the memristor array;

[0030] Experiments have shown that applying a constant voltage source to a memristor in a high-resistance state will change the resistance of the memristor from the high-resistance state R off Changes to low resistance state R on In this process, the resistance shows a continuous and monotonically decreasing trend. The resistance of the memristor in this process is regarded as a function R that changes with time. MEM (t), its maximum and minimum values ​​are R off and R on , according to the intermediate value theorem, R MEM (t) can be obtained between R off and R on All resistance values ​​between, there will be a moment R MEM If the voltage source can be cut off at this moment, the resistance of the memristor will remain at the target resistance.

[0031] According to this idea, the present invention is designed Figure 3 In the circuit structure shown, the "8"-shaped element between the output terminal and the inverting input terminal of the operational amplifier U2 represents a memristor.

[0032] During simulation, the target resistance is set to 8kΩ (input in the form of voltage), and the resistance of the memristor changes as follows: Figure 4 , after about 0.07s, the resistance value becomes 7.997kΩ, with an error within 1%.

[0033] Step 2: inputting the initial PR value signal into the column signal input terminal of the set memristor array to complete the first matrix-vector product operation;

[0034] Taking the multiplication of a 2-dimensional vector by a 2-order square matrix as an example, the present invention designs Figure 5 The storage and computing integrated solution shown.

[0035] Each memristor unit of the memristor array stores the corresponding element value of the transition probability matrix A; then, the input vector The components of are written into the row line. According to the "virtual ground" of the op amp, Ohm's law, Kirchhoff's current law and the rules of matrix multiplication, it can be obtained that the currents i1 and i2 here are proportional to the output vector Finally, after the current flows through the resistor R and the voltage inverter, it becomes the same as the value at the output. The voltage components are equal or proportional. This completes the solution. task.

[0036] Step 3: Connect the row signal output end of the memristor array back to the column input end of the array through current-voltage conversion, and the stable distribution of the output row signal is the PR value calculation result.

[0037] First, assume that in the first clock cycle, the initial PR value vector x0 is added to the input, and the output terminal will get x1; then enter the second cycle, at this time x1 is known, and the goal of the second cycle is to find x2. Add the output voltage x1 of the previous cycle to the input terminal of the original circuit, then the output terminal voltage value is equal to x2; and so on, repeating the above operations, you can calculate x n The stationary distribution of .

[0038] In this example, a sample-and-hold circuit is used to complete the conversion between the output vector and the input vector, such as Figure 7 When the Hold terminal is low, Vout = Vin, and the circuit samples. When the Hold terminal is high, Vout remains unchanged, and the output vector voltage is applied to the input terminal, completing the matrix power multiplication calculation.

[0039] The complete circuit diagram is as follows Figure 8 As shown in (a), (1) to (4) are sample-and-hold circuits, and V1 and V2 are voltage sources. During the calculation process, it is only necessary to continuously change the Hold signal and the positions of switches S1 to S4 in a certain timing sequence. After enough clock cycles, the matrix multiplication x is obtained at the output. n The limit of PageRank is the goal of the algorithm.

[0040] According to the above model, simulation is performed in LTspice, and the simulation results are as follows Figure 9 The error between the simulation results and the theoretical calculation values ​​is within 1%.

[0041] Specifically, the following is another example of the present invention's solution to calculate the limit result in one step using feedback. The PageRank problem is not concerned with the result of matrix exponentiation at a certain power, but the limit when the power tends to infinity, and only cares about the size relationship between the various components. Through simulation, it can be found that Figure 6 The voltage inverter in the circuit becomes an inverting amplifier with a gain factor slightly greater than 1, and its output is directly connected to the Figure 8 After connecting ports 1 of S3 and S4 in (a), the limit result of the power multiplication can be calculated in one step. The voltage values ​​are proportional to the corresponding values ​​in the theoretical solution, which is the final result of the PageRank problem. The simulation waveform is shown in Figure 10.

[0042] Make a physical circuit with an array size of 2*2 as follows Figure 11As shown in the figure, based on the actual resistance value of the resistor on the circuit board, the theoretical solution is (0.57128, 0.42857), while the result given by the real circuit is as follows Figure 12 As shown, the oscilloscope reading is (13.3, 10.05), and the ratio between the two is less than 1%, which is enough to believe that this circuit can correctly solve the PageRank problem.

Claims

1. A method for implementing a PageRank algorithm hardware circuit based on a memristor array, characterized in that: The following steps are involved: Step 1: Use a resistance control circuit to set the conductance value of the memristor array, and write the state transition matrix of the website link jump into the memristor array; Step 2: Input the initial PR value signal to the column signal input end of the set memristor array to complete the first matrix-vector product operation; Step 3: Connect the row signal output end of the memristor array to the memristor array input end through current-voltage conversion, and output the stable distribution of the row signal as the PR value calculation result; The resistance control circuit adjusts the conductance value of the corresponding memristor unit of the memristor array according to the input voltage signal; The resistance control circuit also includes a controller and a digital-to-analog converter; the controller is used to control the row selection and column selection signals of the memristor array; The digital-to-analog converter is used to map the elements in the state transition matrix of the digital storage into a voltage signal, which serves as the input signal of the resistance control circuit and represents the conductance value of the memristor unit that needs to be adjusted; The hardware circuit enters step 3 from step 2 and is controlled by analog switches; In step 3, the output signal of the memristor array is converted into an input signal and then input into a proportional amplification circuit composed of a sample-and-hold circuit or an operational amplifier in the memristor array; The stable distribution of the memristor array output voltage obtained in step 3 is converted into a digital quantity through an analog-to-digital converter for storage.

2. The method according to claim 1, characterized in that The memristor units in the memristor array used are made of different materials and have different unit structures. The memristor array adopts a cross structure, and the memristor units are located at the intersections.

3. The method according to claim 1, characterized in that The voltage signal mapped by the DAC is proportional to the size of the elements in the state transition matrix.

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