Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the forming method comprising: performing ion doping on a core layer of a second region, which is suitable for improving the etch resistance of the core layer, and the core layer located in the second region is used as an etch-resistant layer; forming a first trench that penetrates at least part of the core layer of the first region along a first direction, and part of the core layer of the first region is reserved on both sides of the first trench in a second direction and is used as a sacrificial layer; forming sidewalls on the sidewalls of the first trench so that the sidewalls located on the sidewalls of the first trench enclose a first groove; removing the sacrificial layer to form a second groove in the etch-resistant layer; in any one or both of the first groove and the second groove, a dividing layer extending along the second direction is formed, and the dividing layer divides the corresponding groove along the first direction; using the etch-resistant layer, the sidewalls, and the dividing layer as masks to etch a target layer below the first groove and the second groove to form a target pattern. Embodiments of the present invention are beneficial to further compress the pitch between target patterns.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] During the development of integrated circuits, generally, as the function density (i.e., the number of internal connection structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, in the case of continuously shrinking technology nodes, how to improve the matching degree between the patterns formed on the wafer and the target patterns has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which further compresses the pitch between target patterns.

[0006] To solve the above problem, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern; forming a core layer on the substrate, including a first region and a second region surrounding the first region; performing a first ion doping on the core layer in the second region, suitable for improving the etch resistance of the core layer, and the core layer doped with ions in the second region is used as an anti-etching layer; forming a first trench penetrating at least part of the core layer in the first region along a first direction, a direction perpendicular to the first direction is a second direction, and in the second direction, part of the core layer in the first region is reserved on both sides of the first trench for use as a sacrificial layer; forming sidewalls on the sidewalls of the first trench, so that the sidewalls located on the sidewalls of the first trench enclose a first groove; after performing the first ion doping and forming the sidewalls, removing the sacrificial layer to form a second groove in the anti-etching layer; wherein, in any one or both of the first groove and the second groove, a dividing layer extending along the second direction is formed, and the dividing layer divides the corresponding groove along the first direction; using the anti-etching layer, the sidewalls, and the dividing layer as a mask, etching the target layer below the first groove and the second groove to form a target pattern.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the core layer of the second region is subjected to first ion doping, which is suitable for improving the etching resistance of the core layer. The core layer doped with ions in the second region serves as an etching-resistant layer. In the step of forming the first trench, a part of the core layer of the first region is reserved on both sides of the first trench in the second direction to serve as a sacrificial layer. That is to say, the first region spans across the first trench in the second direction, and sidewalls are formed on the sidewalls of the first trench, so that the sidewalls located on the sidewalls of the first trench enclose a first groove. The second groove formed by removing the sacrificial layer is correspondingly located on both sides of the first groove. Compared with the size of the second groove, the size of the first region is larger, which is easy to meet the requirements of the photolithography process conditions. Moreover, the part of the first region excluding the region overlapping with the first trench is used to define the shape and size of the second groove. Therefore, in the embodiment of the present invention, by superimposing the first region pattern and the first trench pattern, the second groove can achieve a smaller size, and the interval (space) between the second groove and the first groove is defined by the thickness of the sidewall. It is easy to meet the designed minimum interval between the first groove and the second groove, and further, without changing the limit conditions of the photolithography process, it is beneficial to make the target pattern achieve a smaller critical dimension and further compress the pitch between the target patterns to meet the requirements of high density and high integration of integrated circuits, and the modification to the existing process is small, the process complexity is low, and the photolithography process friendliness is high. In addition, in any one or both of the first groove and the second groove, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction, so that in the first direction, a smaller distance is achieved between adjacent grooves, and further, it is beneficial to make the target pattern achieve a smaller line end distance at the head to head (HTH) position and improve the design freedom of the target pattern. Description of the Drawings

[0009] Figures 1 to 20 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention;

[0010] Figures 21 to 22 is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0011] Figures 23 to 24 is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0012] Figures 25 to 27 is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. Detailed implementation manners

[0013] As can be seen from the background art, with the continuous reduction of technology nodes, how to improve the matching degree between the patterns formed on the wafer and the target patterns has become a challenge.

[0014] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, which is beneficial to achieving a smaller critical dimension of the target pattern and further compressing the pitch between the target patterns without changing the limit conditions of the lithography process, so as to meet the requirements of high density and high integration of integrated circuits. Moreover, the modification to the existing process is small, the process complexity is low, and the lithography process has high friendliness. In addition, in any one or both of the first groove and the second groove, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction, so that a smaller distance is achieved between adjacent grooves in the first direction, which is beneficial to achieving a smaller line end distance at the head-to-head position of the target pattern and improving the design freedom of the target pattern.

[0015] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the drawings. Figures 1 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0016] Refer to Figure 1 , Figure 1 a is a top view, Figure 1 b is Figure 1 a cross-sectional view along the y1-y1 secant line of a. A substrate 200 is provided, including a target layer 100 for forming a target pattern. The target layer 100 is a film layer to be patterned to form a target pattern. Among them, the target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork-sheet transistor, a hard mask (HM) layer, etc.

[0017] In this embodiment, the target layer 100 is a dielectric layer, and the target pattern is an interconnect trench. Subsequently, the dielectric layer is patterned to form a plurality of interconnect trenches, and then metal interconnections are formed in the interconnect trenches. The dielectric layer is used to achieve electrical isolation between the metal interconnections. Therefore, the dielectric layer is an inter-metal dielectric (IMD) layer.

[0018] The substrate 200 further includes a substrate 110 at the bottom of the target layer 100. In this embodiment, the substrate 200 further includes a hard mask material layer 115 on the target layer 100.

[0019] Continue to refer toFigure 1 On the substrate 200, a core layer 120 is formed. The core layer 120 includes a first region 120a and a second region 120b surrounding the first region 120a. Subsequently, the core layer 120 in the second region 120b is subjected to a first ion doping, which is suitable for improving the etching resistance of the core layer 120. The core layer 120 doped with ions in the second region 120b is used as an anti-etching layer.

[0020] The material of the core layer 120 includes one or several of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the core layer 120 is amorphous silicon.

[0021] For the convenience of illustration and description in this embodiment, only one first region 120a is shown. However, the shape, position, and number of the first region 120a are not limited thereto. For example: In other embodiments, the number of the first regions may also be multiple and arranged along the second direction, and the multiple first regions are separated from each other.

[0022] Reference Figures 2 to 4 By subjecting the core layer 120 in the second region 120b to a first ion doping, it is suitable for improving the etching resistance of the core layer 120. The core layer 120 doped with ions in the second region 120b serves as an anti-etching layer 130. The anti-etching layer 130 is used as a mask for the subsequent patterning of the target layer 100.

[0023] After the subsequent formation of a first trench that penetrates at least part of the core layer 120 in the first region 120a along the first direction, the remaining core layer 120 in the first region 120a is used as a sacrificial layer, and the sacrificial layer is used to occupy a spatial position for the formation of a second groove. The subsequent manufacturing process further includes: forming sidewalls on the sidewalls of the first trench, and surrounding the sidewalls located on the sidewalls of the first trench to form a first groove.

[0024] By performing a first ion doping on the core layer 120, an anti-etching layer 130 is formed, thereby realizing the patterning of the core layer 120. And the first ion doping is suitable for improving the etching resistance of the core layer 120, so that the etching resistance of the anti-etching layer 130 is greater than that of the core layer 120 without doped ions. There is a high etching selectivity between the core layer 120 without doped ions and the anti-etching layer 130. Subsequently, a first trench is formed, and the remaining core layer 120 in the first region 120a serves as a sacrificial layer. Correspondingly, in the subsequent step of removing the sacrificial layer to form a second groove, the probability of mis-etching the anti-etching layer 130 is low, which is beneficial to reducing the probability of double etching of the first groove, ensuring the pattern accuracy of the first groove, and enabling the anti-etching layer 130 to be retained as a mask for the patterning target layer 100.

[0025] In this embodiment, the etching-resistant layer 130 surrounds the core layer 120 of the first region 120a. In this embodiment, the ions for the first ion doping include one or more of boron ions, phosphorus ions, and argon ions.

[0026] In this embodiment, the etching selectivity between the undoped core layer 120 and the etching-resistant layer 130 is at least 20:1. The high etching selectivity between the undoped core layer 120 and the etching-resistant layer 130 helps to significantly prevent the etching-resistant layer 130 from being accidentally etched during the subsequent process of removing the sacrificial layer.

[0027] As an example, after forming the core layer 120 and before forming the first trench, the core layer 120 of the second region 120b is subjected to the first ion doping. However, the step of performing the first ion doping on the core layer 120 of the second region 120b is not limited to this. In other embodiments, the first ion doping can also be performed on the core layer of the second region after forming the first trench and before forming the sidewall. In some other embodiments, the first ion doping can also be performed on the core layer of the second region after forming the sidewall and before removing the sacrificial layer.

[0028] In this embodiment, the step of performing the first ion doping on the core layer 120 of the second region 120b includes:

[0029] As Figure 2 shown, Figure 2 a is a top view, Figure 2 b is Figure 2 a cross-sectional view along the y1 - y1 cut line. A shielding layer 150 is formed on the core layer 120 of the first region 120a. The shielding layer 150 exposes the second region 120b. The shielding layer 150 is used as a mask for the first ion doping of the core layer 120, and the shielding layer 150 correspondingly defines the shape and position of the etching-resistant layer 130. In this embodiment, the shielding layer 150 includes a first planarization layer 151 and a first patterned layer 152 located on the first planarization layer 151.

[0030] The first planarization layer 151 is used to provide a flat surface for forming the first patterned layer 152, thereby improving the accuracy of pattern transfer. In this embodiment, the material of the first planarization layer 151 is Spin-On Carbon (SOC). The first patterned layer 152 is used as an etching mask for forming the first planarization layer 151, and the first patterned layer 152 correspondingly defines the shapes and positions of the sacrificial layer 140 and the etching-resistant layer 130. In this embodiment, the material of the first patterned layer 152 is photoresist.

[0031] As Figure 3 shown, Figure 3 a is a top view, Figure 3 b isFigure 3 A cross-sectional view along the y1-y1 secant line, using the masking layer 150 as a mask, the core layer 120 is subjected to the first ion doping. In this embodiment, the first ion doping is carried out by an ion implantation process. As Figure 4 shown, Figure 4 a is a top view, Figure 4 b is Figure 4 A cross-sectional view along the y1-y1 secant line of a, removing the masking layer 150. One or both of an ashing process and a wet stripping process are used to remove the masking layer 150.

[0032] Refer to Figures 5 to 8 , a first trench 180 of the core layer 120 that penetrates at least part of the first region 120a along the first direction (as shown by the X direction in Figure 7 a) is formed. The direction perpendicular to the first direction is the second direction (as shown by the Y direction in Figure 7 b). In the second direction, parts of the core layer 120 of the first region 120a are reserved on both sides of the first trench 180 for use as a sacrificial layer 140.

[0033] In the second direction, parts of the core layer 120 of the first region 120a are reserved on both sides of the first trench 120 for use as a sacrificial layer 140. That is to say, the first region 120a spans the first trench 180 along the second direction. Then, sidewalls are formed on the sidewalls of the first trench 180, and the sidewalls located on the sidewalls of the first trench 180 enclose a first groove. In the subsequent step of removing the sacrificial layer 140 to form a second groove, the second groove is correspondingly located on both sides of the first groove, and the first groove and the second groove are separated by the sidewalls.

[0034] Compared with the size of the second groove, the size of the first region 120a is larger, which is easy to meet the requirements of the lithography process conditions. Moreover, the part of the first region 120a excluding the overlapping region with the first trench 180, that is, the sacrificial layer 140, is used to define the shape and size of the second groove. Thus, by superimposing the pattern of the first region 120a and the pattern of the first trench 180, the second groove can achieve a smaller size, and the interval between the second groove and the first groove is defined by the thickness of the sidewalls. It is easy to meet the designed minimum interval between the first groove and the second groove. Furthermore, without changing the limit conditions of the lithography process, it is beneficial to make the target pattern achieve a smaller critical dimension and further compress the pitch between the target patterns to meet the requirements of high density and high integration of integrated circuits, with little modification to the existing process, low process complexity, and high lithography process friendliness.

[0035] In this embodiment, the first trench 180 includes a first sidewall 181 along the second direction and a second sidewall 182 that is opposite to and parallel to the first sidewall 181.

[0036] In this embodiment, along the first direction, the first groove 180 penetrates the core layer 120 of the first region 120a; alternatively, along the first direction, the first groove 180 penetrates the core layer 120 of the first region 120a, and any one or both of the first sidewall 181 and the second sidewall 182 further extend into the core layer 120 (i.e., the etching-resistant layer 130) of the adjacent second region 120b. Therefore, in this embodiment, the core layers 120 of the first region 120a on both sides of the first groove 180 are spaced apart, that is, the sacrificial layers 140 on both sides of the first groove 180 are spaced apart, and the second grooves formed by subsequently removing the sacrificial layer 140 are also spaced apart.

[0037] As an example, along the first direction, the first groove 180 penetrates the core layer 120 of the first region 120a, and both the first sidewall 181 and the second sidewall 182 extend into the core layer 120 (i.e., the etching-resistant layer 130) of the adjacent second region 120b, that is, along the first direction, the end of the first groove 180 protrudes from the first region 120a. After the sacrificial layer 140 is removed to form the second groove, the end of the first groove protrudes from the second groove correspondingly along the first direction.

[0038] For the convenience of illustration and description, this embodiment only shows one first region 120a and one first groove 180 that penetrates at least part of the core layer 120 of the first region 120a along the first direction. However, the shape, position, and number of the first regions 120a, as well as the positional relationship with the first groove 180, are not limited thereto.

[0039] As an example, the number of the first regions is multiple and arranged along the second direction, and the multiple first regions are separated from each other. The first groove may be formed only in the core layers of some of the first regions, and the first groove may not be formed in the core layers of the remaining first regions. In other embodiments, according to actual design requirements, the first groove may also be formed in the core layers of all the first regions.

[0040] For the convenience of illustration and description, this embodiment only shows the first region 120a, the second region 120b, and the first groove 180, and does not show the graphic structure around the first region 120a. It should be understood that in actual processes, the first region 120a and the first groove 180 may not be independent graphics. According to design requirements, other graphic structures may be provided around the first region 120a, for example: as Figure 8 shown, a second groove 185 may be formed on one or both sides of the first region 120a along the second direction. In the subsequent step of forming sidewalls on the sidewalls of the first groove 180, sidewalls are also formed on the sidewalls of the second groove 185, and the sidewalls located on the sidewalls of the second groove 185 enclose a third groove, and the third groove is also used to define the graphics of the target graphics.

[0041] In this embodiment, the steps of forming the first trench 180 include: As Figure 5 shown, Figure 5 a is a top view, Figure 5 b is Figure 5 a cross-sectional view along the y1-y1 secant line of a. A mask layer 160 is formed on the core layer 120. The mask layer 160 has a mask opening 170 extending along the first direction (as shown by the X direction in Figure 5 a); on the projection plane parallel to the substrate 200, the first region 120a straddles the mask opening 170 along the second direction (as shown by the Y direction in Figure 5 ; b); As Figure 6 shown, Figure 6 a is a top view, Figure 6 b is Figure 6 a cross-sectional view along the y1-y1 secant line of a. Using the mask layer 160 as a mask, the core layer 120 below the mask opening 170 is removed to form the first trench 180; As Figure 7 shown, Figure 7 a is a top view, Figure 7 b is Figure 7 a cross-sectional view along the y1-y1 secant line of a. The mask layer 160 is removed.

[0042] The mask layer 160 is used as an etching mask for forming the first trench. The mask opening 170 is used to define the shape and position of the first trench. Before forming the mask layer 160, it further includes: forming a second planarization layer 161 and an anti-reflection coating 162 stacked in sequence on the core layer 120. The second planarization layer 161 is used to provide a flat top surface for forming the mask layer 160 to improve the pattern accuracy of the mask opening 170. The anti-reflection coating 162 is used to reduce the reflection effect during exposure.

[0043] In this embodiment, using the mask layer 160 as a mask and adopting a dry etching process (for example: an anisotropic dry etching process) to remove the core layer 120 below the mask opening 170 is beneficial to improving the pattern transfer accuracy and the profile quality of the first trench 180.

[0044] The mask layer 160 is removed to facilitate subsequent process steps. In the step of removing the mask layer 160, the anti-reflection coating 162 and the second planarization layer 161 are also removed.

[0045] Referring to Figures 9 to 10 , in this embodiment, after forming the first trench 180 and before removing the sacrificial layer 140, a second dividing layer 145 extending along the second direction is formed in the sacrificial layer 140 (as Figure 10 shown), and the second dividing layer 145 divides the sacrificial layer 140 along the first direction.

[0046] By forming a second segmentation layer 145, a second segmentation layer 145 is formed in the second groove formed by subsequently removing the sacrificial layer 140. The second segmentation layer 145 extends in the second direction and segments the second groove in the first direction, thereby enabling a smaller distance between the second grooves in the first direction. This is conducive to achieving a smaller line end distance at the head-to-head position of the target pattern and improving the design freedom of the target pattern.

[0047] In this embodiment, the step of forming the second segmentation layer 145 includes:

[0048] As Figure 9 shown, Figure 9 a is a top view, Figure 9 b is Figure 9 a cross-sectional view along the y1-y1 secant line of a. A segmentation mask layer 146 is formed on the core layer 120 (i.e., the etch-resistant layer 130) in the second region 120b. Segmentation grooves 143 are formed in the segmentation mask layer 146. The segmentation grooves 143 in the second direction span across the first region 120a and expose a part of the width of the sacrificial layer 140. The segmentation mask layer 146 is used as a mask for forming the second segmentation layer. Specifically, in this embodiment, the segmentation mask layer 146 is used as a mask for ion doping the sacrificial layer 140 to form the second segmentation layer. The segmentation grooves 143 are used to define the pattern and position of the second segmentation layer.

[0049] In this embodiment, the segmentation mask layer 146 includes a third planarization layer 141 and a third patterned layer 142 located on the third planarization layer 141.

[0050] As Figure 10 shown, using the segmentation mask layer 146 as a mask, the sacrificial layer 140 exposed by the segmentation grooves 143 is subjected to second ion doping, which is suitable for improving the etch resistance of the sacrificial layer 140. The sacrificial layer 140 doped with ions is used as the second segmentation layer 145. In this embodiment, the ions for the second ion doping of the sacrificial layer 140 are the same as those for the first ion doping, which is conducive to improving process compatibility. Specifically, the ions for the second ion doping of the sacrificial layer 140 include one or more of boron ions, phosphorus ions, and argon ions. Therefore, in this embodiment, the material of the second segmentation layer 145 is the same as that of the etch-resistant layer 130.

[0051] As Figure 10 shown, Figure 10 a is a top view, Figure 10 b is Figure 10 a cross-sectional view along the y1-y1 secant line of a. The segmentation mask layer 146 is removed. The process of removing the segmentation mask layer 146 includes one or both of ashing and wet stripping processes.

[0052] The subsequent steps further include: forming sidewalls on the sidewalls of the first trench. Correspondingly, in other embodiments, a second dividing layer may also be formed in the step of forming the sidewalls. Specifically, in other embodiments, the forming method further includes: after forming the core layer and before forming the sidewalls, forming a blocking trench that penetrates the core layer in the first region along the second direction, and the blocking trench divides the core layers on both sides along the first direction; the step of forming the second dividing layer includes: in the step of forming the sidewalls, the sidewalls also fill the blocking trench, and the sidewalls located in the blocking trench are used as the second dividing layer. By first forming the blocking trench and then filling the sidewalls into the blocking trench to form the second dividing layer, it is beneficial to simplify the process and improve process compatibility.

[0053] Reference Figure 11 , Figure 11 a is a top view, Figure 11 b is Figure 11 b is a cross-sectional view along the y2-y2 cut line of a. Sidewalls 190 are formed on the sidewalls of the first trench 180, and the sidewalls 190 located on the sidewalls of the first trench 180 enclose the first groove 210. The first groove 210 is used to define a partial pattern of the target pattern. In this embodiment, using the first trench 180 and the sidewalls 190 to define the shape and position of the first groove 210 is beneficial to make the first groove 210 have smaller dimensions.

[0054] The sidewalls 190 are made of a material that has an etching selectivity with respect to the sacrificial layer 140, the etching-resistant layer 130, and the target layer 100. The materials of the sidewalls 190 include one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon.

[0055] In this embodiment, the sidewalls 190 are formed by atomic layer deposition process, which is beneficial to improve the thickness uniformity of the sidewalls 190 and is easy to precisely control the thickness of the sidewalls 190. The atomic layer deposition process has a high step coverage ability. Therefore, in this embodiment, the sidewalls 190 are also formed on the top surfaces of the etching-resistant layer 130 and the sacrificial layer 140, and on the bottom surface of the first trench 180.

[0056] In this embodiment, the subsequent steps further include: forming a first dividing layer in the first groove 210, the first dividing layer extends along the second direction, and the first dividing layer is in contact with the sidewalls of the first groove 210. The first dividing layer divides the first groove 210 along the first direction.

[0057] Among them, the step of forming the first division layer includes the steps of forming a division material layer and removing the division material layer above the top surface of the sacrificial layer 140. In this embodiment, the sidewalls 190 located on the top surfaces of the anti-etching layer 130 and the sacrificial layer 140 and the bottom surface of the first trench 180 are retained. Thus, during the subsequent back-etching of the division material layer to form the first division layer, the sidewalls 190 on the top surfaces of the anti-etching layer 130 and the sacrificial layer 140 can temporarily define the position where etching stops, so as to reduce the probability of accidentally etching the anti-etching layer 130 and the sacrificial layer 140. Moreover, the process of back-etching the division material layer only needs an etching selectivity ratio between the division material layer and the sidewalls 190, which is also beneficial to reducing the process difficulty of back-etching the division material layer to form the first division layer.

[0058] In other embodiments, after forming sidewalls on the top surfaces of the anti-etching layer and the sacrificial layer, and on the sidewalls and the bottom surface of the first trench, the forming method may further include: removing the sidewalls on the top surfaces of the anti-etching layer and the sacrificial layer, and on the bottom surface of the first trench, so as to only retain the sidewalls located on the sidewalls of the first trench.

[0059] Reference Figures 12 to 14 , a first division layer 215 extending in the second direction is formed in the first groove 210. The first division layer 215 is in contact with the sidewalls of the first groove 210 and divides the first groove 210 in the first direction. In this embodiment, the first division layer 215 divides the first groove 210 in the first direction, so that in the first direction, a smaller distance is achieved between adjacent first grooves 210. Furthermore, it is beneficial to achieve a smaller line end distance at the head-to-head position of the target pattern, improving the design freedom of the target pattern.

[0060] In this embodiment, the first division layer 215 is made of a material having an etching selectivity with respect to the sacrificial layer 140, so that the first division layer 215 can be retained during the subsequent removal of the sacrificial layer 140. Specifically, the material of the first division layer 215 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon. In this embodiment, after forming the first groove 210 and before removing the sacrificial layer 140, the first division layer 215 is formed.

[0061] In this embodiment, the step of forming the first division layer 215 includes:

[0062] As Figure 12 shown, Figure 12 a is a top view, Figure 12 b is Figure 12A cross-sectional view along the y2-y2 secant line, a support layer 213 is formed on the core layer 120 (i.e., the etch-resistant layer 130) and the sacrificial layer 140 in the second region 120b. The support layer 213 is used to form a cutting opening subsequently. After the cutting opening is formed, the support layer 213 is used to provide support for forming the first dividing layer in the cutting opening.

[0063] After the first dividing layer is formed, the support layer 213 is also removed. Therefore, the support layer 213 is selected from materials that are easy to remove to reduce the difficulty of removing the support layer 213. Specifically, the material of the support layer 213 may also include one or several of SOC, Organic Dielectric layer (ODL), bottom anti-reflection coating, Silicon Anti-reflective coating (Si-ARC), Deep UV light absorbing Oxide (DUO), Dielectric Anti-reflective Coating (DARC), and Advanced Patterning Film (APF). In this embodiment, the support layer 213 includes a fourth planarization layer 211 and a fourth patterned layer 212 located on the fourth planarization layer 211.

[0064] As Figure 12 shown, a cutting opening 216 is formed in the support layer 213. The cutting opening 216 extends across the first groove 210 in the second direction and exposes a part of the width of the first groove 210. The cutting opening 216 is used to define the size, shape, and position of the first dividing layer. In this embodiment, an anisotropic dry etching process is used to etch the support layer 213 to form the cutting opening 216. The anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate is greater than the lateral etching rate, which is beneficial to improving the profile controllability of the cutting opening 216, so as to make the opening size and profile morphology of the cutting opening 216 meet the process requirements, and further beneficial to improving the size accuracy and profile morphology quality of the subsequent first dividing layer.

[0065] As Figures 13 to 14 shown, a first dividing layer 215 is formed in the cutting opening 216.

[0066] Specifically, the steps of forming the first dividing layer 215 include: as Figure 13 shown, a dividing material layer 217 is filled in the cutting opening 216, and the dividing material layer 217 also covers the support layer 213; as Figure 14 shown, Figure 14 a is a top view, Figure 14 b isFigure 14 A cross-sectional view along the y2-y2 secant line, removing the divided material layer 217 above the top surface of the sacrificial layer 140, and the remaining divided material layer 217 located in the first groove 210 is used as the first dividing layer 215.

[0067] In this embodiment, the process for forming the divided material layer 217 includes one or two of chemical vapor deposition process, atomic layer deposition process, and spin coating process. The gap filling ability of the process for forming the divided material layer 217 is strong, which is beneficial to improving the filling quality of the divided material layer 217 in the cutting opening 216, reducing the probability of defects such as voids in the divided material layer 217, and further improving the morphological quality of the first dividing layer 215, ensuring the dividing effect of the first dividing layer 215 on the first groove 210.

[0068] In this embodiment, during the process of removing the divided material layer 217 above the top surface of the sacrificial layer 140, the sidewall 190 located on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 is used to define the position where the etching stops, and the process of back-etching the divided material layer 217 only needs to have an etching selectivity ratio for the divided material layer 217 and the sidewall 190, which is beneficial to reducing the process difficulty of removing the divided material layer 217 above the top surface of the sacrificial layer 140.

[0069] As Figure 14 shown, the support layer 213 is removed. The process for removing the support layer 213 includes one or two of dry etching and wet etching processes. In this embodiment, after forming the first dividing layer 215, the sidewall 190 located on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130, and the bottom surface of the first groove 210 is exposed.

[0070] Refer to Figure 15 , Figure 15 a is a top view, Figure 15 b is Figure 15 a cross-sectional view along the y2-y2 secant line. In this embodiment, the forming method further includes: after forming the first dividing layer 215, removing the sidewall 190 located on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first groove 210, so as to expose the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first groove 210, facilitating the subsequent removal of the sacrificial layer 140 and patterning the target layer 100. It should be noted that the sidewall 190 located at the bottom of the first dividing layer 215 is retained under the covering action of the first dividing layer 215.

[0071] Specifically, in this embodiment, an anisotropic dry etching process is adopted to remove the sidewalls 190 located on the top surfaces of the sacrificial layer 140 and the etching-resistant layer 130 and on the bottom surface of the first groove 210. The anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate is greater than the lateral etching rate. Thus, while removing the sidewalls 190 on the top surfaces of the sacrificial layer 140 and the etching-resistant layer 130 and on the bottom surface of the first groove 210, the lateral etching of the sidewalls 190 on the sidewalls of the first groove 210 is less, so that the sidewalls 190 on the sidewalls of the first groove 210 can be retained, thereby ensuring the masking function of the sidewalls 190 for the patterned target layer 100 and realizing the spacing function between the first groove 210 and the second groove.

[0072] Reference Figures 16 to 17 , Figure 16 is a top view, Figure 17 a is Figure 16 a cross-sectional view along the secant line y2 - y2, Figure 17 b is Figure 16 a cross-sectional view along the secant line y3 - y3. After the first ion doping and the formation of the sidewalls 190, the sacrificial layer 140 is removed, and a second groove 220 is formed in the etching-resistant layer 130.

[0073] The second groove 220 is correspondingly located on both sides of the first groove 210. The second groove 220 and the first groove 210 jointly define the pattern of the target pattern. The second groove 220 and the first groove 210 are isolated by the sidewalls 190, which is easy to make the minimum design spacing between the second groove 220 and the first groove 210 satisfied. In this embodiment, the end of the first groove 210 protrudes from the second groove 220 along the first direction, the second groove 220 is located on both sides of the first groove 210, and the second grooves 220 are spaced apart from each other.

[0074] In this embodiment, there is a high etching selectivity between the sacrificial layer 140 and the etching-resistant layer 130. In the step of removing the sacrificial layer 140 to form the second groove 220, it is not easy to cause double etching to the first groove 210, correspondingly reducing the process risk and ensuring the pattern accuracy of the first groove 210.

[0075] It should be noted that in any one or both of the first groove 210 and the second groove 220, a dividing layer extending along the second direction is formed, and the dividing layer divides the corresponding groove along the first direction. The dividing layer divides the corresponding groove along the first direction, so that in the first direction, a smaller distance can be achieved between adjacent grooves, which is conducive to making the target pattern have a smaller line end distance at the head-to-head position and improving the design freedom of the target pattern.

[0076] As an example, a first dividing layer 215 is formed in the first groove 210. The first dividing layer 215 extends along the second direction and is in contact with the side wall of the first groove 210. As an example, a second dividing layer 145 is formed in the second groove 220. The second dividing layer 145 extends along the second direction and divides the second groove 220 along the first direction. In other embodiments, a dividing layer is formed in any one of the first groove and the second groove.

[0077] The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching. As an example, the wet etching process is used to remove the sacrificial layer 140. In this embodiment, the etching solution for wet etching includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution or an SC2 solution. The SC1 solution refers to a mixed solution of NH4OH and H2O2, and the SC2 solution refers to a mixed solution of HCl and H2O2.

[0078] Reference Figures 18 to 19 , Figure 18 is a top view, Figure 19 a is Figure 18 a cross-sectional view along the y2-y2 secant line, Figure 19 b is Figure 18 a cross-sectional view along the y3-y3 secant line. Using the anti-etching layer 130, the sidewall 190, and the dividing layer as a mask, the target layer 100 below the first groove 210 and the second groove 220 is etched to form the target pattern 230.

[0079] Specifically, in this embodiment, using the anti-etching layer 130, the sidewall 190, and the first dividing layer 215 and the second dividing layer 145 as a mask, the target layer 100 below the first groove 210 and the second groove 220 is etched.

[0080] In this embodiment, by superimposing the pattern of the first region 120a and the pattern of the first trench 180, the pattern of the second groove 220 is defined, so that the second groove 220 can achieve a smaller size, and it is easy to meet the minimum design interval between the second groove 220 and the first groove 210. Furthermore, without changing the limit conditions of the lithography process, it is beneficial to make the target pattern 230 achieve a smaller critical dimension and further compress the pitch between the target patterns 230 to meet the requirements of high density and high integration of integrated circuits. Moreover, the modification to the existing process is small, the process complexity is low, the lithography process is highly friendly, which is beneficial to improving the matching degree between the target pattern 230 and the design pattern, and improving the pattern accuracy of the target pattern 230.

[0081] In addition, the dividing layer divides the corresponding grooves along the first direction, so that a smaller distance can be achieved between adjacent grooves along the first direction. Furthermore, it is beneficial to enable a smaller line-end distance at the head-to-head position of the target pattern, thereby improving the design freedom of the target pattern.

[0082] In this embodiment, the target layer 100 is a dielectric layer. Using the anti-etching layer 130, the sidewall 190, and the dividing layer as masks, the dielectric layer below the first groove 210 and the second groove 220 is etched to form the interconnect groove 30. The target pattern 230 is correspondingly the interconnect groove 30, which provides space for forming metal interconnections.

[0083] Specifically, using the anti-etching layer 130, the sidewall 190, and the dividing layer as masks, the hard mask material layer 115 below the first groove 210 and the second groove 220 is etched to form the hard mask layer 105. Using the hard mask layer 105 as a mask, the dielectric layer is patterned to form the interconnect groove 30. In this embodiment, in the step of etching the target layer 100 below the first groove 210 and the second groove 220, the anti-etching layer 130, the sidewall 190, and the dividing layer are also consumed by a certain thickness.

[0084] Reference Figure 20 , a metal interconnection 240 is formed in the interconnect groove 30. The metal interconnection 240 is used to realize the electrical connection between the semiconductor structure and an external circuit or other interconnection structures.

[0085] In this embodiment, the interconnect groove 30 can achieve a smaller critical dimension, and the pitch between the interconnect grooves 30 is further compressed, which is beneficial to further compressing the pitch of the metal interconnection 240 to meet the requirements of high density and high integration of integrated circuits. Moreover, it is easy to meet the design minimum spacing between the interconnect grooves 30, and the pattern accuracy of the interconnect groove 30 is relatively high. Correspondingly, it is beneficial to make the metal interconnections 240 meet the design minimum spacing and improve the pattern accuracy of the metal interconnections 240, thereby enhancing the performance of the semiconductor structure. In addition, the interconnect groove 30 can achieve a smaller line-end distance at the head-to-head position, so that the metal interconnection 240 can achieve a smaller line-end distance, which is beneficial to improving the design freedom of the metal interconnection 240 and the wiring ability of the metal interconnection 240.

[0086] Figures 21 to 22 is the top view corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. The same parts as those in the foregoing embodiment will not be described herein again. The differences are as follows:

[0087] Reference Figure 21a. A first ion doping is performed on the core layer (not shown) in the second region (not labeled) to improve the etching resistance of the core layer 320. The ion-doped core layer 320 in the second region serves as an anti-etching layer 330. As an example, the first ion doping is performed before forming the first trench.

[0088] refer to Figure 21 b, forming a first direction (such as Figure 21 The first groove 380 (shown in the X direction) penetrates at least a portion of the first region core layer 320, and the direction perpendicular to the first direction is the second direction (shown in the X direction). Figure 21 In the second direction, a portion of the core layer 320 in the first region is retained on both sides of the first trench 380 to serve as a sacrificial layer 340 .

[0089] The first trench 380 includes a first sidewall 381 extending along the second direction, and a second sidewall 382 opposite to and parallel to the first sidewall 381. In this embodiment, the first sidewall 381 of the first trench 380 is located in the first region, with a gap between the first sidewall 381 and the boundary on the same side of the first region; the second sidewall 382 of the first trench 380 is flush with the boundary on the same side of the first region, or the second sidewall 382 of the first trench 380 is located in the adjacent second region.

[0090] Specifically, in this embodiment, the first sidewall 381 of the first trench 380 is located in the sacrificial layer 340, and a gap exists between the first sidewall 381 and the sidewall on the same side of the sacrificial layer 340. The second sidewall 382 of the first trench 380 is flush with the sidewall on the same side of the sacrificial layer 340, or the second sidewall 382 of the first trench 380 is located in the adjacent anti-etching layer 330. As an example, the first sidewall 381 of the first trench 380 is located in the sacrificial layer 340, and a gap exists between the first sidewall 381 and the sidewall on the same side of the sacrificial layer 340, and the second sidewall 382 of the first trench 380 is located in the adjacent anti-etching layer 330.

[0091] refer to Figure 22 a. Form sidewalls 390 on the sidewalls of the first trench 380 , so that the sidewalls 390 located on the sidewalls of the first trench 380 surround a first recess 310 .

[0092] refer to Figure 22b. After performing the first ion doping and forming the sidewall 390, the sacrificial layer 340 is removed, and a second groove 320 is formed in the etch-resistant layer 330. Among the first groove 310 and the second groove 320, a dividing layer extending in the second direction is formed in any one or both of the grooves, and the dividing layer divides the corresponding groove in the first direction. In the step of removing the sacrificial layer 340, the second groove 320 communicates with the first sidewall 381 at the position of the first sidewall 381. The second groove 320 correspondingly exposes the sidewall of the first sidewall 381.

[0093] Therefore, the second groove 320 not only extends in the first direction, but also the second groove 320 located outside the first sidewall 381 extends in the second direction. Thus, by using the superposition of the first region pattern and the first trench 380 pattern, the pattern of the second groove 320 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with implementing the two-dimensional pattern using the mask pattern, in this embodiment, it is beneficial to reduce the process difficulty and increase the lithography process window.

[0094] In this embodiment, the target layer is a dielectric layer. Subsequently, using the etch-resistant layer 330 and the sidewall 390 as masks, the dielectric layer below the first groove 310 and the second groove 320 is etched to form an interconnect groove, and the interconnect groove is used to provide a spatial position for forming metal interconnections. Correspondingly, the metal interconnection corresponding to the position of the second groove 320 not only extends in the first direction but also extends in the second direction, so that two-dimensional routing can be realized, which is beneficial to improving the graphic design and layout freedom of the metal interconnections and also improving the wiring ability of the metal interconnections.

[0095] As an example, a first dividing layer 315 is formed in the first groove 310. The first dividing layer 315 extends in the second direction and the first dividing layer 315 is in contact with the sidewall of the first groove 310. As an example, a second dividing layer 325 is formed in the second groove 320. The second dividing layer 325 extends in the second direction and divides the second groove 320 in the first direction.

[0096] For the specific descriptions of the first dividing layer 315 and the second dividing layer 325, reference can be made to the corresponding descriptions in the foregoing embodiments, and details are not repeated here. For the specific description of the formation method of the semiconductor structure in this embodiment, reference can be made to the corresponding descriptions in the foregoing embodiments, and details are not repeated here.

[0097] Figures 23 to 24 It is the top view corresponding to each step in another embodiment of the formation method of the semiconductor structure of the present invention. The same parts as those in the foregoing embodiments are not repeated here, and the differences are as follows:

[0098] Reference Figure 23a. Perform a first ion doping on the core layer 420 of the second region, which is suitable for improving the etching resistance of the core layer 420. The core layer 420 doped with ions and located in the second region serves as the etching-resistant layer 430.

[0099] As an example, the first ion doping is performed before forming the first trench.

[0100] Reference Figure 23 b. Form a first trench 480 that penetrates at least part of the core layer 420 of the first region along the first direction (such as the X direction shown in Figure 23 ). The direction perpendicular to the first direction is the second direction (such as the Y direction shown in Figure 23 ). In the second direction, part of the core layer 420 of the first region is reserved on both sides of the first trench 480 for serving as the sacrificial layer 440. The first trench 480 is located in the core layer 420 of the first region, and in the first direction, there is a gap between the sidewall of the first trench 480 and the boundary on the same side of the first region.

[0101] Specifically, in the first direction, there is a gap between the sidewall of the first trench 480 and the sidewall on the same side of the sacrificial layer 440. Moreover, in the second direction, part of the core layer 420 of the first region is reserved on both sides of the first trench 480, that is, in the second direction, there is also a gap between the sidewall of the first trench 480 and the sidewall on the same side of the sacrificial layer 440. Therefore, the sacrificial layer 440 surrounds the first trench 480.

[0102] Reference Figure 24 a. Form sidewalls 490 on the sidewalls of the first trench 480, so that the sidewalls 490 located on the sidewalls of the first trench 480 enclose a first groove 410.

[0103] Reference Figure 24 b. After performing the first ion doping and forming the sidewalls 490, remove the sacrificial layer 440 to form a second groove 420 in the etching-resistant layer 430. Among the first groove 410 and the second groove 420, a dividing layer extending along the second direction is formed in any one or both of the grooves, and the dividing layer divides the corresponding groove along the first direction. In this embodiment, the sacrificial layer 440 surrounds the first groove 410. Therefore, after removing the sacrificial layer 440, the formed second groove 420 surrounds the first groove 410. Specifically, the second groove 420 surrounds the outer sidewall of the sidewalls 490, and the second groove 420 is an annular groove.

[0104] Accordingly, the second groove 420 not only extends along the first direction but also along the second direction. Thus, by using the superposition of the first region pattern and the first trench 480 pattern, the pattern of the second groove 420 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with implementing the two-dimensional pattern by using the mask pattern, this embodiment is beneficial to reducing the process difficulty and increasing the lithography process window.

[0105] In this embodiment, the target layer is a dielectric layer. Subsequently, using the anti-etching layer 430 and the sidewall 490 as masks, the dielectric layer below the first groove 410 and the second groove 420 is etched to form an interconnect groove, which is used to provide a spatial position for forming metal interconnect lines. Accordingly, the metal interconnect line corresponding to the position of the second groove 420 not only extends along the first direction but also along the second direction, so that two-dimensional wiring can be realized, which is beneficial to improving the graphic design and layout freedom of the metal interconnect line and also improving the wiring ability of the metal interconnect line.

[0106] In this embodiment, a first dividing layer 415 is formed in the first groove 410 to divide the first groove 410 along the first direction; a second dividing layer 425 is formed in the second groove 420 to divide the second groove 420 along the first direction. For a detailed description of the formation method of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and this embodiment will not be elaborated herein.

[0107] Figures 25 to 27 It is a top view corresponding to each step in another embodiment of the formation method of the semiconductor structure of the present invention. The same parts of this embodiment and the foregoing embodiments will not be elaborated herein. The differences are as follows:

[0108] As Figure 25 shown in a, a core layer 12 is formed on the substrate, including a first region 12a and a second region 12b surrounding the first region 12a; the number of the first regions 12a is multiple and arranged along the second direction, and the multiple first regions 12a are separated from each other. The shape, position, arrangement mode, and number of the first regions 12a in this embodiment are only examples, and the shape, position, number, and arrangement mode of the first regions 12a are not limited thereto.

[0109] As Figure 25 shown in b, the second region 12b of the core layer 12 is subjected to a first ion doping, which is suitable for improving the etching resistance of the core layer 12. The core layer 12 with doped ions in the second region 12b serves as the anti-etching layer 13.

[0110] As Figure 26 shown in a, a first trench 15 of the core layer 12 is formed along the first direction (as shown by the X direction in Figure 26 ) that penetrates at least part of the first regions 12a. The direction perpendicular to the first direction is the second direction (as shown by the Figure 26As shown in the Y direction in the figure, in the second direction, a core layer 12 of a partial first region 12a is reserved on both sides of the first trench 15 and used as a sacrificial layer 14.

[0111] As an example, the first trench 15 may be formed only in the core layer 12 of a partial number of first regions 12a, and the first trench 15 may not be formed in the core layer 12 of the remaining number of first regions 12a. In other embodiments, according to design requirements, the first trench may also be formed in all the first regions.

[0112] As Figure 26 As shown in a, the forming method further includes: after forming the core layer 12, forming a second trench 16 that penetrates the core layer 12 located between the first regions 12a along the second direction.

[0113] As an example, after the first ion doping, the second trench 16 is formed, and the second trench 16 correspondingly penetrates the etching-resistant layer 13 located between the sacrificial layers 14 along the second direction. It should be noted that the second trench 16 and the first trench 15 may be formed in the same step or in different steps respectively. In this embodiment, the specific steps for forming the first trench 15 and the second trench 16 are not limited herein.

[0114] As Figure 26 As shown in b, a sidewall 17 is formed on the sidewall of the first trench 15, and the sidewalls 17 located on the sidewall of the first trench 15 enclose a first groove 21. In this embodiment, the sidewall 17 is also formed on the sidewall of the second trench 16, and the sidewalls 17 located on the sidewall of the second trench 16 enclose a third groove 23. The third groove 23 is also used to define the pattern of the target pattern accordingly. Correspondingly, the sacrificial layer 14 is removed subsequently to form a second groove, and the second groove, the first groove 21, and the third groove 23 are arranged along the second direction, and adjacent grooves are isolated from each other by the sidewall 17.

[0115] As Figure 27 As shown in the figure, the sacrificial layer 14 is removed to form a second groove 22 in the etching-resistant layer 13. Among them, in any one or both of the first groove 21 and the second groove 22, a dividing layer extending along the second direction is formed, and the dividing layer divides the corresponding groove along the first direction. The first groove 21, the second groove 22, and the third groove 23 are jointly used to define the pattern of the target pattern. Correspondingly, subsequently, using the etching-resistant layer 13, the sidewall 17, and the dividing layer as a mask, the target layer below the first groove 21, the second groove 22, and the third groove 23 is etched to form the target pattern.

[0116] As an example, a first dividing layer 2105 is formed in the first groove 21, and a second dividing layer 2205 is formed in a part of the second groove 22. In other embodiments, a third dividing layer may also be formed in the third groove, and the third dividing layer divides the third groove along the first direction.

[0117] For a detailed description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details thereof are not described herein again.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a target layer for forming a target pattern; Forming a core layer on the substrate, including a first region and a second region surrounding the first region; Performing a first ion doping on the core layer of the second region, suitable for improving the etching resistance of the core layer, and the core layer doped with ions in the second region is used as an etching-resistant layer; Forming a first trench penetrating at least part of the core layer of the first region along a first direction, the direction perpendicular to the first direction is the second direction, and on both sides of the first trench in the second direction, part of the core layer of the first region is reserved for use as a sacrificial layer; Forming sidewalls on the sidewalls of the first trench, so that the sidewalls located on the sidewalls of the first trench enclose a first groove; After performing the first ion doping and forming the sidewalls, removing the sacrificial layer to form a second groove in the etching-resistant layer; Wherein, in any one or both of the first groove and the second groove, a dividing layer extending along the second direction is formed, and the dividing layer divides the corresponding groove along the first direction; A second dividing layer is formed in the second groove, the second dividing layer extends along the second direction, and divides the second groove along the first direction; Using the etching-resistant layer, the sidewalls, and the dividing layer as a mask to etch the target layer below the first groove and the second groove to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein, A first dividing layer is formed in the first groove, the first dividing layer extends along the second direction, and the first dividing layer is in contact with the sidewall of the first groove.

3. The method for forming a semiconductor structure according to claim 2, wherein Before removing the sacrificial layer after forming the first groove, forming the first dividing layer in the first groove, and the first dividing layer divides the first groove along the first direction.

4. The method for forming a semiconductor structure according to claim 3, wherein The step of forming the first dividing layer includes: forming a support layer on the core layer of the second region and the sacrificial layer; forming a cutting opening in the support layer, the cutting opening crosses the first groove along the second direction and exposes a part of the width of the first groove; forming the first dividing layer in the cutting opening; removing the support layer.

5. The method for forming a semiconductor structure according to claim 1, wherein, After forming the first trench and before removing the sacrificial layer, forming the second dividing layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The step of forming the second dividing layer includes: forming a dividing mask layer on the core layer of the second region, a dividing groove is formed in the dividing mask layer, the dividing groove crosses the first region along the second direction and exposes a part of the width of the sacrificial layer; using the dividing mask layer as a mask, performing a second ion doping on the sacrificial layer exposed by the dividing groove, suitable for improving the etching resistance of the sacrificial layer, and the sacrificial layer doped with ions is used as the second dividing layer.

7. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the sidewalls, forming the second dividing layer; the method for forming the semiconductor structure further includes: after forming the core layer and before forming the sidewalls, forming a blocking groove penetrating the core layer of the first region along the second direction, and the blocking groove divides the core layer of the first region along the first direction; The step of forming the second dividing layer includes: in the step of forming the sidewall, the sidewall also fills the blocking groove, and the sidewall located in the blocking groove is used as the second dividing layer.

8. The method for forming a semiconductor structure according to claim 1, wherein In the step of forming the first trench, the first trench includes a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall; Along the first direction, the first trench penetrates the core layer of the first region; Alternatively, along the first direction, the first trench penetrates the core layer of the first region, and any one or both of the first sidewall and the second sidewall further extend into the core layer of the adjacent second region; In the step of removing the sacrificial layer, the second grooves are spaced apart from each other.

9. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the first trench, the first trench includes a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall; the first sidewall of the first trench is located in the first region, and there is a gap between the first sidewall and the boundary on the same side of the first region; the second sidewall of the first trench is flush with the boundary on the same side of the first region, or the second sidewall of the first trench is located in the adjacent second region; In the step of removing the sacrificial layer, the second grooves communicate with each other at the position of the first sidewall.

10. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the first trench, the first trench is located in the core layer of the first region, and in the first direction, there is a gap between the sidewall of the first trench and the boundary on the same side of the first region; In the step of removing the sacrificial layer, the second grooves surround the first groove.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the core layer and before forming the first trench, perform a first ion doping on the core layer of the second region; or, after forming the first trench and before forming the sidewall, perform a first ion doping on the core layer of the second region; or, after forming the sidewall and before removing the sacrificial layer, perform a first ion doping on the core layer of the second region.

12. The method for forming a semiconductor structure according to claim 1, wherein, The material of the core layer includes one or several of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and carbon oxynitride.

13. The method for forming a semiconductor structure according to claim 1, wherein, The ions for the first ion doping include one or more of boron ions, phosphorus ions, and argon ions.

14. The method for forming a semiconductor structure according to claim 1, wherein, Adopt an ion implantation process to perform a first ion doping on the core layer of the second region.

15. The method for forming a semiconductor structure according to claim 1, wherein The step of forming the first trench includes: forming a mask layer on the core layer, the mask layer having a mask opening extending along the first direction; on the projection plane parallel to the substrate, the first region spans the mask opening along the second direction; using the mask layer as a mask, removing the core layer below the mask opening to form the first trench; removing the mask layer.

16. The method for forming a semiconductor structure according to claim 1, wherein The etching selectivity between the sacrificial layer and the anti-etching layer is at least 20:

1.

17. The method for forming a semiconductor structure according to claim 1, wherein, The number of the first regions is multiple and arranged along the second direction, and the multiple first regions are separated from each other; The method for forming the semiconductor structure further includes: after forming the core layer and before forming the sidewall, forming a second trench that penetrates the core layer located between the first regions along a second direction; In the step of forming the sidewall, the sidewall is further formed on the sidewalls of the second trench, and the sidewalls located on the sidewalls of the second trench enclose a third groove; Using the anti-etching layer and the sidewall as masks, etching the first groove, the second groove, and the target layer under the third groove to form a target pattern.

18. The method for forming a semiconductor structure according to claim 1, wherein, The process of removing the sacrificial layer includes a wet etching process.

19. The method for forming a semiconductor structure according to claim 1, wherein, The target layer is a dielectric layer; the target pattern is an interconnect trench; The method for forming the semiconductor structure further includes: after forming the interconnect trench, forming a metal interconnect in the interconnect trench.

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