Three-dimensional memory and fabrication methods, storage systems, electronic devices

Abstract

The disclosure provides a three-dimensional memory and a manufacturing method, a storage system and an electronic device, and relates to the technical field of semiconductor chips, aiming to improve the problem of incomplete filling of gate line material. The three-dimensional memory comprises a plurality of dielectric layers, a plurality of channel structures and a plurality of contact structures, a first gate line isolation structure, an intermediate isolation structure and a second gate line isolation structure. The intermediate isolation structure extends from the array region to the transition region, and the first gate line isolation structure and the second gate line isolation structure extend from the array region to the contact region. The dielectric layer comprises a first sub-gate line, a second sub-gate line and a connecting portion. The connecting portion exceeds the intermediate isolation structure in the first direction and is in contact with the first sub-gate line and the second sub-gate line. The first sub-gate line has a first notch in the middle of one end close to the contact region, and the second sub-gate line has a second notch in the middle of one end close to the contact region. In the second direction, the connecting portion does not exceed the edges of the first notch and the second notch close to each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a three-dimensional memory, a manufacturing method thereof, a storage system and an electronic device. BACKGROUND

[0002] As the feature size of the storage unit approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of the 2D or planar NAND flash memory to approach the upper limit.

[0003] In order to overcome the limitations of the 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve the storage density by arranging the storage units three-dimensionally on the substrate.

[0004] In the process of manufacturing the 3D NAND, a gap can be formed by removing part of the material layer. Then, the gate line material can be deposited in the gap to form the gate line in the 3D NAND. However, in the above manufacturing process, when the gate line material is deposited in the gap, there is a problem of incomplete filling of the gate line material, which affects the performance of the 3D NAND. SUMMARY

[0005] Embodiments of the present disclosure provide a three-dimensional memory, a manufacturing method thereof, a storage system and an electronic device, aiming to improve the problem of incomplete filling of the gate line material.

[0006] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a three-dimensional memory having an array region, a transition region, and a contact region is provided. The transition region is disposed between the array region and the contact region. The three-dimensional memory includes a plurality of dielectric layers disposed in a stack, a plurality of channel structures and a plurality of contact structures extending in the plurality of dielectric layers, a first gate line isolation structure, an intermediate isolation structure, and a second gate line isolation structure penetrating the plurality of dielectric layers. The plurality of channel structures are disposed in the array region, and the plurality of contact structures are disposed in the contact region. The intermediate isolation structure is between the first gate line isolation structure and the second gate line isolation structure. The intermediate isolation structure extends from the array region to the transition region, and the first gate line isolation structure and the second gate line isolation structure extend from the array region to the contact region. The dielectric layer includes a first sub-gate line, a second sub-gate line, and a connecting portion. The first sub-gate line is between the first gate line isolation structure and the intermediate isolation structure, the second sub-gate line is between the second gate line isolation structure and the intermediate isolation structure, and the connecting portion is beyond the intermediate isolation structure in a first direction and contacts the first sub-gate line and the second sub-gate line. The first sub-gate line has a first gap in a middle of an end close to the contact region, and the second sub-gate line has a second gap in a middle of an end close to the contact region. In a second direction perpendicular to the first direction, the connecting portion is not beyond edges of the first gap and the second gap that are close to each other.

[0008] In some embodiments, the dielectric layer further includes a first connecting line and a second connecting line. The first connecting line and the second connecting line extend from the transition region to the contact region. The first connecting line is located at a side of the first gate line isolation structure close to the plurality of contact structures. The second connecting line is located at a side of the second gate line isolation structure close to the plurality of contact structures. The three-dimensional memory includes a first contact structure and a first dielectric layer. The first contact structure is one of the plurality of contact structures, and the first dielectric layer is one of the plurality of dielectric layers. The first contact structure is electrically connected to the first sub-gate line in the first dielectric layer through the first connecting line in the first dielectric layer.

[0009] In some embodiments, a distance between the first contact structure and the first gate line isolation structure is less than a distance between the first contact structure and the second gate line isolation structure.

[0010] In some embodiments, the three-dimensional memory further includes a second contact structure and a second dielectric layer. The second contact structure is one of the plurality of contact structures, and the second dielectric layer is one of the plurality of dielectric layers. The second contact structure is electrically connected to the second sub-gate line in the second dielectric layer through the second connecting line in the second dielectric layer. A distance between the second contact structure and the second gate line isolation structure is less than a distance between the second contact structure and the first gate line isolation structure.

[0011] In some embodiments, the contact structure includes, in sequence along the thickness direction of the three-dimensional memory, a contact portion and a connecting pillar, the contact portion and the connecting pillar are electrically connected, the contact portion is electrically connected to the first sub-gate line, the second sub-gate line and the connecting portion and is located at the same level.

[0012] In some embodiments, along a direction perpendicular to the thickness direction of the three-dimensional memory, a size of the connecting pillar is greater than a size of the channel structure, and / or, along the direction perpendicular to the thickness direction of the three-dimensional memory, a size of the contact portion is greater than a size of the connecting pillar.

[0013] In some embodiments, the dielectric layer further includes an embedded portion, the embedded portion is located between the first gate line isolation structure and the second gate line isolation structure, the embedded portion extends from the contact region to the transition region, and is embedded in the first gap and the second gap.

[0014] In some embodiments, the three-dimensional memory further includes a first dummy channel structure disposed at the contact region, the first dummy channel structure penetrates the first connecting line; and / or, a second dummy channel structure disposed at the contact region, the second dummy channel structure penetrates the second connecting line; and / or, a third dummy channel structure disposed at the transition region.

[0015] In some embodiments, the three-dimensional memory further includes a source layer and a peripheral circuit. The channel structure and the source layer are electrically connected, the channel structure and the peripheral circuit are electrically connected, and the source layer and the peripheral circuit are disposed on both sides of the channel structure.

[0016] In another aspect, a storage system is provided, including the three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0017] In another aspect, an electronic device is provided, including the storage system as described above.

[0018] In another aspect, a method of fabricating a three-dimensional memory is provided, including: forming a stack structure on a substrate, the stack structure including a plurality of first material layers and a plurality of second material layers stacked, the stack structure having a first region and a second region. Forming a first gate line slit, an isolation slit, and a second gate line slit extending through the stack structure and from the first region to the second region, the isolation slit being between the first gate line slit and the second gate line slit, a length of the isolation slit in the second region being less than a length of the first gate line slit and the second gate line slit in the second region. Removing a portion of the first material layers through the first gate line slit, the isolation slit, and a portion of the second gate line slit in the first region, forming a first gap between the first gate line slit and the isolation slit, and a second gap between the second gate line slit and the isolation slit, the portion of the isolation slit in the second region including an overhang portion, the overhang portion overhanging the first gap and the second gap in a first direction, the first direction being parallel to an extension direction of the isolation slit. Removing a portion of the first material layers along a circumferential direction of the overhang portion through the portion of the isolation slit in the second region.

[0019] In some embodiments, a width of the portion of the first material layers removed along the circumferential direction of the overhang portion through the portion of the isolation slit in the second region is less than half of a width of the first gap and less than half of a width of the second gap.

[0020] In some embodiments, the method of fabricating a three-dimensional memory further includes: removing a portion of the first material layers through the portion of the first gate line slit in the second region. Removing a portion of the first material layers through the portion of the second gate line slit in the second region.

[0021] In some embodiments, the method of fabricating a three-dimensional memory further includes: forming a first sub-gate line, a second sub-gate line, a connection portion, a first connection line, and a second connection line through the first gate line slit, the second gate line slit, and the isolation slit. The first sub-gate line is between the first gate line slit and the isolation slit, the second sub-gate line is between the second gate line slit and the isolation slit, the connection portion overhangs the isolation slit in the first direction and contacts the first sub-gate line and the second sub-gate line, the first connection line contacts the first sub-gate line, and the second connection line contacts the second sub-gate line.

[0022] In some embodiments, the method of fabricating a three-dimensional memory further includes forming a contact structure extending in a third direction in the stack structure with the first connection line and the second connection line, the contact structure being electrically connected to the first connection line and the second connection line, the third direction being parallel to a thickness direction of the stack structure.

[0023] In some embodiments, forming the contact structure extending along the third direction in the stack structure with the first connection line and the second connection line comprises: forming a contact hole on the surface of the stack structure away from the substrate, the contact hole exposing a portion of the first material layer, and a sidewall of the contact hole being enclosed by the third material. A portion of the first material layer is removed through the contact hole. The contact structure is formed through the contact hole.

[0024] In some embodiments, forming the contact hole on the surface of the stack structure away from the substrate comprises: forming a first hole on the surface of the stack structure away from the substrate, the first hole being located at a side of the first material layer away from the substrate and exposing a portion of the second material layer in contact with the first material layer. The third material is deposited in the first hole to obtain a second hole. The bottom of the second hole is etched to form the contact hole.

[0025] In some embodiments, the method for manufacturing the three-dimensional memory further comprises: before forming the first gap and the second gap, forming a first shielding structure located at the first region and a second shielding structure located at the second region in the first gate line slit, the isolation structure, and the second gate line slit. The first shielding structure is removed, and the second shielding structure is retained.

[0026] In some embodiments, the method for manufacturing the three-dimensional memory further comprises: after forming the first gap and the second gap, before removing the portion of the first material layer along the circumferential direction of the overhang, the second shielding structure is removed.

[0027] In some embodiments, the method for manufacturing the three-dimensional memory further comprises: before forming the first gate line slit, the isolation slit, and the second gate line slit extending through the stack structure and extending from the first region to the second region, a channel structure extending along a third direction is formed in the stack structure, the third direction being parallel to a thickness direction of the three-dimensional memory.

[0028] In the three-dimensional memory provided by the embodiments of the present disclosure, since the first gate line isolation structure and the second gate line isolation structure extend from the array region to the contact region, and the intermediate isolation structure extends from the array region to the transition region, in other words, the intermediate isolation structure is not arranged in the contact region, the size of the contact structure located in the contact region can be larger. Further, since the first sub-gate line has the first notch in the middle of the end close to the contact region, the second sub-gate line has the second notch in the middle of the end close to the contact region, and in the second direction, the connecting portion does not exceed the edges of the first notch and the second notch close to each other, in the process of manufacturing the gate line, the gap used to form the connecting portion can be smaller, for example, the gap does not exceed the edges of the first notch and the second notch close to each other in the second direction. When the gate line material is deposited, the gate line material can be deposited in the gap with smaller volume, that is, the connecting portion can be formed. In this way, the problem of incomplete filling of the gate line material can be improved, and the structural stability of the three-dimensional memory can be improved.

[0029] It is understood that the beneficial effects of the three-dimensional memory manufacturing method, storage system and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the three-dimensional memory mentioned above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a schematic diagram of the structure of a three-dimensional memory according to some embodiments;

[0032] Figure 2 An equivalent circuit diagram of a storage cell block in a three-dimensional memory according to some embodiments;

[0033] Figure 3 This is a structural diagram of a string of storage cells in a three-dimensional memory according to some embodiments;

[0034] Figure 4 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0035] Figure 5 for Figure 4 A top view of the first semiconductor structure in a three-dimensional memory;

[0036] Figure 6 for Figure 5 A cross-sectional view of the first semiconductor structure along section line AA';

[0037] Figure 7 for Figure 5 A cross-sectional view of the first semiconductor structure along section line BB';

[0038] Figure 8 for Figure 6 A magnified view of a portion of region W1 in the first semiconductor structure;

[0039] Figure 9 A top view of a first semiconductor structure in a three-dimensional memory according to some embodiments;

[0040] Figure 10 and Figure 11 This is a cross-sectional view of the first semiconductor structure;

[0041] Figure 12A is a top view of a first semiconductor structure in a three-dimensional memory in the related art;

[0042] Figure 12B is a process flow diagram of forming a gap by an etching process in the related art;

[0043] Figure 13 is a cross-sectional view of the first semiconductor structure;

[0044] Figures 14A-14C is a process flow diagram of a method of fabricating a contact structure in a three-dimensional memory according to some embodiments;

[0045] Figure 15 is a cross-sectional view of a first semiconductor structure in a three-dimensional memory according to some embodiments;

[0046] Figure 16 is a block diagram of a memory system according to some embodiments;

[0047] Figure 17 is a block diagram of a memory system according to some embodiments;

[0048] Figure 18 is a flow diagram of a method of fabricating a three-dimensional memory according to some embodiments;

[0049] Figures 19A-19M is a process flow diagram of a method of fabricating a three-dimensional memory according to some embodiments;

[0050] Figure 20 is a process flow diagram of forming a gap by an etching process in the related art;

[0051] Figures 21-27 is a process flow diagram of a method of fabricating a contact structure in a three-dimensional memory according to some embodiments. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0053] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "horizontal", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the present disclosure.

[0054] Unless otherwise required by context, the term "including" as used herein is to be interpreted as open, i.e. meaning "including, but not limited to." In the description of the embodiments, the terms "one embodiment," "some embodiments," "an exemplary embodiment," "an example embodiment," "exemplary embodiments," or "some examples" are not necessarily referring to the same embodiment or example, but are used to describe different embodiments or examples, some of which can be mutually exclusively, some can be inclusive, and some can be partially exclusive.

[0055] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and are not to be construed as indicating or implying relative importance or implying the number of the technical features indicated. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0056] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0057] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0058] The use of "configured to" herein means open and inclusive language that does not exclude devices that are adapted to perform additional tasks or steps.

[0059] In addition, the use of "based on" means open and inclusive, as the process, step, calculation, or other action that is "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0060] As used herein, "approximately" or "about" includes the recited value and the average value within an acceptable range of deviation from the specific value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error in measurement associated with the specific quantity being measured (i.e., the limitations of the measurement system).

[0061] In the present disclosure, the meaning of "on," and "over" should be interpreted in the broadest context, such that "on" means not only "directly on" but also "on with an intervening feature or layer therebetween," and "over" means not only "over" but also "over" without an intervening feature or layer therebetween (i.e., directly on).

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0063] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0064] The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "memory cell strings," e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate or source layer and extending in a direction perpendicular to the major surface (i.e., lateral surface) of the substrate or source layer. As used herein, the term "perpendicular / perpendicularly" means nominally perpendicular to the major surface of the substrate or source layer.

[0065] Some embodiments of the present disclosure provide a three-dimensional memory. Figure 1 A schematic diagram of a structure of a three-dimensional memory according to some embodiments. Figure 2 An equivalent circuit diagram of a memory cell block in a three-dimensional memory according to some embodiments. Figure 3 A structure diagram of a memory cell string in a three-dimensional memory according to some embodiments.

[0066] Referring to Figure 1 The three-dimensional memory 10 can include a first semiconductor structure 100. The three-dimensional memory 10 can also include a peripheral circuit 210 electrically connected to the first semiconductor structure 100.

[0067] Specifically, the first semiconductor structure 100 includes one or more memory cell blocks BLK, such as memory cell blocks BLK1-BLKm (m is an integer greater than or equal to 2). Figure 1 Each of the plurality of memory cell blocks BLK in the first semiconductor structure 100 can be implemented as shown in Figure 2 .

[0068] Referring to Figure 2 , the memory cell block BLK includes at least one (e.g., one; or alternatively, a plurality of) memory cell transistor string NS (referred to herein as a "memory cell string", such as a NAND memory cell string), such as memory cell strings NS11-NS33. It should be noted that Figure 2 The number of memory cell strings in a memory cell block shown is merely illustrative, and embodiments of the present disclosure do not limit the number of memory cell strings in a memory cell block.

[0069] Referring to Figure 2 , the memory cell block BLK can also include a source layer SL. A memory cell string NS (e.g., each memory cell string NS) in the memory cell block BLK is electrically connected to the source layer SL.

[0070] The source layer SL can include a semiconductor material, such as monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL can be partially or entirely doped.

[0071] Continuing to refer to Figure 2 , a memory cell string NS (e.g., each memory cell string NS) includes a plurality of transistors T.

[0072] Referring to Figure 2 , the plurality of transistors T can include at least one (e.g., one; or alternatively, a plurality of) memory cell transistor MC (referred to herein as a memory cell MC), such as memory cells MC1-MC4. The plurality of memory cells MC can be connected in series with each other. The memory cell MC can be configured to store data. In the first semiconductor structure 100, the memory cells MC are distributed in an array, and thus the first semiconductor structure 100 can also be referred to as an array device. It should be noted that Figure 2 The number of memory cells MC in a memory cell string shown is merely illustrative, and embodiments of the present disclosure do not limit the number of memory cells in a memory cell string.

[0073] In some embodiments, the plurality of transistors T in the memory cell string NS can further include at least one (e.g., one; alternatively, a plurality) string selection transistor SST and at least one (e.g., one; alternatively, a plurality) ground selection transistor GST located on both sides of each memory cell MC in series. The at least one string selection transistor SST and the at least one ground selection transistor GST can be in series with each memory cell MC. Further, one pole (e.g., drain) of the string selection transistor SST can be electrically connected with the bit line BL, and one pole (e.g., source) of the ground selection transistor GST can be electrically connected with the source layer SL. That is, the memory cell string NS can include the at least one string selection transistor SST, the plurality of memory cells MC, and the at least one ground selection transistor GST connected in series, and one pole of the string selection transistor SST is electrically connected with the bit line BL, and one pole of the ground selection transistor GST is electrically connected with the source layer SL.

[0074] Referring to Figure 2 and Figure 3 , Figure 2 each of the plurality of memory cell strings NS can be implemented as shown in Figure 3 . The memory cell string NS can extend in a direction perpendicular to the source layer SL, or in other words, the memory cell string NS can extend in a thickness direction of the three-dimensional memory 10. Based on this, the plurality of transistors T in the memory cell string NS can be distributed in a direction perpendicular to the source layer SL. Further, the channel of each transistor T in a memory cell string NS can form a vertical channel structure 141 (which can also be referred to as a channel structure 141 herein), which can include the channel of each memory cell MC in the memory cell string NS, and can also include the channel of one or more string selection transistors SST and one or more ground selection transistors GST. The vertical channel structure 141 can extend in a direction perpendicular to the source layer SL (e.g., parallel to the Z-axis direction).

[0075] Continuing to refer to Figure 2 and Figure 3 , the memory cell block BLK can further include at least one (e.g., one; alternatively, a plurality) gate line G surrounding the channel structure. A channel structure and one gate line G surrounding the channel structure can form one transistor T, in which the gate line G can serve as the gate electrode of the transistor T and can control the on-off state of the transistor T.

[0076] Specifically, at least one (e.g., one; or alternatively, multiple) of the plurality of gate lines G can be configured as a word line WL. One word line WL (e.g., each word line WL) can serve as a gate of each memory cell MC located on the same logical page in the memory cell block BLK. At least one (e.g., one; or alternatively, multiple) of the plurality of gate lines G can be configured as a string select line SSL, which can serve as a gate of one or more string select transistors SST. At least one (e.g., one; or alternatively, multiple) of the plurality of gate lines G can be configured as a ground select line GSL, which can serve as a gate of one or more ground select transistors GST.

[0077] It should be noted that, in Figure 2 In the memory cell block BLK, the string select lines SSL1-SSL3 are separated from each other, the ground select lines GSL are electrically connected to each other, and the word lines at the same level can be electrically connected to each other. However, embodiments of the present disclosure do not particularly limit the connection relationship of the above-mentioned signal lines. For example, in some embodiments, the ground select lines GSL can be separated from each other like the string select lines SSL1-SSL3.

[0078] Referring to Figure 1 The peripheral circuit 210 is electrically connected to the first semiconductor structure 100, specifically, the peripheral circuit 210 can be electrically connected to one or more channel structures. The peripheral circuit 210 is configured to receive signals from the outside of the three-dimensional memory 10, for example, including address signals ADDR, command signals CMD, control signals CTRL, and data signals DA, and input signals to and / or receive signals from the first semiconductor structure 100 in response to the signals, so that the three-dimensional memory 10 can perform a storage operation, for example, a read operation, a program operation, and an erase operation.

[0079] In some embodiments, the peripheral circuit 210 can include a page buffer 211, a row decoder 212, and a control logic 213. Exemplarily, the peripheral circuit 210 can further include various sub-circuits, for example, an input / output circuit, a voltage generation circuit for generating voltages used for operating the three-dimensional memory 10, and an error correction circuit for correcting errors in data read from the first semiconductor structure 100.

[0080] Specifically, in some embodiments, the control logic 213 is electrically connected to the row decoder 212, and can also be electrically connected to the voltage generation circuit and the input / output circuit. The control logic 213 can control the operation of the three-dimensional memory 10. Exemplarily, the control logic 213 can generate various internal control signals used in the three-dimensional memory 10 in response to the control signals CTRL. For example, when the three-dimensional memory 10 performs a program operation or an erase operation, the control logic 213 can adjust the voltage level provided to the word lines WL and the bit lines BL.

[0081] In some embodiments, the row decoder 212 selects at least one (e.g., one; or, alternatively, multiple) of the plurality of memory cell blocks BLK in response to the address signal ADDR, and selects at least one word line WL, at least one string select line SSL, and at least one ground select line GSL of the selected memory cell block(s) BLK. Illustratively, the row decoder 212 can be configured to send a voltage for performing a memory operation to the word line WL of the selected memory cell block BLK.

[0082] In some embodiments, the page buffer 211 can be configured as a write driver or a sense amplifier. Illustratively, in a program operation, the page buffer 211 can be configured as a write driver through which a voltage can be applied to the bit line BL in order to store data DA in the memory cell. In a read operation, the page buffer 211 can be configured as a sense amplifier through which data DA stored in the memory cell can be read out.

[0083] Figure 4 A cross-sectional view of a three-dimensional memory according to some embodiments.

[0084] Referring to Figure 4 As described above, the three-dimensional memory 10 can include the first semiconductor structure 100, and the three-dimensional memory 10 can further include a second semiconductor structure 200 electrically connected with the first semiconductor structure 100. The second semiconductor structure 200 can include the peripheral circuit described above. In some embodiments, the second semiconductor structure 200 can be disposed on a side of the channel structure away from the source layer SL, or in other words, the source layer SL and the peripheral circuit are disposed on two sides of the channel structure.

[0085] Specifically, the first semiconductor structure 100 can include an array interconnection layer 110. The array interconnection layer 110 can be electrically connected with the memory cell string NS. The array interconnection layer 110 can include one or more first interlayer insulating layers 111, and further include a plurality of contacts insulated from each other by the first interlayer insulating layers 111, the contacts including, for example, a gate line contact G-CNT electrically connected with the gate line G, and a bit line contact electrically connected with the bit line. The array interconnection layer 110 can further include one or more first interconnection conductor layers 112. The first interconnection conductor layer 112 can include a plurality of connection lines, such as a bit line, and a word line connection line electrically connected with the word line. The material of the first interconnection conductor layer 112 and the contacts can be a conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and a metal silicide, or a combination thereof, or other suitable materials. The material of the first interlayer insulating layer 111 can be an insulating material, such as one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0086] The second semiconductor structure 200 can include a substrate 210, transistors 220 disposed on the substrate 210, and a peripheral interconnection layer 230 disposed on the substrate 210.

[0087] The material of the substrate 210 can include a semiconductor material, such as monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The substrate 210 can be partially or entirely doped.

[0088] The peripheral interconnection layer 230 is electrically connected with the transistors 220 to enable transmission of electrical signals between the transistors 220 and the peripheral interconnection layer 230. The peripheral interconnection layer 230 can include one or more second interlayer insulating layers 231 and one or more second interconnection conductor layers 232. The different second interconnection conductor layers 232 can be electrically connected through contacts. The material of the second interconnection conductor layers 232 and the contacts can be an electrically conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the second interlayer insulating layers 231 can be an insulating material, such as one or more of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0089] The peripheral interconnection layer 230 can be electrically connected with the array interconnection layer 110, so that the first semiconductor structure 100 and the second semiconductor structure 200 can be electrically connected. Specifically, since the peripheral interconnection layer 230 is electrically connected with the array interconnection layer 110, the peripheral circuit in the second semiconductor structure 200 can be electrically connected with the first semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuit and the string of memory cells. In some possible implementations, a bonding interface IF can be disposed between the peripheral interconnection layer 230 and the array interconnection layer 110, through which the peripheral interconnection layer 230 and the array interconnection layer 110 can be bonded and electrically connected with each other.

[0090] Figure 5 FIG. 1 is a top view of a first semiconductor structure in a three-dimensional memory. Figure 4 FIG. 2 is a cross-sectional view of the first semiconductor structure in FIG. 1 along a cross-sectional line AA’. Figure 6 FIG. 3 is a cross-sectional view of the first semiconductor structure in FIG. 1 along a cross-sectional line BB’. Figure 5 FIG. 4 is an enlarged view of a region W1 in the first semiconductor structure in FIG. 1. Figure 7 FIG. 5 is an enlarged view of a region W2 in the first semiconductor structure in FIG. 1. Figure 5 FIG. 6 is an enlarged view of a region W3 in the first semiconductor structure in FIG. 1. Figure 8 FIG. 7 is an enlarged view of a region W4 in the first semiconductor structure in FIG. 1. Figure 6 FIG. 8 is an enlarged view of a region W5 in the first semiconductor structure in FIG. 1.

[0091] FIG. 9 is a top view of a second semiconductor structure in the three-dimensional memory in FIG. 1. Figure 5The first semiconductor structure 100 in the three-dimensional memory has an array region RA, a transition region DA, and a contact region CA. Correspondingly, it can also be said that the three-dimensional memory has the array region RA, the transition region DA, and the contact region CA. The transition region DA is arranged between the array region RA and the contact region CA. Exemplarily, the array region RA, the transition region DA, and the contact region CA can be sequentially arranged along a first direction, for example, parallel to the X-axis direction. It should be noted that in this document, the X-axis, the Y-axis, and the Z-axis can form a three-dimensional orthogonal coordinate system. Among them, the Z-axis direction can be parallel to the thickness direction of the three-dimensional memory, and the X-axis direction and the Y-axis direction can be parallel to the extension direction of the three-dimensional memory (for example, parallel to the extension direction of the source layer SL).

[0092] As described above, the first semiconductor structure 100 in the three-dimensional memory includes a plurality of channel structures 140, which can be located in the array region RA. The first semiconductor structure 100 can also include a plurality of contact structures 150, which can be located in the contact region CA. The first semiconductor structure 100 can also include a plurality of dummy channel structures 160, at least part (for example, part; or all) of the plurality of dummy channel structures 160 can be located in the transition region DA. The channel structure 140, the dummy channel structure 160, and the contact structure 150 will be described below.

[0093] Referring to Figure 5 and Figure 6 The first semiconductor structure 100 includes a plurality of dielectric layers 130 arranged in a stack, and the three-dimensional memory also includes a plurality of dielectric layers 130 arranged in a stack. The first semiconductor structure 100 can also include a plurality of insulating layers 120 arranged in a stack. In the thickness direction of the three-dimensional memory (for example, parallel to the Z-axis direction), the plurality of insulating layers 120 and the plurality of dielectric layers 130 are arranged in a stack, and one insulating layer 120 can be arranged between every two dielectric layers 130, or in other words, two adjacent dielectric layers 130 are separated by an insulating layer 120.

[0094] Exemplarily, the three-dimensional memory includes insulating layers 120a-120h and dielectric layers 130a-130g arranged in a stack. It should be noted that, Figure 6 The number of insulating layers and dielectric layers in the above is only illustrative, and the embodiments of the present disclosure do not limit the number of insulating layers and dielectric layers.

[0095] For convenience of description, in the following, the plurality of insulating layers 120 and the plurality of dielectric layers 130 arranged in a stack (for example, the whole of the insulating layers 120a-120h and the dielectric layers 130a-130g) are referred to as a first stack structure SK1.

[0096] In the plurality of insulating layers 120, a material of an insulating layer 120 (e.g., each insulating layer 120) can be an insulating material, for example, a material of an insulating layer 120 is silicon oxide or silicon nitride.

[0097] Referring to Figure 5 and Figure 6 Hereinafter, a dielectric layer will be described by way of example with the dielectric layer 130d, unless specifically stated otherwise. In the three-dimensional memory, a structure of other dielectric layers can be the same as that of the dielectric layer 130d, and reference can be made to the relevant description hereinafter.

[0098] The dielectric layer 130d can include a gate line G. The dielectric layer 130d can also include an embedded portion IL at a same level as the gate line G.

[0099] It is noted that, in this document, A and B being at a same level can mean that, with a point in the three-dimensional memory (e.g., a center of the three-dimensional memory, or a point on a surface of the source layer away from the first stack structure) as an origin, with a direction of the source layer pointing to the first stack structure as a positive direction of a Z axis, coordinates of a center of A and a center of B on the Z axis relative to the origin are equal to each other. Similarly, A being at a higher level than B can mean that the coordinate of the center of A on the Z axis is greater than the coordinate of the center of B on the Z axis, e.g., A is farther away from the source layer than B; A being at a lower level than B can mean that the coordinate of the center of A on the Z axis is less than the coordinate of the center of B on the Z axis, e.g., A is closer to the source layer than B.

[0100] A material of the embedded portion IL can be an insulating material, for example, a material of the embedded portion IL is silicon oxide or silicon nitride. In some embodiments, a material of the embedded portion IL is different from a material of the insulating layer 120.

[0101] Referring to Figure 6 and Figure 8 In some embodiments, the gate line G can include a conductor layer Ga. A material of the conductor layer 130a can include a conductive material, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, silicide. In some embodiments, a material of the conductor layer Ga can be tungsten.

[0102] In some embodiments, the gate line G can further include a metal compound layer Gb. With the metal compound layer Gb, the conductor layer Ga can be separated from the insulating layer 120 and the channel structure 140. The metal compound layer Gb can be configured as a barrier layer, which can reduce diffusion of impurity atoms or gas to the insulating layer 120 and the channel structure 140. The metal compound layer Gb can also be configured as an adhesion layer, which can strengthen the adhesion between the conductor layer Ga and the insulating layer 120 and the channel structure 140. It is noted that when the gate line G is provided with the high-k layer KL between the gate line G and the channel structure 140, and / or when the gate line G is provided with the high-k layer KL between the gate line G and the insulating layer 120, the metal compound layer Gb can be provided between the conductor layer Ga and the high-k layer KL, which can strengthen the adhesion between the conductor layer Ga and the high-k layer KL. The high-k layer KL will be described below.

[0103] The material of the metal compound layer Gb can include a metal compound, such as one or more of a combination of titanium nitride, tantalum nitride, tungsten carbide, or other suitable material.

[0104] Referring to Figure 5 and Figure 6 Based on the above description, the dielectric layer 130d can include one or more materials, for example, the dielectric layer 130d can include the material of the gate G. For another example, the dielectric layer 130d can further include the material of the gate G and the material of the embedded portion IL. In the case where the dielectric layer 130d includes multiple materials, the dielectric layer 130d can also be referred to as a composite dielectric layer or a composite material layer.

[0105] Referring to Figure 5 and Figure 7 As described above, the first semiconductor structure 100 can include a plurality of channel structures 140, and it can also be said that the three-dimensional memory includes a plurality of channel structures 140, which are located in the array region RA.

[0106] A channel structure 140 (for example, each channel structure 140) extends in the plurality of dielectric layers 130 which are stacked. Further, a channel structure 140 (for example, each channel structure 140) extends in the plurality of insulating layers 120 and the plurality of dielectric layers 130 which are stacked. Exemplarily, the channel structure 140 can extend in the plurality of insulating layers 120 and the plurality of dielectric layers 130 which are stacked along a third direction, which is parallel to the thickness direction (for example, parallel to the Z-axis direction) of the three-dimensional memory. In some embodiments, the channel structure 140 can extend through the first stack structure SK1 along the third direction and extend to the source layer SL. In this way, the channel structure 140 can be in contact with the source layer SL to realize the electrical connection between the channel structure 140 and the source layer SL.

[0107] Further, the channel structure 140 can extend along the third direction through each of the plurality of gate lines G in the plurality of dielectric layers 130, such that the plurality of gate lines G can surround the channel structure 140, and a plurality of transistors in a memory cell string can be formed. For example, the channel structure 140 can extend through a gate line G in the dielectric layer 130d, and one transistor in the memory cell string can be formed.

[0108] It should be noted that, Figure 5 and Figure 7 The number and distribution of the channel structures shown in FIGS. 1A-1C are merely illustrative, and embodiments of the present disclosure do not limit the number and distribution of the channel structures. In addition, for the sake of simplicity of the drawings, Figure 7 some of the channel structures are omitted in FIGS. 2A-2C.

[0109] Referring to Figure 6 and Figure 8 In some embodiments, the channel structure 140 includes a semiconductor channel 141. The material of the semiconductor channel 141 can include a semiconductor material, such as a combination of one or more of amorphous, poly-crystalline, or single-crystalline silicon. The semiconductor channel 141 can be electrically connected with the source layer SL, for example, as shown in FIG. 1A, the semiconductor channel 141 can be in contact with the source layer SL. The semiconductor channel 141 can be used as a channel of each transistor in a memory cell string. Figure 6

[0110] The channel structure 140 can further include a functional layer 142. The functional layer 142 can be disposed between the plurality of gate lines G and the semiconductor channel 141. In some embodiments, the functional layer 142 can be disposed between the semiconductor channel 141 and the first stack structure SK1.

[0111] Continuing to refer to Figure 6 and Figure 8 The functional layer 142 can include a tunneling layer 142a and a charge storage layer 142b.

[0112] The tunneling layer 142a can be disposed between the gate line G and the semiconductor channel 141. Illustratively, the tunneling layer 142a can be disposed between the first stack structure SK1 and the semiconductor channel 141, for example, the tunneling layer 142a can be a continuous film layer extending in the first stack structure SK1 along a thickness direction of the three-dimensional memory, such that the fabrication process of the tunneling layer 142a is relatively simple. The material of the tunneling layer 142a can include an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the tunneling layer 142a is silicon oxide. Electrons and holes in the semiconductor channel 141 can tunnel through the tunneling layer 142a into the charge storage layer 142b.

[0113] ​The charge storage layer 142b can be disposed between the tunneling layer 142a and the gate line G. Illustratively, the charge storage layer 142b can be disposed between the tunneling layer 142a and the first stack structure SK1, e.g., the charge storage layer 142b can be a continuous film layer extending in the thickness direction of the three-dimensional memory in the first stack structure SK1, which makes the fabrication process of the charge storage layer 142b relatively simple. The material of the charge storage layer 142b can include one or more of silicon nitride, silicon oxynitride, silicon. In some embodiments, the material of the charge storage layer 142b is silicon nitride. The charge storage layer 142b can be configured to store charges, and one or more memory cells in the memory cell string can be operated by storing or removing charges in the charge storage layer 142b. Illustratively, when a certain voltage is applied to the semiconductor channel 141 through the gate line G, the storage or removal of charges in the charge storage layer 142b can affect the conduction state of the semiconductor channel 141.

[0114] Continuing to refer to Figure 6 and Figure 8 In some embodiments, the channel structure 140 can further include a blocking layer 142c. The blocking layer 142c can be disposed between the charge storage layer 142b and the gate line G. Illustratively, the blocking layer 142c can be disposed between the charge storage layer 142b and the first stack structure SK1, i.e., the blocking layer 142c can be a continuous film layer extending in the thickness direction of the three-dimensional memory in the first stack structure SK1, which makes the fabrication process of the blocking layer 142c relatively simple. The blocking layer 142c can be configured to prevent the charges stored in the charge storage layer 142b from leaking to the gate line G. The material of the blocking layer 142c can include an insulating material, e.g., the material of the blocking layer 142c is one or more of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the blocking layer 142c is silicon oxide.

[0115] Continuing to refer to Figure 6 and Figure 8 In some embodiments, the channel structure 140 further includes a channel filler 143. The material of the channel filler 143 can include an insulating material, e.g., the material of the channel filler 143 is one or more of silicon oxide, silicon nitride, or silicon oxynitride. The channel filler 143 can improve the structural stability of the channel structure 140. In some possible implementations, the channel filler 143 can further include one or more air gaps 143’. The air gaps 143’ can relieve structural stress, further improving the structural stability of the channel structure 140.

[0116] Continuing to refer to Figure 6 and Figure 8In some embodiments, the three-dimensional memory further includes a high-k layer KL. The material of the high-k layer KL can include a high-k material, such as a combination of one or more of the following: aluminum oxide, hafnium dioxide, lanthanum oxide, yttrium oxide, tantalum oxide, a silicate of one of the above materials, and a nitrogen-doped compound of one of the above materials.

[0117] The high-k layer KL is disposed at least partially between the gate line G and the channel structure 140. In some possible implementations, the functional layer 142 in the channel structure 140 includes a blocking layer 142c, and the high-k layer KL can be disposed between the blocking layer 142c and the gate line G, i.e., the blocking layer 142c and the high-k layer KL can be disposed between the gate line G and the charge storage layer 142b. At this time, the high-k layer KL can be configured to control the work function between the gate line G and the charge storage layer 142b. In other possible implementations, the functional layer 142 in the channel structure 140 does not include the blocking layer 142c, at this time, the high-k layer KL can be disposed between the gate line G and the charge storage layer 142b, and the charge storage layer 142b can be in contact with the high-k layer KL. At this time, the high-k layer KL can be configured to prevent the charge stored in the charge storage layer 142b from leaking to the gate line G.

[0118] Continuing to refer to Figure 5 and Figure 6 As described above, the first semiconductor structure 100 further includes a plurality of contact structures 150, and the three-dimensional memory also includes a plurality of contact structures 150, which are located in the contact area CA. Specifically, a contact structure 150 (e.g., each contact structure 150) extends in the plurality of dielectric layers 130 disposed in layers. Illustratively, a contact structure 150 (e.g., each contact structure 150) can extend in the plurality of insulating layers 120 and the plurality of dielectric layers 130 disposed in layers, and it can also be said that a contact structure 150 (e.g., each contact structure 150) extends in the first stack structure SK1. Illustratively, the contact structure 150 can extend in the first stack structure SK1 along a third direction, which is parallel to the thickness direction of the three-dimensional memory (e.g., parallel to the Z-axis direction).

[0119] A contact structure 150 (e.g., each contact structure 150) is configured to write an electrical signal to a gate line G. Illustratively, the contact structure 150 can be electrically connected to the gate line G, and can also be electrically connected to the peripheral circuit, so that the peripheral circuit can write an electrical signal to the gate line G through the contact structure 150.

[0120] Referring to Figure 6In some embodiments, the contact structure 150 can extend in the first stack structure SK1 along a thickness direction of the three-dimensional memory, and one end (e.g., an end close to the source layer SL) of the contact structure 150 is located at a same level as a dielectric layer 130 (e.g., the dielectric layer 130d) and contacts a gate line G in the dielectric layer 130 to achieve electrical connection between the contact structure 150 and the gate line G. The specific structure of the contact structure 150 and the contact manner between the contact structure and the gate line G will be described below.

[0121] Further, in the three-dimensional memory, in a third direction (parallel to the thickness direction of the three-dimensional memory), the sizes of the plurality of contact structures 150 can be different, or in other words, the depths of the plurality of contact structures 150 extending in the third direction in the three-dimensional memory are different, so that one contact structure 150 (e.g., each contact structure 150) can contact a gate line G at a level, and the plurality of contact structures 150 can respectively contact gate lines G at different levels to achieve electrical connection between the plurality of contact structures 150 and the gate lines G at different levels. In this way, through the plurality of contact structures 150, each of the plurality of gate lines G can be controlled individually.

[0122] Referring back to Figure 5 , the first semiconductor structure 100 further includes a first gate line isolation structure 170, a second gate line isolation structure 180, and an intermediate isolation structure 190, or in other words, the three-dimensional memory further includes the first gate line isolation structure 170, the second gate line isolation structure 180, and the intermediate isolation structure 190. The intermediate isolation structure 190 is located between the first gate line isolation structure 170 and the second gate line isolation structure 180. Exemplarily, the first gate line isolation structure 170, the intermediate isolation structure 190, and the second gate line isolation structure 180 can be arranged along a second direction, which is perpendicular to the first direction, for example, the second direction can be parallel to the Y-axis direction.

[0123] It should be noted that embodiments of the present disclosure do not limit the relative positions of the first gate line isolation structure 170 and the second gate line isolation structure 180. Exemplarily, as shown in Figure 5 , the first gate line isolation structure 170 and the second gate line isolation structure 180 can be sequentially arranged along the positive direction of the Y-axis. Exemplarily, as shown in Figure 9 , the first gate line isolation structure 170 and the second gate line isolation structure 180 can be sequentially arranged along the negative direction of the Y-axis. In the following, unless otherwise specified, the first gate line isolation structure 170 and the second gate line isolation structure 180 are sequentially arranged along the positive direction of the Y-axis as an example for description.

[0124] Continuing to refer to Figure 5The first gate line isolation structure 170 and the second gate line isolation structure 180 extend from the array region RA to the contact region CA. Exemplarily, the first gate line isolation structure 170 and the second gate line isolation structure 180 can extend from the array region RA to the contact region CA along a first direction (e.g., parallel to the X-axis direction).

[0125] Referring to Figure 7 The first gate line isolation structure 170 penetrates the plurality of insulating layers 120 and the plurality of dielectric layers 130 arranged in a stack, and can also be said to penetrate the first stack structure SK1.

[0126] The first gate line isolation structure 170 includes a first insulating isolation portion 171. The first insulating isolation portion 171 can penetrate the first stack structure SK1. The material of the first insulating isolation portion 171 can include an insulating material, for example, the material of the first insulating isolation portion 171 can include one or more of silicon oxide, silicon nitride, or silicon oxynitride. Since the first gate line isolation structure 170 includes the first insulating isolation portion 171, portions located on both sides of the first gate line isolation structure 170 (e.g., portions located on both sides of the first gate line isolation structure 170 along the Y-axis direction) can be insulated from each other through the first gate line isolation structure 170.

[0127] In some embodiments, the first gate line isolation structure 170 can further include one or more first penetrating portions 172. The first penetrating portion 172 can be located in the first insulating isolation portion 171 and can penetrate one or more insulating layers 120 and one or more dielectric layers 130. The material of the first penetrating portion 172 can include a doped or undoped semiconductor material, for example, doped or undoped polysilicon. The first penetrating portion 172 can play a role in mediating stress and can improve the structural stability of the three-dimensional memory. In some possible implementations, the material of the first penetrating portion 172 can include a doped semiconductor material, for example, doped polysilicon, in which case the first penetrating portion 172 can be configured as a source contact, specifically, the first penetrating portion 172 can be electrically connected to the source layer SL, and through the first penetrating portion 172, an electrical signal can be written to the source layer SL.

[0128] Referring to Figure 6The structure of the second gate line isolation structure 180 can be similar to that of the first gate line isolation structure, as described above. Specifically, the second gate line isolation structure 180 also penetrates the multiple insulating layers 120 and multiple dielectric layers 130 stacked together; in other words, the second gate line isolation structure 180 penetrates the first stacked structure SK1. The second gate line isolation structure 180 may include a second insulating isolation portion 181 and one or more second penetration portions 182. The material, structure, and beneficial effects of the second insulating isolation portion 181 can be similar to those of the first insulating isolation portion, and the material, structure, and beneficial effects of the second penetration portion 182 can be similar to those of the first penetration portion. See the description of the first gate line isolation structure above; further details will not be repeated here.

[0129] Figure 10 This is a cross-sectional view of a first semiconductor structure in a three-dimensional memory according to some embodiments, the cross-section being perpendicular to the thickness direction of the three-dimensional memory, for example, parallel to the XY plane. This cross-section can be... Figure 6 A cross-section at dielectric layer 130d shows the structure of dielectric layer 130d. To illustrate the dielectric layer more clearly, [the following is provided] Figure 11 Compared to Figure 10 , Figure 11 The channel structure and dummy channel structure are omitted to clearly show the structure of the dielectric layer. It should be noted that... Figure 10 and Figure 11 The shapes of the gate lines in the dielectric layer shown are merely illustrative. It will be understood that different process parameters in the fabrication process of a three-dimensional memory (described in detail below) can result in gate lines with different shapes in the formed three-dimensional memory. The embodiments of this disclosure do not limit the specific shape of the gate lines in the dielectric layer, as long as the electrical connection relationships described herein are satisfied, enabling the three-dimensional memory to perform storage operations.

[0130] See Figure 5 The first gate isolation structure 170 and the second gate isolation structure 180 can be configured to define a block of memory cells. Exemplarily, in a three-dimensional memory, the portion located between the first gate isolation structure 170 and the second gate isolation structure 180 can be a block of memory cells (BLK). See also... Figure 10 and Figure 11 The first gate isolation structure 170 and the second gate isolation structure 180 can also be configured to define gate lines. Exemplarily, a gate line (e.g., each gate line) can be located between the first gate isolation structure 170 and the second gate isolation structure 180, and can extend from the first gate isolation structure 170 to the second gate isolation structure 180. By writing an electrical signal to this gate line G, multiple memory cells located at the same level in a memory cell block can be controlled.

[0131] See alsoFigure 5 The intermediate isolation structure 190 extends from the array region RA to the transition region DA. Specifically, the intermediate isolation structure 190 extends from the array region RA to the transition region DA along a first direction, which can also be said as the first direction is parallel to the extending direction of the intermediate isolation structure 190, for example, the first direction is parallel to the X-axis direction. The extending direction of the intermediate isolation structure 190 can be substantially parallel to the extending direction of the first gate line isolation structure 170 and the second gate line isolation structure 180. For example, the intermediate isolation structure 190, the first gate line isolation structure 170 and the second gate line isolation structure 180 can extend along the first direction, for example, the first direction is parallel to the X-axis direction.

[0132] As described above, the first gate line isolation structure 170 and the second gate line isolation structure 180 extend from the array region RA to the contact region CA, and the intermediate isolation structure 190 extends from the array region RA to the transition region DA. Based on this, it can also be said that, in the first direction (for example, parallel to the X-axis direction), the size of the intermediate isolation structure 190 is smaller than the size of the first gate line isolation structure 170 and the second gate line isolation structure 180.

[0133] Referring to Figure 12A , Figure 12A is a top view of a first semiconductor structure in a three-dimensional memory in the related art. In the three-dimensional memory in the related art, the intermediate isolation structure 530 extends from the array region RA to the contact region CA, which can also be said as the intermediate isolation structure 530 is arranged between the first gate line isolation structure 510 and the second gate line isolation structure 520 in the contact region CA, occupying part of the space of the contact region CA, and thus the size (for example, the size of the contact structure 540 in the X-Y plane) of the contact structure 540 located in the contact region CA is small. In contrast, continuing to refer to Figure 5 In the three-dimensional memory provided in the embodiments of the present disclosure, since the intermediate isolation structure 190 extends from the array region RA to the transition region DA, but does not extend to the contact region CA, which can also be said as the intermediate isolation structure 190 is not arranged in the contact region CA, thus the size (for example, the size of the contact structure 150 in the X-Y plane) of the contact structure 150 located in the contact region CA can be large, and thus the process of manufacturing the contact structure 150 can be simple. For example, the aspect ratio of the contact structure 150 can be reduced, and the etching process in manufacturing the contact structure 150 can be simplified.

[0134] Referring to Figure 7The structure of the intermediate isolation structure 190 can be the same as that of the first gate line isolation structure, i.e., the intermediate isolation structure 190 can also include third insulating isolation portions 191 and one or more third penetrating portions 192, where the material, structure, and beneficial effects of the third insulating isolation portions 191 can be similar to those of the first insulating isolation portions, and the material, structure, and beneficial effects of the third penetrating portions 192 can be similar to those of the first penetrating portions. For details, please refer to the description of the first gate line isolation structure above, which will not be repeated here.

[0135] Referring to Figure 10 and Figure 11 The intermediate isolation structure 190 can be configured to divide the gate line into a plurality of smaller sub-gate lines. Specifically, the gate line G includes a first sub-gate line 131 and a second sub-gate line 132, and the dielectric layer 130d also includes the first sub-gate line 131 and the second sub-gate line 132. The first sub-gate line 131 is located between the first gate line isolation structure 170 and the intermediate isolation structure 190, and the second sub-gate line 132 is located between the second gate line isolation structure 180 and the intermediate isolation structure 190.

[0136] It should be noted that, in this article, A is located between B and C can mean that, along the arrangement direction of B and C, B, A, and C are arranged in sequence, and, in the direction perpendicular to the arrangement direction of B and C, the edge of A is flush with or inwardly recessed from the edge of B and C.

[0137] Specifically, the first sub-gate line 131 being located between the first gate line isolation structure 170 and the intermediate isolation structure 190 can mean that, along the arrangement direction of the first gate line isolation structure 170 and the intermediate isolation structure 190 (e.g., parallel to the Y-axis direction), the first gate line isolation structure 170, the first sub-gate line 131, and the intermediate isolation structure 190 are arranged in sequence, and, in the direction perpendicular to the arrangement direction of the first gate line isolation structure 170 and the intermediate isolation structure 190, e.g., in the direction parallel to the X-axis, the edge of the first sub-gate line 131 is flush with or inwardly recessed from the edge of the first gate line isolation structure 170, and the edge of the first sub-gate line 131 is flush with or inwardly recessed from the edge of the intermediate isolation structure 190. For example, referring to the description above, in the X-axis direction, the size of the intermediate isolation structure 190 can be smaller than that of the first gate line isolation structure 170, and thus the first sub-gate line 131 can be defined by the intermediate isolation structure 190. Specifically, the position line L1 is the extension line of the edge 190' of the intermediate isolation structure 190 in the X-axis direction, and the edge of the first sub-gate line 131 in the X-axis direction can be flush with the position line L1.

[0138] The description of the second sub-gate line 132 located between the second gate line isolation structure 180 and the intermediate isolation structure 190 can refer to the description of the first sub-gate line 131 located between the first gate line isolation structure 170 and the intermediate isolation structure 190, which will not be repeated here.

[0139] Based on the above, the first sub-gate line 131 is located between the first gate line isolation structure 170 and the intermediate isolation structure 190, and the second sub-gate line 132 is located between the second gate line isolation structure 180 and the intermediate isolation structure 190. It can also be said that the first sub-gate line 131 and the second sub-gate line 132 are separated by the intermediate isolation structure 190, so that the operation crosstalk (such as write crosstalk and read crosstalk) on the gate line G can be reduced. Accordingly, referring to Figure 5 , the intermediate isolation structure 190 can be configured to divide a memory cell block BLK into a plurality of finger structures, such as finger structure FB1 and finger structure FB2. The finger structure FB1 can include the first sub-gate line in one or more dielectric layers, and the finger structure FB2 can include the second sub-gate line in one or more dielectric layers.

[0140] Continuing to refer to Figure 10 and Figure 11 , the dielectric layer 130d further includes a connection portion 133. The connection portion 133 extends beyond the intermediate isolation structure 190 in the first direction, where the first direction is the extension direction of the intermediate isolation structure 190, such as parallel to the X-axis direction. And the connection portion 133 is in contact with the first sub-gate line 131 and the second sub-gate line 132, and the connection portion 133 is exemplarily integrated with the first sub-gate line 131 and the second sub-gate line 132. In this way, by writing an electrical signal into the gate line G, each channel structure 140 located between the first gate line isolation structure 170 and the second gate line isolation structure 180 can be controlled.

[0141] Continuing to refer to Figure 10 and Figure 11 In some implementations, the gate line G further includes a first connection line 134 and a second connection line 135, and it can also be said that the dielectric layer (such as the dielectric layer 130d) further includes a first connection line 134 and a second connection line 135. The first connection line 134 and the second connection line 135 extend from the transition area DA to the contact area CA. Exemplarily, the first connection line 134 and the second connection line 134 can extend from the transition area DA to the contact area CA along the first direction (such as parallel to the X-axis direction).

[0142] Further, the first connection line 134 is located at one side of the first gate line isolation structure 170 close to the plurality of contact structures 150. The second connection line 135 is located at one side of the second gate line isolation structure 180 close to the plurality of contact structures 150. At least one (e.g., one; or, for example, a plurality) of the plurality of contact structures 150 can be electrically connected with the first connection line 134 or the second connection line 135, so as to realize writing of an electrical signal into the gate line G in the dielectric layer 130d through the contact structure 150.

[0143] Continuing to refer to Figure 11 Further, the first sub-gate line 131 has a first gap U1 at a middle portion of one end close to the contact area CA, and the second sub-gate line 132 has a second gap U2 at a middle portion of one end close to the contact area CA. Herein, the middle portion of the first sub-gate line 131 can be a middle portion of the first sub-gate line 131 along the second direction (e.g., parallel to the Y-axis direction), and the middle portion of the second sub-gate line 132 can be a middle portion of the second sub-gate line 132 along the second direction.

[0144] Specifically, since the first sub-gate line 131 has the first gap U1 at the middle portion of one end close to the contact area CA, a middle line L3 of the first sub-gate line 131 can pass through the first gap U1. Herein, the middle line L3 of the first sub-gate line 131 can be a straight line passing through a point T1 of the first sub-gate line 131 and parallel to the first direction (e.g., parallel to the X-axis direction), wherein a distance d1 between the point T1 and an edge of the first sub-gate line 131 close to the first gate line isolation structure 170 is equal to a distance d2 between the point T1 and an edge of the first sub-gate line 131 close to the middle isolation structure 190. Similarly, since the second sub-gate line 132 has the second gap U2 at the middle portion of one end close to the contact area CA, a middle line L4 of the second sub-gate line 132 can pass through the second gap U2. Herein, the middle line L3 of the second sub-gate line 132 can be a straight line passing through a point T2 of the second sub-gate line 132 and parallel to the first direction (e.g., parallel to the X-axis direction), wherein a distance d3 between the point T2 and an edge of the second sub-gate line 132 close to the middle isolation structure 190 is equal to a distance d4 between the point T2 and an edge of the second sub-gate line 132 close to the second gate line isolation structure 180.

[0145] Continuing to refer to Figure 11 Further, in the second direction (e.g., parallel to the Y-axis direction), the connection portion 133 does not exceed edges of the first gap U1 and the second gap U2 close to each other. For example, the first gap U1 and the second gap U2 can be arranged along the second direction (e.g., parallel to the Y-axis direction), an edge U1’ of the first gap U1 close to the second gap U2, and an edge U2’ of the second gap U2 close to the first gap U1.

[0146] In the following, the beneficial effects of the above structure of the first sub-gate line 131, the second sub-gate line 132 and the connecting part 133 will be described in connection with the manufacturing process of the gate line.

[0147] In the manufacturing process of the gate line, a plurality of first material layers and a plurality of second material layers can be formed on the substrate in a stacked manner to form a stack structure. For the sake of distinction, the stack structure including the plurality of first material layers and the plurality of second material layers formed in a stacked manner will be referred to as a second stack structure in the following.

[0148] Further, the first gate line slit, the isolation slit and the second gate line slit can be formed through the second stack structure, and a portion of the first material layer can be removed (e.g. by dry or wet etching process) through the first gate line slit, the isolation slit and the second gate line slit to form a gap, and then a gate line material can be deposited in the gap through the first gate line slit, the isolation slit and the second gate line slit to form the gate line.

[0149] Based on the above, continuing to refer to Figure 11 The shape of the gap can be approximately the same as the shape of the gate line, which can be represented by the shape of the gate line G. In addition, in the subsequent process, an insulating material or the like can be filled into the first gate line slit to form a first gate line isolation structure, and thus the position of the first gate line isolation structure 170 can be used to represent the position of the first gate line slit. Similarly, the position of the second gate line isolation structure 180 can be used to represent the position of the second gate line slit, and the position of the intermediate isolation structure 190 can be used to represent the position of the isolation slit.

[0150] Figure 12B The process flow chart for forming the gap by etching process in the related art. Referring to Figure 12BThe first material layer ML can be removed by an etching process to form a first gap 440 between the first gate line slit 410 and the isolation slit 430, and to form a second gap 450 between the second gate line slit 420 and the isolation slit 430. In order to ensure that the subsequently formed first sub-gate line covers all the channel structures between the first gate line slit 410 and the isolation slit 430 in the Y-axis direction, and that the subsequently formed second sub-gate line covers all the channel structures between the second gate line slit 420 and the isolation slit 430 in the Y-axis direction, the etching process can be performed for a relatively long time, so that the first gap 440 can connect the first gate line slit 410 and the isolation slit 430, and the second gap 450 can connect the second gate line slit 420 and the isolation slit 430. Since the etching process can be an isotropic etching process, in the etching process, a third gap 460 can be formed along the X-axis direction beyond the isolation slit 430, and the third gap 460 can connect the first gate line slit 410 and the second gate line slit 420.

[0151] In a subsequent process of depositing a gate line material, in the Y-axis direction, for the first gap 440, the gate line material can be deposited through the first gate line slit 410 and the isolation slit 430. Similarly, for the second gap 450, the gate line material can be deposited through the second gate line slit 420 and the isolation slit 430. In contrast, for the third gap 460, since the third gap 460 extends along the X-axis direction beyond the isolation slit 430, and can connect the first gate line slit 410 and the second gate line slit 420, it is necessary to fill the relatively large volume gap through the first gate line slit 410 and the second gate line slit 420. Thus, in the third gap 460, the problem of incomplete filling of the gate line material can occur. In the process of depositing the gate line material, an auxiliary gas, such as a fluorine-containing gas or a chlorine-containing gas, can be used. When the gate line material is not filled in the gap, a large amount of auxiliary gas can be left in the formed gate line. The residual auxiliary gas can seep into the insulating layer, thereby damaging the insulating layer, which can cause the problem of short circuit between adjacent gate lines.

[0152] Based on the above, referring to Figure 11In the three-dimensional memory provided in the embodiments of the present disclosure, because the first sub-gate line 131 has the first notch U1 in the middle of the end close to the contact region CA, the second sub-gate line 132 has the second notch U2 in the middle of the end close to the contact region CA, and in the second direction (for example, parallel to the Y-axis direction), the connecting portion 133 does not exceed the edges of the first notch U1 and the second notch U2 close to each other, therefore, in the process of manufacturing the gate line, the gap for forming the connecting portion 133 can be small, that is, the gap exceeding the isolation slit in the first direction (for example, parallel to the X-axis direction) can be small. For example, the gap does not exceed the edges of the first notch U1 and the second notch U2 close to each other in the second direction. The gate line material can be deposited in the gap with small volume through the isolation slit, that is, the connecting portion 133 can be formed. In this way, the problem of incomplete filling of the above-mentioned gate line material can be improved, and in turn, the problem of short circuit between adjacent gate lines can be improved, and the structural stability of the three-dimensional memory can be improved.

[0153] Referring to Figure 11 , based on the above, a part of the first material layer can be removed (for example, a part of the first material layer is removed through a dry or wet etching process) through the first gate line slit, the isolation slit and the second gate line slit to form a gap, and then the gate line material is deposited in the gap through the first gate line slit, the isolation slit and the second gate line slit to form the gate line G. Based on this, in some embodiments, the first material layer remaining after removing a part of the first material layer can form an embedded portion IL, that is, the embedded portion IL can be located between the first gate line isolation structure 170 and the second gate line isolation structure 180, and the embedded portion IL can extend from the contact region CA to the transition region DA and embed the first notch U1 and the second notch U2. Based on the above, the embedded portion IL can define the shape of the gate line G. In addition, the embedded portion IL can also play a role in supporting and protecting the gate line G, and can improve the structural stability of the dielectric layer, and in turn, improve the structural stability of the three-dimensional memory.

[0154] Referring to Figure 5 , Figure 6 and Figure 7 , in some embodiments, because the dielectric layer 130 includes the gate line G and the embedded portion IL, the structure of the part of the first stack structure SK1 located in the array region RA (as shown in Figure 7 ) and the structure of the part of the first stack structure SK1 located in the contact region CA (as shown in Figure 6 ) can be different. For example, referring to Figure 7 , the part of the first stack structure SK1 located in the array region RA can include an alternating stack structure of the gate line G and the insulating layer 120. Referring to Figure 6 , the structure of the part of the first stack structure SK1 located in the contact region CA can include an alternating stack structure of the embedded portion IL and the insulating layer 120.

[0155] Referring to Figure 5 , Figure 6 and Figure 11 , in some embodiments, each contact structure 150 includes a contact portion 151 and a connecting pillar 152 arranged in sequence along the thickness direction of the three-dimensional memory (e.g., parallel to the direction of the Z axis). Illustratively, the contact portion 151 is closer to the source layer SL than the connecting pillar 152. Also, the contact portion 151 and the connecting pillar 152 are electrically connected, illustratively, the contact portion 151 and the connecting pillar 152 are in contact. For example, the contact portion 151 and the connecting pillar 152 can form an integral body.

[0156] Based on the foregoing description, the contact structure 150 can be electrically connected with the gate line G, for example, the contact structure 150 can be in contact with the gate line G to achieve electrical connection between the contact structure 150 and the gate line G. In some embodiments, the contact portion 151 in the contact structure can be located at the same level as the first sub-gate line 131, the second sub-gate line 132, and the connecting portion 133 in the dielectric layer 130, and the contact portion 151 can be electrically connected with the first sub-gate line 131, the second sub-gate line 132, and the connecting portion 133 in the dielectric layer 130. In some possible implementations, the contact portion 151 can be electrically connected with the first sub-gate line 131, the second sub-gate line 132, and the connecting portion 133 in the dielectric layer 130 through the first connecting line or the second connecting line, for example, the contact portion 151 can be in contact with the first connecting line or the second connecting line (to be described in detail below).

[0157] Continuing to refer to Figure 5 , Figure 6 and Figure 11 , in some embodiments, each dielectric layer 130 can include a gate line G and an embedded portion IL, and the size and shape of the gate line G and the embedded portion IL of each dielectric layer can be substantially the same, for example, the area and shape of the orthographic projection of the gate line G of each dielectric layer on the source layer SL can be substantially the same. Referring to Figure 6In order to realize that the contact structure 150 is electrically connected with a gate line G, the size 151' of the contact portion 151 can be greater than the size 152' of the connecting column 152 in the direction perpendicular to the thickness direction of the three-dimensional memory, for example, parallel to the X-Y plane which is the plane determined by the X-axis direction and the Y-axis direction. The size 151' of the contact portion 151 can be the maximum size of the contact portion 151 in the direction perpendicular to the thickness direction of the three-dimensional memory. Similarly, the size 152' of the connecting column 152 can be the maximum size of the connecting column 152 in the direction perpendicular to the thickness direction of the three-dimensional memory. In this way, the contact structure 150 can be electrically connected with the gate line G by the contact between the contact portion 151 and the gate line G, and the contact structure 150 does not contact the gate line G in each medium layer 130 through which the contact structure 150 penetrates, so that the electrical signal can be written to each gate line G individually by the plurality of contact structures 150.

[0158] Referring to Figure 5 and Figure 7 , Figure 5 shows the cross section of the plurality of contact columns in the X-Y plane and the cross section of the plurality of channel structures in the X-Y plane, Figure 7 shows the cross section of the channel structure. In some embodiments, the size 152' of the connecting column in the contact structure 150 (for example, each contact structure 150) is greater than or equal to the size 140' of the channel structure 140 in the direction perpendicular to the thickness direction of the three-dimensional memory, for example, parallel to the X-Y plane which is the plane determined by the X-axis direction and the Y-axis direction. The size 140' of the channel structure 140 can be the maximum size of the channel structure 140 in the direction perpendicular to the thickness direction of the three-dimensional memory. In this way, the size 152' of the connecting column 152 of the contact structure 150 can be large, and the process of manufacturing the connecting column 152 can be simple. Moreover, the electrical connection stability between the contact structure 150 and the gate line G can be better.

[0159] Figure 13 is a cross-sectional view of a first semiconductor structure in a three-dimensional memory according to some embodiments, the cross section being perpendicular to the thickness direction of the three-dimensional memory, for example, parallel to the X-Y plane. Figure 13 the cross section in Figure 11 the cross sections in Figure 11 the cross section in Figure 6 the cross section in Figure 13 the cross section in Figure 13 the channel structure and the dummy channel structure are omitted in

[0160] Referring to Figure 13 , the first semiconductor structure includes the first contact structure 150c and the first dielectric layer 130c, and the three-dimensional memory also includes the first contact structure 150c and the first dielectric layer 130c. Among them, the first contact structure 150c is one of the plurality of contact structures 150 in the three-dimensional memory, and the first dielectric layer 130c is one of the plurality of dielectric layers 130 in the three-dimensional memory. And the first contact structure 150c is electrically connected to the first sub-gate line 131 in the first dielectric layer 130c through the first connecting line 134 in the first dielectric layer 130c. In this way, an electrical signal can be written to the gate line G in the first dielectric layer 130c through the contact structure 150c. Exemplarily, the first contact structure 150c can be in contact with the first connecting line 134, and the first connecting line 134 can be integrated with the first sub-gate line 131 to achieve the electrical connection between the first contact structure 150c and the first sub-gate line 131 in the first dielectric layer 130c through the first connecting line 134 in the first dielectric layer 130c.

[0161] Further, referring to Figure 13 In some embodiments, the distance q1 between the first contact structure 150c and the first gate line isolation structure 170 is less than the distance q2 between the first contact structure 150c and the second gate line isolation structure 180.

[0162] It should be noted that, referring to Figure 6 In this paper, considering the three-dimensional shape of the contact structure 150, the distance q between the contact structure 150 and the first or second gate line isolation structure 180 can be the distance between the center of the contact structure 150 and the surface of the first or second gate line isolation structure 180 close to the contact structure 150.

[0163] Based on the above, referring to Figure 13Since the distance q1 between the first contact structure 150c and the first gate line isolation structure 170 is smaller than the distance q2 between the first contact structure 150c and the second gate line isolation structure 180, the distance between the second gate line isolation structure 180 and the first contact structure 150c is larger. In order to realize the individual control of each gate line, each contact structure 150 can be spaced apart from each other. Exemplarily, for two of the plurality of contact structures 150, the contact portions of the two can be located at different levels, so that the two can be electrically connected with the dielectric layers located at different levels respectively. The contact structure with the contact portion located at the lower level can be referred to as the lower level contact structure, and the contact structure with the contact portion located at the higher level can be referred to as the higher level contact structure. Based on this, the orthogonal projection of the connecting column in the lower level contact structure on the source layer does not overlap with the orthogonal projection of the contact portion in the higher level contact structure on the source layer, so that each contact structure 150 can be spaced apart from each other. Based on the above, since the distance between the second gate line isolation structure 180 and the first contact structure 150c is larger, for a contact structure located at a lower level of the first contact structure 150c, at least a part (for example, part; for example, all) of the contact structure can be arranged between the first contact structure 150c and the second connecting line 135 and in contact with the second connecting line 135. In this way, the plurality of contact structures 150 can be distributed in a staggered array (as shown in Figure 5 Based on the above, the size of the three-dimensional memory in the first direction (for example, parallel to the X-axis direction) can be reduced.

[0164] Referring back to Figure 11 In some embodiments, the first semiconductor structure further includes a second contact structure 150d and a dielectric layer 130d, which can also be said that the three-dimensional memory further includes a second contact structure 150d and a dielectric layer 130d. Hereinafter, in order to distinguish, the dielectric layer 130d is referred to as the second dielectric layer. Among them, the second contact structure 150d is one of the plurality of contact structures 150 in the three-dimensional memory, and the second dielectric layer 130d is one of the plurality of dielectric layers 130 in the three-dimensional memory. And the second contact structure 150d is electrically connected with the second sub-gate line 132 in the second dielectric layer 130d through the second connecting line 135 in the second dielectric layer 130d. In this way, the second contact structure 150d can write an electrical signal to the gate line G in the second dielectric layer 130d. Exemplarily, the second contact structure 150d can be in contact with the second connecting line 135, and the second connecting line 135 can be integrated with the second sub-gate line 132 to realize the electrical connection between the second contact structure 150d and the second sub-gate line 132 in the second dielectric layer 130d through the second connecting line 135 in the second dielectric layer 130d.

[0165] Continuing to refer to Figure 11In some embodiments, similar to the first contact structure, the distance q3 between the second contact structure 150d and the second gate line isolation structure 180 is smaller than the distance q4 between the second contact structure 150d and the first gate line isolation structure 170. In this way, the plurality of contact structures 150 can be distributed in a staggered array (as shown in FIG. 1B), which can reduce the size of the three-dimensional memory in the first direction (e.g., parallel to the X-axis direction). Figure 5

[0166] Referring back to FIG. 1A, in some embodiments, the first semiconductor structure can further include a plurality of dummy channels, which can also be referred to as a plurality of dummy channel structures. Specifically, the three-dimensional memory can include at least one (e.g., one; or alternatively, a plurality) of first dummy channel structures 160-a disposed in the contact area CA, and / or at least one (e.g., one; or alternatively, a plurality) of second dummy channel structures 160-b disposed in the contact area CA, and / or at least one (e.g., one; or alternatively, a plurality) of third dummy channel structures 160-c disposed in the transition area DA. Each of the first dummy channel structures 160-a can extend through the first connection line 134. Each of the second dummy channel structures 160-b can extend through the second connection line 135. Figure 10

[0167] In some embodiments, the first dummy channel structures 160-a, the second dummy channel structures 160-b, and the third dummy channel structures 160-c can have similar structures as the channel structures 140. Specifically, the first dummy channel structures 160-a, the second dummy channel structures 160-b, and the third dummy channel structures 160-c can also include a functional layer and a semiconductor channel, which can have similar structures as described above and will not be repeated here. Since the first dummy channel structures 160-a, the second dummy channel structures 160-b, and the third dummy channel structures 160-c can have similar structures as the channel structures 140, the first dummy channel structures 160-a, the second dummy channel structures 160-b, and the third dummy channel structures 160-c can be fabricated in the same process as the channel structures 140, which can simplify the fabrication process of the three-dimensional memory.

[0168] ​​The first dummy channel structure 160-a, the second dummy channel structure 160-b, and the third dummy channel structure 160-c can play a supporting role and can improve the structural stability of the three-dimensional memory. In addition, as described above, in the process of manufacturing the gate lines, because the first dummy channel structure 160-a, the second dummy channel structure 160-b, and the third dummy channel structure 160-c are arranged in the three-dimensional memory, the etching uniformity of the etching process for removing the first material layer can be improved, which is conducive to improving the control of the etching process and can improve the yield of the three-dimensional memory.

[0169] Referring to Figure 6 In some embodiments, the three-dimensional memory provided by the embodiments of the present disclosure can not be provided with a step structure, that is, the electrical connection between the plurality of contact structures and the plurality of gate lines can be achieved. In this way, the manufacturing process of the three-dimensional memory is relatively simple, which can save costs and improve the yield of the three-dimensional memory.

[0170] Continuing to refer to Figure 6 In some embodiments, the three-dimensional memory can further include a third material layer XL. The third material layer XL can surround part or all of the connecting columns 152 in the contact structure.

[0171] Specifically, Figures 14A-14C is a process flow diagram of a manufacturing method of a contact structure. Referring to Figures 14A-14C , in the process of manufacturing the contact structure, referring to Figure 14A The contact hole CTH can be formed in the second stack structure SK2, and the contact hole CTH can expose part of the first material layer 320d. Referring to Figure 14B Part of the first material layer 320d can be removed through the contact hole CTH to expose part of the gate line G. Referring to Figure 14C The contact structure 150 is formed through the contact hole CTH, so that the contact structure 150 is in contact with the gate line G to achieve electrical connection between the contact structure 150 and the gate line G. In the above process, the side wall of the contact hole CTH can be surrounded by the third material layer XL, so that in the step of removing part of the first material layer 320d through the contact hole CTH, the third material layer XL can protect each first material layer at a higher level of the first material layer 320d, so that these first material layers are not etched.

[0172] Referring to Figure 6 In some possible implementations, part of the third material layer XL can also be arranged on the side of the first stack structure SK1 away from the source layer SL. Referring to Figure 15 , Figure 15FIG. 1 is a cross-sectional view of a first semiconductor structure in a three-dimensional memory according to some embodiments. In some possible implementations, a portion of the third material layer XL located on a side of the first stack structure SK1 away from the source layer SL can be removed, i.e., the third material layer XL is not disposed on a surface of the side of the first stack structure SK1 away from the source layer SL.

[0173] In some embodiments, the three-dimensional memory described above can be a word line center driven three-dimensional memory, i.e., the three-dimensional memory can have two array regions distributed relatively along the first direction, and a contact region disposed between the two array regions. Further, a transition region can be disposed between one array region (e.g., each array region) and the contact region. The word line center driving can be achieved by simultaneously controlling a plurality of channel structures located in the two array regions distributed relatively along the first direction through a plurality of contact structures disposed in the contact region.

[0174] Figure 16 FIG. 2 is a block diagram of a storage system according to some embodiments. Figure 17 FIG. 3 is a block diagram of a storage system according to some other embodiments.

[0175] Referring to Figure 16 and Figure 17 , some embodiments of the disclosure further provide a storage system 1. The storage system 1 includes a controller 20 and a three-dimensional memory 10 as some embodiments described above, the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0176] The storage system 1 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1 can be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having a storage.

[0177] In some embodiments, referring to Figure 16 , the storage system 1 includes a controller 20 and one three-dimensional memory 10, and the storage system 1 can be integrated into a memory card.

[0178] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (Compact Flash, CF for short) card, smart media (Smart Media, SM for short) card, memory stick, multimedia card (Multimedia Card, MMC for short), secure digital memory card (Secure Digital Memory Card, SD for short), and UFS.

[0179] In some embodiments, the memory system 1 includes a controller 20 and a plurality of three-dimensional memories 10, and the memory system 1 can be integrated into a solid state drive (SSD for short). Figure 17 In the memory system 1, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a universal serial bus (USB for short) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0180] In some embodiments, the controller 20 can be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (such as a host). In some embodiments, the controller 20 can also be configured to control the operation of the three-dimensional memory 10, such as read, erase and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes related to data read from or written to the three-dimensional memory 10.

[0181] Of course, the controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 can communicate with an external device (such as a host) through at least one of various interface protocols.

[0182]

[0183]

[0184] ​​It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic device (IDE) protocol, and a Firewire protocol.

[0185] Some embodiments of the present disclosure also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0186] The electronic device can include the storage system 1 described above, and can further include at least one of a central processing unit (CPU) and a cache.

[0187] Some embodiments of the present disclosure also provide a method for manufacturing a three-dimensional memory. Through the method, the three-dimensional memory provided in any of the above embodiments can be manufactured.

[0188] Figure 18 A flowchart of the method for manufacturing a three-dimensional memory according to some embodiments. Figures 19A-19M A process flowchart of the method for manufacturing a three-dimensional memory according to some embodiments.

[0189] Referring to Figure 18 , Figures 19A-19M The method for manufacturing a three-dimensional memory includes the following steps:

[0190] S1, forming a stack structure on a substrate.

[0191] Referring to Figure 19Awherein (a) is a top-down view of the stack structure, and (b) is a cross-sectional view of (a) along the cross-sectional line CC'. In some embodiments, the substrate 310 can be a composite substrate with a multi-layer structure. Exemplarily, the substrate 310 can include a base 311, a first sacrificial layer 312, and a second sacrificial layer 313. The material of the base 311 can include amorphous silicon, polycrystalline silicon, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials; the base 311 can also be made of a non-conductive material such as glass, plastic, or sapphire wafer. The material of the first sacrificial layer 312 can be an insulating material such as silicon oxide, silicon nitride, etc. The material of the second sacrificial layer 313 can be a semiconductor material such as a combination of one or more of amorphous, polycrystalline, or monocrystalline silicon.

[0192] In other embodiments, the substrate 310 can be a single-layer structure, in which case the substrate 310 can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.; the substrate 310 can also be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0193] The stack structure SK2 includes a plurality of first material layers 320 and a plurality of second material layers 330 stacked in layers. Specifically, in the thickness direction (e.g., parallel to the Z-axis direction) of the stack structure SK2, the plurality of first material layers 320 and the plurality of second material layers 330 are stacked in layers, and one second material layer 330 can be disposed between every two first material layers 320, or in other words, two adjacent first material layers 320 are separated by a second material layer 330.

[0194] Hereinafter, for the sake of distinction, the stack structure including the plurality of first material layers 320 and the plurality of second material layers 330 stacked in layers is referred to as a second stack structure SK2.

[0195] Exemplarily, the second stack structure SK2 can include first material layers 320a-320g and second material layers 330a-330h. It should be noted that, Figure 19I The number of first material layers and second material layers in the second stack structure SK2 is only illustrative, and the second stack structure SK2 can have other numbers of first material layers and second material layers, which are not limited by embodiments of the present disclosure.

[0196] The material of the first material layer 320 can include one or more of silicon oxide, silicon nitride, or silicon oxynitride. The first material layer 320 can be used to form the dielectric layer in the three-dimensional memory described above.

[0197] The material of the second material layer 330 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride. The second material layer 330 may be used to form an insulating layer in the three-dimensional memory described above.

[0198] It should be noted that the materials of the first material layer 320 and the second material layer 330 can be combined so that, during the etching process, the etching rate of the first material layer 320 is different from that of the second material layer 330. Therefore, during the etching process, a portion of the first material layer 320 can be removed while the second material layer 330 is retained. For example, the material of the first material layer 320 is silicon nitride, and the material of the second material layer 330 is silicon oxide.

[0199] A first material layer 320 and a second material layer 330 can be formed on the substrate 310 using a thin film deposition process, such as one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroplating.

[0200] Further, see Figure 19A In (a), the second stacked structure SK2 has a first region EA1 and a second region EA2. The first region EA1 and the second region EA2 can be distributed along a first direction, for example, parallel to the X-axis direction.

[0201] In some implementations, an etch stop layer 340 may be formed on substrate 310 before forming the second stacked structure SK2 on substrate 310. The etch stop layer 340 may include a first etch stop layer 341 and a second etch stop layer 342. The material of the first etch stop layer 341 may include one or more combinations of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the first etch stop layer 341 includes silicon oxide. The material of the second etch stop layer 342 may include a semiconductor material, such as one or more combinations of amorphous, polycrystalline, or monocrystalline silicon. In some embodiments, the material of the second etch stop layer 342 includes polycrystalline silicon.

[0202] In the subsequent possible etching process for removing the substrate 310, the etching rate of the material of the first etching stop layer 341 can be different from the etching rate of the material of the second etching stop layer 342. In addition, the etching rate of the material of the layer in the substrate 310 in contact with the first etching stop layer 341, such as the material of the second sacrificial layer 313, can be different from the etching rate of the material of the first etching stop layer 341. For example, the material of the first etching stop layer 341 includes silicon oxide, the material of the second etching stop layer 342 and the second sacrificial layer 313 are both polysilicon, and in the subsequent possible etching process for removing the substrate 310 and / or removing other materials with an etching rate close to the substrate 310, the first etching stop layer 341 can be exposed without further etching the second etching stop layer 342; in the subsequent possible etching process for removing the first etching stop layer 341 and / or removing other materials with an etching rate close to the first etching stop layer 341, the second etching stop layer 342 can be exposed without further etching the film layer disposed on the side of the second etching stop layer 342 away from the substrate 310, such as the second material layer 330.

[0203] In addition, in the subsequent possible process of forming a source layer on the side of the second etching stop layer 342 away from the second stack structure SK2, a laser annealing process can be performed. At this time, after the laser annealing process, the second etching stop layer 342 can act as an interface layer, which can strengthen the combination of the source layer and the second stack structure SK2 and improve the peeling problem between the source layer and the second stack structure SK2.

[0204] The etching stop layer 340 can be formed on the substrate 310 by a thin film deposition process, such as one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating process.

[0205] S2 (optionally), forming a channel structure extending in a third direction in the stack structure (i.e., the second stack structure).

[0206] Referring to Figure 19B , (a) is a top view of the substrate and the second stack structure, and (b) is a cross-sectional view of the substrate and the second stack structure in (a) along the cross-sectional line CC’. It should be noted that, for the sake of simplicity of the drawings, Figure 19B (b) in (a) omits some channel structures.

[0207] The channel structure 140 can extend through the second stack structure SK2 and the etching stop layer 340 in the third direction and into the substrate 310. The third direction is parallel to the thickness direction of the second stack structure, for example, parallel to the Z-axis direction.

[0208] In some embodiments, forming the channel structure 140 extending along the third direction in the second stack structure SK2 includes forming a channel hole. The channel hole can extend through the second stack structure SK2 and the etching stop layer 340 and into the substrate 310. Illustratively, the channel hole can be formed in the second stack structure SK2 and the etching stop layer 340 by a dry etching or wet etching process. In some possible implementations, the substrate 310 can include a second sacrificial layer 313, which can be configured as an etching stop layer for forming the channel hole. Illustratively, the etching of the channel hole can be stopped by the second sacrificial layer 313, such that the channel hole does not further extend to the first sacrificial layer 312 and the base 311.

[0209] Forming the channel structure 140 extending along the third direction in the second stack structure SK2 can further include, after forming the channel hole, sequentially forming a functional layer and a semiconductor channel on the inner wall of the channel hole. The materials and structures of the functional layer and the semiconductor channel can refer to the above description and will not be repeated here. In some embodiments, forming the functional layer on the inner wall of the channel hole can include sequentially forming a charge storage layer and a tunneling layer on the inner wall of the channel hole. In some embodiments, forming the functional layer on the inner wall of the channel hole further includes forming a blocking layer on the inner wall of the channel hole before forming the charge storage layer and the tunneling layer. That is, based on the above, forming the channel structure 140 can include sequentially forming a blocking layer, a charge storage layer, a tunneling layer, and a semiconductor channel in the channel hole.

[0210] Illustratively, the blocking layer, the charge storage layer, the tunneling layer, and the semiconductor channel layer can be formed on the inner wall of the channel hole by a thin film deposition process, such as one or more of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process, and an electroplating process.

[0211] In some possible implementations, after sequentially forming the functional layer and the semiconductor channel on the inner wall of the channel hole, a channel filling portion can be formed in the channel hole. The materials and structures of the channel filling portion can refer to the above description and will not be repeated here. The channel filling portion can be formed by a thin film deposition process. Illustratively, the channel filling portion can be formed by controlling the thin film deposition process such that one or more air gaps are formed in the channel filling portion.

[0212] In some embodiments, step S2 can further include forming dummy channel structures 160 in the second stack structure SK2. The structure and position of the dummy channel structures 160 can refer to the above description, which will not be repeated here. In addition, the manufacturing method of the dummy channel structures 160 can be the same as that of the channel structures 140, which can refer to the above description, which will not be repeated here. In some possible implementations, the channel structures 140 and the dummy channel structures 160 can be manufactured by the same process. In this way, the manufacturing process of the three-dimensional memory can be relatively simple.

[0213] S3, forming a first gate line slit, an isolation slit, and a second gate line slit.

[0214] Referring to Figure 19C , where (a) is a top view of the second stack structure and the substrate, and (b) is a cross-sectional view of the second stack structure and the substrate in (a) along the cross-sectional line DD’. The first gate line slit 350, the isolation slit 370, and the second gate line slit 360 pass through the second stack structure SK2, which can also be said that the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 pass through the plurality of first material layers 320 and the plurality of second material layers 330 which are stacked.

[0215] The first gate line slit 350, the isolation slit 370, and the second gate line slit 360 extend from the first area EA1 to the second area EA2. Exemplarily, the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 can extend from the first area EA1 to the second area EA2 along a first direction, for example, parallel to the X-axis direction.

[0216] Further, the length l1 of the portion of the isolation slit 370 located in the second area EA2 is less than the length l2 of the portion of the first gate line slit 350 located in the second area EA2, and less than the length l3 of the portion of the second gate line slit 360 located in the second area EA2. Wherein, the length l1, the length l2, and the length l3 can be the size of the slit along the first direction (for example, parallel to the X-axis direction).

[0217] Since the length l1 of the portion of the isolation slit 370 located in the second area EA2 is less than the length l2 of the portion of the first gate line slit 350 located in the second area EA2, and less than the length l3 of the portion of the second gate line slit 360 located in the second area EA2, there can be an area between the first gate line slit 350 and the second gate line slit 360 which is not provided with the isolation slit 370. Subsequently, a contact structure can be provided in the area, so that the size of the contact structure can be larger, and the manufacturing process of the contact structure can be relatively simple.

[0218] Similarly to forming the channel hole, the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 can be formed in the second stack structure SK2 by a dry etching or a wet etching process. The specific process can refer to the process of forming the channel hole described above, and will not be repeated here.

[0219] Referring to Figure 19B and Figure 19C In some embodiments, step S2 is performed before step S3, i.e., the channel structure 140 is formed in the second stack structure SK2 before the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 are formed in the second stack structure SK2 and extend from the first area EA1 to the second area EA2. In this way, the manufacturing process of the channel structure 140 will not affect the structure of the first gate line slit 350, the isolation slit 370, and the second gate line slit 360, and the manufacturing process of the three-dimensional memory can be relatively simple.

[0220] S4 (optionally), forming a first shielding structure and a second shielding structure in the first gate line slit, the isolation slit, and the second gate line slit.

[0221] Referring to Figure 19D , (b) is a cross-sectional view of the second stack structure and the substrate in (a) along the cross-sectional line DD'. The first shielding structure OB1 and the second shielding structure OB2 are formed in the first gate line slit 350, the isolation slit 370, and the second gate line slit 360. The first shielding structure OB1 is located in the first area EA1, and the second shielding structure OB2 is located in the second area EA2.

[0222] In some embodiments, the first shielding structure OB1 and the second shielding structure OB2 are of the same material, for example, the material of the first shielding structure OB1 and the material of the second shielding structure OB2 both include polysilicon. At this time, the first shielding structure OB1 and the second shielding structure OB2 can be formed integrally. For example, the first shielding structure OB1 and the second shielding structure OB2 can be formed in the same process. Of course, the material of the first shielding structure OB1 and the material of the second shielding structure OB2 can be different, and the first shielding structure OB1 and the second shielding structure OB2 can also be formed in different processes, and the embodiments of the present disclosure do not limit this.

[0223] The first shielding structure OB1 and the second shielding structure OB2 can be formed in the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 by a thin film deposition process, such as one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating process.

[0224] In some embodiments, a protective layer PL can be formed in the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 before the first and second barrier structures OB1 and OB2 are formed in the first gate line slit 350, the isolation slit 370, and the second gate line slit 360. The protective layer PL can cover the etch stop layer 340 and the substrate 310 exposed by the first gate line slit 350, the isolation slit 370, and the second gate line slit 360. The material of the protective layer PL can include one or more of a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0225] In a subsequent process that can remove the first and second barrier structures OB1 and OB2, the protective layer PL can protect the etch stop layer 340 and the substrate 310 exposed by the first gate line slit 350, the isolation slit 370, and the second gate line slit 360. Illustratively, the material of the first and second barrier structures OB1 and OB2 includes polysilicon, the material of the etch stop layer 340 (e.g., the second etch stop layer 342) also includes polysilicon, and the material of the substrate 310 (e.g., the second sacrificial layer 313) also includes polysilicon. In the subsequent process that can remove the first and second barrier structures OB1 and OB2, the protective layer PL can reduce etching of the etch stop layer 340 (e.g., the second etch stop layer 342) and the substrate 310 (e.g., the second sacrificial layer 313) by an etchant used to etch the first and second barrier structures OB1 and OB2.

[0226] S5 (optionally) removing the first barrier structure, leaving the second barrier structure.

[0227] Referring to Figure 19D and Figure 19E , in Figure 19E , (a) is a top-down view of the second stack structure and the substrate, and (b) is a cross-sectional view of the second stack structure and the substrate in (a) along a cross-sectional line CC’. Note that in (a) of Figure 19E , some of the channel structures are omitted for simplicity of the drawing. In some embodiments, a mask layer can be formed on a side of the second barrier structure OB2 away from the substrate 310, and the material of the mask layer is, for example, silicon oxide. The mask layer can cover the second barrier structure OB2 and expose the first barrier structure OB1. Thereafter, an etching process (e.g., a dry etching process or a wet etching process) can be used to remove the first barrier structure OB1 not covered by the mask layer, leaving the second barrier structure OB2 covered by the mask layer.

[0228] Continuing to refer to Figure 19D and Figure 19E , in some embodiments, after the first barrier structure OB1 is removed, the portion of the protective layer PL exposed by the second barrier structure OB2 can be removed.

[0229] S6, removing a portion of the first material layer through the portion of the first gate line slit, the isolation slit, and the second gate line slit located in the first area, to form a first gap and a second gap.

[0230] Referring to Figure 19F wherein (a) is a top-down view of the second stack structure and the substrate, (b) is a cross-sectional view of the second stack structure and the substrate in (a) along a cross-sectional line CC’, and (c) is a cross-sectional view of the second stack structure in (b) at the first material layer 320d, the cross-section being perpendicular to a thickness direction of the second stack structure, for example, parallel to the X-Y plane. It is noted that in (c) of Figure 19F In (c) of FIG. 3, the channel structure and the dummy channel structure are omitted for simplicity of the drawing.

[0231] Hereinafter, the first material layer will be described by taking the first material layer 320d as an example, unless otherwise specified. In the method of fabricating the three-dimensional memory, the structures of other first material layers in the second stack structure and the fabrication processes can be the same as those of the first material layer 320d.

[0232] A portion of the first material layer 320d can be removed through the portion of the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 located in the first area EA1, to form a first gap ST1 and a second gap ST2. The first gap ST1 is located between the first gate line slit 350 and the isolation slit 370, and the second gap ST2 is located between the second gate line slit 360 and the isolation slit 370.

[0233] To ensure that the subsequently formed first sub-gate line covers all the channel structures located between the first gate line slit 350 and the isolation slit 370 in the second direction (for example, parallel to the Y-axis direction), and that the subsequently formed second sub-gate line covers all the channel structures located between the second gate line slit 360 and the isolation slit 370 in the second direction, the first gap ST1 can be continuous with the first gate line slit 350 and the isolation slit 370, and the second gap ST2 can be continuous with the second gate line slit 360 and the isolation slit 370.

[0234] Further, the portion of the isolation slit 370 located in the second area EA2 includes an overhang portion 371. The overhang portion 371 overhangs the first gap ST1 and the second gap ST2 in the first direction, wherein the first direction is parallel to an extension direction of the isolation slit 370, for example, parallel to the X-axis direction.

[0235] Referring to Figures 19D-19FIn some embodiments, before forming the first gap ST1 and the second gap ST2, i.e., before performing step S6, the method for manufacturing the three-dimensional memory further comprises the above-mentioned steps S4 and S5, or in other words, the step S4 and the step S5 can be performed first, and then the step S6 is performed. At this time, after removing the first blocking structure OB1 and retaining the second blocking structure OB2, a part of the first material layer 320d can be removed through the first gate line slit 350, the isolation slit 370, and the part of the second gate line slit 360 exposed by the second blocking structure OB2, i.e., the part located in the first area EA1, to form the first gap ST1 and the second gap ST2. For example, an etchant can be introduced into the second stack structure SK2 through the first gate line slit 350, the isolation slit 370, and the part of the second gate line slit 360 exposed by the second blocking structure OB2, i.e., the part located in the first area EA1, to remove a part of the first material layer 320d, for example, to remove the part of the first material layer 320d located between the first gate line slit 350 and the isolation slit 370 and between the second gate line slit 360 and the isolation slit 370, and to form the first gap ST1 and the second gap ST2.

[0236] Further, in the step S6, since the second blocking structure OB2 is retained, a part of the second blocking structure OB2 can be arranged in the overhanging part 371. In this way, the overhanging part 371 is blocked by the second blocking structure OB2, so that the part of the first material layer 320d located in the circumferential direction of the overhanging part 371 (for example, the circumferential direction of the overhanging part 371 along the X-Y plane, which can include the two sides of the overhanging part 371 along the Y-axis direction and the side of the overhanging part 371 along the positive direction of the X-axis) cannot be in contact with the etchant, and thus is not removed.

[0237] Referring to Figure 19F In other embodiments, the method for manufacturing the three-dimensional memory does not comprise the above-mentioned steps S4 and S5. At this time, a part of the first material layer 320d located in the first area EA1 can be removed through the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 by other methods, which are not limited by the embodiments of the present disclosure as long as a part of the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 located in the first area EA1 can be exposed and a part of the first material layer 320d can be removed through the exposed part.

[0238] S7 (optionally), removing the second blocking structure.

[0239] Referring to Figure 19D , Figure 19E and Figure 19G In Figure 19GIn some embodiments, the method for manufacturing the three-dimensional memory further comprises steps S7 and S8. In some embodiments, the method for manufacturing the three-dimensional memory further comprises steps S7 and S8, and the step S7 can be performed after the step S4 and the step S5 are performed.

[0240] In some embodiments, the second blocking structure OB2 can be removed by an etching process (e.g., a dry etching process or a wet etching process).

[0241] After the second blocking structure OB2 is removed, the portions of the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 in the second area EA2 can expose the respective first material layers 320 (e.g., the first material layer 320d) in the second stack structure SK2, so that an etchant can be introduced into the second stack structure SK2 through the portions of the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 in the second area EA2, and then a portion of the first material layer 320d can be removed by an etching process.

[0242] Referring to Figure 19D and Figure 19G In some embodiments, after the second blocking structure OB2 is removed, the portions of the protective layer PL exposed by the first gate line slit 350, the isolation slit 370, and the second gate line slit 360 can be removed.

[0243] S8, removing a portion of the first material layer along a circumferential direction of the overhang through the portion of the isolation slit in the second area.

[0244] Referring to Figure 19H , Figure 19H is a cross-sectional view of the second stack structure, the cross-section being perpendicular to a thickness direction of the second stack structure, e.g., parallel to the X-Y plane. The cross-section can be a cross-section at the first material layer 320d in the second stack structure.

[0245] Referring to Figure 19H , removing a portion of the first material layer 320d along a circumferential direction of the overhang 371 through the portion of the isolation slit 370 in the second area EA2. The circumferential direction of the overhang 371 can be a circumferential direction of the overhang 371 along the X-Y plane. Illustratively, the circumferential direction of the overhang 371 can include two sides of the overhang 371 along the Y-axis direction and one side of the overhang 371 along the positive direction of the X-axis.

[0246] Referring to Figure 19G and Figure 19HIn some embodiments, the method for fabricating the three-dimensional memory includes step S7, which can be performed first, followed by step S8. At this time, after removing the second obscuring structure, the portion of the isolation slit 370 located in the second region EA2 can be exposed. Then, a portion of the first material layer 320d can be removed circumferentially along the extended portion 371 through the portion of the isolation slit 370 located in the second region EA2. Exemplarily, an etching process can be employed to introduce etchant into the second stacked structure SK2 through the portion of the isolation slit 370 located in the second region EA2 to remove a portion of the first material layer 320d, for example, the portion of the first material layer 320d near the isolation slit 370 located in the second region EA2 can be removed.

[0247] Figure 20 This is a process flow diagram for forming gaps through etching in related technologies. See also... Figure 20 In (a) of the related art, a gap W2 can be formed by removing a portion of the first material layer ML through the first gate slit 410, the isolation slit 430, and the second gate slit 420 located in the third region EA3, for example, by an etching process. The gap W2 may include a first gap 440 located between the first gate slit 410 and the isolation slit 430, and a second gap 450 located between the second gate slit 420 and the isolation slit 430. In the related art, the isolation slit 430 does not extend beyond the gap W2 in a first direction (e.g., parallel to the X-axis direction).

[0248] See Figure 20 In step (b), gaps W3 can be formed by removing a portion of the first material layer ML through the first gate slit 410 and the second gate slit 420 located in the fourth region EA4 (the third region EA3 and the fourth region EA4 can be distributed along the X-axis direction), for example, through another etching process. Gap W3 can include the first gap 440, the second gap 450, the fourth gap 470, and the fifth gap 480. Then, gate line material can be deposited in gap W2 to form gate lines.

[0249] Since etching processes can be isotropic, therefore, in Figure 20In the etching process shown in (a) in FIG. 4, in addition to forming the first gap 440 connecting the first gate line slit 410 and all the isolation slits 430 and the second gap 450 connecting the second gate line slit 420 and all the isolation slits 430, a fifth gap 460 extending beyond the isolation slit 430 in the X-axis direction is also formed, and the fifth gap 460 can connect the first gate line slit 410 and the second gate line slit 420. In the subsequent process of depositing the gate line material, in the Y-axis direction, for the first gap 440, the gate line material can be deposited through the first gate line slit 410 and the isolation slit 430. In contrast, for the fifth gap 460, since the fifth gap 460 extends beyond the isolation slit 430 in the X-axis direction and connects the first gate line slit 410 and the second gate line slit 420, the volume of the gap to be filled is larger, and thus the gate line material needs to be filled through the first gate line slit 410 and the second gate line slit 420. In this way, in the fifth gap 460, the problem of incomplete filling of the gate line material can occur. In the process of depositing the gate line material, an auxiliary gas such as a fluorine-containing gas or a chlorine-containing gas can be used. When the filling of the gate line material in the gap is incomplete, a large amount of the auxiliary gas can be left in the formed gate line. The left auxiliary gas can penetrate into the insulating layer, thereby damaging the insulating layer and possibly causing the problem of short circuit between adjacent gate lines.

[0250] In contrast, in the method for manufacturing a three-dimensional memory provided by the embodiments of the present disclosure, the step of removing part of the first material layer can be performed multiple times to form a gap (in which the gate line material can be subsequently deposited to form a gate line). Specifically, referring to FIG. 5, in the method for manufacturing a three-dimensional memory provided by the embodiments of the present disclosure, the step S6 can be performed first, and then the step S8 can be performed. In the step S6, the part of the isolation slit 370 located in the second area EA2 includes the overhanging portion 371, and the overhanging portion 371 extends beyond the first gap ST1 and the second gap ST2 in the first direction. Therefore, the part of the first material layer 320d located around the overhanging portion 371 can be removed in the step S8. In this way, the processes of the step S6 and the step S8 can be controlled respectively. For example, in the step S6, a long-time etching process can be used, so that the first gap ST1 can connect the first gate line slit 350 and the isolation slit 370, and the second gap ST2 can connect the second gate line slit 360 and the isolation slit 370. In contrast, in the step S8, a short-time etching process can be used, so that the gap formed by removing part of the first material layer 320d along the circumference of the overhanging portion 371 has a small volume. In the subsequent process of depositing the gate line material, the gate line material can be deposited in the gap with a small volume through the isolation slit 370, which can improve the problem of incomplete filling of the gate line material and improve the problem of short circuit between adjacent gate lines, thereby improving the structural stability of the three-dimensional memory. Figure 19F Figure 19H In the method for manufacturing a three-dimensional memory provided by the embodiments of the present disclosure, the step S6 can be performed first, and then the step S8 can be performed. In the step S6, the part of the isolation slit 370 located in the second area EA2 includes the overhanging portion 371, and the overhanging portion 371 extends beyond the first gap ST1 and the second gap ST2 in the first direction. Therefore, the part of the first material layer 320d located around the overhanging portion 371 can be removed in the step S8. In this way, the processes of the step S6 and the step S8 can be controlled respectively. For example, in the step S6, a long-time etching process can be used, so that the first gap ST1 can connect the first gate line slit 350 and the isolation slit 370, and the second gap ST2 can connect the second gate line slit 360 and the isolation slit 370. In contrast, in the step S8, a short-time etching process can be used, so that the gap formed by removing part of the first material layer 320d along the circumference of the overhanging portion 371 has a small volume. In the subsequent process of depositing the gate line material, the gate line material can be deposited in the gap with a small volume through the isolation slit 370, which can improve the problem of incomplete filling of the gate line material and improve the problem of short circuit between adjacent gate lines, thereby improving the structural stability of the three-dimensional memory. ​

[0251] Based on the above, continuing to refer to Figure 19H In some embodiments, the width t1 of the portion of the first material layer 320d removed along the circumferential direction of the overhang 371 is less than half of the width of the first gap ST1 and the second gap ST2, through the portion of the isolation slit 370 located in the second area EA2. Specifically, the width t1 of the portion of the first material layer 320d removed along the circumferential direction of the overhang 371 is less than half of the width t2 of the first gap ST1 and less than half of the width t3 of the second gap ST2. Wherein, the width t1 can be the size of the gap formed by removing a portion of the first material layer 320d along the circumferential direction of the overhang 371. The width t2 of the first gap ST1 can be the size of the first gap ST1 along the second direction (for example, parallel to the Y-axis direction). Similarly, the width t3 of the second gap ST2 can be the size of the second gap ST2 along the second direction. In this way, the volume of the gap formed by removing a portion of the first material layer 320d along the circumferential direction of the overhang 371 is small, and in the subsequent process of depositing the gate line material, the gate line material can be deposited in the small volume gap through the isolation slit 370, which can improve the problem of incomplete filling of the above-mentioned gate line material, thereby improving the problem of short circuit between adjacent gate lines, and can improve the structural stability of the three-dimensional memory.

[0252] S9 (optionally), removing a portion of the first material layer through the portion of the first gate line slit located in the second area. Removing a portion of the first material layer through the portion of the second gate line slit located in the second area.

[0253] Referring to Figure 19I Wherein, (a) is a top view of the second stack structure and the substrate, (b) is a cross-sectional view of the second stack structure and the substrate in (a) along the cross-sectional line DD', and (c) is a cross-sectional view of the second stack structure in (b) at the first material layer 320d, the cross-section being perpendicular to the thickness direction of the second stack structure, for example, parallel to the X-Y plane. It should be noted that in (c) of Figure 19I In (c) of the above, the channel structure and the dummy channel structure are omitted for the sake of simplicity of the drawing.

[0254] Referring to Figure 19I A portion of the first material layer 360d can be removed through the portion of the first gate line slit 350 located in the second area EA2, and a third gap ST3 can be formed. For example, a portion of the first material layer 320d can be removed through the portion of the first gate line slit 350 located in the second area EA2 by introducing an etchant into the second stack structure SK2 through an etching process (for example, a dry etching process or a wet etching process), for example, a portion of the first material layer 320d located in the second area EA2 and close to the first gate line slit 350 can be removed.

[0255] Continuing with the annex Figure 19I A portion of the first material layer 360d can be removed by the portion of the second gate line slit 360 located in the second area EA2, for example, a fourth gap ST4 can be formed. Exemplarily, a portion of the first material layer 320d can be removed by introducing an etchant into the second stack structure SK2 through the portion of the second gate line slit 360 located in the second area EA2 by an etching process (e.g., a dry etching process or a wet etching process).

[0256] Referring to Figure 19G and Figure 19I In some embodiments, the method of fabricating the three-dimensional memory includes step S7, which can be performed before step S9.

[0257] Specifically, after the second shielding structure is removed, the first gate line slit 350 and the portion of the second gate line slit 360 located in the second area EA2 can expose each of the first material layers 320 (e.g., the first material layer 320d) in the second stack structure SK2, so that an etchant can be introduced into the second stack structure SK2 through the first gate line slit 350 and the portion of the second gate line slit 360 located in the second area EA2, and then a portion of the first material layer 320d can be removed by an etching process.

[0258] In some embodiments, step S8 and step S9 can be performed in the same process. Exemplarily, the method of fabricating the three-dimensional memory includes step S7, which can be performed first, i.e., the second shielding structure is removed, and then the portion of the isolation slit 370 located in the second area EA2 can be exposed, and the portion of the first gate line slit 350 and the second gate line slit 360 located in the second area EA2 can also be exposed. After that, step S8 and step S9 are performed, for example, an etchant is introduced into the second stack structure SK2 through the portion of the first gate line slit 350, the second gate line slit 360, and the isolation slit 370 located in the second area EA2 by an etching process, and then a portion of the first material layer 320d is removed by an etching process.

[0259] In this case, since the step S8 and the step S9 are performed in the same process, in the same process, a portion of the first material layer 320d along the circumferential direction of the overhang 371 can be removed, and a portion of the first material layer 360d through the portion of the first gate line slit 350 located in the second area EA2 can be removed, for example, a third gap ST3 can be formed. A portion of the first material layer 360d through the portion of the second gate line slit 360 located in the second area EA2 can be removed, for example, a fourth gap ST4 can be formed. Since the etching process can be an isotropic etching process, the width of the first material layer 320d removed along the circumferential direction of the overhang 371 can be substantially the same as the width of the third gap ST3 (for example, the dimension of the third gap ST3 along the second direction). Based on this, referring to Figure 19H and Figure 19I and referring to the above description, since the width t1 of the first material layer 320d removed along the circumferential direction of the overhang 371 through the portion of the isolation slit 370 located in the second area EA2 is less than half of the width of the first gap ST1 and the second gap ST2, the gap formed by removing the first material layer 320d along the circumferential direction of the overhang 371 in the second direction (for example, parallel to the Y-axis direction) can not be in communication with the third gap ST3. Similarly, the gap formed by removing the first material layer 320d along the circumferential direction of the overhang 371 can not be in communication with the fourth gap ST4, so that the volume of the gap formed by removing a portion of the first material layer 320d along the circumferential direction of the overhang 371 is small, and in the subsequent process of depositing the gate line material, the gate line material can be deposited in the gap with the small volume through the isolation slit 370, the problem of incomplete filling of the gate line material can be improved, the problem of short circuit between adjacent gate lines can be improved, and the structural stability of the three-dimensional memory can be improved.

[0260] S10 (optionally), forming the first sub-gate line, the second sub-gate line, the connection portion, the first connection line and the second connection line through the first gate line slit, the second gate line slit and the isolation slit.

[0261] The material and structure of the first sub-gate line, the second sub-gate line, the connection portion, the first connection line and the second connection line can refer to the above description, which will not be repeated here.

[0262] Referring to Figure 19J , (a) is a top view of the second stack structure and the substrate, (b) is a cross-sectional view of the second stack structure and the substrate in (a) along the cross-sectional line DD', and (c) is a cross-sectional view of the second stack structure in (b) at the first material layer 320d, the cross section being perpendicular to the thickness direction of the second stack structure, for example, parallel to the X-Y plane. It should be noted that in (c) of Figure 19J , the channel structure and the dummy channel structure are omitted for simplicity of the drawing.

[0263] Referring to Figure 19J The first sub-gate line 131 can be located between the first gate line slit 350 and the isolation slit 370. The second sub-gate line 132 can be located between the second gate line slit 360 and the isolation slit 370. The connection portion 133 extends beyond the isolation slit 370 in the first direction (e.g., parallel to the X-axis direction), for example, the connection portion 133 extends beyond the isolation slit 370 in the positive direction of the X-axis. Also, the connection portion 133 is in contact with the first sub-gate line 131 and the second sub-gate line 132, for example, the connection portion 133, the first sub-gate line 131, and the second sub-gate line 132 can form an integral body. The first connection line 134 is in contact with the first sub-gate line 131, for example, the first connection line 134 and the first sub-gate line 131 can form an integral body. The second connection line 135 is in contact with the second sub-gate line 132, for example, the second connection line 135 and the second sub-gate line 132 form an integral body.

[0264] In some embodiments, the formation of the first sub-gate line 131, the second sub-gate line 132, the connection portion 133, the first connection line 134, and the second connection line 135 through the first gate line slit 350, the second gate line slit 360, and the isolation slit 370 can be performed in the same process. Illustratively, after performing the above steps S1-S9, a gap can be formed in which the gate line material can be deposited, and the first sub-gate line 131, the second sub-gate line 132, the connection portion 133, the first connection line 134, and the second connection line 135 can be formed, at this time, the first sub-gate line 131, the second sub-gate line 132, the connection portion 133, the first connection line 134, and the second connection line 135 can form an integral body.

[0265] In other embodiments, the formation of the first sub-gate line 131, the second sub-gate line 132, the connection portion 133, the first connection line 134, and the second connection line 135 through the first gate line slit 350, the second gate line slit 360, and the isolation slit 370 can also be performed in multiple processes. For example, after performing step S6 and before performing step S7, the gate line material can be deposited through the first gate line slit 350, the second gate line slit 360, and the isolation slit 370 located in the portion of the first area EA1. After this, steps S7, S8, and S9 are performed, and then the gate line material is deposited through the first gate line slit 350, the second gate line slit 360, and the isolation slit 370 located in the portion of the second area EA2, and the first sub-gate line 131, the second sub-gate line 132, the connection portion 133, the first connection line 134, and the second connection line 135 can be formed.

[0266] The gate line materials can be deposited in the gap by a thin film deposition process, such as one or more of a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD), and an electroplating process, to form the first sub-gate line 131, the second sub-gate line 132, the connecting part 133, the first connecting line 134, and the second connecting line 135.

[0267] In addition, in some embodiments, before step S10, a high dielectric constant layer can be formed in the gap. The material and structure of the high dielectric constant layer can refer to the above description, which will not be repeated here. The high dielectric constant layer can be formed in the gap by a thin film deposition process, such as one or more of a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD), and an electroplating process.

[0268] S11 (optionally), forming a first gate line isolation structure, an intermediate isolation structure, and a second gate line isolation structure.

[0269] Referring to Figure 19J and Figure 19K In Figure 19K , (a) is a top view of the second stack structure and the substrate, and (b) is a cross-sectional view of the second stack structure and the substrate in (a) along the cross-sectional line DD'. The first gate line isolation structure 170 can be formed in the first gate line slit 350, the intermediate isolation structure 190 can be formed in the isolation slit 370, and the second gate line isolation structure 180 can be formed in the second gate line slit 360.

[0270] The specific structure and material of the first gate line isolation structure 170, the second gate line isolation structure 180, and the intermediate isolation structure 190 can refer to the above description, which will not be repeated here.

[0271] The first gate line isolation structure 170, the second gate line isolation structure 180, and the intermediate isolation structure 190 can be formed by a thin film deposition process. The thin film deposition process is, for example, one or more of a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD), and an electroplating process.

[0272] S12 (optionally), forming a contact structure extending in a third direction in the stack structure (i.e., the second stack structure).

[0273] Referring to Figure 19LIn the diagram, (a) is a top view of the second stacked structure and the substrate, (b) is a cross-sectional view of the second stacked structure and the substrate in (a) along section line DD', and (c) is a cross-sectional view of the second stacked structure in (b) located at the first material layer 320d, the cross-section being perpendicular to the thickness direction of the second stacked structure, for example, parallel to the XY plane. Unless otherwise specified, the contact structure 150d, which is electrically connected to the gate lines in the first material layer 320d, will be used as an example to illustrate the contact structure. Understandably, the fabrication methods for other contact structures are similar to those for contact structure 150d, and can be referred to the following description, which will not be repeated here.

[0274] A contact structure 150 (e.g., each contact structure 150) is electrically connected to a first connecting line 134 or a second connecting line 135. See, for example, [link to example]. Figure 19L In (c), the contact structure 150d can be electrically connected to the second connecting line 135. Specifically, the contact structure 150d can contact the second connecting line 135 to achieve electrical connection between the contact structure 150d and the second connecting line 135.

[0275] Figures 21-27 This is a process flow diagram illustrating the fabrication process of the contact structure according to some embodiments of a three-dimensional memory fabrication method. It should be noted that... Figures 21-27 It can be Figure 19K The second stacked structure shown in (a) is a cross-sectional view along section line DD'. See also Figures 21-27 In some embodiments, step S12 may include the following steps:

[0276] S121, see also Figure 21 A contact hole CTH is formed on the surface of the second stacked structure SK2 away from the substrate 310, exposing a portion of the first material layer 320d. Furthermore, the sidewall CTH' of the contact hole CTH is surrounded by a third material. Alternatively, the sidewall CTH' of the contact hole CTH can be partially or entirely surrounded by a third material layer XL, where the material of the third material layer XL is a third material.

[0277] In some embodiments, the third material may be one or more combinations of silicon oxide, silicon nitride, or silicon oxynitride. The third material may cooperate with the material of the first material layer 320d such that, in a subsequent etching process to remove a portion of the first material layer 320d, the etching rate of the third material differs from the etching rate of the material of the first material layer 320d, thereby allowing the removal of a portion of the first material layer 320d while retaining the third material during the etching process. Exemplarily, the material of the first material layer 320d includes silicon nitride, and the third material includes silicon oxide.

[0278] In some embodiments, step S111 may include sub-steps:

[0279] S121a, see Figure 22 A first hole H1 is formed on the second stack structure SK2 away from the surface of the substrate 310. The first hole H1 is located on the side of the first material layer 320d away from the substrate 310 and exposes a portion of the second material layer 330e in contact with the first material layer 320d, for example, the first hole H1 can expose the second material layer 330e located on the side of the first material layer 320d away from the substrate 310 and in contact with the first material layer 320d.

[0280] S121b, see Figure 22 and Figure 23 A third material is deposited in the first hole H1 to obtain a second hole H2.

[0281] The third material can be deposited on the sidewall and bottom of the first hole H1 to form a third material layer XL, and the second hole H2 can be obtained. Accordingly, the sidewall H2' of the second hole H2 can be surrounded by part or all of the third material layer XL, and the bottom H2b of the second hole H2 can expose a portion of the third material layer XL.

[0282] The third material can be deposited by a thin film deposition process, such as one or more of a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating process.

[0283] S121c, see Figure 23 and Figure 24 The bottom H2b of the second hole H2 is etched to form a contact hole CTH.

[0284] Exemplarily, a dry etching process can be used to remove the third material exposed by the bottom H2b of the second hole H2, and further, a portion of the second material layer 330e can also be removed to form the contact hole CTH, so that the contact hole CTH can expose the first material layer 320d in contact with the second material layer 330e and located on the side of the second material layer 330e close to the substrate 310.

[0285] Based on the above, see Figures 22-24Since the first hole H1 is located on the side of the first material layer 320d away from the substrate 310 and exposes a part of the second material layer 330e in contact with the first material layer 320d, the first hole H1 does not extend into the first material layer 320d, and accordingly, the sidewall H2' of the second hole H2 formed subsequently also does not extend into the first material layer 320d. When the sidewall H2' of the second hole H2 extends into the first material layer 320d, the sidewall CTH' of the contact hole CTH formed subsequently can also extend into the first material layer 320d, which will affect the shape of the contact structure formed subsequently, and further affect the electrical connection stability of the contact structure. Based on this, since the first hole H1 is located on the side of the first material layer 320d away from the substrate 310 and exposes a part of the second material layer 330e in contact with the first material layer 320d, the electrical connection stability of the contact structure in the three-dimensional memory made can be improved, and further the performance of the three-dimensional memory can be improved.

[0286] S122, referring to Figure 24 and Figure 25 a part of the first material layer 320d is removed through the contact hole CTH.

[0287] Exemplarily, an etching process (for example, a dry etching process or a wet etching process) can be adopted, and through the contact hole CTH, an etchant can be introduced into the second stack structure SK2, and further a part of the first material layer 320d can be removed.

[0288] In some embodiments, in step S112, the second connection line 350 can be configured as an etching stop layer. Specifically, by reasonably selecting the etchant used in step S112, the etching rate of the material of the first material layer 320d is greater than the etching rate of the material of the second connection line 350 in the etching process of step S112, so that after a part of the first material layer 320d is removed in step S112, a gap is formed, which exposes a part of the second connection line 350, so that the contact structure 150d formed subsequently in the gap can be in contact with the second connection line 350 to realize the electrical connection between the contact structure 150d and the second connection line 350. In this way, the etching process in step S112 is easier to control, and the manufacturing process of the three-dimensional memory can be simplified, and the yield of the three-dimensional memory can be improved.

[0289] S123, referring to Figure 25 and Figure 26 a contact structure 150d is formed through the contact hole CTH.

[0290] The material and structure of the contact structure 150d can refer to the related description above, which will not be repeated here.

[0291] The contact structure 150d can be fabricated by a thin film deposition process, such as one or more of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process, and an electroplating process.

[0292] In some embodiments, referring to Figure 23 In step S121b, the third material can also be deposited on the surface of the second stack structure SK2 away from the substrate 310, in other words, a portion of the third material layer XL is located on the surface of the second stack structure SK2 away from the substrate 310. Referring to Figure 27 In some possible implementations, after step S123, the portion of the third material layer XL located on the surface of the second stack structure SK2 away from the substrate 310 can be removed.

[0293] S13, removing the substrate to form a source layer.

[0294] Referring to Figure 19L and Figure 19M In some embodiments, the substrate 310 can be removed from the back side of the substrate 310 (i.e., the side of the substrate 310 away from the second stack structure SK2), for example, by a chemical mechanical planarization (CMP) process, a dry / wet etching process.

[0295] For example, the base 311 can be removed by a chemical mechanical planarization (CMP) process and / or an etching process (e.g., including a dry etching process and / or a wet etching process); for another example, the first sacrificial layer 312 can be removed by an etching process, and the second sacrificial layer 313 can act as an etching stop layer in the process of removing the first sacrificial layer 312 by the etching process; for another example, the second sacrificial layer 313 can be removed by an etching process, and the first etching stop layer 341 can act as an etching stop layer in the process of removing the second sacrificial layer 313 by the etching process.

[0296] Further, after the substrate 310 is removed, the first etching stop layer 341 and a portion of the functional layer in the channel structure can be exposed, and the first etching stop layer 341 and the portion of the functional layer can be removed by an etching process to expose the semiconductor channel. Illustratively, a suitable etchant can be selected so that the etching can stop at the second etching stop layer 342 and the semiconductor channel, without further etching the second material layer.

[0297] In some embodiments, after the substrate 310 is removed, a source layer SL can be formed on the side of the second etching stop layer 342 away from the second stack structure SK2.

[0298] In some embodiments, before the substrate is removed, the first semiconductor structure 100 and the second semiconductor structure 200 can be bonded by setting a bonding interface IF between the array interconnection layer 110 and the peripheral interconnection layer 230, and then the first semiconductor structure 100 and the second semiconductor structure 200 bonded together can be flipped 180° as a whole, and then the step of removing the substrate can be performed from the back of the substrate (i.e. the side of the substrate away from the stack structure). In this way, the second semiconductor structure 200 including the peripheral circuit and the first semiconductor structure 100 can be manufactured separately. For example, the peripheral circuit can be manufactured on a substrate, and the first semiconductor structure can be manufactured on another substrate. In this way, the manufacturing process of the array device and the peripheral device can be prevented from affecting each other, and the performance of the three-dimensional memory can be improved. Moreover, in the step of removing the substrate, since the first semiconductor structure is electrically connected to the second semiconductor structure first, and then the step of removing the substrate is performed, in the step of removing the substrate, the second semiconductor structure can provide support for the first semiconductor structure, and the structural stability of the three-dimensional memory can be improved, and the yield of the product can be improved.

[0299] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A three-dimensional memory, comprising: has an array region, a transition region, and a contact region, the transition region is disposed between the array region and the contact region; The three-dimensional memory includes: A plurality of dielectric layers are stacked; A plurality of channel structures and a plurality of contact structures extend in the plurality of dielectric layers, the plurality of channel structures are disposed in the array region, and the plurality of contact structures are disposed in the contact region; A first gate line isolation structure, an intermediate isolation structure, and a second gate line isolation structure penetrate the plurality of dielectric layers, the intermediate isolation structure is located between the first gate line isolation structure and the second gate line isolation structure, the intermediate isolation structure extends from the array region to the transition region, and the first gate line isolation structure and the second gate line isolation structure extend from the array region to the contact region; Wherein, the dielectric layer includes a first sub-gate line, a second sub-gate line, and a connecting portion, the first sub-gate line is located between the first gate line isolation structure and the intermediate isolation structure, the second sub-gate line is located between the second gate line isolation structure and the intermediate isolation structure, the connecting portion exceeds the intermediate isolation structure in a first direction and is in contact with the first sub-gate line and the second sub-gate line, the first sub-gate line has a first notch in the middle of one end close to the contact region, the second sub-gate line has a second notch in the middle of one end close to the contact region, and in a second direction, the connecting portion does not exceed the edges of the first notch and the second notch close to each other, the first direction is the extension direction of the intermediate isolation structure, and the second direction is perpendicular to the first direction.

2. The three-dimensional memory of claim 1, wherein The dielectric layer further includes a first connection line and a second connection line, the first connection line and the second connection line extend from the transition region to the contact region; The first connection line is located on one side of the first gate line isolation structure close to the plurality of contact structures, and the second connection line is located on one side of the second gate line isolation structure close to the plurality of contact structures; The three-dimensional memory includes a first contact structure and a first dielectric layer, the first contact structure is one of the plurality of contact structures, and the first dielectric layer is one of the plurality of dielectric layers; The first contact structure is electrically connected to a first sub-gate line in the first dielectric layer through a first connection line in the first dielectric layer.

3. The three-dimensional memory of claim 2, wherein The distance between the first contact structure and the first gate line isolation structure is less than the distance between the first contact structure and the second gate line isolation structure.

4. The three-dimensional memory of claim 2, wherein The three-dimensional memory further includes a second contact structure and a second dielectric layer, the second contact structure is one of the plurality of contact structures, and the second dielectric layer is one of the plurality of dielectric layers; The second contact structure is electrically connected to a second sub-gate line in the second dielectric layer through a second connection line in the second dielectric layer. The distance between the second contact structure and the second gate line isolation structure is less than the distance between the second contact structure and the first gate line isolation structure.

5. The three-dimensional memory of claim 1, wherein: The contact structure comprises a contact portion and a connecting column arranged in sequence along the thickness direction of the three-dimensional memory, the contact portion and the connecting column are electrically connected, and the contact portion is electrically connected to the first sub-gate line, the second sub-gate line, and the connecting portion at the same level.

6. The three-dimensional memory of claim 5, wherein: In a direction perpendicular to the thickness direction of the three-dimensional memory, the size of the connecting column is greater than or equal to the size of the channel structure; and / or, In a direction perpendicular to the thickness direction of the three-dimensional memory, the size of the contact portion is greater than the size of the connecting column.

7. The three-dimensional memory of claim 1, wherein: The dielectric layer further comprises an embedded portion, the embedded portion is located between the first gate line isolation structure and the second gate line isolation structure, the embedded portion extends from the contact region to the transition region, and is embedded in the first gap and the second gap.

8. The three-dimensional memory of claim 2, wherein, Further comprising: A first dummy channel structure arranged in the contact region, the first dummy channel structure penetrates the first connecting line; And / or, A second dummy channel structure arranged in the contact region, the second dummy channel structure penetrates the second connecting line; and / or, A third dummy channel structure arranged in the transition region.

9. The three-dimensional memory of claim 1, wherein, Further comprising: A source layer, the channel structure and the source layer are electrically connected; A peripheral circuit, the channel structure and the peripheral circuit are electrically connected; Wherein, the source layer and the peripheral circuit are arranged on both sides of the channel structure.

10. A storage system, characterized by Comprising: A three-dimensional memory, the three-dimensional memory is any one of claims 1-9; A controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

11. An electronic device, comprising: The storage system of claim 10 is included.

12. A method of fabricating a three-dimensional memory as claimed in any one of claims 1-9, characterized by, Comprising: Forming a stack structure on a substrate, the stack structure comprising a plurality of first material layers and a plurality of second material layers arranged in layers, the stack structure having a first region and a second region; Forming a first gate line slit, an isolation slit, and a second gate line slit penetrating the stack structure and extending from the first region to the second region, the isolation slit being located between the first gate line slit and the second gate line slit, the length of the portion of the second region where the isolation slit is located being less than the length of the portion of the second region where the first gate line slit and the second gate line slit are located; A portion of the first material layer is removed through the first gate line slit, the isolation slit and the portion of the first gate line slit and the isolation slit located in the first region, forming a first gap between the first gate line slit and the isolation slit and a second gap between the second gate line slit and the isolation slit, and the portion of the isolation slit located in the second region includes an overhanging portion which overhangs the first gap and the second gap in a first direction, the first direction being parallel to the extension direction of the isolation slit; A portion of the first material layer is removed along the circumferential direction of the overhanging portion through the portion of the isolation slit located in the second region.

13. The manufacturing method of the three-dimensional memory according to claim 12, wherein The width of the portion of the first material layer removed along the circumferential direction of the overhanging portion through the portion of the isolation slit located in the second region is less than half of the width of the first gap and less than half of the width of the second gap.

14. The method of making a three-dimensional memory of claim 12, wherein, Further comprising: A portion of the first material layer is removed through the portion of the first gate line slit located in the second region; A portion of the first material layer is removed through the portion of the second gate line slit located in the second region.

15. The method of making a three-dimensional memory of claim 14, wherein, Further comprising: The first sub-gate line, the second sub-gate line, the connecting portion, the first connecting line and the second connecting line are formed through the first gate line slit, the second gate line slit and the isolation slit; The first sub-gate line is located between the first gate line slit and the isolation slit; the second sub-gate line is located between the second gate line slit and the isolation slit; the connecting portion overhangs the isolation slit in the first direction and contacts the first sub-gate line and the second sub-gate line; the first connecting line contacts the first sub-gate line and the second connecting line contacts the second sub-gate line.

16. The method of making a three-dimensional memory of claim 15, wherein, Further comprising: The contact structure extending along a third direction is formed in the stack structure with the first connecting line and the second connecting line, the contact structure is electrically connected with the first connecting line or the second connecting line, and the third direction is parallel to the thickness direction of the stack structure.

17. The method of making a three-dimensional memory of claim 16, wherein, Forming the contact structure extending along a third direction in the stack structure with the first connecting line and the second connecting line comprises: A contact hole is formed on the surface of the stack structure away from the substrate, the contact hole exposes a portion of the first material layer, and the sidewall of the contact hole is surrounded by a third material; A portion of the first material layer is removed through the contact hole; The contact structure is formed through the contact hole.

18. The method of making a three-dimensional memory of claim 17, wherein, Forming the contact hole on the surface of the stack structure away from the substrate comprises: A first hole is formed on the surface of the stack structure away from the substrate, the first hole is located on the side of the first material layer away from the substrate and exposes a portion of the second material layer in contact with the first material layer; A third material is deposited in the first hole to obtain a second hole; The bottom of the second hole is etched to form the contact hole.

19. The method of producing a three-dimensional memory of claim 12, wherein, Before forming the first gap and the second gap, further comprising: forming a first shield structure in the first region and a second shield structure in the second region in the first gate line slit, the isolation slit, and the second gate line slit; removing the first shield structure and retaining the second shield structure.

20. The method of making a three-dimensional memory of claim 19, wherein, after forming the first gap and the second gap, further comprising: removing the second shield structure.

21. The method of making a three-dimensional memory of claim 12, wherein, before forming the first gate line slit, the isolation slit, and the second gate line slit extending through the stack structure and from the first region to the second region, further comprising: forming a channel structure extending in a third direction in the stack structure, the third direction being parallel to a thickness direction of the three-dimensional memory.

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