Three-dimensional memory devices and methods of manufacturing the same

Abstract

The application provides a three-dimensional memory device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, a stack structure is formed on the substrate, the stack structure comprises alternately stacked sacrificial layers and insulating layers; forming a channel hole penetrating through the stack structure along a longitudinal direction perpendicular to the substrate; forming a first functional layer on an inner wall of the channel hole and a second functional layer corresponding to the first functional layer, wherein the first functional layer comprises a plurality of sub-charge trapping layers spaced apart from each other along a direction surrounding a central axis of the channel hole, and the second functional layer comprises a plurality of sub-channel layers spaced apart from each other along the direction surrounding the central axis; and forming a dielectric layer on an inner surface of the plurality of sub-channel layers, so that the channel hole is filled with the dielectric layer. Since the plurality of sub-channel layers spaced apart from each other form a plurality of storage strings, one sub-channel layer is located in one storage string, the storage density is improved without increasing the number of layers of the stack, and the plurality of sub-storage layers spaced apart from each other avoid the crosstalk phenomenon between adjacent storage strings.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a three-dimensional memory device and a manufacturing method thereof. BACKGROUND

[0002] With the increasing demand for memory capacity, as two-dimensional memory devices have reached the practical limit of expansion, in order to further improve the storage capacity and reduce the storage cost per bit, the industry has proposed 3D NAND memory. In the 3D NAND memory structure, a vertically stacked multi-layer data storage unit is used to realize a stacked memory structure. The existing design of 3D NAND is a concentric circle structure, which usually fills the charge trapping layer, the tunneling layer and the channel layer in the channel hole in sequence, and finally fills the dielectric layer in the concentric circle, thereby forming a continuous charge trapping memory from top to bottom. The advantage is that the storage density can be maximized by increasing the density and the number of stacked layers of the concentric circle with the minimum expenditure.

[0003] However, in order to improve the storage density, the excessive number of stacked concentric circle structures will not only cause alignment deviation problems between the upper channel hole and the lower channel hole, but also bring challenges to the etching process. At the same time, as the thickness of each layer of the vertical stack is thinned, the design of the concentric circle structure will also cause the charge loss ratio in the 3D NAND to be greater than that in the two-dimensional memory device, and therefore the reliability of the corresponding 3D NAND is low. SUMMARY

[0004] The present application provides a three-dimensional memory device and a manufacturing method thereof, which effectively improves the reliability of the three-dimensional memory device.

[0005] In order to solve the above problems, the present application provides a manufacturing method of a three-dimensional memory device, comprising: providing a substrate, a stack structure is formed on the substrate, the stack structure comprises alternatingly stacked sacrificial layers and insulating layers; forming a channel hole penetrating through the stack structure along the longitudinal direction perpendicular to the substrate; forming a first functional layer on the inner wall of the channel hole and a second functional layer corresponding to the first functional layer, wherein the first functional layer comprises a plurality of sub-charge trapping layers spaced apart from each other in the direction around the central axis of the channel hole, and the second functional layer comprises a plurality of sub-channel layers spaced apart from each other in the direction around the central axis; forming a dielectric layer on the inner surface of the plurality of sub-channel layers, so that the channel hole is filled with the dielectric layer.

[0006] The step of forming the channel hole through the stack structure along the vertical direction of the substrate comprises: etching the stack structure along the vertical direction of the substrate by using a mask plate to form the channel hole having a plurality of alternately connected convex portions and concave portions in a planar direction parallel to the substrate, and the plurality of alternately connected convex portions and concave portions are distributed around a central axis of the channel hole.

[0007] The step of forming the first functional layer on the inner wall of the channel hole and the second functional layer corresponding to covering the first functional layer comprises: sequentially forming a continuous and through-channel-hole blocking layer and a continuous and through-channel-hole charge capturing layer on the inner wall of the channel hole; sequentially forming a continuous and through-channel-hole tunneling layer and a continuous and through-channel-hole channel layer on the inner surface of the charge capturing layer; etching part of the channel layer and part of the tunneling layer located at the concave portion to separate the channel layer and the tunneling layer into a plurality of sub-channel layers and a plurality of sub-tunneling layers in a direction around the central axis; and etching part of the charge capturing layer located at the concave portion to separate the charge capturing layer into a plurality of sub-charge capturing layers in the direction around the central axis.

[0008] The step of forming the channel hole through the stack structure along the vertical direction of the substrate further comprises: etching the sacrificial layer through the channel hole to form a groove on a first interface where the channel hole and the sacrificial layer intersect, and making the diameter of the channel hole at the sacrificial layer larger than the diameter at the insulating layer.

[0009] The step of forming the first functional layer on the inner wall of the channel hole and the plurality of second functional layers corresponding to covering the first functional layer comprises: forming a blocking layer on the surface of the groove; forming a charge capturing layer on the inner surface of the blocking layer so that the charge capturing layer fills the groove and is isolated by the insulating layer in the vertical direction; sequentially forming a continuous and through-channel-hole tunneling layer and a continuous and through-channel-hole channel layer on a second interface where the channel hole and the insulating layer intersect and on the inner surface of the charge capturing layer; etching part of the channel layer and part of the tunneling layer located at the concave portion to separate the channel layer and the tunneling layer into a plurality of sub-channel layers and a plurality of sub-tunneling layers in a direction around the central axis; and etching part of the charge capturing layer located at the concave portion to separate the charge capturing layer into a plurality of sub-charge capturing layers in the direction around the central axis.

[0010] The step of forming the charge trapping layer on the inner surface of the blocking layer so that the charge trapping layer fills the recess and is isolated in the longitudinal direction by the insulating layer comprises: depositing a charge trapping material on the inner surface of the blocking layer so that the charge trapping material fills the recess; and removing the charge trapping material outside the recess to form the charge trapping layer aligned with the second interface in the longitudinal direction.

[0011] The method further comprises, before the step of sequentially etching the channel layer and the tunneling layer at the recess, the steps of: depositing a sacrificial material on the inner surface of the channel layer; and removing the sacrificial material at the recess to expose the inner surface of the channel layer at the recess.

[0012] The method further comprises, after the step of etching the charge trapping layer at the recess, the step of: etching the blocking layer at the recess to divide the blocking layer into a plurality of sub-blocking layers in a direction around the central axis.

[0013] The method of manufacturing the three-dimensional memory device further comprises: replacing the sacrificial layer with a gate layer.

[0014] The present application also provides a three-dimensional memory device, comprising: a substrate; a stack structure of insulating layers and gate layers alternately stacked on the substrate; a channel hole penetrating the stack structure in a longitudinal direction perpendicular to the substrate; a first functional layer on an inner wall of the channel hole and a second functional layer corresponding to the first functional layer, wherein the first functional layer comprises a plurality of sub-charge trapping layers spaced apart in a direction around a central axis of the channel hole, and the second functional layer comprises a plurality of sub-channel layers spaced apart in the direction around the central axis; and a dielectric layer on the inner surface of the plurality of sub-channel layers and filling the channel hole.

[0015] The channel hole forms a plurality of alternating protrusions and recesses in a planar direction parallel to the substrate, and the plurality of alternating protrusions and recesses are distributed around the central axis.

[0016] The first interface of the channel hole and the gate layer is staggered, and a groove is arranged on the first interface, so that the aperture of the channel hole at the gate layer is larger than the aperture of the channel hole at the insulating layer; the first functional layer further comprises a barrier layer, the barrier layer is located on the surface of the groove, each sub-charge capturing layer is located on the inner surface of the barrier layer and fills the groove, and the second interface of the channel hole and the insulating layer is flush with the inner surface of each sub-charge capturing layer in the longitudinal direction; the second functional layer is located at the protruding part, the second functional layer further comprises a plurality of sub-tunneling layers which are spaced apart from each other in the direction around the central axis, each sub-tunneling layer and each sub-channel layer penetrate the channel hole, and sequentially stack on the second interface and the inner surface of each sub-charge capturing layer.

[0017] The first functional layer and the second functional layer are both located at the protruding part; the first functional layer further comprises a plurality of sub-barrier layers which are spaced apart from each other in the direction around the central axis, each sub-barrier layer and each sub-charge capturing layer penetrate the channel hole, and sequentially stack on the inner surface of the channel hole; the second functional layer further comprises a plurality of sub-tunneling layers which are spaced apart from each other in the direction around the central axis, each sub-tunneling layer and each sub-channel layer penetrate the channel hole, and each sub-tunneling layer and each sub-channel layer sequentially stack on the inner surface of each sub-charge capturing layer.

[0018] The shape of the channel hole in the direction parallel to the plane of the substrate comprises at least one of trilobal shape, quadrilobal shape and star shape.

[0019] The three-dimensional memory device and the manufacturing method thereof provided by the application can improve the storage density without increasing the number of stacked layers, and can avoid crosstalk between adjacent storage strings by forming a plurality of sub-charge capturing layers which are spaced apart from each other, so that the reliability of the three-dimensional memory device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the description of each embodiment according to the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a flowchart of a manufacturing method of a three-dimensional memory device provided by an embodiment of the present application;

[0022] Figures 2A-2K is a schematic diagram of a cross section of a three-dimensional memory device at various stages of a method of manufacture according to embodiments of the present application;

[0023] Figure 2L is a schematic diagram of a structure of a three-dimensional memory device after filling a dielectric layer according to embodiments of the present application;

[0024] Figures 3A-3C is a schematic diagram of a top view of a channel hole according to embodiments of the present application;

[0025] Figures 4A-4B is a schematic diagram of a cross section of a three-dimensional memory device at various stages of another method of manufacture according to embodiments of the present application;

[0026] Figures 5A-5F is a schematic diagram of a top view of a three-dimensional memory device at a channel hole according to embodiments of the present application;

[0027] Figure 6 is a further flowchart of step S13. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present application.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0030] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mount", "connect", "connection" should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0031] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "under", "below" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0032] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not in itself indicate a relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0033] Please refer to Figure 1 , Figure 1 is a process flow chart of a manufacturing method of a three-dimensional memory device provided by the embodiment of the application, as Figure 1 shown, the manufacturing method can specifically include the following steps:

[0034] Step S11: providing a substrate, a stack structure is formed on the substrate, and the stack structure includes alternately stacked sacrificial layers and insulating layers.

[0035] In which, the half-section structure schematic diagram after step S11 is completed as Figure 2A shown.

[0036] Specifically, the material of the substrate 10 can be a semiconductor material such as silicon, germanium or silicon-on-insulator (SOI). In the stack structure 20, the material of the insulating layer 22 can be selected as silicon oxide or other high-K dielectric layer, and the material of the sacrificial layer 21 can be selected as nitride such as silicon nitride. When the insulating layer 22 is a silicon oxide layer and the substrate 10 is selected as a silicon substrate, the forming process of the insulating layer 22 on the substrate 10 is preferably a chemical vapor deposition (CVD) process. Further, in the CVD process, a tetraethyl orthosilicate (TEOS) / ozone (O3) system can be used to deposit a corresponding silicon oxide film layer. The sacrificial layer 21 can be formed on the insulating layer 22 by an atomic layer deposition (ALD) process or a CVD process.

[0037] Step S12: Forming a channel hole penetrating the stack structure along the longitudinal direction perpendicular to the substrate.

[0038] Specifically, the step S12 can include the following steps:

[0039] Step S121: Etching the stack structure by using a mask plate along the longitudinal direction perpendicular to the substrate to form a channel hole having a plurality of alternately connected convex portions and concave portions in the plane direction parallel to the substrate, the plurality of alternately connected convex portions and concave portions being distributed around the central axis of the channel hole.

[0040] Specifically, the step S121 can include the following steps: Figure 2B Figure 2B In order to further simplify the drawings, the substrate 10 is not shown in the following figures, the longitudinal direction is the z direction in the figures, the plane direction parallel to the substrate is composed of the x direction and the y direction in the figures, and any two of the x, y and z directions are perpendicular to each other.

[0041] Specifically, please refer to Figures 3A-3C The shape of the channel hole 30 can be various, Figures 3A-3C respectively, which are three top view schematic diagrams of the channel hole 30, as shown in Figure 3A and 3B The shape of the channel hole 30 in the plane (xy) direction parallel to the substrate 10 can be a four-leaf shape or a three-leaf shape, as shown in Figure 3C It can also be a star shape, as shown in Figures 3A-3C ​As shown, the channel hole 30 has a plurality of alternating convex portions A and concave portions B in the xy plane, which are distributed around the central axis OO' of the channel hole 30. The convex portions A protrude outward relative to the channel hole 30, and the concave portions B are recessed inward relative to the channel hole 30. The planar shape of the channel hole 30 can be freely defined by designing the pattern of the mask plate, and then the corresponding specific structure is formed in the stack structure 20 through the photolithography and etching processes. Please continue to refer to Figure 2B The inner wall 300 of the channel hole includes a first interface 301 where the channel hole 30 intersects the sacrificial layer 21, and a second interface 302 where the channel hole 30 intersects the insulating layer 22, and the first interface 301 and the second interface 302 are alternately connected.

[0042] In addition, step S12 can further include step S122 based on step S121, wherein step S122: refer to Figures 2B to 2C The sacrificial layer 21 is etched through the channel hole 30 to form a groove 31 on the first interface 301 where the channel hole 30 intersects the sacrificial layer 21, wherein Figure 2B The topmost sacrificial layer 21 is also etched accordingly.

[0043] The half-section structure diagram after step S122 is completed is shown in Figure 2C .

[0044] Specifically, when the sacrificial layer 21 is nitride (such as silicon nitride), wet etching of the sacrificial layer 21 through the channel hole 30 can be selected to form the groove 31 on the first interface 301 where the channel hole 30 intersects the sacrificial layer 21, and the surface 310 of the groove 31 is also shown in Figure 2C . The etching solution can include phosphoric acid aqueous solution, and the etching solution is also selectively added with ammonium salt and sulfuric acid and other adjusting agents for adjusting the etching effect of the etching solution. In addition, it should be noted that after the groove 31 is formed, the diameter of the channel hole 30 at the sacrificial layer 21 is greater than the diameter of the channel hole 30 at the insulating layer 22.

[0045] Step S13: forming a first functional layer on the inner wall of the channel hole and a second functional layer corresponding to covering the first functional layer. The first functional layer includes a plurality of sub-charge trapping layers spaced apart in the direction around the central axis of the channel hole, and the second functional layer includes a plurality of sub-channel layers corresponding to covering the inner surfaces of the plurality of sub-charge trapping layers.

[0046] In this embodiment, step S13 can be selected to be implemented directly after step S121, or can be implemented after step S122. When step S13 is implemented after step S122, as shown in Figure 6 , step S13 specifically includes the following steps:

[0047] Step S131: Form a barrier layer on the surface of the groove.

[0048] The schematic diagram of the half-section structure after step S131 is shown below. Figure 2D As shown.

[0049] Specifically, in the step of forming the barrier layer 40 on the surface 310 of the groove 31, when the sacrificial layer 21 is selected as a nitride (such as silicon nitride), the barrier layer 40 can be formed by oxidizing the sacrificial layer 21. The material of the barrier layer 40 can be a nitrogen oxide. In this embodiment, the oxidation process can specifically be a rapid thermal oxidation process.

[0050] Step S132: A charge trapping layer is formed on the inner surface of the barrier layer so that the charge trapping layer fills the groove and is isolated by the insulating layer in the longitudinal direction.

[0051] The schematic diagram of the half-section structure after step S132 is shown below. Figure 2F As shown.

[0052] Step S132 may specifically include the following steps:

[0053] First, such as Figure 2E As shown, on the inner surface of the barrier layer 400 ( Figure 2D As shown in the figure, charge trapping material 50' is deposited on the groove 31 to fill the groove 31. Figure 2D (shown in the diagram) and channel hole 30; then, excess charge trapping material 50' outside the groove 31 is removed to form as shown in the diagram. Figure 2F The charge trapping layer 50 shown is aligned longitudinally with the second interface 302.

[0054] Specifically, charge-trapping material 50' can be deposited on the inner surface 400 of the barrier layer 40 using CVD or PVD processes. The charge-trapping material 50' can be selected as silicon nitride. The excess charge-trapping material 50' outside the groove 31 can be removed by first oxidizing this portion of the charge-trapping material 50', and then etching it with acid. Controlling the etching time allows for precise control of the etching position. Etching stops when the charge-trapping material 50' is aligned with the second interface 302 along the z-direction, thus forming a charge-trapping layer 50 isolated in the z-direction by the insulating layer 22. This reduces charge migration in the z-direction of the three-dimensional memory device, improving its charge retention performance.

[0055] Step S133: A continuous tunneling layer and a channel layer that penetrate the channel hole are sequentially formed on the second interface where the channel hole and the insulating layer intersect and on the inner surface of the charge trapping layer.

[0056] The schematic diagram of the half-section structure after step S133 is shown in Figure 2G

[0057] Specifically, as shown in Figures 2F to 2G , the tunneling layer 60 and the channel layer 70 are sequentially formed on the second interface 302 and the inner surface 500 of the charge trapping layer 50, and the tunneling layer 60 and the channel layer 70 extend along the z direction and pass through the channel hole 30, so that the tunneling layer 60 and the channel layer 70 are continuously distributed in the z direction and the direction of the xy plane. The material of the tunneling layer 60 is an oxide material, such as silicon oxide. The material of the channel layer 70 is a polysilicon material. In this embodiment, the tunneling layer 60 and the channel layer 70 can be sequentially formed by CVD or ALD process.

[0058] Step S134: etching part of the channel layer and part of the tunneling layer located at the recessed part to separate the channel layer and the tunneling layer into multiple sub-channel layers and multiple sub-tunneling layers in the direction around the central axis.

[0059] Specifically, as shown in Figure 2H , a sacrificial material 80 is first deposited on the inner surface 700 of the channel layer 70; then, as shown in Figure 2I , part of the sacrificial material (not shown in the figure) located at the recessed part B is removed to expose the inner surface of part of the channel layer 70B located at the recessed part.

[0060] Specifically, the sacrificial material 80 can be deposited on the inner surface 700 of the channel layer 70 by ALD or CVD process, and the sacrificial material can be selected as a nitride such as silicon nitride. It should be noted that, in this embodiment, the channel hole 30 has alternating recessed parts B and protruding parts A, so that when the sacrificial material 80 is deposited, the sacrificial material 80 on the top surface of the insulating layer 22 will sink into the channel hole 30, resulting in that the thickness of the sacrificial material 80 distributed in the channel hole 30 is not uniform, and the specific characteristics can be referred to Figure 2H , the thickness of the sacrificial material 80 distributed at the recessed part B is thinner, and the thickness of the sacrificial material 80 distributed at the protruding part A is thicker.

[0061] It should be further noted that, in this embodiment, since the thickness of the sacrificial material 80 distributed at the recessed part B is thinner, and the thickness of the sacrificial material 80 distributed at the protruding part A is thicker, under the same process condition (etching time), when part of the sacrificial material distributed at the recessed part is etched and removed to expose the inner surface of part of the channel layer 70B located at the recessed part B, another part of the sacrificial material 80A at the protruding part A still remains, which serves to protect the first functional layer and the second functional layer at the protruding part A in the subsequent process flow.

[0062] ​After step S134, a schematic diagram of the half cross-section of the three-dimensional memory device is shown in Figure 2J

[0063] In the present embodiment, since the material of the channel layer 70 is polysilicon material, the material of the tunneling layer 60 is oxide material, and the material of the sacrificial layer 80 is nitride material, the partial channel layer 70B and the partial tunneling layer (not shown in the figure) located at the recessed portion B are etched by using a selective acidic solution in sequence, and the inner surface of the partial charge trapping layer 50B located at the recessed portion B is exposed as shown in Figure 2J

[0064] Step S135: etching the partial charge trapping layer located at the recessed portion to separate the charge trapping layer into multiple sub charge trapping layers in the direction around the central axis.

[0065] After step S135, a schematic diagram of the half cross-section is shown in Figure 2K

[0066] Step S135 can be implemented by etching and removing another partial sacrificial layer 80A located at the protruding portion A while etching the partial charge trapping layer 50B located at the recessed portion B.

[0067] Specifically, in the present embodiment, since the material of the sacrificial layer 80 is nitride material, and the material of the charge trapping layer is also nitride material, another partial sacrificial layer 80A can be etched and removed synchronously while etching the partial charge trapping layer 50B. As shown in Figure 2K

[0068] In the present embodiment, step S13 can be implemented directly after step S121, and at this time, step S13 includes the following steps:

[0069] Referring to Figure 2B and Figure 4A ​​​​, sequentially forming a continuous and penetrating barrier layer 40 and a charge trapping layer 50 on the inner wall 300 of the channel hole 30; then sequentially forming a continuous and penetrating tunnel layer 60 and a channel layer 70 on the inner surface of the charge trapping layer 50, which penetrates the channel hole 30; then, referring to Figure 4B , etching part of the channel layer and part of the tunnel layer at the recess B to separate the channel layer 70 and the tunnel layer 60 into multiple sub-channel layers 70A and multiple sub-tunnel layers 60A in the direction around the central axis OO'; finally, etching part of the charge trapping layer at the recess B to separate the charge trapping layer 50 into multiple sub-charge trapping layers 50A in the direction around the central axis OO'.

[0070] Specifically, based on the channel layer 70 and the tunnel layer 60 shown in Figure 4A , before the step of sequentially etching part of the channel layer and part of the tunnel layer at the recess B, the following steps are also included: depositing a sacrificial material on the inner surface of the channel layer 70; removing part of the sacrificial material at the recess B to expose part of the inner surface of the channel layer at the recess B. The above etching process can be analogously referred to Figures 2H-2I . And whether step S13 is followed by step S121 or step S122, after the step of etching part of the charge trapping layer at the recess B, part of the barrier layer at the recess B can be further etched to separate the barrier layer 40 into multiple sub-barrier layers 40A in the direction around the central axis OO' (for example, refer to Figure 4B ).

[0071] Step S14: Forming a medium layer filling the channel hole on the inner surface of the multiple sub-channel layers.

[0072] After step S14, the structure of the three-dimensional memory device is shown in Figure 2L .

[0073] Specifically, the medium layer 90 has an electrically insulating effect. Since the medium layer 90 fills the channel hole 30 at the same time, it also fills the void 31B. Therefore, after step S14, the adjacent multiple sub-charge trapping layers 50A are still separated in the xy plane direction.

[0074] In the manufacturing method of the three-dimensional memory device provided in the embodiment, the sacrificial layer 21 is replaced by a gate layer.

[0075] After replacement, the position of the gate layer is the same as that of the original sacrificial layer 21, and the material of the gate layer is metal, such as tungsten.

[0076] Please refer to Figure 2LThe application also provides a three-dimensional memory device 100, which can be formed by the manufacturing method described above, and thus the forming process of the three-dimensional memory device 100 can refer to Figures 2A-2L , wherein Figures 2A-2K The half-section structure diagram shown is a schematic diagram after being cut along the C-C' section.

[0077] As shown in Figure 2L , the three-dimensional memory device 100 includes a substrate 10, a stack structure 20 formed by alternately stacking insulating layers 22 and gate layers on the substrate 10, a channel hole 30 (shown in Figures 2B-2K ) penetrating through the stack structure 20 along a longitudinal direction (z direction) perpendicular to the substrate 10, a first functional layer on an inner wall 300 (shown in Figure 2B ) of the channel hole 30, and a second functional layer corresponding to the first functional layer. Figure 5A , Figure 5A is Figure 2L , a top view schematic diagram of the three-dimensional memory device in the channel hole), wherein the first functional layer includes a plurality of sub-charge trapping layers 50A (shown in Figure 2K ) spaced apart from each other along a direction around a central axis OO' of the channel hole 30, and the second functional layer includes a plurality of sub-channel layers 70A spaced apart from each other along a direction around the central axis OO'.

[0078] Specifically, please refer to Figures 3A-3C , the shape of the channel hole 30 can be various, Figures 3A-3C respectively are top view schematic diagrams of three kinds of channel holes, as shown in Figure 3A and 3B , the shape of the channel hole 30 in a plane (xy) direction parallel to the substrate 10 can be a four-leaf shape or a three-leaf shape. As shown in Figure 3C , it can also be a star shape. As shown in Figures 3A-3C , the channel hole 30 has a plurality of alternating convex portions A and concave portions B in the xy plane, and the plurality of alternating convex portions A and concave portions B are distributed around the central axis OO' of the channel hole 30. The planar shape of the channel hole 30 can be freely defined by designing the pattern of the mask plate, and then the corresponding specific structure is formed in the stack structure 20 by the photoetching and etching process. Please continue to refer to Figure 2B , the inner wall 300 of the channel hole includes a first interface 301 where the channel hole 30 and the gate layer (sacrificial layer 21) are staggered, and a second interface 302 where the channel hole 30 and the insulating layer 22 are staggered, and the first interface 301 and the second interface 302 are alternately connected.

[0079] , please refer to Figure 2C, the first interface 301 where the channel hole 30 intersects the gate layer is provided with a groove 31, so that the aperture of the channel hole 30 at the gate layer is larger than the aperture at the insulating layer 22. Please refer to Figure 5A , the first functional layer further comprises a barrier layer 40, please further refer to Figure 2D and Figure 2F , the barrier layer 40 is located on the surface of the groove 31, each sub-charge trapping layer 50A is located on the inner surface of the barrier layer 40 and fills the groove 31, and the second interface 302 where the channel hole 30 intersects the insulating layer 22 is flush with the inner surface of each sub-charge trapping layer 50A in the z direction. The second functional layer is located at the protruding portion A, and the second functional layer further comprises a plurality of sub-tunneling layers 60A spaced apart from each other in a direction around the central axis OO'. Each sub-tunneling layer 60A and each sub-channel layer 70A penetrate the channel hole 30 and are sequentially stacked on the inner surface of each sub-charge trapping layer 50A and the second interface 302.

[0080] Please refer to Figure 5B , the embodiment of the present application provides another top view schematic diagram of a three-dimensional memory device at a channel hole, compared with the three-dimensional memory device 100 in Figure 5A , the difference lies in that the barrier layer 40 is also separated at the recessed portion B, so that the first functional layer comprises a plurality of sub-barrier layers 40A spaced apart from each other in a direction around the central axis OO' of the channel hole 30.

[0081] Please refer to Figure 5C , the embodiment of the present application provides another top view schematic diagram of a three-dimensional memory device at a channel hole, compared with the three-dimensional memory device 100 in Figure 5A , the difference lies in that Figure 5C , the three-dimensional memory device 100 in does not provide the groove 31, so that the barrier layer 40 and the sub-charge trapping layer 50A are sequentially stacked on the inner surface 300 of the channel hole 30.

[0082] Please refer to Figure 5D , the embodiment of the present application further provides another top view schematic diagram of a three-dimensional memory device at a channel hole, as shown in Figure 5D , the first functional layer and the second functional layer are both located at the protruding portion A. The first functional layer further comprises a plurality of sub-barrier layers 40A spaced apart from each other in a direction around the central axis OO', each sub-barrier layer 40A and each sub-charge trapping layer 50A penetrate the channel hole 30 and are sequentially stacked on the inner surface 300 of the channel hole 30. The second functional layer further comprises a plurality of sub-tunneling layers 60A spaced apart from each other in a direction around the central axis OO', each sub-tunneling layer 60A and each sub-channel layer 70A penetrate the channel hole 30, and each sub-tunneling layer 60A and each sub-channel layer 70A are sequentially stacked on the inner surface of each sub-charge trapping layer 50A. In addition, based on the change of the shape of the channel hole 30, the three-dimensional memory device 100 can also present as shown inFigure 5E and Figure 5F the shape shown.

[0083] The three-dimensional memory device and the manufacturing method thereof provided by the present application can form multiple sub-charge trapping layers and multiple sub-channel layers which are spaced apart in the direction around the central axis of the channel hole. Since the multiple sub-channel layers which are spaced apart can form multiple storage strings, one sub-channel layer is located in one storage string, the storage density can be improved without increasing the number of stacked layers. Meanwhile, the multiple sub-charge trapping layers which are spaced apart can avoid the crosstalk phenomenon between adjacent storage strings, so that the reliability of the three-dimensional memory device is improved.

[0084] In addition to the above-mentioned embodiments, the present application can have other implementation manners. Any technical solution formed by equivalent replacement or equivalent substitution falls within the protection scope required by the present application.

[0085] To sum up, although the preferred embodiments of the present application have been disclosed above, the above-mentioned preferred embodiments are not used to limit the present application. Any modification and decoration made by those skilled in the art without departing from the spirit and scope of the present application is also included in the protection scope of the present application.

Claims

1. A method for manufacturing a three-dimensional storage device, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure comprising alternating layers of sacrificial layers and insulating layers; A channel hole is formed through the stacked structure along a longitudinal direction perpendicular to the substrate, and the channel hole has a plurality of alternating protrusions and recesses in a plane direction parallel to the substrate; The sacrificial layer is etched through the channel hole to form a groove at the first interface where the channel hole and the sacrificial layer intersect, and the diameter of the channel hole at the sacrificial layer is larger than the diameter at the insulating layer. A first functional layer is formed in the groove and a second functional layer is formed on the inner wall of the channel hole, covering the first functional layer; Deposit sacrificial material on the surface of the second functional layer; Remove a portion of the sacrificial material located in the recess to expose the surface of a portion of the second functional layer located in the recess; Etch a portion of the second functional layer located in the recess to form a plurality of sub-channel layers spaced apart from each other in a direction surrounding the central axis of the channel hole; A portion of the first functional layer located in the recess is etched to form a plurality of sub-charge trapping layers spaced apart from each other in a direction surrounding the central axis of the channel hole; A dielectric layer is formed on the inner surface of the plurality of sub-channel layers so that the channel holes are filled by the dielectric layer.

2. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The step of forming a channel hole through the stacked structure along a longitudinal direction perpendicular to the substrate includes: The stacked structure is etched along a longitudinal direction perpendicular to the substrate using a photomask to form a channel hole with multiple alternating protrusions and recesses in a plane direction parallel to the substrate. The multiple alternating protrusions and recesses are distributed around the central axis of the channel hole.

3. The method for manufacturing a three-dimensional storage device according to claim 2, characterized in that, The step of forming a first functional layer on the inner wall of the channel hole and a corresponding second functional layer covering the first functional layer includes: A continuous barrier layer and a charge trapping layer are sequentially formed on the inner wall of the channel hole and penetrate the channel hole; A continuous tunneling layer and a channel layer that penetrate the channel hole are sequentially formed on the inner surface of the charge trapping layer. A portion of the trench layer and a portion of the tunneling layer located in the recess are sequentially etched to divide the trench layer and the tunneling layer into a plurality of sub-trench layers and a plurality of sub-tunneling layers in a direction surrounding the central axis. The portion of the charge trapping layer located in the recess is etched to divide the charge trapping layer into a plurality of sub-charge trapping layers in a direction surrounding the central axis.

4. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, The step of forming a first functional layer and a plurality of second functional layers correspondingly covering the first functional layer on the inner wall of the channel hole includes: A barrier layer is formed on the surface of the groove; A charge trapping layer is formed on the inner surface of the barrier layer, such that the charge trapping layer fills the groove and is isolated by the insulating layer in the longitudinal direction; A continuous tunneling layer and a channel layer that penetrate the channel hole are sequentially formed on the second interface where the channel hole and the insulating layer intersect, and on the inner surface of the charge trapping layer. A portion of the trench layer and a portion of the tunneling layer located in the recess are sequentially etched to divide the trench layer and the tunneling layer into a plurality of sub-trench layers and a plurality of sub-tunneling layers in a direction surrounding the central axis. The portion of the charge trapping layer located in the recess is etched to divide the charge trapping layer into a plurality of sub-charge trapping layers in a direction surrounding the central axis.

5. The method for manufacturing a three-dimensional storage device according to claim 4, characterized in that, The step of forming a charge-trapping layer on the inner surface of the barrier layer, such that the charge-trapping layer fills the groove and is isolated by the insulating layer in the longitudinal direction, includes: A charge-capturing material is deposited on the inner surface of the barrier layer to fill the groove; Excess charge-capturing material outside the groove is removed to form a charge-capturing layer aligned with the second interface along the longitudinal direction.

6. The method for manufacturing a three-dimensional storage device according to claim 3 or 4, characterized in that, Prior to the step of sequentially etching a portion of the trench layer and a portion of the tunneling layer located in the recess, the method further includes: Sacrificial material is deposited on the inner surface of the channel layer; Remove a portion of the sacrificial material located in the recess to expose the inner surface of a portion of the channel layer located in the recess.

7. The method for manufacturing a three-dimensional storage device according to claim 3 or 4, characterized in that, After etching a portion of the charge trapping layer located in the recess, the method further includes etching a portion of the barrier layer located in the recess to divide the barrier layer into a plurality of sub-barrier layers in a direction surrounding the central axis.

8. The method for manufacturing a three-dimensional storage device according to claim 1, characterized in that, Also includes: The sacrificial layer is replaced with a gate layer.

9. A three-dimensional storage device, characterized in that, include: Substrate; A stacked structure consisting of alternating insulating layers and gate layers located on the substrate; A channel hole extends through the stacked structure along a longitudinal direction perpendicular to the substrate. The channel hole has a groove at a first interface where it intersects with the gate layer, and the diameter of the channel hole at the gate layer is larger than the diameter at the insulating layer. A first functional layer located within the groove and a second functional layer located on the inner wall of the channel hole, covering the first functional layer, wherein the first functional layer includes a plurality of sub-charge trapping layers spaced apart from each other along a direction surrounding the central axis of the channel hole, and the second functional layer includes a plurality of sub-channel layers spaced apart from each other along a direction surrounding the central axis. A dielectric layer located on the inner surface of the plurality of sub-channel layers and filling the channel holes.

10. The three-dimensional storage device according to claim 9, characterized in that, The channel hole is formed in a plane direction parallel to the substrate, having a plurality of alternating protrusions and recesses, the plurality of alternating protrusions and recesses being distributed around the central axis.

11. The three-dimensional storage device according to claim 10, characterized in that, The first functional layer further includes a barrier layer located on the surface of the groove, each of the sub-charge trapping layers located on the inner surface of the barrier layer and filling the groove, and the second interface between the channel hole and the insulating layer being longitudinally flush with the inner surface of each of the sub-charge trapping layers; The second functional layer is located at the protrusion. The second functional layer also includes a plurality of sub-tunneling layers spaced apart from each other along a direction surrounding the central axis. Each of the sub-tunneling layers and each of the sub-channel layers penetrates the channel hole and is sequentially stacked on the inner surface of the second interface and each of the sub-charge trapping layers.

12. The three-dimensional storage device according to claim 10, characterized in that, Both the first functional layer and the second functional layer are located at the protrusion; The first functional layer further includes a plurality of sub-blocking layers spaced apart from each other along a direction surrounding the central axis, each of the sub-blocking layers and each of the sub-charge trapping layers penetrating the channel hole and being sequentially stacked and covering the inner surface of the channel hole; The second functional layer further includes a plurality of sub-tunneling layers spaced apart from each other along a direction surrounding the central axis, each sub-tunneling layer and each sub-channeling layer penetrating the channel hole, and each sub-tunneling layer and each sub-channeling layer being sequentially stacked and covering the inner surface of each sub-charge trapping layer.

13. The three-dimensional storage device according to claim 9, characterized in that, The shape of the channel aperture in the plane direction parallel to the substrate includes at least one of the following: trilobal, tetralobal, and star-shaped.

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