semiconductor devices

Abstract

The present invention provides a highly reliable semiconductor device that increases the high-temperature, high-humidity bias voltage of a chip's terminal structure (terminal region) through a relatively simple method, while suppressing the effects on device characteristics. The device comprises an active region disposed on a main surface of a semiconductor substrate and a terminal region disposed on the main surface so as to surround the active region. The terminal region comprises an interlayer insulating film formed on the main surface of the semiconductor substrate and an organic protective film formed so as to cover the interlayer insulating film. A nitrogen-containing insulating film having a thickness of 100 nm or less is disposed between the interlayer insulating film and the organic protective film.

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technology that is effective and applicable to the terminal structure of a power semiconductor chip. Background Art

[0002] One of the causes of voltage degradation in power semiconductor chips is electric field concentration at the chip terminals. When a junction is formed on the surface of a power semiconductor chip, the depletion layer at the terminal expands in a fan-shaped pattern when a reverse bias is applied. The electric field lines of force from the charge in the fan-shaped region converge at the chip terminals, causing so-called electric field concentration. This results in avalanche breakdown (insulation breakdown) at voltages significantly lower than the theoretical withstand voltage.

[0003] To mitigate the electric field concentration at the chip terminal, it is necessary to disperse the electric field lines of the charge from the fan-shaped depletion layer region away from the chip terminal to the entire terminal structure (hereinafter referred to as the terminal region) when a reverse bias is applied. Various methods have been proposed for this, including a junction termination extension (JTE) structure in which a low-concentration region with the same polarity as the surface side of the junction is formed on the semiconductor surface adjacent to the junction terminal, and a guard ring structure in which multiple rings are formed along the junction terminal with the same polarity as the surface side of the junction.

[0004] As background technology in this technical field, there is a technique such as Patent Document 1. Patent Document 1 describes a technique in which, in order to prevent degradation of device characteristics such as reduced withstand voltage and increased leakage current due to moisture, a plasma TEOS oxide film is formed on a semiconductor substrate having an interlayer insulating film, a source electrode, and a drain electrode. The plasma TEOS oxide film is then etched so that a step portion at the bottom of the film remains in a gap-like pattern. Furthermore, a plasma nitride film is formed on the plasma TEOS oxide film as a passivation film. Paragraph 0016 of Patent Document 1 describes forming the plasma nitride film 13 to a thickness of 1 μm.

[0005] Furthermore, Patent Document 2 describes a technique for forming two films of different film qualities using plasma CVD: a lower silicon nitride film with a higher refractive index and an upper silicon nitride film with a relatively lower refractive index, in order to prevent corrosion of aluminum wiring caused by moisture in the molding resin and a reduction in the life of the semiconductor device due to increased leakage current. Furthermore, paragraph 0013 of Patent Document 2 describes forming the first silicon nitride film 15 to a thickness of 1 μm, and paragraph 0015 describes forming the second silicon nitride film 16 to a thickness of 1 μm.

[0006] In addition, it is described in Patent Document 3 (Patent Document 3 Figure 4Patent Document 3, paragraphs 0066-0068, etc., discloses that a stacked structure comprising, from the bottom up, an oxide film 42, a resistive silicon nitride film 44 with a refractive index of 2.9 to 3.3, an interlayer insulating film 46, an insulating silicon nitride film 47 with a refractive index of 1.8 to 2.2, and a polyimide film 48 is formed in the end region 120 to improve crack resistance. Furthermore, paragraph 0039 of Patent Document 3 describes the resistive silicon nitride film 44 as having a thickness of 0.5 μm to 0.8 μm, and paragraph 0066 describes the insulating silicon nitride film 47 as having a thickness of approximately 1.2 μm.

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2001-345319

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2001-352056

[0009] Patent Document 3: Japanese Patent Application Laid-Open No. 2017-92360 Summary of the Invention

[0010] As mentioned above, in order to improve the reliability of power semiconductor chips and further increase their withstand voltage, improving the insulation resistance of the terminal structure (terminal region) of power semiconductor chips has become an important issue. Therefore, as one of the reliability tests for power semiconductor chips, it is required to improve the high-temperature and high-humidity bias resistance used to evaluate the durability when used in high-temperature and high-humidity environments.

[0011] In Patent Document 1, a 1μm-thick plasma nitride film is formed as a passivation film to prevent moisture intrusion and prevent degradation of device characteristics such as reduced withstand voltage and increased leakage current. However, plasma nitride films generally have high internal stress, which may affect device characteristics, such as fluctuations in electron mobility.

[0012] Furthermore, in Patent Document 2, two silicon nitride films having different film qualities are formed, and the total film thickness of the silicon nitride films becomes thicker than 2 μm. Therefore, internal stress of the film still becomes a problem.

[0013] Furthermore, in Patent Document 3, a resistive silicon nitride film and an insulating silicon nitride film having different refractive indices are formed. Similar to Patent Document 2, the total film thickness of the silicon nitride film increases from 1.7 μm to 2.0 μm, which may affect device characteristics.

[0014] Therefore, an object of the present invention is to provide a highly reliable semiconductor device that can improve the high-temperature and high-humidity bias resistance of a terminal structure (terminal region) of a chip by a relatively simple method and suppress the influence on device characteristics.

[0015] In order to solve the above-mentioned problem, the present invention is characterized in that it has an active area arranged on the main surface of a semiconductor substrate and a terminal area arranged on the main surface in a manner surrounding the active area, the terminal area has an interlayer insulating film formed on the main surface of the semiconductor substrate and an organic protective film formed in a manner covering the interlayer insulating film, and an insulating film containing nitrogen with a film thickness of less than 100 nm is provided between the interlayer insulating film and the organic protective film.

[0016] According to the present invention, a highly reliable semiconductor device can be realized by a relatively simple method, which improves the high-temperature and high-humidity bias resistance of the terminal structure (terminal region) of a chip and suppresses the influence on device characteristics.

[0017] Other problems, structures, and effects than those described above will become clear from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a plan view showing the appearance of the IGBT chip according to the first embodiment of the present invention.

[0019] Figure 2 yes Figure 1 A-A' cross-sectional view.

[0020] Figure 3A This is a diagram showing the results of a high-temperature and high-humidity bias test on the IGBT chip according to Example 1 of the present invention.

[0021] Figure 3B This is a graph showing the results of a high-temperature and high-humidity bias test of a conventional IGBT chip.

[0022] Figure 4 This is a partial cross-sectional view of an IGBT chip according to a second embodiment of the present invention.

[0023] Figure 5 This is a partial cross-sectional view of an IGBT chip according to a third embodiment of the present invention.

[0024] Figure 6 This is a partial cross-sectional view of an IGBT chip according to a fourth embodiment of the present invention.

[0025] Figure 7A 1 is a cross-sectional view showing a manufacturing process of the IGBT chip according to the first embodiment of the present invention.

[0026] Figure 7B Yes Figure 7A Cross-sectional view of the subsequent manufacturing process.

[0027] Figure 7C Yes Figure 7B Cross-sectional view of the subsequent manufacturing process.

[0028] Figure 7D Yes Figure 7C Cross-sectional view of the subsequent manufacturing process.

[0029] Figure 7E Yes Figure 7D Cross-sectional view of the subsequent manufacturing process.

[0030] Figure 8A It is a cross-sectional view showing the manufacturing process of the IGBT chip according to the second embodiment of the present invention.

[0031] Figure 8B Yes Figure 8A Cross-sectional view of the subsequent manufacturing process.

[0032] Figure 8C Yes Figure 8B Cross-sectional view of the subsequent manufacturing process. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and detailed descriptions of the overlapping components are omitted.

[0034] [Example 1]

[0035] Reference Figures 1 to 3B as well as 7A to 7E , a semiconductor device and a method for manufacturing the same according to embodiment 1 of the present invention are described. Figure 1 1 is a plan view showing the appearance of the semiconductor device of the present embodiment, and shows an IGBT chip (Insulated Gate Bipolar Transistor) as an example. Figure 2 yes Figure 1 A-A' cross-sectional view. Figure 3A : is a voltage-current characteristic diagram showing an example of the effect of the present invention. Figure 3B 1 is a graph showing voltage-current characteristics of a conventional semiconductor device as a comparative example. 7A to 7E 1 and 2 are cross-sectional views showing main manufacturing steps in the method for manufacturing a semiconductor device according to this embodiment.

[0036] In the following description, an IGBT chip is used as an example of a semiconductor device. However, the present invention is not limited thereto and can also be applied to diodes, thyristors, power MOSFETs, DMOSFETs (Double-Diffused MOSFETs), and the like.

[0037] like Figure 1As shown, the IGBT chip 1 of this embodiment includes an active region 5 disposed on the main surface of a semiconductor substrate and a termination region 4 disposed so as to surround the active region 5. An emitter electrode 2 and a gate electrode 3 are formed on the active region 5. The termination region 4 is a termination structure, i.e., an electric field mitigation region, that mitigates electric field concentration at the chip termination portion of the IGBT chip 1.

[0038] For example, Figure 2 As shown, the terminal region 4 has a - A plurality of guard rings 7 are provided on the main surface of a semiconductor substrate 6 of the type, an interlayer insulating film 8 is formed on the main surface of the semiconductor substrate 6, a field plate electrode 9 is formed on the interlayer insulating film 8 and passes through an opening formed in the interlayer insulating film 8 and is connected to the guard rings 7, and an organic protective film 10 is formed in a manner covering the interlayer insulating film 8 and the field plate electrode 9.

[0039] Furthermore, a nitrogen-containing insulating film 11 having a thickness of 100 nm or less (preferably 50 nm or less) is provided between the interlayer insulating film 8 and the organic protective film 10. The lower limit of the thickness of the nitrogen-containing insulating film 11 is 10 nm or more (preferably 20 nm or more). The significance of these upper and lower limits of the thickness will be described later.

[0040] Here, as n - The semiconductor substrate 6 is described assuming a Si substrate, but a SiC substrate, GaN substrate, or the like may also be used. The guard ring 7 is a p-type diffusion layer formed on the surface of the semiconductor substrate 6 by ion implantation. The interlayer insulating film 8 is composed of a gate oxide film formed by thermal oxidation (pyrogenic oxidation) or the like, described later, and an interlayer film such as a TEOS film (tetraethoxysilane) or BPSG film (boron-phospho silicate glass), all of which are silicon oxide films (SiO2).

[0041] Field plate electrode 9 is a laminated film of, for example, Ti / TiN / Al or MoSi / Al, and is formed in the same layer as emitter electrode 2 and pad electrode 14 of active region 5. Organic protective film 10 is, for example, a polyimide film.

[0042] As the insulating film 11 containing nitrogen, for example, a silicon nitride film (Si 3 N 4 ), a silicon oxynitride film (SiON), or the like is used.

[0043] On the back surface of the semiconductor substrate 6, n - type diffusion layer 15 , p-type diffusion layer 16 , and collector electrode 17 .

[0044] In the active region 5, when a voltage is applied between the gate electrode 3 and the emitter electrode 2, an n-channel inversion layer forms directly beneath the gate oxide film, turning the MOSFET on. Furthermore, when a voltage is applied between the collector electrode 17 and the emitter electrode 2, an avalanche of holes occurs from the collector electrode 17 to the emitter electrode 2, causing current to flow between the collector electrode 17 and the emitter electrode 2, turning the IGBT on. When the voltage between the gate electrode 3 and the emitter electrode 2 is returned to 0 (zero), the inversion layer disappears, the n-channel of the MOSFET is cut off, and the IGBT is turned off (off).

[0045] The IGBT chip 1 of this embodiment is constructed as described above. In addition to the organic protective film 10, in the terminal region 4, an insulating film 11 containing nitrogen with a film thickness of not less than 10 nm (preferably not less than 20 nm) and not more than 100 nm (preferably not more than 50 nm) is provided between the interlayer insulating film 8 and the organic protective film 10. This can more reliably prevent moisture from penetrating from the surface side of the IGBT chip 1 and can improve the high-temperature and high-humidity bias resistance.

[0046] Insulating films containing nitrogen, such as silicon nitride film (Si3N4) and silicon oxynitride film (SiON), generally have a dense structure and excellent moisture barrier and insulation properties. On the other hand, due to high internal stress, they may affect the device characteristics of the IGBT chip 1, such as changes in electron mobility.

[0047] Therefore, in this embodiment, the upper limit of the thickness of the nitrogen-containing insulating film 11 is set to 100 nm or less (preferably 50 nm or less) to prevent any impact on the device characteristics of the IGBT chip 1. On the other hand, by setting the lower limit of the film thickness to 10 nm or more (preferably 20 nm or more), moisture resistance is ensured and a process margin (allowance for ensuring a certain film quality) is obtained when forming the nitrogen-containing insulating film 11 using plasma CVD or reactive sputtering.

[0048] exist Figure 3A and Figure 3B 2 shows the results of the high temperature and high humidity bias test of the IGBT chip. Figure 3A is the test result of the IGBT chip of this embodiment, Figure 3BThis is the test result of the previous IGBT chip.

[0049] The test conditions for the high-temperature and high-humidity bias test were 85°C, 85% humidity, and Vcc = 80 V. The test samples used a 10 μm-thick polyimide film for the organic protective film 10 and a 30 nm-thick silicon oxynitride film (SiON) for the nitrogen-containing insulating film 11 .

[0050] like Figure 3B As shown in FIG. 1 , in a conventional IGBT chip in which the nitrogen-containing insulating film 11 is not provided between the interlayer insulating film 8 and the organic protective film 10, the voltage-current characteristics change at 168 hours (h). Figure 3A As shown, in the IGBT chip of this embodiment, the voltage-current characteristics do not change even after 1000 hours (h), and the withstand voltage is maintained.

[0051] use 7A to 7E The manufacturing method of the semiconductor device of the present embodiment described above will be described. In each figure, a cross section of the manufacturing process of the termination region 4 is mainly shown.

[0052] First, if Figure 7A As shown in FIG, dry oxidation using dry oxygen (O2) and selective oxidation using wet oxidation (thermal oxidation) using water vapor generated by the combustion reaction of oxygen (O2) and hydrogen (H2) are performed. - A gate oxide film (SiO2) 19 is formed on the main surface of the semiconductor substrate 6. Then, a polysilicon film (Poly-Si) 20 is formed on the gate oxide film 19 by a low-pressure CVD device, and a gate electrode ( Figure 2 Next, p-type impurities such as boron (B) are implanted into the main surface of the semiconductor substrate 6 by ion implantation to form a p-type diffusion layer 18. This p-type diffusion layer 18 serves as a guard ring ( Figure 2 The symbol 7) performs its function.

[0053] Then, if Figure 7B As shown, an interlayer film (SiO2) 21 such as a TEOS film or a BPSG film is formed on the main surface of the semiconductor substrate 6 by a plasma CVD device, an atmospheric pressure CVD device, or the like so as to cover the gate oxide film 19 and the gate electrode 13 (20). Then, by patterning and etching using photolithography, an opening (contact hole) 23 is formed in the interlayer film 21 that penetrates the p-type diffusion layer 18. At this time, an opening (contact hole) 23 is also formed on the gate electrode 13 (20).

[0054] Then, if Figure 7CAs shown, the interlayer film 21 is covered by a plasma CVD device, a sputtering device, etc., and an electrode film 22 composed of, for example, Ti / TiN / Al, MoSi / Al, etc. is formed on the main surface of the semiconductor substrate 6 so as to fill the opening (contact hole) 23 formed in the interlayer film 21. Then, the field plate electrode ( Figure 2 symbol 9).

[0055] Then, if Figure 7D As shown, an insulating film 11 containing nitrogen, such as a silicon nitride film (Si3N4) or a silicon oxynitride film (SiON), is formed on the main surface of the semiconductor substrate 6 by a plasma CVD device, a reactive sputtering device, etc., so as to cover the interlayer film 21 and the field plate electrode 9 (22).

[0056] Finally, if Figure 7E As shown, an organic protective film (polyimide film) 10 is applied on the main surface of the semiconductor substrate 6 by a coating device so as to cover the insulating film 11 containing nitrogen. Then, the pad electrode ( Figure 2 14) on the organic protective film 10 and the insulating film 11 containing nitrogen.

[0057] After the above manufacturing process, the Figure 2 The terminal structure shown.

[0058] As described above, according to the semiconductor device of this embodiment, in the termination region 4, the insulating film 11 containing nitrogen is provided between the interlayer insulating film 8 and the organic protective film 10, thereby reliably preventing moisture from penetrating from the surface side of the IGBT chip 1 and improving the high-temperature and high-humidity bias resistance.

[0059] Furthermore, by setting the thickness of the insulating film 11 containing nitrogen to 100 nm or less (preferably 50 nm or less), the internal stress of the insulating film 11 containing nitrogen can be suppressed to be as low as possible, thereby suppressing the influence on device characteristics.

[0060] On the other hand, by setting the thickness of the nitrogen-containing insulating film 11 to be greater than 10 nm (preferably greater than 20 nm), moisture intrusion can be reliably prevented, and a process margin (for ensuring a certain film quality margin) can be obtained when forming the nitrogen-containing insulating film 11.

[0061] The present invention is particularly effective for high-voltage products that often have a structure such as the one described above in which guard rings 7 and field plate electrodes 9 are provided in the terminal region 4. However, the present invention is not necessarily limited to this structure. It can also be applied to semiconductor chips using other terminal structures that do not use guard rings 7 and field plate electrodes 9, as well as to products with relatively low voltage resistance.

[0062] [Example 2]

[0063] Reference Figure 4 and Figures 8A to 8C , a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention are described. Figure 4 is a partial cross-sectional view of the semiconductor device of this embodiment, which is a partial cross-sectional view of the semiconductor device of embodiment 1 ( Figure 2 ) is a variation of . Figures 8A to 8C 1 and 2 are cross-sectional views showing main manufacturing steps in the method for manufacturing a semiconductor device according to this embodiment.

[0064] In Example 1, Figure 7C and Figure 7D As shown, after the electrode film 22 is formed, the insulating film 11 containing nitrogen is formed. In this embodiment, Figure 8A and Figure 8B As shown in FIG. 1 , the electrode film 22 is formed after the insulating film 11 containing nitrogen is formed, which is different from the first embodiment.

[0065] like Figure 4 As shown, by exchanging the film formation order of the electrode film 22 and the insulating film 11 containing nitrogen, the insulating film 11 containing nitrogen is not set on the upper surface of the field plate electrode 9, but the insulating film 11 containing nitrogen is also set below the field plate electrode 9, that is, between the interlayer insulating film 8 and the field plate electrode 9.

[0066] use Figures 8A to 8C , the manufacturing method of the semiconductor device of the above embodiment is described. In addition, the process of forming the gate electrode 13 (20) is the same as that of the embodiment 1. Figure 7A The same, so the description is omitted.

[0067] In through Figure 7A After forming the gate electrode 13 (20) in the same manner, Figure 8A As shown, an interlayer film 21 such as a TEOS film or a BPSG film is formed on the main surface of the semiconductor substrate 6 by a plasma CVD device, an atmospheric pressure CVD device, or the like so as to cover the gate oxide film 19 and the gate electrode 13 (20). Subsequently, an insulating film 11 containing nitrogen such as a silicon nitride film (Si3N4) or a silicon oxynitride film (SiON) is formed on the main surface of the semiconductor substrate 6 by a plasma CVD device, a reactive sputtering device, or the like so as to cover the interlayer film 21. Next, an opening (contact hole) 23 penetrating to the p-type diffusion layer 18 is formed in the insulating film 11 containing nitrogen and the interlayer film 21 by patterning and etching using photolithography. At this time, an opening (contact hole) 23 is also formed in the gate electrode 13 (20).

[0068] Then, if Figure 8BAs shown, the insulating film 11 containing nitrogen is covered by a plasma CVD device, a sputtering device, etc., and an electrode film 22 composed of, for example, Ti / TiN / Al, MoSi / Al, etc. is formed on the main surface of the semiconductor substrate 6 so as to fill the opening (contact hole) 23 formed in the insulating film 11 containing nitrogen and the interlayer film 12. Then, the field plate electrode ( Figure 4 symbol 9).

[0069] Finally, if Figure 8C As shown, an organic protective film (polyimide film) 10 is coated on the main surface of the semiconductor substrate 6 by a coating device so as to cover the insulating film 11 containing nitrogen and the field plate electrode ( Figure 4 Then, the pad electrode ( Figure 4 The organic protective film 10 on the symbol 14).

[0070] In this embodiment, as in the first embodiment, the upper and lower limits of the thickness of the insulating film 11 containing nitrogen are defined, thereby achieving the same effects as those of the first embodiment.

[0071] [Example 3]

[0072] Reference Figure 5 , a semiconductor device according to a third embodiment of the present invention is described. Figure 5 is a partial cross-sectional view of the semiconductor device of this embodiment, which is a partial cross-sectional view of the semiconductor device of embodiment 1 ( Figure 2 ) is another variation of .

[0073] In Example 1, Figure 7D as well as Figure 7E As shown, the pad electrode ( Figure 5 The nitrogen-containing insulating film 11 on the symbol 14) is removed together with the organic protective film 10. In this embodiment, as shown in FIG. Figure 5 As shown, when the organic protective film 10 on the pad electrode is removed by etching, the insulating film 11 containing nitrogen is not etched away and remains on the pad electrode, which is different from the first embodiment.

[0074] The insulating film 11 containing nitrogen remains on the pad electrode 14 , so that the surface of the pad electrode 14 can be protected by the insulating film 11 containing nitrogen until a bonding wire is connected to the pad electrode 14 by wire bonding during the semiconductor device mounting process.

[0075] As described in Example 1, the thickness of the nitrogen-containing insulating film 11 is 100 nm or less (preferably 50 nm or less), so the nitrogen-containing insulating film 11 can be easily pierced by wire bonding, allowing the bonding wire to be connected to the pad electrode 14. As a result, the nitrogen-containing insulating film 11 remains on at least a portion of the surface of the pad electrode 14.

[0076] In this embodiment, the upper and lower limits of the thickness of the insulating film 11 containing nitrogen are specified in the same manner as in Example 1, thereby achieving the same effects as in Example 1. Furthermore, by protecting the surface of the pad electrode 14 with the insulating film 11 containing nitrogen until wire bonding, oxidation and corrosion of the surface of the pad electrode 14 can be prevented.

[0077] [Example 4]

[0078] Reference Figure 6 , a semiconductor device according to a fourth embodiment of the present invention is described. Figure 6 This is a partial cross-sectional view of the semiconductor device of the present embodiment 1, which is an embodiment 1 ( Figure 2 ) is another variation of .

[0079] like Figure 6 As shown, the semiconductor device of this embodiment is different from the embodiment 1 in that an insulating film 11 containing nitrogen is provided above and below the field plate electrode 9. That is, the embodiment 1 ( Figure 2 ) and Example 2 ( Figure 4 ) composite structure.

[0080] The nitrogen-containing insulating film 11 is provided between the interlayer insulating film 8 and the field plate electrode 9 and the organic protection film 10 so as to cover the interlayer insulating film 8 and the field plate electrode 9 , and is also provided between the interlayer insulating film 8 and the field plate electrode 9 .

[0081] Furthermore, the total thickness of the nitrogen-containing insulating film 11 provided above and below the field plate electrode 9 is set to be the same as that of Example 1. Specifically, the nitrogen-containing insulating film 11 provided above and below the field plate electrode 9 is formed so that the upper limit of the total thickness is 100 nm or less (preferably 50 nm or less). Furthermore, the nitrogen-containing insulating film 11 provided above and below the field plate electrode 9 is formed so that the lower limit of the total thickness is 10 nm or more (preferably 20 nm or more).

[0082] As in this embodiment, an insulating film 11 containing nitrogen is provided on the upper and lower sides of the field plate electrode 9. As in the first and second embodiments, the influence of the internal stress of the insulating film 11 containing nitrogen on the device characteristics can be suppressed while reliably preventing moisture from penetrating from the surface side of the IGBT chip 1. This can further reduce the possibility of corrosion of the field plate electrode 9 due to moisture and improve the high-temperature and high-humidity bias resistance.

[0083] In addition, as Figure 6 A modified example can be set as Example 2 ( Figure 4 ) and Example 3 ( Figure 5 That is, in addition to providing the insulating film 11 containing nitrogen above and below the field plate electrode 9, it is also possible to Figure 5 ) as in the case of a conventional method, the surface of the pad electrode 14 is protected by the insulating film 11 containing nitrogen until the time of wire bonding.

[0084] Furthermore, the present invention is not limited to the described embodiments and includes various variations. For example, the described embodiments are described in detail to facilitate understanding of the present invention and are not necessarily limited to the entire structure described. Furthermore, a portion of the structure of one embodiment can be replaced with a structure of another embodiment, and a structure of another embodiment can be added to the structure of another embodiment. Furthermore, with respect to a portion of the structure of each embodiment, other structures can be added, deleted, or substituted.

[0085] Explanation of symbols

[0086] 1…IGBT chip

[0087] 2…Emitter electrode

[0088] 3…Gate electrode

[0089] 4…Terminal area

[0090] 5…Active area

[0091] 6…(n - Type) semiconductor substrate

[0092] 7…Guard ring (p-type diffusion layer)

[0093] 8…Interlayer insulating film (silicon oxide film)

[0094] 9…Field plate electrode

[0095] 10…Organic protective film (polyimide film)

[0096] 11…Insulating film containing nitrogen

[0097] 12…p-type diffusion layer

[0098] 13…Gate electrode

[0099] 14…pad electrode

[0100] 15…n - Type diffusion layer

[0101] 16…p-type diffusion layer

[0102] 17…Collector

[0103] 18…p-type diffusion layer

[0104] 19…Gate oxide film (SiO2)

[0105] 20…Polysilicon film (Poly-Si)

[0106] 21…Interlayer film (SiO2)

[0107] 22…Electrode film (Ti / TiN / Al)

[0108] 23 ... opening (contact hole).

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: an active region disposed on a main surface of a semiconductor substrate; and a termination region arranged on the main surface so as to surround the active region; The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate and an organic protective film formed so as to cover the interlayer insulating film. An insulating film containing nitrogen and having a thickness of 20 nm to 50 nm is provided between the interlayer insulating film and the organic protective film.

2. The semiconductor device according to claim 1, wherein The termination region includes a guard ring formed on the main surface of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein The termination region includes a field plate electrode formed on the interlayer insulating film and penetrating through an opening formed in the interlayer insulating film to be connected to the guard ring.

4. The semiconductor device according to claim 3, wherein The organic protection film is formed so as to cover the interlayer insulating film and the field plate electrode.

5. The semiconductor device according to claim 4, wherein The insulating film containing nitrogen is provided between the interlayer insulating film and the field plate electrode and the organic protection film so as to cover the interlayer insulating film and the field plate electrode.

6. The semiconductor device according to claim 4, wherein The insulating film containing nitrogen is also provided between the interlayer insulating film and the field plate electrode.

7. The semiconductor device according to claim 4, wherein The insulating film containing nitrogen is not provided on the upper surface of the field plate electrode.

8. The semiconductor device according to claim 4, wherein The active region has a pad electrode formed on the main surface of the semiconductor substrate. The insulating film containing nitrogen is provided on at least a portion of the surface of the pad electrode.

9. The semiconductor device according to claim 4, wherein The insulating film containing nitrogen is provided between the interlayer insulating film and the field plate electrode and the organic protection film so as to cover the interlayer insulating film and the field plate electrode, and is also provided between the interlayer insulating film and the field plate electrode.

10. The semiconductor device according to claim 1, wherein The insulating film containing nitrogen is a silicon nitride film or a silicon nitride oxide film.

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