Shift register unit and driving method thereof, gate driving circuit and display device

Abstract

A shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: a control circuit (10) connected to an input signal terminal (IN), a clock signal terminal (CLK) and an output control terminal (GP), configured to provide an output control signal to the output control terminal (GP) based on signals of the input signal terminal (IN) and the clock signal terminal (CLK); and an output circuit (20) connected to the output control terminal (GP), an output signal terminal (GO) and a threshold voltage control terminal (DG), configured to provide an output signal to the output signal terminal (GP) under the control of the potential of the output control terminal (GP), and to adjust the threshold voltage of at least one transistor among a plurality of transistors in the output circuit (20) under the control of the signal of the threshold voltage control terminal (DG).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] In a display device, the voltage that controls the brightness of a pixel changes over time due to leakage. In order to keep the pixel brightness fluctuation within a reasonable range, even for static images, the gate drive circuit needs to scan the pixel at a certain frequency to refresh the display data (voltage) provided to the pixel, which will result in higher power consumption. Usually, the purpose of reducing power consumption is achieved by reducing the refresh frequency. Conventional gate drive circuits can work normally at normal refresh frequencies (e.g., above 30 Hz), but will generate large noise in the scan signal output at ultra-low refresh frequencies (e.g., 1 Hz), affecting pixel display. Summary of the invention

[0003] According to one aspect of the present disclosure, there is provided a shift register unit, comprising:

[0004] a control circuit connected to the input signal terminal, the clock signal terminal and the output control terminal, and configured to provide an output control signal to the output control terminal based on signals at the input signal terminal and the clock signal terminal; and

[0005] An output circuit is connected to the output control terminal, the output signal terminal and the threshold voltage control terminal, and is configured to provide an output signal to the output signal terminal under the control of the potential of the output control terminal, and to adjust the threshold voltage of at least one transistor among the multiple transistors in the output circuit under the control of the signal of the threshold voltage control terminal.

[0006] In some embodiments, the output circuit comprises:

[0007] a charging subcircuit, connected to the power signal terminal, the output control terminal and the output signal terminal, and configured to provide the potential of the power signal terminal to the output signal terminal under the control of the potential of the output control terminal;

[0008] a discharge subcircuit connected to a discharge control node, a reference signal terminal and the output signal terminal, and configured to provide the potential of the reference signal terminal to the output signal terminal under the control of the potential of the discharge control node; and

[0009] a control subcircuit connected to the output control terminal and the discharge control node, and configured to control the potential of the discharge control node based on the potential of the output control terminal,

[0010] At least one of the charging subcircuit, the discharging subcircuit and the controlling subcircuit is also connected to the threshold voltage control terminal and is also configured to adjust the threshold voltage of at least one transistor contained therein under the control of a signal of the threshold voltage control terminal.

[0011] In some embodiments, the charging subcircuit includes a first transistor, a gate of the first transistor is connected to the output control terminal, a first electrode of the first transistor is connected to the power signal terminal, and a second electrode of the first transistor is connected to the output signal terminal.

[0012] In some embodiments, the threshold voltage control terminal includes a first threshold voltage control terminal, the first transistor is a dual-gate transistor having a first gate and a second gate, the first gate of the first transistor is connected to the output control terminal, and the second gate of the first transistor is connected to the first threshold voltage control terminal.

[0013] In some embodiments, the discharge subcircuit comprises:

[0014] a second transistor, wherein a gate of the second transistor is connected to the discharge control node, a first electrode of the second transistor is connected to the reference signal terminal, and a second electrode of the second transistor is connected to the output signal terminal; and

[0015] A first capacitor, wherein a first end of the first capacitor is connected to the discharge control node, and a second end of the first capacitor is connected to the output signal end.

[0016] In some embodiments, the threshold voltage control terminal includes a second threshold voltage control terminal, the second transistor is a dual-gate transistor having a first gate and a second gate, the first gate of the second transistor is connected to the discharge control node, and the second gate of the second transistor is connected to the second threshold voltage control terminal.

[0017] In some embodiments, the threshold voltage control terminal includes a first threshold voltage control terminal and a second threshold voltage control terminal, the first transistor and the second transistor are both double-gate transistors having a first gate and a second gate, wherein:

[0018] A first gate of the first transistor is connected to the output control terminal, and a second gate of the first transistor is connected to the first threshold voltage control terminal;

[0019] A first gate of the second transistor is connected to the discharge control node, and a second gate of the second transistor is connected to the second threshold voltage control terminal.

[0020] In some embodiments, the control subcircuit comprises:

[0021] a third transistor, wherein a gate of the third transistor is connected to the output control terminal, a first electrode of the third transistor is connected to the power signal terminal, and a second electrode of the third transistor is connected to the discharge control node;

[0022] a fourth transistor, wherein a gate of the fourth transistor is connected to the first clock signal terminal, a first electrode of the fourth transistor is connected to the reference signal terminal, and a second electrode of the fourth transistor is connected to the discharge control node; and

[0023] A second capacitor, wherein a first terminal of the second capacitor is connected to the second clock signal terminal, and a second terminal of the second capacitor is connected to the discharge control node.

[0024] In some embodiments, the threshold voltage control terminal includes a first threshold voltage control terminal, the third transistor is a dual-gate transistor having a first gate and a second gate, the first gate of the third transistor is connected to the output control terminal, and the second gate of the third transistor is connected to the first threshold voltage control terminal.

[0025] In some embodiments, the threshold voltage control terminal includes a second threshold voltage control terminal, the fourth transistor is a dual-gate transistor having a first gate and a second gate, the first gate of the fourth transistor is connected to the first clock signal terminal, and the second gate of the fourth transistor is connected to the second threshold voltage control terminal.

[0026] In some embodiments, the threshold voltage control terminal includes a first threshold voltage control terminal and a second threshold voltage control terminal, and the third transistor and the fourth transistor are both double-gate transistors having a first gate and a second gate, wherein:

[0027] A first gate of the third transistor is connected to the output control terminal, and a second gate of the third transistor is connected to the first threshold voltage control terminal;

[0028] A first gate of the fourth transistor is connected to the first clock signal terminal, and a second gate of the fourth transistor is connected to the second threshold voltage control terminal.

[0029] In some embodiments, the control circuit comprises:

[0030] an input subcircuit connected to an input signal terminal, a reference signal terminal, a third clock signal terminal, a first control node, and a second control node, and configured to provide the potential of the input signal terminal to the first control node and the potential of the reference signal terminal to the second control node under the control of a signal of the third clock signal terminal;

[0031] an output subcircuit connected to the first control node, the second control node, the output control terminal, a fourth clock signal terminal and a power signal terminal, and configured to provide the potential of the fourth clock signal terminal to the output control terminal under the control of the potential of the first control node, and to provide the potential of the power signal terminal to the output control terminal under the control of the second control node; and

[0032] An adjustment subcircuit is connected to a third clock signal terminal, a fourth clock signal terminal, a power signal terminal, the first control node and the second control node, and is configured to provide the potential of the third clock signal terminal to the second control node under the control of the potential of the first control node, and to provide the potential of the power signal terminal to the first control node under the control of the potential of the fourth clock signal terminal and the second control node.

[0033] In some embodiments, the input subcircuit comprises:

[0034] a fifth transistor, wherein a gate of the fifth transistor is connected to the third clock signal terminal, a first electrode of the fifth transistor is connected to the input signal terminal, and a second electrode of the fifth transistor is connected to the first control node; and

[0035] A sixth transistor, wherein a gate of the sixth transistor is connected to the third clock signal terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the second control node.

[0036] In some embodiments, the output subcircuit comprises:

[0037] a seventh transistor, wherein a gate of the seventh transistor is connected to the reference signal terminal, and a first electrode of the seventh transistor is connected to the first control node;

[0038] an eighth transistor, wherein a gate of the eighth transistor is connected to a second electrode of the seventh transistor, a first electrode of the eighth transistor is connected to the fourth clock signal terminal, and a second electrode of the eighth transistor is connected to the output control terminal;

[0039] a ninth transistor, wherein a gate of the ninth transistor is connected to the second control node, a first electrode of the ninth transistor is connected to the power signal terminal, and a second electrode of the ninth transistor is connected to the output control terminal;

[0040] a third capacitor, wherein a first end of the third capacitor is connected to the gate electrode of the eighth transistor, and a second end of the third capacitor is connected to the second electrode of the eighth transistor; and

[0041] A fourth capacitor, wherein a first end of the fourth capacitor is connected to the gate of the ninth transistor, and a second end of the fourth capacitor is connected to the first electrode of the ninth transistor.

[0042] In some embodiments, the adjustment subcircuit includes:

[0043] a tenth transistor, wherein a gate of the tenth transistor is connected to the first control node, a first electrode of the tenth transistor is connected to the third clock signal terminal, and a second electrode of the tenth transistor is connected to the second control node;

[0044] an eleventh transistor, a gate of the eleventh transistor being connected to the second control node, and a first electrode of the eleventh transistor being connected to the power signal terminal; and

[0045] A twelfth transistor, wherein a gate of the twelfth transistor is connected to the fourth clock signal terminal, a first electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor, and a second electrode of the twelfth transistor is connected to the first control node.

[0046] According to another aspect of the present disclosure, a gate driving circuit is provided, comprising a plurality of cascaded shift register units, wherein threshold voltage control terminals of the plurality of shift register units are connected to receive threshold voltage control signals.

[0047] According to another aspect of the present disclosure, a display device is provided, comprising the above-mentioned gate driving circuit.

[0048] According to another aspect of the present disclosure, a driving method of the above-mentioned shift register unit is provided, comprising:

[0049] In a first period, the control circuit provides an output control signal to the output control terminal based on signals at the input signal terminal and the clock signal terminal, and the output circuit provides an output signal to the output signal terminal under the control of the potential of the output control terminal; and

[0050] In the second period, the control circuit provides an output control signal to the output control terminal based on the signals at the input signal terminal and the clock signal terminal. The output circuit maintains the level of the output signal at the output signal terminal under the control of the potential of the output control terminal, and adjusts the threshold voltage of at least one transistor among the multiple transistors in the output circuit under the control of the signal at the threshold voltage control terminal.

[0051] In some embodiments, the output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, the threshold voltage control terminal includes a first threshold voltage control terminal, at least one of the first transistor and the third transistor is a double-gate transistor having a first gate and a second gate connected to the first threshold voltage control terminal, and the adjusting the threshold voltage of at least one transistor among the plurality of transistors in the output circuit under the control of a signal of the threshold voltage control terminal includes:

[0052] A threshold voltage control signal of a first level is applied to the first threshold voltage control terminal, so that the threshold voltage of at least one of the first transistor and the third transistor is changed, thereby becoming an enhancement type transistor.

[0053] In some embodiments, the first level is higher than a level of a power signal at a power signal terminal connected to the first transistor and the third transistor.

[0054] In some embodiments, the output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, the threshold voltage control terminal includes a second threshold voltage control terminal, at least one of the second transistor and the fourth transistor is a dual-gate transistor having a first gate and a second gate connected to the second threshold voltage control terminal, and adjusting the threshold voltage of at least one transistor among the plurality of transistors in the output circuit under the control of a signal of the threshold voltage control terminal includes:

[0055] A threshold voltage control signal of a second level is applied to the second threshold voltage control terminal, so that the threshold voltage of at least one of the second transistor and the fourth transistor changes, thereby becoming a depletion-type transistor.

[0056] In some embodiments, the second level is lower than a level of a reference signal at a reference signal terminal connected to the second transistor and the fourth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A schematic block diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0058] Figure 2 A schematic block diagram of an output circuit in a shift register unit according to an embodiment of the present disclosure is shown.

[0059] Figure 3 A circuit diagram of an output circuit according to an embodiment of the present disclosure is shown.

[0060] Figure 4 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown.

[0061] Figure 5 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown.

[0062] Figure 6 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown.

[0063] Figure 7 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown.

[0064] Fig. 8A An equivalent circuit diagram of a dual-gate transistor used in an output circuit according to an embodiment of the present disclosure is shown.

[0065] Figure 8B Shows Fig. 8A Cross-sectional view of a dual-gate transistor

[0066] Fig. 9 A transfer curve diagram of a dual-gate transistor used in an output circuit according to an embodiment of the present disclosure is shown.

[0067] Fig.10 A circuit diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0068] Fig.11 A schematic diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0069] Fig.12 FIG. 4 shows an operation timing diagram of a shift register unit in a data update phase according to an embodiment of the present disclosure.

[0070] Fig.13 The operation timing diagram of the shift register unit in the data updating phase and the data holding phase according to the embodiment of the present disclosure is shown.

[0071] Fig.14 A flow chart of a driving method of a shift register unit according to an embodiment of the present disclosure is shown.

[0072] Fig.15 A schematic diagram of a display device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0074] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0075] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0076] The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. Preferably, the thin film transistors used in the embodiments of the present disclosure may be oxide semiconductor transistors. Since the source and drain of the thin film transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, one of the source and the drain is referred to as the first electrode, and the other of the source and the drain is referred to as the second electrode. In the following examples, a P-type thin film transistor is used as an example for description. Those skilled in the art can understand that the embodiments of the present disclosure can obviously be applied to the case of an N-type thin film transistor.

[0077] Figure 1 A schematic block diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0078] like Figure 1 As shown, the shift register unit includes a control circuit 10 and an output circuit 20 .

[0079] The control circuit 10 is connected to the input signal terminal IN, the clock signal terminal CLK and the output control terminal GP. The control circuit 10 can provide an output control signal to the output control terminal GP based on the signals of the input signal terminal IN and the clock signal terminal CLK.

[0080] The output circuit 20 is connected to the output control terminal GP, the output signal terminal GO and the threshold voltage control terminal DG. The output circuit 20 can provide an output signal to the output signal terminal GO under the control of the potential of the output control terminal GP, and adjust the threshold voltage of at least one transistor among the plurality of transistors in the output circuit 20 under the control of the signal of the threshold voltage control terminal DG.

[0081] The output circuit of the shift register unit usually includes a plurality of transistors. During the operation of the shift register, one or some of these transistors are in the on state, while another or some are in the off state. The transistor in the off state may generate a certain leakage current due to a certain voltage difference between the source and the drain, thereby causing leakage; the transistor in the on state may be insufficiently turned on due to unstable gate voltage, which may cause noise in the output signal at the output signal end. The embodiment of the present disclosure adjusts the threshold voltage of at least one of the plurality of transistors in the output circuit under the control of a signal at the threshold voltage control end, thereby reducing the current of the transistor that needs to be in the off state and increasing the current of the transistor that needs to be in the on state without changing the gate voltage of the transistor, thereby reducing the noise generated in the output signal due to transistor leakage or insufficient conduction.

[0082] The following will refer to Figures 2 to 7 Some examples of output circuits according to embodiments of the present disclosure are described below.

[0083] Figure 2 A schematic block diagram of an output circuit in a shift register unit according to an embodiment of the present disclosure is shown.

[0084] The output circuit 200 includes a charging sub-circuit 210 , a discharging sub-circuit 220 , and a control sub-circuit 230 .

[0085] The charging sub-circuit 210 is connected to the power signal terminal VDD, the output control terminal GP and the output signal terminal GO. The charging sub-circuit 210 can provide the potential of the power signal terminal VDD to the output signal terminal GO under the control of the potential of the output control terminal GP.

[0086] The discharge sub-circuit 220 is connected to the discharge control node PD_ox, the reference signal terminal VSS and the output signal terminal GO. The discharge sub-circuit 220 can provide the potential of the reference signal terminal VSS to the output signal terminal GO under the control of the potential of the discharge control node PD_ox.

[0087] The control sub-circuit 230 is connected to the output control terminal GP and the discharge control node PD_ox. The control sub-circuit 230 may control the potential of the discharge control node PD_ox based on the potential of the output control terminal GP.

[0088] At least one of the charging sub-circuit 210, the discharging sub-circuit 220 and the control sub-circuit 230 is also connected to the threshold voltage control terminal DG. Figure 2 The possible connection with the threshold voltage control terminal DG is shown by a dotted line. The subcircuit connected to the threshold voltage control terminal DG in the charging subcircuit 210, the discharging subcircuit 220 and the control subcircuit 230 can adjust the threshold voltage of at least one transistor contained therein under the control of the signal of the threshold voltage control terminal DG.

[0089] Figure 3 A circuit diagram of an output circuit according to an embodiment of the present disclosure is shown.

[0090] like Figure 3 As shown, the output circuit 300 includes a charging subcircuit 310, a discharging subcircuit 320 and a control subcircuit 330. The above description of the charging subcircuit 210, the discharging subcircuit 220 and the control subcircuit 230 is also applicable to the charging subcircuit 310, the discharging subcircuit 320 and the control subcircuit 330, which will not be repeated here.

[0091] The charging subcircuit 310 includes a first transistor T1 , the discharging subcircuit 320 includes a second transistor T2 and a first capacitor C1 , and the control subcircuit 330 includes a third transistor T3 , a fourth transistor T4 , and a second capacitor C2 .

[0092] In this embodiment, the first transistor T1 is a dual-gate transistor having a first gate and a second gate. The first gate of the first transistor T1 is connected to the output control terminal GP, the second gate of the first transistor T1 is connected to the first threshold voltage control terminal CK_DG, the first electrode of the first transistor T1 is connected to the power signal terminal VDD, and the second electrode of the first transistor T1 is connected to the output signal terminal GO.

[0093] A gate of the second transistor T2 is connected to the discharge control node PD_ox, a first electrode of the second transistor T2 is connected to the reference signal terminal VSS, and a second electrode of the second transistor T2 is connected to the output signal terminal GO.

[0094] A first end of the first capacitor C1 is connected to the discharge control node PD_ox, and a second end of the first capacitor C1 is connected to the output signal terminal GO.

[0095] A gate of the third transistor T3 is connected to the output control terminal GP, a first electrode of the third transistor T3 is connected to the power signal terminal VDD, and a second electrode of the third transistor T3 is connected to the discharge control node PD_ox.

[0096] A gate of the fourth transistor T4 is connected to the first clock signal terminal CK, a first electrode of the fourth transistor T4 is connected to the reference signal terminal VSS, and a second electrode of the fourth transistor T4 is connected to the discharge control node PD_ox.

[0097] A first terminal of the second capacitor C2 is connected to the second clock signal terminal CB, and a second terminal of the second capacitor C2 is connected to the discharge control node PD_ox.

[0098] Figure 4 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown. Figure 4 The output circuit and Figure 3 The output circuits are similar, the difference is at least Figure 4 The second transistor T2 is a dual-gate transistor. For the sake of simplicity, the following will mainly describe the differences in detail.

[0099] like Figure 4 As shown, the output circuit 400 includes a charging subcircuit 410, a discharging subcircuit 420, and a control subcircuit 430. The control subcircuit 430 can be connected to Figure 3 The control subcircuit 330 in is implemented in the same manner, and the above description of the control subcircuit 330 is also applicable to the control subcircuit 430.

[0100] The charging sub-circuit 410 includes a first transistor T1 , a gate of the first transistor T1 is connected to the output control terminal GP, a first electrode of the first transistor T1 is connected to the power signal terminal VDD, and a second electrode of the first transistor T1 is connected to the output signal terminal GO.

[0101] The discharge subcircuit comprises a second transistor T2 and a first capacitor C1.

[0102] In this embodiment, the second transistor T2 is a dual-gate transistor having a first gate and a second gate. The first gate of the second transistor T2 is connected to the discharge control node PD_ox, the second gate of the second transistor T2 is connected to the second threshold voltage control terminal CB_DG, the first electrode of the second transistor T2 is connected to the reference signal terminal VSS, and the second electrode of the second transistor T2 is connected to the output signal terminal GO. Figure 3 , Figure 4 A first end of the first capacitor C1 is connected to the discharge control node PD_ox, and a second end of the first capacitor C1 is connected to the output signal terminal GO.

[0103] Figure 5A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown. Figure 5 The output circuit and Figure 3 The output circuits are similar, the difference is at least Figure 5 The first transistor T1 and the third transistor T3 in the embodiment are both dual-gate transistors. For the sake of simplicity, the following will mainly describe the differences in detail.

[0104] like Figure 5 As shown, the output circuit 500 includes a charging subcircuit 510, a discharging subcircuit 520 and a control subcircuit 530. The charging subcircuit 510 and the discharging subcircuit 520 can be respectively connected to Figure 3 The charging sub-circuit 310 and the discharging sub-circuit 320 in the embodiment are implemented in the same manner, and the above description of the charging sub-circuit 310 and the discharging sub-circuit 320 is also applicable to the charging sub-circuit 510 and the discharging sub-circuit 520 .

[0105] The control subcircuit 530 includes a third transistor T3 and a fourth transistor T4. In this embodiment, in addition to the first transistor T1, the third transistor T3 is also a dual-gate transistor having a first gate and a second gate. The second gate of the first transistor T1 and the second gate of the third transistor T3 are both connected to the first threshold voltage control terminal CK_DG. The first gate of the third transistor T3 is connected to the output control terminal GP, the first electrode of the third transistor T3 is connected to the power signal terminal VDD, and the second electrode of the third transistor T3 is connected to the discharge control node PD_ox. Similar to Figure 3 , Figure 5 A gate of the fourth transistor T4 is connected to the first clock signal terminal CK, a first electrode of the fourth transistor T4 is connected to the reference signal terminal VSS, and a second electrode of the fourth transistor T4 is connected to the discharge control node PD_ox.

[0106] Figure 6 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown. Figure 6 The output circuit and Figure 3 The output circuits are similar, the difference is at least Figure 6 The second transistor T2 and the fourth transistor T4 in the embodiment are both dual-gate transistors. For the sake of simplicity, the following will mainly describe in detail the differences.

[0107] like Figure 6 As shown, the output circuit 600 includes a charging subcircuit 610, a discharging subcircuit 620, and a control subcircuit 630. The charging subcircuit 610 can be connected to Figure 3 The charging sub-circuit 310 in FIG. 6 is implemented in the same manner, and the above description of the charging sub-circuit 310 is also applicable to the charging sub-circuit 610 .

[0108] The discharge subcircuit 620 includes a second transistor T2 and a first capacitor C1, and the control subcircuit 630 includes a third transistor T3 and a fourth transistor T4. In this embodiment, the second transistor T2 and the fourth transistor T4 are both double-gate transistors having a first gate and a second gate, and the second gate of the second transistor T2 and the second gate of the fourth transistor are both connected to the second threshold voltage control terminal CB_DG.

[0109] The first gate of the second transistor T2 is connected to the discharge control node PD_ox, the first electrode of the second transistor T2 is connected to the reference signal terminal VSS, and the second electrode of the second transistor T2 is connected to the output signal terminal GO. The first gate of the fourth transistor T4 is connected to the first clock signal terminal CK, the first electrode of the fourth transistor T4 is connected to the reference signal terminal VSS, and the second electrode of the fourth transistor T4 is connected to the discharge control node PD_ox. Similar to Figure 3 , Figure 6 The first end of the first capacitor C1 is connected to the discharge control node PD_ox, and the second end of the first capacitor C1 is connected to the output signal terminal GO; the gate of the third transistor T3 is connected to the output control terminal GP, the first electrode of the third transistor T3 is connected to the power signal terminal VDD, and the second electrode of the third transistor T3 is connected to the discharge control node PD_ox.

[0110] Figure 7 A circuit diagram of an output circuit according to another embodiment of the present disclosure is shown. Figure 7 The output circuit and Figure 5 The output circuits are similar, the difference is at least Figure 7 The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all dual-gate transistors. For the sake of simplicity, the following will mainly describe in detail the differences.

[0111] like Figure 7 As shown, the output circuit 700 includes a charging subcircuit 710, a discharging subcircuit 720 and a control subcircuit 730. The charging subcircuit 710 and the discharging subcircuit 720 can be connected to Figure 5 The charging sub-circuit 510 and the discharging sub-circuit 520 in the embodiment are implemented in the same manner, and the above description of the charging sub-circuit 510 and the discharging sub-circuit 520 is also applicable to the charging sub-circuit 710 and the discharging sub-circuit 720 .

[0112] The control subcircuit 730 includes a third transistor T3, a fourth transistor T4, and a second capacitor C2. In the present embodiment, the third transistor T3 and the fourth transistor T4 are both double-gate transistors having a first gate and a second gate. The second gate of the third transistor T3 and the second gate of the first transistor T1 are both connected to the first threshold voltage control terminal CK_DG, and the second gate of the fourth transistor T4 and the second gate of the second transistor T2 are both connected to the second threshold voltage control terminal CB_DG.

[0113] The first gate of the third transistor T3 is connected to the output control terminal GP, the first electrode of the third transistor T3 is connected to the power signal terminal VDD, and the second electrode of the third transistor T3 is connected to the discharge control node PD_ox. The first gate of the fourth transistor T4 is connected to the first clock signal terminal CK, the first electrode of the fourth transistor T4 is connected to the reference signal terminal VSS, and the second electrode of the fourth transistor T4 is connected to the discharge control node PD_ox. Similar to Figure 5 , Figure 7 A first end of the second capacitor C2 is connected to the second clock signal terminal CB, and a second end of the second capacitor C2 is connected to the discharge control node PD_ox.

[0114] In the above embodiments of the present disclosure, at least one of the multiple transistors (e.g., T1 to T4) in the output circuit is implemented as a dual-gate transistor, the first gate of the dual-gate transistor is normally connected in the output circuit, and the second gate is controlled by the voltage of the corresponding threshold voltage control terminal. In this way, the threshold voltage of the transistor in the output circuit can be adjusted so that the adjusted transistor can be fully turned on or off, thereby reducing the noise in the output signal. Fig. 8A , Figure 8B and Fig. 9 To illustrate the structure and electrical characteristics of the dual-gate transistor used in the embodiment of the present disclosure.

[0115] Fig. 8A An equivalent circuit diagram of a dual-gate transistor used in an output circuit according to an embodiment of the present disclosure is shown. Figure 8B Shows Fig. 8A A cross-sectional view of a dual-gate transistor. Fig. 8A As shown, the double-gate transistor has a first gate G1, a second gate G2, a first electrode (e.g., source D) and a second electrode (e.g., drain S). The double-gate transistor can transmit a signal from the first electrode to the second electrode under the control of a signal at the first gate G1. The double-gate transistor can also adjust its threshold voltage under the control of a signal at the second gate G2, which will be referred to below. Fig. 9 This is explained in detail.

[0116] like Figure 8BAs shown, the dual-gate transistor includes a second gate 803 (bottom gate) formed on a substrate 801. Optionally, a barrier layer 802 may be provided between the substrate 801 and the second gate 803. The second gate 803 is covered with a first insulating layer 804. An active layer is formed on the first insulating layer 804, and the active layer includes a channel 805 and doped regions 806 located on both sides of the channel 805. A second insulating layer 807 is formed on the active layer, and a first gate 808 (top gate) is formed on the second insulating layer 807. The first gate 808 (top gate) is covered by an interlayer dielectric layer 811. Optionally, an additional gate 810 may be formed between the first gate 808 and the interlayer dielectric layer 811, and an additional insulating layer 809 may be provided between the additional gate 810 and the first gate 808. A through hole may be formed above the doped region 806, and the through hole passes through the second insulating layer 807, the additional insulating layer 809 (if any) and the interlayer dielectric layer 811. A first electrode 812 and a second electrode 813 are formed in the through hole. The first electrode 812 and the second electrode 813 are electrically connected to the doping regions 806 on both sides of the channel 805, respectively. The substrate 801 may be a glass substrate. The first gate 808, the second gate 803 and the additional gate 810 may be made of molybdenum (Mo), and the first insulating layer 804, the second insulating layer 807 and the additional insulating layer 809 may be made of silicon oxide (SiOx).

[0117] When the dual-gate transistor is turned on, Figure 8B The middle channel 805 generates a current, and the magnitude of the current can be changed by applying different voltages to the second gate when the same voltage is applied to the first gate. Fig. 9 Provide detailed explanation on this.

[0118] Fig. 9 A transfer curve diagram of a dual-gate transistor used in an output circuit according to an embodiment of the present disclosure is shown, wherein the abscissa represents the gate-source voltage Vgs of the dual-gate transistor, ie, the voltage between the first gate and the source, and the ordinate represents the current Id flowing through the dual-gate transistor. Fig. 9 1 and 2 show the transfer curves of the double-gate transistor when different voltages are applied to the second electrode G2 of the double-gate transistor. Fig. 9As shown, compared with the case where the voltage of the second gate G2 of the dual-gate transistor is equal to 0V, when the voltage of the second gate G2 is less than 0V (for example, -2V), the transfer curve of the dual-gate transistor shifts to the right, that is, for the same gate-source voltage Vgs, the threshold voltage increases, and the current Id increases (also called the threshold voltage right shift); when the voltage of the second gate G2 is greater than 0V (for example, 2V), the transfer curve of the dual-gate transistor shifts to the left, that is, for the same gate-source voltage Vgs, the threshold voltage decreases, and the current Id decreases (also called the threshold voltage left shift). For P-type transistors, an increase in the threshold voltage means an increase in the current, so that the transistor can become a depletion type; a decrease in the threshold voltage means a decrease in the current, so that the transistor can become an enhancement type. For N-type transistors, an increase in the threshold voltage means an increase in the current, so that the transistor can become an enhancement type; a decrease in the threshold voltage means a decrease in the current, so that the transistor can become a depletion type.

[0119] Fig.10 A circuit diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0120] The shift register unit 1000 includes a control circuit and an output circuit 1200 .

[0121] like Fig.10 As shown, the control circuit may include an input subcircuit 1101, an output subcircuit 1102, and an adjustment subcircuit 1103. Fig.10 In the embodiment, the clock signal terminals connected to the control circuit include a third clock signal terminal CK' and a fourth clock signal terminal CB'. The third clock signal terminal CK' may be the same as or different from the first clock signal terminal CK, and the fourth clock signal terminal CB' may be the same as or different from the second clock signal terminal CB.

[0122] The input subcircuit 1101 is connected to the input signal terminal IN, the reference signal terminal VSS, the third clock signal terminal CK', the first control node PD_in and the second control node PU. Under the control of the signal of the third clock signal terminal CK', the input subcircuit 1101 can provide the potential of the input signal terminal IN to the first control node PD_in and provide the potential of the reference signal terminal VSS to the second control node PU. Fig.10 In the embodiment, the input sub-circuit 1101 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is connected to the third clock signal terminal CK', the first electrode of the fifth transistor is connected to the input signal terminal IN, and the second electrode of the fifth transistor T5 is connected to the first control node PD_in. The gate of the sixth transistor T6 is connected to the third clock signal terminal CK', the first electrode of the sixth transistor T6 is connected to the reference signal terminal VSS, and the second electrode of the sixth transistor T6 is connected to the second control node PU.

[0123] The output subcircuit 1102 is connected to the first control node PD_in, the second control node PU, the output control terminal GP, the fourth clock signal terminal CB' and the power signal terminal VDD. The output subcircuit 1102 can provide the potential of the fourth clock signal terminal CB' to the output control terminal GP under the control of the potential of the first control node PD_in, and provide the potential of the power signal terminal VDD to the output control terminal GP under the control of the second control node PU. Fig.10 In the embodiment, the output subcircuit 1102 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a third capacitor C3 and a fourth capacitor C4. The gate of the seventh transistor T7 is connected to the reference signal terminal VSS, and the first electrode of the seventh transistor T7 is connected to the first control node PD_in. The gate of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7 (for example, connected to the third control node PD_out), the first electrode of the eighth transistor T8 is connected to the fourth clock signal terminal CB', and the second electrode of the eighth transistor T8 is connected to the output control terminal GP. The gate of the ninth transistor T9 is connected to the second control node PU, the first electrode of the ninth transistor T9 is connected to the power signal terminal VDD, and the second electrode of the ninth transistor T9 is connected to the output control terminal GP. The first end of the third capacitor C3 is connected to the gate of the eighth transistor T8, and the second end of the third capacitor C3 is connected to the second electrode of the eighth transistor T8. The first end of the fourth capacitor C4 is connected to the gate of the ninth transistor T9, and the second end of the fourth capacitor C4 is connected to the first electrode of the ninth transistor T9.

[0124] The adjustment subcircuit 1103 is connected to the third clock signal terminal CK', the fourth clock signal terminal CB', the power signal terminal VDD, the first control node PD_in and the second control node PU. The adjustment subcircuit 1103 can provide the potential of the third clock signal terminal CK' to the second control node PU under the control of the potential of the first control node PD_in, and provide the potential of the power signal terminal VDD to the first control node PD_in under the control of the potential of the fourth clock signal terminal CB' and the second control node PU. Fig.10In the embodiment, the adjustment subcircuit 1103 includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The gate of the tenth transistor T10 is connected to the first control node PD_in, the first electrode of the tenth transistor T10 is connected to the third clock signal terminal CK', and the second electrode of the tenth transistor T10 is connected to the second control node PU. The gate of the eleventh transistor T11 is connected to the second control node PU, and the first electrode of the eleventh transistor T11 is connected to the power signal terminal VDD. The gate of the twelfth transistor T12 is connected to the fourth clock signal terminal CB', the first electrode of the twelfth transistor T12 is connected to the second electrode of the eleventh transistor T11 (for example, connected to the fourth control node PD_f), and the second electrode of the twelfth transistor T12 is connected to the first control node PD_in.

[0125] Fig.11 A schematic diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0126] like Fig.11 As shown, the gate driving circuit 2000 includes multiple stages of cascaded shift register units. For ease of description, only the first four stages of shift register units GOA1 to GOA4 are shown. Each shift register unit GOA1 to GOA4 can be implemented by the shift register unit of any of the above embodiments.

[0127] The threshold voltage control terminal of the multi-stage shift register unit is connected to receive a threshold voltage control signal, for example, Fig.11 In the embodiment, the first threshold voltage control terminals CK_DG of the shift register units GOA1 to GOA4 are all connected to receive the first threshold voltage control signal ck_dg, and the second threshold voltage control terminals CB_DG are all connected to receive the second threshold voltage control signal cb_dg. Fig.11 In the embodiment, for odd-numbered shift register units, such as the first-level shift register unit GOA1 and the third-level shift register unit GOA3, the first clock signal terminal CK is connected to receive the first clock signal ck, and the second clock signal terminal CB is connected to receive the second clock signal cb; for even-numbered shift register units, such as the second-level shift register unit GOA2 and the fourth-level shift register unit GOA4, the first clock signal terminal CK is connected to receive the second clock signal cb, and the second clock signal terminal CB is connected to receive the first clock signal ck. The so-called "odd" and "even" here can be used interchangeably. The third clock signal terminal and the fourth clock signal terminal (if any, for example in Fig.10In the example of ) can be connected in a similar manner. The input signal terminal IN of the n-th stage shift register unit GOA(n) is connected to the output control terminal GP of the n-1-th stage shift register unit GOA(n-1), where n is an integer greater than 1. The input signal terminal IN of the first stage shift register unit GOA1 can be connected to receive the start signal STV.

[0128] Each shift register unit can generate a corresponding output signal at its output signal end according to the signal at its input signal end and the clock signal end. Through this cascade connection, the multi-stage shift register unit generates multiple output signals OUT that are shifted in sequence. <1> ,OUT <2> ,OUT <3> ,OUT <4> ..., used to scan each row of pixels on the display panel.

[0129] Generally, a frame may include a data update phase and a data hold phase. In the data update phase, each shift register unit generates an output signal to scan each row of pixels, and the scanned pixels may emit light based on the data signal applied to the pixel. This process is also called data update. After each shift register unit completes pixel scanning, it enters the data hold phase. In the data hold phase, the output signal level of each shift register unit remains unchanged, and each row of pixels continues to display with the data signal received in the data update phase. This process is also called data hold. Fig.12 and Fig.13 The operation of the shift register unit according to the embodiment of the present disclosure is described below.

[0130] Fig.12 The operation timing diagram of the shift register unit in the data update phase according to the embodiment of the present disclosure is shown. Fig.10 The circuit structure of the shift register unit is used to Fig.12 For the convenience of description, it is assumed that the first clock signal terminal CK and the third clock signal terminal CK′ receive the same clock signal, and the second clock signal terminal CB and the fourth clock signal terminal CB′ receive the same clock signal.

[0131] In period t1, the input signal terminal IN inputs a low level, the third clock signal terminal CK' is a low level, and the fourth clock signal terminal CB' is a high level. The third clock signal terminal CK' is a low level, which turns on the fifth transistor T5, so that the first control node PD_in is a low level. The low level of the reference signal terminal VSS turns on the seventh transistor T7, and the low level of the first control node PD_in is transmitted to the third control node PD_out, so that the eighth transistor T8 is turned on. The third clock signal terminal CK' is a low level and also turns on the sixth transistor T6, and the low level of the reference signal terminal VSS is provided to the second control node PU, so that the ninth transistor T9 is turned on. The eighth transistor T8 and the ninth transistor T9 are both turned on so that the output control terminal GP outputs a high-level output control signal. The high level of the output control terminal GP turns off the first transistor T1 and the third transistor T3. The low level of the first clock signal terminal CK turns on the fourth transistor T4, so that the low level of the reference signal terminal VSS is provided to the discharge control node PD_ox. The low level of the discharge control node PD_ox turns on the second transistor T2, so that the output signal terminal GO outputs a low level output signal. This period t1 is also called an input period.

[0132] In period t2, the input signal terminal IN inputs a high level, the third clock signal terminal CK' is a high level, and the fourth clock signal terminal CB' is a low level. The third clock signal terminal CK' is a high level, so that the fifth transistor T5 and the sixth transistor T6 are both turned off, and the potential of the first control node PD_in is maintained at a low level. The first control node PD_in is a low level, so that the tenth transistor T10 is turned on, thereby transmitting the high level of the third clock signal terminal CK' to the second control node PU. The second control node PU is a high level, so that the ninth transistor T9 and the eleventh transistor T11 are both turned off. Since the seventh transistor T7 is in the on state, the low level of the first control node PD_in is transmitted to the third control node PD_out, and the eighth transistor T8 is turned on, so that the low level of the fourth clock signal terminal CB' is provided to the output control terminal GP, so that the output control terminal GP outputs a low-level output control signal. The low level of the output control terminal GP turns on the first transistor T1 and the third transistor T3. The conduction of the first transistor T1 provides the high level of the power supply signal terminal VDD to the output signal terminal GO. The conduction of the third transistor T3 provides the high level of the power signal terminal VDD to the discharge control node PD_ox. The high level of the discharge control node PD_ox turns off the second transistor T2, thereby stopping the pull-down of the output signal terminal GO. This period t2 is also called the output period.

[0133] In period t3, the input signal terminal IN inputs a high level, the third clock signal terminal CK' is a low level, and the fourth clock signal terminal CB' is a high level. The third clock signal terminal CK' is a low level, so that the fifth transistor T5 and the sixth transistor T6 are both turned on, so that the first control node PD_in is a high level, and the second control node PU is a low level. The second control node PU is a low level, so that the ninth transistor T9 is turned on, so that the output control terminal GP outputs a high-level output control signal. The output control terminal GP is a high level, so that the first transistor T1 and the third transistor T3 are turned off. The first clock signal terminal CK is a low level, so that the fourth transistor T4 is turned on, so that the potential of the discharge control node PD_ox is a low level. The discharge control node PD_ox is a low level, so that the second transistor T2 is turned on, so that a low level is output at the output signal terminal GO. This period t3 is also called a reset period.

[0134] In time period t4, the input signal terminal IN inputs a high level, the third clock signal terminal CK' is a high level, the fourth clock signal terminal CB' is a low level, the output control terminal GP outputs a high level output control signal, and the first transistor T1, the third transistor T3 and the fourth transistor T4 are all turned off. Due to the coupling effect of the second capacitor C2, the low level of the fourth clock signal terminal CB' causes the potential of the discharge control node PD_ox to be pulled down, the second transistor T2 is turned on, and the output signal terminal GO outputs a low level.

[0135] Fig.13 The operation timing diagram of the shift register unit in the data update phase and the data retention phase according to the embodiment of the present disclosure is shown. Fig.10 The circuit structure of the shift register unit is used to Fig.13 The operation sequence is described below.

[0136] like Fig.13 As shown, one frame includes a data updating phase and a data holding phase.

[0137] In the data update phase, the shift register unit can be as mentioned above Fig.12 During this period, the first threshold voltage control terminal CK_DG and the second threshold voltage control terminal CB_DG can be at an intermediate level VHM, and the intermediate level VHM can be 0V, so that the threshold voltages of the transistors T1 to T4 of the output circuit are not changed. Of course, other values ​​of VHM can also be applied to adjust the threshold voltages of the transistors T1 to T4 to the desired reference values ​​as needed.

[0138] In the data holding stage, the shift register unit maintains the output signal at a low level. In the data holding stage, the input signal terminal IN continues to be at a high level, which can keep the third clock signal CK' and the fourth clock signal CB' at a low level, so that the output control terminal GP is maintained at a high level. Of course, the output control terminal GP can also be maintained at a high level in other ways, for example, by keeping the third clock signal CK' and the fourth clock signal CB' at a high level or changing between a high level and a low level as needed, the output control terminal GP can also be maintained at a high level. The first clock signal CK and the second clock signal CB are maintained at a low level, so that the output signal terminal GO is maintained at a low level. In the data holding stage, the first threshold voltage control signal at the first threshold voltage control terminal CK_DG is a first level VHH higher than the intermediate level VHM, and the second threshold voltage control signal at the second threshold voltage control terminal CB_DG is a second level VHL lower than the intermediate level VHM.

[0139] The second threshold voltage control terminal CB_DG is at the second level VHL (negative voltage) so that the threshold voltages of the second transistor T2 and the fourth transistor T4 shift rightward. Fig.10 The second level VHL can be set to be lower than the level of the reference signal terminal VSS, for example, about one time lower. For example, VSS = -7V, VHL = -15V.

[0140] The first threshold voltage control terminal CK_DG is VHH (positive voltage) so that the threshold voltages of the first transistor T1 and the third transistor T3 are shifted to the left. Fig.10 The first level VHH can be set to a power supply signal level higher than the source signal terminal VDD, for example, several volts higher, but not more than twice VDD. For example, VDD = 7V, VHH = 10V.

[0141] for Fig.10For the circuit structure, if the first transistor T1 to the fourth transistor T4 are all single-gate transistors, there will be large noise in the output signal at an ultra-low refresh rate (such as 1 Hz), which may even be as high as 1.46 V. In contrast, the embodiment of the present disclosure effectively reduces the noise in the output signal by providing a dual-gate transistor in the output circuit of the shift register unit and adjusting its threshold voltage, and can keep the output signal at a stable level even at a low refresh rate.

[0142] Although the above reference Fig.10 The shift register unit of the present disclosure describes the operation timing, but the embodiments of the present disclosure are not limited to this. For the shift register unit of any embodiment of the present disclosure, a similar method can be used to adjust the threshold voltage of any one or more transistors in the output circuit. In addition, although the embodiments of the present disclosure are described using P-type transistors as an example, the embodiments of the present disclosure can also be applied to N-type transistors, and the threshold voltage of any one or more transistors in the output circuit can also be adjusted by correspondingly changing the waveform of the threshold voltage control signal.

[0143] Fig.14 A flow chart of a driving method of a shift register unit according to an embodiment of the present disclosure is shown.

[0144] In step S101, in the first time period (such as the above-mentioned data update phase), the control circuit provides an output control signal to the output control terminal based on the signals of the input signal terminal and the clock signal terminal, and the output circuit provides an output signal to the output signal terminal under the control of the potential of the output control terminal.

[0145] In step S102, in the second time period (for example, the above-mentioned data holding stage), the control circuit provides an output control signal to the output control terminal based on the signals at the input signal terminal and the clock signal terminal, and the output circuit maintains the level of the output signal at the output signal terminal under the control of the potential of the output control terminal, and adjusts the threshold voltage of at least one transistor among the multiple transistors in the output circuit under the control of the signal at the threshold voltage control terminal.

[0146] For example, in the case where at least one of the first transistor T1 and the third transistor T3 is a double-gate transistor (such as Figure 3 , Figure 5 and Figure 7 As shown), a threshold voltage control signal of a first level VHH may be applied to the first threshold voltage control terminal CK_DG, so that the threshold voltage of the first transistor T1 and / or the third transistor T3 is shifted rightward, thereby becoming an enhancement transistor.

[0147] For the case where at least one of the second transistor T2 and the fourth transistor T4 is a dual-gate transistor (such as Figure 4 , Figure 6 and Figure 7 As shown), a threshold voltage control signal of the second level VHL can be applied to the second threshold voltage control terminal CB_DG, so that the threshold voltage of the second transistor T2 and / or the fourth transistor T4 shifts leftward, thereby becoming a depletion-type transistor.

[0148] Fig.15 FIG. 2 shows a schematic diagram of a display device according to an embodiment of the present disclosure. Fig.15 As shown, the display device 3000 includes a gate drive circuit 3100. The gate drive circuit 3100 can be implemented by the gate drive circuit of any of the above embodiments. The display device 3000 according to the embodiment of the present disclosure can be any product or component with a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.

[0149] It should be noted that, in the above description, the technical solution of the embodiment of the present disclosure is shown only by way of example, but it does not mean that the embodiment of the present disclosure is limited to the above steps and structures. Where possible, the steps and structures can be adjusted and selected as needed. Therefore, some steps and units are not necessary elements for implementing the overall inventive concept of the embodiment of the present disclosure.

[0150] The present disclosure has been described so far in conjunction with the preferred embodiments. It should be understood that those skilled in the art may make various other changes, substitutions and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the above-mentioned specific embodiments, but should be limited by the appended claims.

Claims

1. A shift register unit, comprising: a control circuit connected to the input signal terminal, the clock signal terminal and the output control terminal, and configured to provide an output control signal to the output control terminal based on signals at the input signal terminal and the clock signal terminal; as well as an output circuit connected to the output control terminal, the output signal terminal and the threshold voltage control terminal, configured to provide an output signal to the output signal terminal under the control of the potential of the output control terminal, and to adjust the threshold voltage of at least one transistor among the plurality of transistors in the output circuit under the control of the signal of the threshold voltage control terminal; Wherein, the output circuit comprises: a charging subcircuit, connected to the power signal terminal, the output control terminal and the output signal terminal, and configured to provide the potential of the power signal terminal to the output signal terminal under the control of the potential of the output control terminal; a discharge subcircuit connected to a discharge control node, a reference signal terminal and the output signal terminal, and configured to provide the potential of the reference signal terminal to the output signal terminal under the control of the potential of the discharge control node; and a control subcircuit connected to the output control terminal and the discharge control node, and configured to control the potential of the discharge control node based on the potential of the output control terminal, Wherein, at least one of the charging subcircuit, the discharging subcircuit and the control subcircuit is also connected to the threshold voltage control terminal and is also configured to adjust the threshold voltage of at least one transistor contained therein under the control of a signal of the threshold voltage control terminal; The charging subcircuit comprises a first transistor, a gate of the first transistor is connected to the output control terminal, a first electrode of the first transistor is connected to the power signal terminal, and a second electrode of the first transistor is connected to the output signal terminal; The threshold voltage control terminal includes a first threshold voltage control terminal and a second threshold voltage control terminal, the first transistor is a dual-gate transistor having a first gate and a second gate, the first gate of the first transistor is connected to the output control terminal, and the second gate of the first transistor is connected to the first threshold voltage control terminal; Wherein, the discharge subcircuit comprises: a second transistor, the second transistor being a double-gate transistor having a first gate and a second gate, the first gate of the second transistor being connected to the discharge control node, the second gate of the second transistor being connected to the second threshold voltage control terminal, the first electrode of the second transistor being connected to the reference signal terminal, and the second electrode of the second transistor being connected to the output signal terminal; and A first capacitor, a first end of the first capacitor is connected to the discharge control node, and a second end of the first capacitor is connected to the output signal end; Wherein, the control subcircuit comprises: a third transistor, wherein a gate of the third transistor is connected to the output control terminal, a first electrode of the third transistor is connected to the power signal terminal, and a second electrode of the third transistor is connected to the discharge control node; a fourth transistor, wherein a gate of the fourth transistor is connected to the first clock signal terminal, a first electrode of the fourth transistor is connected to the reference signal terminal, and a second electrode of the fourth transistor is connected to the discharge control node; and a second capacitor, wherein a first end of the second capacitor is connected to a second clock signal end, and a second end of the second capacitor is connected to the discharge control node; and the third transistor is a dual-gate transistor having a first gate and a second gate, wherein the first gate of the third transistor is connected to the output control end, and the second gate of the third transistor is connected to the first threshold voltage control end.

2. The shift register unit according to claim 1, wherein: The fourth transistor is a double-gate transistor having a first gate and a second gate. The first gate of the fourth transistor is connected to the first clock signal terminal, and the second gate of the fourth transistor is connected to the second threshold voltage control terminal.

3. The shift register unit according to any one of claims 1 to 2, wherein: The control circuit comprises: an input subcircuit connected to an input signal terminal, a reference signal terminal, a third clock signal terminal, a first control node, and a second control node, and configured to provide the potential of the input signal terminal to the first control node and the potential of the reference signal terminal to the second control node under the control of a signal of the third clock signal terminal; an output subcircuit connected to the first control node, the second control node, the output control terminal, a fourth clock signal terminal and a power signal terminal, and configured to provide the potential of the fourth clock signal terminal to the output control terminal under the control of the potential of the first control node, and to provide the potential of the power signal terminal to the output control terminal under the control of the second control node; and An adjustment subcircuit is connected to a third clock signal terminal, a fourth clock signal terminal, a power signal terminal, the first control node and the second control node, and is configured to provide the potential of the third clock signal terminal to the second control node under the control of the potential of the first control node, and to provide the potential of the power signal terminal to the first control node under the control of the potential of the fourth clock signal terminal and the second control node.

4. The shift register unit according to claim 3, wherein: The input subcircuit comprises: a fifth transistor, wherein a gate of the fifth transistor is connected to the third clock signal terminal, a first electrode of the fifth transistor is connected to the input signal terminal, and a second electrode of the fifth transistor is connected to the first control node; and A sixth transistor, wherein a gate of the sixth transistor is connected to the third clock signal terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the second control node.

5. The shift register unit according to claim 3, wherein: The output subcircuit comprises: a seventh transistor, wherein a gate of the seventh transistor is connected to the reference signal terminal, and a first electrode of the seventh transistor is connected to the first control node; an eighth transistor, wherein a gate of the eighth transistor is connected to a second electrode of the seventh transistor, a first electrode of the eighth transistor is connected to the fourth clock signal terminal, and a second electrode of the eighth transistor is connected to the output control terminal; a ninth transistor, wherein a gate of the ninth transistor is connected to the second control node, a first electrode of the ninth transistor is connected to the power signal terminal, and a second electrode of the ninth transistor is connected to the output control terminal; a third capacitor, wherein a first end of the third capacitor is connected to the gate electrode of the eighth transistor, and a second end of the third capacitor is connected to the second electrode of the eighth transistor; and A fourth capacitor, wherein a first end of the fourth capacitor is connected to the gate of the ninth transistor, and a second end of the fourth capacitor is connected to the first electrode of the ninth transistor.

6. The shift register unit according to claim 3, wherein: The adjustment subcircuit comprises: a tenth transistor, wherein a gate of the tenth transistor is connected to the first control node, a first electrode of the tenth transistor is connected to the third clock signal terminal, and a second electrode of the tenth transistor is connected to the second control node; an eleventh transistor, a gate of the eleventh transistor being connected to the second control node, and a first electrode of the eleventh transistor being connected to the power signal terminal; and A twelfth transistor, wherein a gate of the twelfth transistor is connected to the fourth clock signal terminal, a first electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor, and a second electrode of the twelfth transistor is connected to the first control node.

7. A method for driving a shift register unit according to any one of claims 1 to 6, comprising: In a first period, the control circuit provides an output control signal to the output control terminal based on the signals at the input signal terminal and the clock signal terminal, and the output circuit provides an output signal to the output signal terminal under the control of the potential of the output control terminal; as well as In the second period, the control circuit provides an output control signal to the output control terminal based on the signals at the input signal terminal and the clock signal terminal. The output circuit maintains the level of the output signal at the output signal terminal under the control of the potential of the output control terminal, and adjusts the threshold voltage of at least one transistor among the multiple transistors in the output circuit under the control of the signal at the threshold voltage control terminal.

8. The driving method according to claim 7, wherein: The output circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor, the threshold voltage control terminal includes a first threshold voltage control terminal, at least one of the first transistor and the third transistor is a double-gate transistor having a first gate and a second gate connected to the first threshold voltage control terminal, and the threshold voltage of at least one transistor among the plurality of transistors in the output circuit is adjusted under the control of a signal of the threshold voltage control terminal, comprising: A threshold voltage control signal of a first level is applied to the first threshold voltage control terminal, so that the threshold voltage of at least one of the first transistor and the third transistor is changed, thereby becoming an enhancement type transistor.

9. The driving method according to claim 8, wherein: The first level is higher than a level of a power signal at a power signal terminal connected to the first transistor and the third transistor.

10. The driving method according to claim 7, wherein: The output circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor, the threshold voltage control terminal includes a second threshold voltage control terminal, at least one of the second transistor and the fourth transistor is a double-gate transistor having a first gate and a second gate connected to the second threshold voltage control terminal, and the threshold voltage of at least one transistor among the plurality of transistors in the output circuit is adjusted under the control of a signal of the threshold voltage control terminal, comprising: A threshold voltage control signal of a second level is applied to the second threshold voltage control terminal, so that the threshold voltage of at least one of the second transistor and the fourth transistor changes, thereby becoming a depletion-type transistor.

11. The driving method according to claim 10, wherein: The second level is lower than a level of a reference signal at a reference signal terminal connected to the second transistor and the fourth transistor.

12. A gate driving circuit, comprising a plurality of cascaded shift register units as claimed in any one of claims 1 to 6, wherein the threshold voltage control terminals of the plurality of cascaded shift register units are connected to receive a threshold voltage control signal.

13. A display device comprising the gate driving circuit according to claim 12.

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