A aging and screening device for antifuse type FPGA devices

Abstract

This invention relates to a aging and screening device for antifuse-type FPGA devices, comprising a data stream generation module, an aging driver board, and an aging station board. The data stream generation module is implemented using Matlab software and generates an excitation JTAG data stream file through program design and algorithm iteration. The data stream generation module communicates with the aging driver board via a digital channel; the aging driver board and the aging station board are connected via a dedicated interface. This invention configures the serial data stream through a JTAG boundary scan port and is equipped with a large-capacity test code storage space and multiple programmable analog channels, providing and real-time monitoring of the device's operating voltage and current, as well as the device's operating status. It can meet the hardware resource and bit stream capacity requirements of antifuse-type FPGA devices of different types and sizes in aging and screening, and has wide applicability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit reliability testing, and in particular to a aging and screening device for antifuse type FPGA devices. Background Technology

[0002] Antifuse FPGA devices are characterized by high reliability, good confidentiality, and strong radiation resistance, and are widely used in complex environments and military fields.

[0003] The combination of antifuse technology and FPGA enables numerous advantages of antifuse FPGA devices. As the configuration memory unit of this type of FPGA device, the antifuse cell is in a high-blocking open state before programming, with a resistance of several hundred megaohms. After high-voltage pulse programming, it enters a low-blocking connected state, with a resistance of tens of ohms. The antifuse cell is a non-volatile memory unit with a one-time programming characteristic. This makes it impossible to test and screen the internal logic resources of an antifuse FPGA by configuring test codes with different fault models multiple times. Furthermore, since the antifuse cell plays a decisive role in the overall reliability of the device, effectively aging and screening unprogrammed antifuse FPGA devices in the early stages and eliminating devices with defective antifuse cells has a profound impact on the long-term reliability of the system.

[0004] Currently, foreign device manufacturers have only provided some documentation on the aging and screening of antifuse FPGA devices, without providing detailed descriptions and implementation methods of the aging and screening device. This invention, combining the characteristics of different types of antifuse FPGA devices, discloses a specific implementation method of a general antifuse FPGA aging and screening device. Summary of the Invention

[0005] Therefore, this invention discloses a aging and screening device for antifuse FPGA devices, providing a complete aging and screening solution for antifuse FPGA series products.

[0006] To address the aforementioned technical problems, the present invention provides a aging and screening device for antifuse type FPGA devices, comprising a data stream generation module, an aging driver board, and an aging station board. The data stream generation module is implemented using Matlab software, and generates an excitation JTAG data stream file through program design and algorithm iteration. The data stream generation module is connected to the aging driver board via a digital channel. The aging driver board and the aging station board are connected via a dedicated interface, which integrates a power channel, a digital channel, and an analog channel.

[0007] The digital channel consists of an FPGA and a level conversion chip. The FPGA acts as an external memory for the main control MCU. The MCU uses a DMA (Direct Memory Access) controller to realize high-speed data transfer between the SD card and the FPGA. After the FPGA reads the data, it decodes it and allocates the JTAG data stream to the designated digital channel. On the rising edge of the JTAG clock, it reads the data from TDO (JTAG output port) or PRX (device probe port) and compares it with the expected data. The running program file and the comparison result are output to the status indication module.

[0008] The aging station board is laid out according to the shape and structure of the socket of the device being tested. The aging driver board integrates a microprocessor main control MCU, a large-capacity SD card, a voltage and current acquisition module, a display module, a status indicator module, an audible and visual alarm module, and a mode selection module. The main control MCU is connected to the large-capacity SD card, the display module, and the status indicator module through a built-in DMA controller. The main control MCU also integrates power management and is connected to an external DC / DC power management chip to form a power channel. The main control MCU is connected to the voltage and current acquisition module and the audible and visual alarm module through a built-in ADC converter to form a voltage and current judgment alarm loop. The main control MCU is connected to the mode selection module to form an operating mode setting function loop.

[0009] In one embodiment of the present invention, the power channel generates four programmable output power supplies, and the power-on sequence is controlled by the main control chip.

[0010] The digital channel, which consists of an FPGA and a level conversion chip, allocates JTAG data streams to designated channels for data transmission and reception.

[0011] The analog channel generates 17 programmable analog channel outputs to provide voltage to the programming ports specific to the antifuse FPGA device.

[0012] In one embodiment of the present invention, the high-capacity SD card serves as a vector storage space, storing stimulus JTAG files.

[0013] In one embodiment of the present invention, the data stream generation module is used to generate a aging data stream file for a specified model of antifuse FPGA device and store it in an SD card.

[0014] In one embodiment of the present invention, the voltage and current acquisition module acquires voltage and current of the power supply channel.

[0015] In one embodiment of the present invention, the main control MCU of the old-fashioned driver board reads the configuration information and JTAG data stream file in the SD card and transmits the data with the FPGA to realize the configuration of the power channel, digital channel and analog channel, and to perform data acquisition and monitoring alarm.

[0016] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The present invention realizes an antifuse FPGA aging and screening device that can cover the electrical stress characteristic requirements of major antifuse technologies (MTM (Metal to Metal) type antifuse and ONO (Oxide-Nitride-Oxide) type antifuse), meet the aging vector space requirements of antifuse FPGA devices of different sizes, and allows for flexible development. It solves the problem that conventional aging and screening devices cannot meet the hardware resource, vector depth, and flexible configuration development requirements of antifuse FPGAs in aging and screening. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a block diagram of the antifuse type FPGA aging and screening device of the present invention;

[0019] Figure 2 This is a block diagram of the antifuse type FPGA aging screen driver board described in this invention. Detailed Implementation

[0020] like Figure 1 and Figure 2 As shown in the figure, this embodiment provides a aging and screening device for antifuse type FPGA devices, including a data stream generation module, an aging station board, and an aging driver board, the block diagram of which is shown below. Figure 1 As shown. The boards are connected via two 2.54mm pitch gold-fingered connectors. These connectors can be custom-installed on a specified model of high-temperature aging chamber, forming a standard interface inside and outside the chamber, enabling reliable connection between the workstation board and the drive board under high temperatures. The connectors define the reference designators for the power channel, digital channel, and analog channel; the aging drive board and aging workstation board can be designed independently according to these definitions. The following describes each component of the aging screening device separately.

[0021] The data stream generation module is implemented using Matlab software. Based on the testability design principles of different types of antifuse FPGA devices, the definition of JTAG scan chain, and the definition of mode instruction data register, it generates a JTAG data stream file that covers the truth table of the device's logic macrocells, the functions of the device's I / O ports, and can apply forward and reverse electrical stress to the device's antifuse array and excite the testable resources through program design and algorithm iteration. This file is stored in a high-capacity SD card for the main control MCU to call and execute.

[0022] The design of the old refining workstation board is mainly based on the shape and structure of the device sockets for workstation layout. According to the characteristics of different types and sizes of antifuse FPGA devices, there are three main types of routing channels: 1. Power Channel: Connect the device's core power, port power, JTAG configuration power, and charge pump power to the corresponding power channel on the terminal. 2. Digital Channel: Antifuse FPGA devices use JTAG boundary scan ports for data transmission and reception. Connect the device's JTAG ports to a bus. TDO (JTAG output port) or PRX (device probe port) is used to characterize the operating status of each device, therefore it is connected to the digital channel through a separate port. 3. Analog Channel: A high-voltage programming channel unique to antifuse FPGA devices. Two types of programming channels are defined in the terminals. By connecting to the corresponding analog channel, stress screening of the device's antifuse array is achieved.

[0023] The schematic diagram of the old-fashioned driver board is as follows: Figure 2 As shown, the main control section consists of a microprocessor (MCU), the vector storage space consists of a high-capacity SD card, the power supply section consists of a multi-channel DC / DC power management chip, the digital channel section consists of an FPGA and a level conversion chip, and the analog channel section consists of a digital-to-analog converter (DAC) paired with a multi-channel amplifier. In addition, it is equipped with voltage and current acquisition modules, a display module, a status indicator module, an audible and visual alarm module, and a mode selection module, thus realizing the overall functionality. The following is a detailed explanation of the implementation process of the aging driver board.

[0024] The MCU main controller is responsible for scheduling and running the entire aging and screening process. After power-on initialization, it first reads and verifies the aging and screening voltage configuration file from the SD card. This file records the voltage conditions required for different aging processes. The MCU controller converts the contents of this file into an array that can be called by the DAC converter. Then, it controls the DC / DC power management chip to power on the devices on the aging station board according to the specified power-on sequence. After power-on, it collects real-time data through the voltage and current acquisition modules. In case of short circuit or overcurrent, it cuts off the power and records the fault, displaying the fault and issuing an audible and visual alarm. After entering normal operation, the MCU controller operates according to the set aging and screening process. It reads the corresponding operation execution file from the SD card and transfers the parsed data to the FPGA. The FPGA performs JTAG data transmission and reception. According to the voltage stress conditions specified in the execution file, the MCU controller calls the corresponding array value through the DAC to output the voltage to the multi-channel amplifier, realizing the corresponding analog channel voltage output.

[0025] Because antifuse FPGAs use JTAG boundary scan ports for serial data stream configuration, the bit stream length of the data frame increases with the size of the device, thus requiring more vector storage space. This device uses a high-capacity SD card for vector space storage, which can meet the vector space requirements of devices of different sizes. The FATFS file system is used for data operations, facilitating debugging and management.

[0026] The power supply for the aging and refining driver board is provided by a DC / DC power management chip. This chip is powered by a single 12V supply and generates four programmable output power supplies. The power-on sequence is controlled by the main control chip. It features high power efficiency, high current load, and low self-heating, and provides PWGood status indication and temperature sensor output for real-time monitoring by the main control MCU. In case of output voltage deviation or overheating due to overcurrent, the main control MCU can promptly cut off the power supply to prevent the components on the aging and refining station board from being burned out due to abnormal conditions.

[0027] The digital channel consists of an FPGA and a level conversion chip. The FPGA acts as an external memory for the main control MCU, which uses a DMA (Direct Memory Access) controller to achieve high-speed data transfer between the SD card and the FPGA. After reading the data, the FPGA decodes it, allocates the JTAG data stream to the designated digital channel, and reads the data from the TDO (JTAG Output Port) or PRX (Device Probe Port) on the rising edge of the JTAG clock, comparing it with the expected data. The running program file and the comparison results are output to the status indicator module to observe the operation of each station in the aging and screening process. The FPGA offers great flexibility in hardware configuration, meeting the data decoding requirements of different types of devices; the level conversion chip implements voltage transformation of the digital channel, covering the level requirements of different devices.

[0028] The analog channels consist of a DAC (Digital-to-Analog Converter) and a multi-channel amplifier in the main control MCU. The FPGA sends the parsed analog channel information back to the MCU controller to select the data from the corresponding aging screening voltage configuration array. This array contains voltage information for 17 analog channels, which are converted by two DAC controllers. One DAC controller performs direct data conversion and power amplification, outputting one VSV voltage for controlling the switching of the antifuse FPGA fuse array; the other DAC controller uses time-division multiplexing to sequentially output the voltage values ​​of 16 analog channels to the multi-channel amplifier to generate the VPP voltage applied to the fuse array, thus meeting the electrical stress requirements of antifuse FPGA devices of different sizes. The multi-channel amplifier consists of analog switches and a power amplification module. By switching the output voltages of the 16 analog channels and performing sample-and-hold and power amplification, it realizes the output of multiple analog channels.

[0029] The voltage and current acquisition module mainly collects voltage and current data from the power supply channel, displays the data in real time through the display module, and uploads the data periodically through the communication interface.

[0030] The display module consists of a 12864 LCD screen, used to display the model of the old and refined components and the real-time collected voltage and current information. If a fault occurs, the corresponding fault information will be displayed.

[0031] The status indicator module consists of an LED array, used to indicate the current aging process program information and the operating status of the aging station.

[0032] The audible and visual alarm module consists of a fault indicator light and a buzzer. When a short circuit, overcurrent, or overheating fault occurs, it will trigger an audible and visual alarm to prompt inspection personnel to troubleshoot the fault.

[0033] The mode selection module consists of DIP switches, allowing the main control MCU to operate in different modes, thus achieving configuration flexibility.

[0034] The above is an introduction to the implementation process of each module of the aging driver board. The modules are organically combined to form a unified whole, which realizes the requirement of aging and screening different types of antifuse FPGA devices.

[0035] Antifuse FPGAs are one-time programmable devices that use antifuses as logic configuration storage units. Unlike reconfigurable SRAM and flash FPGAs, antifuse FPGAs cannot be aging and screening their internal logic resources by repeatedly configuring test codes for different types of fault models. This invention addresses the characteristics of antifuse FPGAs by providing the hardware resources and software implementation scheme required for device aging and screening. It applies corresponding electrical stress to the internal logic resources, I / O ports, and antifuse cell array of the device in its unprogrammed state, eliminating early failures and achieving the purpose of aging and screening. This solves the problem of effective aging and screening of antifuse FPGAs in their unprogrammed state. This invention uses a JTAG boundary scan port for serial data stream configuration and is equipped with a large-capacity test code storage space and multiple programmable simulation channels. It provides and monitors the device's operating voltage and current, as well as its operating status in real time, meeting the hardware resource and bit stream capacity requirements of antifuse FPGAs of different types and sizes in aging and screening, and has wide applicability.

[0036] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A aging and screening device for antifuse type FPGA devices, characterized in that, It includes a data stream generation module, an aging driver board, and an aging station board. The data stream generation module is implemented using Matlab software. Through program design and algorithm iteration, it generates an excitation JTAG data stream file. The data stream generation module communicates with the aging driver board through a digital channel. The aging driver board and the aging station board are connected through a dedicated interface, which integrates a power channel, a digital channel, and an analog channel. The analog channel consists of a DAC (digital-to-analog converter) and a multi-channel amplifier in the main control MCU; The digital channel consists of an FPGA and a level conversion chip. The FPGA acts as an external memory for the main control MCU. The MCU uses a DMA controller to realize high-speed data transfer between the SD card and the FPGA. After the FPGA reads the data, it decodes it and allocates the JTAG data stream to the designated digital channel. It reads the TDO or PRX data on the rising edge of the JTAG clock and compares it with the expected data. The running program file and the comparison result are output to the status indicator module. The aging station board is laid out according to the shape and structure of the socket of the device being tested. The aging driver board integrates a microprocessor main control MCU, a large-capacity SD card, a voltage and current acquisition module, a display module, a status indicator module, an audible and visual alarm module, and a mode selection module. The main control MCU is connected to the large-capacity SD card, the display module, and the status indicator module through a built-in DMA controller. The main control MCU also integrates power management and is connected to an external DC / DC power management chip to form a power channel. The main control MCU is connected to the voltage and current acquisition module and the audible and visual alarm module through a built-in ADC converter to form a voltage and current judgment alarm loop. The main control MCU is connected to the mode selection module to form an operating mode setting function loop.

2. The aging and screening device for antifuse type FPGA devices according to claim 1, characterized in that: The power channel generates four programmable output power supplies, and the power-on sequence is controlled by the main control chip. The analog channel generates 17 programmable analog channel outputs to provide voltage to the programming ports specific to the antifuse FPGA device.

3. The aging and screening device for antifuse type FPGA devices according to claim 1, characterized in that: The high-capacity SD card serves as a vector storage space, storing stimulus JTAG files.

4. The aging and screening device for antifuse type FPGA devices according to claim 1, characterized in that: The data stream generation module is used to generate aging data stream files for a specified model of antifuse FPGA device and store them on an SD card.

5. The aging and screening device for antifuse type FPGA devices according to claim 1, characterized in that: The voltage and current acquisition module acquires the voltage and current of the power supply channel.

6. The aging and screening device for antifuse type FPGA devices according to claim 1, characterized in that: The main control MCU of the old-fashioned driver board reads the configuration information and JTAG data stream file from the SD card and transmits the data with the FPGA to configure the power channel, digital channel and analog channel, and to perform data acquisition and monitoring alarms.

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