A method for testing free carrier absorption loss and a battery sample

Abstract

The present invention belongs to the technical field of solar cells, and provides a method for testing free carrier absorption loss and a battery sample. The method includes: preparing a battery sample with a specific structure, the battery sample including a first region with no doping in the local areas of the front surface and the rear surface, a second region with a first heavily doped layer in the local area of the front surface and no doping in the local area of the rear surface, and a third region with no doping in the local area of the front surface and a second heavily doped layer in the local area of the rear surface; testing the external quantum efficiency of the first region, the second region and the third region in the near-infrared band; obtaining the integral current density values of the first region, the second region and the third region according to the external quantum efficiency of the first region, the second region and the third region and the AM1.5G spectrum; obtaining the free carrier absorption loss according to the integral current density values of the first region, the second region and the third region. This method is simpler to test, takes less time and has a lower cost, and can quickly and accurately achieve the quantitative detection of free carrier absorption loss.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a method for testing free carrier absorption loss and a battery sample. Background Art

[0002] Crystalline silicon solar cells are a common type of solar cell currently. The optical losses in crystalline silicon solar cells mainly include: metal grid line blocking loss, reflection loss, escape loss, transmission loss, recombination loss, and free carrier absorption loss. Among them, free carrier absorption refers to photons close to the semiconductor bandgap energy (with weak interband absorption) being absorbed by free electrons or holes in the semiconductor material, resulting in intraband transitions, and the energy of the photons is ultimately dissipated in the form of heat, without contributing to the photocurrent, which belongs to parasitic absorption. In crystalline silicon solar cells, due to the abundance of free electrons or holes in heavily doped semiconductors, free carrier absorption is particularly significant. Moreover, in crystalline silicon solar cells, it is inevitable to heavily dope the silicon wafer to form an emitter or a back surface field. On the one hand, through heavy doping, the built-in potential difference of the p-n junction is increased, and the intensity of the built-in electric field is enhanced, which helps with carrier separation and output of a high open-circuit voltage; on the other hand, in order to form a good ohmic contact between the metal electrode and the semiconductor, the semiconductor needs to be heavily doped into a degenerate state to ensure carrier collection. Due to the existence of heavy doping in crystalline silicon solar cells, there is always an optical loss of free carrier absorption in crystalline silicon solar cells.

[0003] In recent years, crystalline silicon solar cells with a passivated contact structure such as TOPCon and HJT have been favored by the market due to their advantages of high open-circuit voltage and high conversion efficiency, and are expected to become the mainstream crystalline silicon solar cells after P-type PERC solar cells. Passivated contact structures, such as the ultra-thin tunneling oxide layer and heavily doped polysilicon layer of TOPCon solar cells, and the ultra-thin intrinsic amorphous silicon layer and heavily doped amorphous silicon layer of HJT solar cells, not only have excellent interface passivation performance but also have excellent contact performance. However, whether it is the heavily doped polysilicon layer or the heavily doped amorphous silicon layer, they will both strengthen the heavy doping in crystalline silicon solar cells. Therefore, there will be serious free carrier absorption, resulting in a reduction in the short-circuit current of passivated contact solar cells and restricting the further improvement of battery efficiency.

[0004] With the continuous optimization of the performance of crystalline silicon solar cells, such as the continuous reduction of reflection loss, escape loss, and recombination loss, the free carrier absorption loss has become increasingly prominent. However, there is currently no direct experimental method to obtain the free carrier absorption loss. The conventional methods reported internationally, such as, include the following steps: 1) First, obtain the refractive index n value and extinction coefficient k value of the doped layer through a full-spectrum ellipsometer (wavelength coverage range of 300 - 1200 nm); 2) Prepare a cell sample with a doped layer and measure the reflectivity, transmittance, and spectral response data; 3) Use a commercial semiconductor simulation software, such as Sentaurus (such as "Efficiency Roadmap for Evolutionary Upgrades of PERC Solar Cells by TOPCon: Impact of Parasitic Absorption", Christoph Messmer et al., pages 1 - 2, IEEE JOURNAL OF PHOTOVOLTAICS, 2019), establish a corresponding optical model according to the structure of the cell sample, input the optical constant data n value and k value collected in 1) and the measured reflectivity, transmittance, and spectral response data in 2) into the optical model for optical fitting; 4) After multiple operations, when the reflectivity, transmittance, and spectral response data obtained by fitting form a self-consistency with the measured data in 2), the free carrier absorption loss can be measured.

[0005] However, this conventional method is extremely complex, time-consuming, and costly: for example, steps 1) and 2) both require preparing cell samples with different structures to obtain the optical constants (i.e., n value and k value) and measured data (i.e., reflectivity, transmittance, and spectral response data) respectively, which makes the test method complex, cumbersome, and time-consuming; and step 1) requires a special device - a full-spectrum ellipsometer to obtain the n value and k value, which increases the investment in test costs; the extraction of the n value and k value, as well as the collection of multiple measured data of reflectivity, transmittance, and spectral response, also makes the test method more complex and time-consuming; moreover, the investment in simulation software such as Sentaurus, and the simulation and fitting process in step 3) usually require large servers for operation, which further increases the cost investment of this test method and makes the test method more cumbersome and time-consuming. Based on this, developing a test method for free carrier absorption loss that is simple, time-saving, and low-cost to quickly and accurately achieve the quantitative calculation of free carrier absorption loss is of great significance for the structural design of solar cells (such as designing the doping structure and the materials used), process optimization, and improving cell efficiency. Summary of the Invention

[0006] One of the objectives of the present invention is to provide a method for testing free carrier absorption loss with simple testing method, short time consumption and low cost in view of the deficiencies of the prior art, so as to quickly and accurately achieve the quantitative calculation of free carrier absorption loss.

[0007] Another objective of the present invention is to provide a battery sample for testing free carrier absorption loss in view of the deficiencies of the prior art.

[0008] Based on this, the present invention discloses a method for testing free carrier absorption loss, including the following steps:

[0009] Step S1: Prepare a battery sample with a specific structure: perform local doping on both the front surface and the back surface of the silicon wafer to respectively form a first heavily doped layer and a second heavily doped layer with opposite conduction types; wherein, the battery sample includes a first region where both the upper and lower corresponding front surface local and back surface local are undoped, a second region where the upper and lower corresponding front surface local is provided with a first heavily doped layer and the back surface local is undoped, and a third region where the upper and lower corresponding front surface local is undoped and the back surface local is provided with a second heavily doped layer;

[0010] Step S2: Use a quantum efficiency tester to respectively test the external quantum efficiency of the first region, the second region and the third region of the battery sample in the near-infrared band;

[0011] Step S3: Obtain the free carrier absorption loss of the battery sample:

[0012] Step S31: According to the external quantum efficiency of the first region, the second region and the third region in the near-infrared band and the AM1.5G spectrum, respectively obtain the integrated current density values of the first region, the second region and the third region;

[0013] Step S32: According to the integrated current density values of the first region, the second region and the third region, obtain the free carrier absorption loss of the battery sample.

[0014] Preferably, the near-infrared band is 900 - 1200 nm;

[0015] In the step S31, the steps of respectively obtaining the integrated current density values of the first region, the second region and the third region according to the external quantum efficiency of the first region, the second region and the third region in the near-infrared band and the AM1.5G spectrum are as follows:

[0016] Respectively integrate the external quantum efficiency EQE(λ) of the first region, the second region and the third region with the AM1.5G spectrum through the following formula in the 900 - 1200 nm band to respectively calculate and obtain the integrated current density values J of the first region, the second region and the third region:

[0017]

[0018] In the formula, EQE(λ) is the external quantum efficiency, AM1.5G is the standard solar spectrum at an air mass of 1.5, q is the elementary charge, and its value is 1.6×10 -19 C; h is Planck's constant, and its value is 6.6×10 -34 J·s, c is the speed of light in vacuum, and its value is 3.0×10 8 m / s, λ is the wavelength, and the integration range is 900 - 1200 nm.

[0019] Further preferably, in step S32, the step of obtaining the free carrier absorption loss of the battery sample according to the integrated current density values of the first region, the second region, and the third region is as follows:

[0020] The difference between the integrated current density values of the first region and the second region is the free carrier absorption loss of the first heavily doped layer on the front surface of the battery sample, and the difference between the integrated current density values of the first region and the third region is the free carrier absorption loss of the second heavily doped layer on the back surface of the battery sample.

[0021] Preferably, the first heavily doped layer and / or the second heavily doped layer is a homojunction structure.

[0022] Further preferably, the homojunction structure is a single-crystal doped layer of N-type or P-type conductivity formed by thermal diffusion, ion implantation, or printing a doped paste;

[0023] The sheet resistance of the single-crystal doped layer is 10 - 500 Ω / sq, and the junction depth is 0.3 - 3 μm.

[0024] Preferably, the first heavily doped layer and / or the second heavily doped layer is a passivated contact structure.

[0025] Further preferably, the passivated contact structure includes a tunneling oxide layer and a heavily doped polysilicon layer arranged in a stack;

[0026] The thickness of the tunneling oxide layer is 0.5 - 3.0 nm;

[0027] The heavily doped polysilicon layer has N-type or P-type conductivity, a thickness of 30 - 600 nm, and a doping concentration of 0.1 - 8.0E+20 cm -3 .

[0028] Preferably, in step S1, the preparation steps of the battery sample include:

[0029] Step S11, forming a front heavily doped layer and a back heavily doped layer with opposite conductivity types on the front surface and the back surface of the silicon wafer respectively;

[0030] Step S12: Locally remove the front heavy doping layer on the front surface of the silicon wafer to obtain the first heavy doping layer, and locally remove the rear heavy doping layer on the rear surface of the silicon wafer to obtain the second heavy doping layer, so that the non-doped regions and the doped regions of the first heavy doping layer on the front surface of the silicon wafer are alternately arranged, the non-doped regions and the doped regions of the second heavy doping layer on the rear surface of the silicon wafer are alternately arranged, and the first heavy doping layer and the second heavy doping layer are arranged in a staggered manner up and down, so that the second region and the third region exist in the corresponding local parts of the front surface and the rear surface up and down, and the first region where the non-doped region on the front surface of the silicon wafer and the non-doped region on the rear surface of the silicon wafer are locally overlapped up and down;

[0031] Step S13: Deposit a first antireflection film on the front surface and a second antireflection film on the rear surface of the silicon wafer respectively;

[0032] Step S14: Prepare a first metal gate line on the front surface of the silicon wafer so that the end of the first metal gate line passes through the first antireflection film and is located on the first heavy doping layer; prepare a second metal gate line on the rear surface of the silicon wafer so that the end of the second metal gate line passes through the second antireflection film and is located on the second heavy doping layer.

[0033] Further preferably, before the step S11, it further includes: cleaning the silicon wafer to remove the damaged layer, and then performing the steps of texturing or polishing the silicon wafer.

[0034] Preferably, the conductivity type of the silicon wafer is N-type or P-type, the resistivity is 5-100 Ω·cm, and the thickness is 150-200 μm.

[0035] The present invention also discloses a battery sample for testing free carrier absorption loss, including: a silicon wafer, the front surface and the rear surface of the silicon wafer are respectively locally provided with a first heavy doping layer and a second heavy doping layer with opposite conductivity types, the first heavy doping layer and the second heavy doping layer are arranged in a staggered manner up and down, and the non-doped region on the front surface of the silicon wafer and the non-doped region on the rear surface of the silicon wafer are locally overlapped up and down; so that the battery sample includes a first region where the corresponding local parts of the front surface and the rear surface up and down are both non-doped, a second region where the corresponding local part of the front surface has a first heavy doping layer and the corresponding local part of the rear surface is non-doped, and a third region where the corresponding local part of the front surface is non-doped and the corresponding local part of the rear surface has a second heavy doping layer;

[0036] The non-doped regions and the doped regions on the front surface of the silicon wafer are provided with a first antireflection film, and the non-doped regions and the doped regions on the rear surface of the silicon wafer are provided with a second antireflection film; a first metal gate line with an end located on the first heavy doping layer is provided on the front surface of the silicon wafer, and a second metal gate line with an end located on the second heavy doping layer is provided on the rear surface of the silicon wafer.

[0037] Compared with the prior art, the present invention has at least the following beneficial effects:

[0038] 1. The testing process of the method of the present invention is simple, time-consuming short, and low-cost, meeting the requirements of large-scale and rapid testing by enterprises. The method for testing the free carrier absorption loss of the present invention only takes a total of 27 hours, while the conventional method reported internationally (hereinafter referred to as the conventional method) takes at least 72 hours. Therefore, the time consumption of the method of the present invention is significantly shortened and the testing is faster. The conventional method requires additional investment in a full-spectrum ellipsometer and simulation software such as Sentaurus compared to the method of the present invention. Therefore, the method of the present invention can also greatly save the investment in equipment costs. The method of the present invention only needs to prepare a battery sample with a specific structure in step 1. Compared with the conventional method, it omits the preparation process of a battery sample once, does not need to obtain multiple data such as n value and k value, and also omits the simulation and fitting process of simulation software such as Sentaurus and its complex calculation amount. Therefore, the testing process of the method of the present invention is simpler.

[0039] 2. The method of the present invention has high precision, accuracy, and repeatability. It can be accurate to 0.01 mA / cm 2 , with high precision. Compared with the values obtained by the conventional method, the free carrier absorption loss data obtained by the method of the present invention have very little difference, and the difference is within 0.03 mA / cm 2 , with high accuracy. The numerical differences of the free carrier absorption loss data measured from multiple battery samples with the same structure are all controlled within 0.03 mA / cm 2 . The test results of the battery samples prepared at different times (such as this week and last week) are also basically the same. Therefore, the repeatability is high.

[0040] 3. The method of the present invention has a wide testing range and is applicable not only to conventional crystalline silicon solar cells with a homojunction structure but also to crystalline silicon solar cells with a passivated contact structure.

[0041] 4. The method of the present invention can quantitatively calculate the current density loss caused by free carrier absorption in crystalline silicon solar cells.

[0042] Generally speaking, the method of the present invention can quickly and accurately test the free carrier absorption loss of crystalline silicon solar cells, laying an important foundation for the battery structure design (such as designing the doping structure and the materials used), process optimization, and improvement of battery efficiency of crystalline silicon solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic structural diagram of the battery sample prepared in Example 1 of the present invention.

[0044] Figure 2 is the external quantum efficiency response diagram of a specific area of the battery sample prepared in Example 1 of the present invention.

[0045] Figure 3 It is a schematic structural diagram of the battery sample prepared in Embodiment 2 of the present invention.

[0046] Figure 4 It is an external quantum efficiency response diagram of a specific area of the battery sample prepared in Embodiment 2 of the present invention.

[0047] Figure 5 It is a schematic structural diagram of the battery sample prepared in Embodiment 3 of the present invention.

[0048] Figure 6 It is an external quantum efficiency response diagram of a specific area of the battery sample prepared in Embodiment 3 of the present invention.

[0049] Explanation of the reference numerals in the drawings: 1 silicon wafer, 2 first heavily doped layer, 3 second heavily doped layer, 31 tunneling oxide layer, 32 heavily doped polysilicon layer, 4 first antireflection film, 5 second antireflection film, 6 first metal grid line, 7 second metal grid line, ① first region, ② second region, ③ third region. Detailed implementation manners

[0050] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with specific implementation manners.

[0051] A method for testing free carrier absorption loss of the present invention includes the following steps:

[0052] Step 1, prepare a battery sample with a specific structure (see Figure 1 and 3 ):

[0053] Step 11, select a silicon wafer 1 with a conductive type of N-type or P-type, and the resistivity of the silicon wafer 1 is 5 - 100 Ω·cm and the thickness is 150 - 200 μm. Clean the silicon wafer 1 to remove the damaged layer, and then texture or polish the silicon wafer 1.

[0054] Step 12, form a front heavily doped layer and a back heavily doped layer with opposite conductive types on the front surface and the back surface of the silicon wafer 1 respectively. For example, if the conductive type of the front heavily doped layer is P-type, then the conductive type of the back heavily doped layer is N-type; vice versa.

[0055] Step 13: Locally remove the front heavy doping layer on the front surface of the silicon wafer 1 to obtain a locally provided first heavy doping layer 2, and locally remove the back heavy doping layer on the back surface of the silicon wafer 1 to obtain a locally provided second heavy doping layer 3; so that the undoped regions and the doped regions of the first heavy doping layer 2 on the front surface of the silicon wafer 1 are alternately arranged, the undoped regions and the doped regions of the second heavy doping layer 3 on the back surface of the silicon wafer 1 are alternately arranged, and the first heavy doping layer 2 and the second heavy doping layer 3 are staggered up and down, the conductive types of the first heavy doping layer 2 and the second heavy doping layer 3 are opposite, and the undoped regions on the front surface of the silicon wafer 1 and the undoped regions on the back surface of the silicon wafer 1 are partially overlapped up and down.

[0056] Thus, through Step S12 and Step 13, local doping of the front surface and the back surface of the silicon wafer 1 is realized to respectively form a first heavy doping layer 2 and a second heavy doping layer 3 with opposite conductive types, so that the battery sample includes a first region ① where both the corresponding front surface part and the back surface part are undoped, a second region ② where the corresponding front surface part is provided with the first heavy doping layer 2 and the back surface part is undoped, and a third region ③ where the corresponding front surface part is undoped and the back surface part is provided with the second heavy doping layer 3; that is, after Step S12 and Step 13, the second region ② and the third region ③ exist in the corresponding front surface part and the back surface part up and down, and the first region ① where the undoped regions on the front surface of the silicon wafer 1 and the undoped regions on the back surface of the silicon wafer 1 are partially overlapped up and down exists.

[0057] An example of the present invention is that the first heavy doping layer 2 and / or the second heavy doping layer 3 is a homojunction structure (see Figure 1 ); the homojunction structure is a single-crystal doping layer with a conductive type of N-type or P-type formed by thermal diffusion, ion implantation or printing doping paste; the sheet resistance of the single-crystal doping layer is 10 - 500 Ω / sq, and the junction depth is 0.3 - 3 μm.

[0058] Another example of the present invention is that the first heavy doping layer 2 and / or the second heavy doping layer 3 is a passivated contact structure; the passivated contact structure is a tunneling oxide layer 31 and a heavily doped polysilicon layer 32 arranged in a stack (see Figure 3 ); the thickness of the tunneling oxide layer 31 is 0.5 - 3.0 nm; the conductive type of the heavily doped polysilicon layer 32 is N-type or P-type, the thickness is 30 - 600 nm, and the doping concentration is 0.1 - 8.0E+20 cm -3 .

[0059] Step 14: Deposit a first antireflection film 4 on the undoped regions and the doped regions corresponding to the first heavy doping layer 2 on the front surface of the silicon wafer 1, and then deposit a second antireflection film 5 on the undoped regions and the doped regions corresponding to the second heavy doping layer 3 on the back surface of the silicon wafer 1; that is, deposit the first antireflection film 4 and the second antireflection film 5 on the front surface and the back surface of the silicon wafer 1 respectively.

[0060] Among them, the first anti-reflection film 4 is one or a combination of alumina, silica, silicon nitride, silicon oxynitride, etc., and the second anti-reflection film 5 is one or a combination of alumina, silica, silicon nitride, silicon oxynitride, etc.; the thicknesses of the first anti-reflection film 4 and the second anti-reflection film 5 are 50 - 150 nm.

[0061] Step 15: Prepare the first metal grid line 6 on the front surface of the silicon wafer 1 so that the end of the first metal grid line 6 passes through the first anti-reflection film 4 and is located on the first heavily doped layer 2; prepare the second metal grid line 7 on the back surface of the silicon wafer 1 so that the end of the second metal grid line 7 passes through the second anti-reflection film 5 and is located on the second heavily doped layer 3.

[0062] Among them, the grid line material of the first metal grid line 6 is silver, silver-aluminum or aluminum, and the grid line material of the second metal grid line 7 is silver, silver-aluminum or aluminum. The grid line material is printed by screen printing. The widths of the first metal grid line 6 and the second metal grid line 7 are 30 - 50 μm, and the heights are 5 - 20 μm; after printing, high-temperature rapid sintering is carried out. The peak temperature of sintering is 760 - 820 °C, and the belt speed of sintering is 4.0 - 10.0 m / min.

[0063] A battery sample prepared in Step 1 for testing free carrier absorption loss, see Figure 1 and 3, including: a silicon wafer 1, a first heavily doped layer 2 is locally disposed on the front surface of the silicon wafer 1, so that the undoped regions on the front surface of the silicon wafer 1 and the doped regions corresponding to the first heavily doped layer 2 are alternately arranged, a second heavily doped layer 3 is locally disposed on the back surface of the silicon wafer 1, so that the undoped regions on the back surface of the silicon wafer 1 and the doped regions corresponding to the second heavily doped layer 3 are alternately arranged, and the first heavily doped layer 2 and the second heavily doped layer 3 are arranged in a staggered manner up and down, the conduction types of the first heavily doped layer 2 and the second heavily doped layer 3 are opposite, and there is a local vertical overlap between the undoped regions on the front surface and the undoped regions on the back surface; thus, the battery sample includes a first region ① where both the corresponding local front surface and the local back surface are undoped, a second region ② where the corresponding local front surface is provided with the first heavily doped layer 2 and the local back surface is undoped, and a third region ③ where the corresponding local front surface is undoped and the local back surface is provided with the second heavily doped layer 3; a first antireflection film 4 is disposed on both the undoped regions on the front surface of the silicon wafer 1 and the doped regions corresponding to the first heavily doped layer 2, and a second antireflection film 5 is disposed on both the undoped regions on the back surface of the silicon wafer 1 and the doped regions corresponding to the second heavily doped layer 3; a first metal grid line 6 is disposed on the front surface of the silicon wafer 1, the end of the first metal grid line 6 passes through the first antireflection film 4 and is located on the first heavily doped layer 2, and a second metal grid line 7 is disposed on the back surface of the silicon wafer 1, the end of the second metal grid line 7 passes through the second antireflection film 5 and is located on the second heavily doped layer 3. Step 1: Prepare a battery sample with the first region ①, the second region ② and the third region ③ having the above specific structure to realize the subsequent test of the free carrier absorption loss of the battery sample.

[0064] Step 2: Respectively test the external quantum efficiency EQE(λ) of the first region ①, the second region ② and the third region ③ of the battery sample in the near-infrared band.

[0065] In actual operation, place the battery sample on the platform of the quantum efficiency tester, and respectively test the external quantum efficiency EQE(λ) response diagrams of the first region ①, the second region ② and the third region ③ (as shown in Figure 2 and 4 ), and the test wavelength range is 900 - 1200 nm.

[0066] Step 3: Obtain the free carrier absorption loss of the battery sample:

[0067] Step 31: According to the external quantum efficiency and the AM1.5G spectrum of the first region ①, the second region ② and the third region ③ in the near-infrared band (i.e., 900 - 1200 nm), respectively obtain the integral current density values of the first region ①, the second region ② and the third region ③:

[0068] The external quantum efficiency EQE(λ) of the first region ①, the second region ②, and the third region ③ is integrated with the AM1.5G spectrum in the wavelength band of 900 - 1200 nm through the following formula to calculate the integrated current density values J of the first region ①, the second region ②, and the third region ③ respectively:

[0069]

[0070] In the formula, EQE(λ) is the external quantum efficiency, AM1.5G is the standard solar spectrum at an air mass of 1.5, q is the elementary charge, and its value is 1.6×10 -19 C; h is Planck's constant, and its value is 6.6×10 -34 J·s, c is the speed of light in vacuum, and its value is 3.0×10 8 m / s, λ is the wavelength, and the integration range is 900 - 1200 nm.

[0071] Step 32: Obtain the free carrier absorption loss of the battery sample according to the integrated current density values of the first region ①, the second region ②, and the third region ③:

[0072] The difference between the integrated current density values of the first region ① and the second region ② is the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample, and the difference between the integrated current density values of the first region ① and the third region ③ is the free carrier absorption loss of the second heavily doped layer 3 on the back surface of the battery sample.

[0073] The method for testing the free carrier absorption loss of the present invention has the following advantages:

[0074] 1. The testing process of this method is simple, time-consuming, and low-cost, meeting the requirements of large-scale and rapid testing by enterprises.

[0075] Among them, in the method for testing the free carrier absorption loss of the present invention, the preparation of the battery sample in step 1 takes 24 h, the testing time in step 2 takes 2 h, and the data processing and analysis for obtaining the free carrier absorption loss of the battery sample in step 3 takes 1 h. Therefore, the total time required for the method for testing the free carrier absorption loss of the present invention is 24 h + 2 h + 1 h = 27 h.

[0076] However, for the conventional method, it takes 24 hours to prepare a battery sample specifically for extracting the n value and the k value. Data analysis and the extraction of the n value and the k value take 12 hours, and a full-spectrum ellipsometer is required for the extraction of the n value and the k value. For step 2), it takes 24 hours to prepare a battery sample with a doping layer, 2 hours to collect data on reflectivity and transmittance, and 2 hours to collect data on spectral response. Among them, for step 2), the collection of reflectivity, transmittance, and spectral response can share the same device with the measurement of the external quantum efficiency in step 2 of the present invention. For step 3), a simulation software such as Sentaurus needs to be invested, and at least 6 hours are required for modeling (which can be reused subsequently after being established). For the process of simulation and fitting, if a large server is used for operation, it takes 1 to 2 hours, while if a personal computer is used, due to limited computing power, it takes at least 2 to 3 days, and the process of simulation and fitting is conservatively estimated to be 2 hours.

[0077] (a) Therefore, the conventional method takes at least: 24h + 12h + 24h + 4h + 6h + 2h = 72h. And the method of the present invention only takes 27h. Obviously, compared with the conventional method, the method of the present invention takes significantly less time and the test is faster. (b) Moreover, the conventional method requires more investment in a full-spectrum ellipsometer and a simulation software such as Sentaurus than the method of the present invention. Therefore, the method of the present invention can also greatly save the investment in equipment costs. (c) In addition, the method of the present invention only needs to prepare a battery sample with a specific structure in step 1. Compared with the conventional method, one preparation process of the battery sample is omitted. The method of the present invention only needs to measure the external quantum efficiency of the first region ①, the second region ②, and the third region ③ of the battery sample in the near-infrared band in step 2, and there is no need to obtain multiple data such as the n value and the k value. The simulation and fitting process of a simulation software such as Sentaurus and its complex computing amount are also omitted. Therefore, the test process of the method of the present invention is simpler.

[0078] 2. The method of the present invention has high precision, accuracy, and repeatability.

[0079] (a) The free carrier absorption loss of the battery sample measured by the method of the present invention can be accurate to two decimal places, that is, it can be accurate to 0.01 mA / cm 2 , with high precision; (b) Compared with the values measured by the conventional method, the data of the free carrier absorption loss of the battery sample measured by the present invention has a very small difference, and the difference is within 0.03 mA / cm 2 , with high accuracy; (c) The inventor prepares 6 battery samples with the same structure each time, and the numerical difference of the free carrier absorption loss data measured for each battery sample is controlled within 0.03 mA / cm 2 . The test results of the battery samples prepared at different times (such as this week and last week) are also basically the same. Therefore, the repeatability is high.

[0080] 3. The method of the present invention has a wide test range and is applicable not only to conventional crystalline silicon solar cells with a homojunction structure but also to crystalline silicon solar cells with a passivated contact structure.

[0081] 4. The method of the present invention can quantitatively calculate the current density loss caused by free carrier absorption in a crystalline silicon solar cell.

[0082] Generally speaking, the method of the present invention can quickly and accurately test the free carrier absorption loss of a crystalline silicon solar cell, which will lay an important foundation for the cell structure design, process optimization and cell efficiency improvement of crystalline silicon solar cells.

[0083] The following gives 3 embodiments of the above-mentioned method for testing free carrier absorption loss of the present invention; unless otherwise specified, the following Examples 1-3 all refer to the above-mentioned method for testing free carrier absorption loss and its cell samples.

[0084] Example 1

[0085] A method for testing free carrier absorption loss in this embodiment includes the following steps:

[0086] Step 1. Prepare a cell sample with a specific structure (see Figure 1 ):

[0087] Step 11. Select a silicon wafer 1 with a conductive type of N, a resistivity of 7 Ω·cm, and a thickness of 160 μm. Perform damage layer removal treatment on the silicon wafer 1, texture it, and then perform single-sided polishing on the back surface of the silicon wafer 1 to obtain a silicon wafer 1 with a front surface being a textured surface and a back surface being a polished surface.

[0088] Step 12. Form a front heavily doped layer and a back heavily doped layer with opposite conductive types on the front surface and the back surface of the silicon wafer 1 respectively. In actual operation, by means of ion implantation, boron ions are implanted into the front surface of the silicon wafer 1, while phosphorus ions are implanted into the back surface of the silicon wafer 1, and then annealing treatment is carried out to activate the doped boron ions or phosphorus ions. After annealing, a boron-doped emitter, that is, a front heavily doped layer, is formed on the front surface of the silicon wafer 1, and a phosphorus-doped back surface field, that is, a back heavily doped layer, is formed on the back surface of the silicon wafer 1.

[0089] Among them, the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) is 100-150 Ω / sq, the junction depth is 0.7-0.9 μm, and the peak concentration is 1.0-2.0E+19 cm -3 ; the sheet resistance of the back heavily doped layer (corresponding to the second heavily doped layer 3) is 80-90 Ω / sq, the junction depth is 0.4-0.6 μm, and the peak concentration is 8.0-10.0E+19 cm -3 .

[0090] Step 13: Deposit masks on both the front surface and the back surface of the silicon wafer 1 to locally remove the front heavy doping layer on the front surface of the silicon wafer 1 to obtain a locally arranged first heavy doping layer 2, and locally remove the back heavy doping layer on the back surface of the silicon wafer 1 to obtain a locally arranged second heavy doping layer 3. The surface topography of the removed area remains the same as before removal (i.e., the front surface of the silicon wafer 1 is a matte surface and the back surface is a polished surface). After removal, the non-doped areas on the front surface of the silicon wafer 1 and the doped areas corresponding to the first heavy doping layer 2 are alternately arranged, while the non-doped areas on the back surface of the silicon wafer 1 and the doped areas corresponding to the second heavy doping layer 3 are alternately arranged, and the first heavy doping layer 2 and the second heavy doping layer 3 are arranged in a staggered manner up and down, and there is a partial vertical overlap between the non-doped areas on the front surface and the non-doped areas on the back surface. In this way, there are three different regions in the prepared battery sample: the first region ① where both the locally corresponding front surface and the back surface are not doped, the second region ② where the locally corresponding front surface has the first heavy doping layer 2 and the back surface is not doped, and the third region ③ where the locally corresponding front surface is not doped and the back surface has the second heavy doping layer 3.

[0091] Step 14: Deposit the first antireflection film 4 and the second antireflection film 5 on the front surface and the back surface of the silicon wafer 1 respectively. In actual operation, an aluminum oxide film with a thickness of 0.5 - 5.0 nm is deposited on the non-doped areas and the doped areas corresponding to the first heavy doping layer 2 on the front surface of the silicon wafer 1 by ALD method, and then a SiNx antireflection film with a thickness of 60 - 85 nm is deposited by PECVD method to form the first antireflection film 4 with a laminated structure of the aluminum oxide film and the SiNx antireflection film. Then, a SiNx antireflection film with a thickness of 60 - 85 nm is deposited on the non-doped areas and the doped areas corresponding to the second heavy doping layer 3 on the back surface of the silicon wafer 1 by PECVD method to form the second antireflection film 5.

[0092] Step 15: Screen-print the grid line materials on the front surface and the back surface of the silicon wafer 1. Among them, the grid line material on the front surface is located on the first heavy doping layer 2, and the grid line material on the back surface is located on the second heavy doping layer 3. Then, high-temperature rapid sintering is carried out to obtain the first metal grid line 6 and the second metal grid line 7.

[0093] So far, the preparation of a battery sample for testing free carrier absorption loss is completed, and its structure is as Figure 1As shown in the figure, it includes: a silicon wafer 1, a first heavily doped layer 2 and a second heavily doped layer 3 with opposite conductive types are locally provided on the front surface and the back surface of the silicon wafer 1 respectively. The first heavily doped layer 2 and the second heavily doped layer 3 are arranged in a staggered manner up and down, and the non-doped regions on the front surface and the back surface of the silicon wafer 1 are partially overlapped up and down; so that the battery sample includes a first region ① where both the corresponding upper and lower front surface parts and the back surface parts are undoped, a second region ② where the corresponding upper front surface part has the first heavily doped layer 2 and the lower back surface part is undoped, and a third region ③ where the corresponding upper front surface part is undoped and the lower back surface part has the second heavily doped layer 3; a first antireflection film 4 is provided on both the non-doped region and the doped region of the front surface of the silicon wafer 1, and a second antireflection film 5 is provided on both the non-doped region and the doped region of the back surface of the silicon wafer 1; a first metal grid line 6 with an end located on the first heavily doped layer 2 is provided on the front surface of the silicon wafer 1, and a second metal grid line 7 with an end located on the second heavily doped layer 3 is provided on the back surface of the silicon wafer 1.

[0094] Step 2: Place the battery sample on the platform of the quantum efficiency tester, and respectively test the external quantum efficiency EQE(λ) response diagrams of the first region ①, the second region ② and the third region ③ (see Figure 2 ), and the test wavelength range is 900 - 1200 nm.

[0095] Step 3: Obtain the free carrier absorption loss of the battery sample:

[0096] Step 31: Respectively integrate the external quantum efficiency EQE(λ) of the first region ①, the second region ② and the third region ③ with the AM1.5G spectrum through the following formula in the wavelength range of 900 - 1200 nm to respectively calculate the integrated current density values J of the first region ①, the second region ② and the third region ③:

[0097]

[0098] In the formula, EQE(λ) is the external quantum efficiency, AM1.5G is the standard solar spectrum when the air mass is 1.5, q is the elementary charge, and its value is 1.6×10 -19 C; h is the Planck constant, and its value is 6.6×10 -34 J·s, c is the speed of light in vacuum, and its value is 3.0×10 8 m / s, λ is the wavelength, and the integration range is 900 - 1200 nm.

[0099] Step 32: Subtract the integrated current density value of the second region ② from the integrated current density value of the first region ① to obtain the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample. Subtract the integrated current density value of the third region ③ from the integrated current density value of the first region ① to obtain the free carrier absorption loss of the second heavily doped layer 3 on the back surface of the battery sample.

[0100] The integral current density values and differences of the first region ①, the second region ②, and the third region ③ of the battery sample measured by the method of this embodiment are shown in Table 1 below:

[0101] Table 1

[0102]

[0103] Referring to Table 1, it can be seen that in this embodiment, the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample is 0.15 mA / cm 2 , and the free carrier absorption loss of the second heavily doped layer 3 on the back surface of the battery sample is 0.26 mA / cm 2 . By using the conventional method, the free carrier absorption loss of the heavily doped layer on the front surface of the battery sample is 0.13 mA / cm 2 , and the free carrier absorption loss of the heavily doped layer on the back surface of the battery sample is 0.27 mA / cm 2 . It can be seen that the difference between the method of this embodiment and the conventional method is within 0.03 mA / cm 2 .

[0104] Example 2

[0105] A method for testing free carrier absorption loss in this embodiment, the specific steps refer to Example 1, and the differences from Example 1 are as follows:

[0106] In step 11, the resistivity of the silicon wafer 1 selected is 5 Ω·cm.

[0107] In step 12, referring to Figure 3 , the preparation process of the front heavily doped layer on the front surface of the silicon wafer 1 is the same as that in Example 1, while the back surface of the silicon wafer 1 is changed to sequentially deposit an ultrathin tunneling oxide layer 31 and an in-situ phosphorus-doped polysilicon layer (i.e., a heavily doped polysilicon layer 32). Therefore, after annealing, a passivation contact structure composed of the tunneling oxide layer 31 and the phosphorus-doped polysilicon layer is formed on the back surface of the silicon wafer 1 as the back heavily doped layer.

[0108] Among them, the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) in this embodiment is 130 - 170 Ω / sq, the junction depth is 0.8 - 1.0 μm, and the peak concentration is 0.7 - 1.0E+19 cm -3 ; in the back heavily doped layer (corresponding to the second heavily doped layer 3), the material of the tunneling oxide layer 31 is silicon dioxide, the thickness is 1.0 - 2.0 nm, the thickness of the phosphorus-doped polysilicon layer is 100 - 150 nm, and the doping concentration is 1.0 - 3.0E+20 cm -3 .

[0109] The structure of a battery sample for testing free carrier absorption loss in this embodiment is as follows Figure 3 as shown. Its structure refers to the battery sample in Embodiment 1. The difference between it and the battery sample in Embodiment 1 is that: the second heavily doped layer 3 is a tunneling oxide layer 31 and a phosphorus-doped polysilicon layer that are locally arranged and stacked.

[0110] In step 2, the external quantum efficiency EQE(λ) response maps of the first region ①, the second region ②, and the third region ③ are respectively tested (see Figure 4 ), and the tested wavelength range is 900 - 1200 nm.

[0111] The integral current density values and differences of the first region ①, the second region ②, and the third region ③ of the battery sample measured by the method of this embodiment are shown in Table 2 below:

[0112]

[0113] As can be seen from Table 2, in this embodiment, the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the measured battery sample is 0.12 mA / cm 2 , and the free carrier absorption loss of the second heavily doped layer 3 on the back surface of the battery sample is 0.32 mA / cm 2 . By using the conventional method, the free carrier absorption loss of the heavily doped layer on the front surface of the measured battery sample is 0.12 mA / cm 2 , and the free carrier absorption loss of the heavily doped layer on the back surface of the battery sample is 0.35 mA / cm 2 . It can be seen that the difference between the method of this embodiment and the conventional method is within 0.03 mA / cm 2 .

[0114] Embodiment 3

[0115] A method for testing free carrier absorption loss in this embodiment, its specific steps refer to Embodiment 1, and the differences from Embodiment 1 are as follows:

[0116] In step 11, the resistivity of the silicon wafer 1 selected is 5 Ω·cm, and the conduction type is P-type.

[0117] In step 12, see Figure 5 , phosphorus ion implantation is performed on the front surface of the silicon wafer 1. Therefore, after annealing, a phosphorus-doped emitter, that is, a front heavily doped layer, is formed on the front surface of the silicon wafer 1; while the back surface of the silicon wafer 1 is not doped, so the back heavily doped layer in Embodiment 1 is omitted. Among them, the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) is 90 - 120 Ω / sq, the junction depth is 0.4 - 0.6 μm, and the peak concentration is 6.0 - 8.0E+19 cm -3 .

[0118] In step 13, the second doped layer 3 with local setting and its preparation process are omitted. Therefore, the battery sample prepared in this embodiment only has the first region ① and the second region ②.

[0119] In step 14, a 60 - 85 nm SiNx antireflection film is deposited on the undoped region and the doped region corresponding to the first doped layer 2 on the front surface of the silicon wafer 1 by PECVD method to form the first antireflection film 4; then, an alumina thin film with a thickness of 5 - 20 nm is deposited on the back surface of the silicon wafer 1 by ALD method, and then an 80 - 100 nm SiNx antireflection film is deposited by PECVD method to form the second antireflection film 5 with a stacked structure of an alumina thin film and a SiNx antireflection film.

[0120] In step 15, the gate line material of the first metal gate line 6 is silver, and the end of the second metal gate line 7 passes through the second antireflection film 5 and is located on the silicon wafer 1. The gate line material of the second metal gate line 7 is aluminum.

[0121] The structure of a battery sample for testing free - carrier absorption loss in this embodiment is as Figure 5 shown. Its structure refers to the battery sample of Embodiment 1. The difference between it and the battery sample of Embodiment 1 is that the second doped layer 3 is omitted, the second antireflection film 5 is directly set on the back surface of the silicon wafer 1, and the battery sample of this embodiment only contains the first region ① and the second region ②.

[0122] In step 2, as shown in Figure 6 , the external quantum efficiency EQE(λ) response diagrams of the first region ① and the second region ② of the battery sample can be measured respectively (the test wavelength range is 900 - 1200 nm).

[0123] In step 31, the integrated current density values of the first region ① and the second region ② are obtained.

[0124] In step 32, the integrated current density value of the first region ① is subtracted from the integrated current density value of the second region ② to obtain the free - carrier absorption loss of the first doped layer 2 on the front surface of the battery sample.

[0125] The integrated current density values and the difference values of the first region ① and the second region ② of the battery sample measured by the method of this embodiment are shown in Table 3 below:

[0126] Table 3

[0127]

[0128] Referring to Table 3, it can be seen that in this embodiment, the free - carrier absorption loss of the first doped layer 2 on the front surface of the measured battery sample is 0.13 mA / cm 2For the battery sample measured by the conventional method, the free carrier absorption loss of the heavily doped layer on the front surface is 0.12 mA / cm 2 It can be seen that the difference between the method of this embodiment and the conventional method is within 0.03 mA / cm 2 .

[0129] In summary, the method of the present invention can quickly and accurately measure the free carrier absorption loss of crystalline silicon solar cells, which will lay an important foundation for the battery structure design, process optimization and battery efficiency improvement of crystalline silicon solar cells.

[0130] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0131] The technical solutions provided by the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for testing free carrier absorption loss, characterized in that, It includes the following steps: Step S1, preparing a battery sample with a specific structure: performing local doping on both the front surface and the back surface of the silicon wafer to respectively form a first heavily doped layer and a second heavily doped layer with opposite conduction types; wherein, the battery sample includes a first region where both the upper and lower corresponding front surface part and back surface part are undoped, a second region where the upper and lower corresponding front surface part is provided with the first heavily doped layer and the back surface part is undoped, and a third region where the upper and lower corresponding front surface part is undoped and the back surface part is provided with the second heavily doped layer; Step S2, respectively testing the external quantum efficiency of the first region, the second region, and the third region of the battery sample in the near-infrared band; Step S3, obtaining the free carrier absorption loss of the battery sample: Step S31, respectively obtaining the integrated current density values of the first region, the second region, and the third region according to the external quantum efficiency of the first region, the second region, and the third region in the near-infrared band and the AM1.5G spectrum; Step S32, obtaining the free carrier absorption loss of the battery sample according to the integrated current density values of the first region, the second region, and the third region; In the said step S32, the step of obtaining the free carrier absorption loss of the battery sample according to the integrated current density values of the first region, the second region, and the third region is: The difference between the integrated current density values of the first region and the second region is the free carrier absorption loss of the first heavily doped layer on the front surface of the battery sample, and the difference between the integrated current density values of the first region and the third region is the free carrier absorption loss of the second heavily doped layer on the back surface of the battery sample.

2. The method for testing the free carrier absorption loss according to claim 1, wherein The said near-infrared band is 900 - 1200 nm; In the said step S31, the step of respectively obtaining the integrated current density values of the first region, the second region, and the third region according to the external quantum efficiency of the first region, the second region, and the third region in the near-infrared band and the AM1.5G spectrum is: Respectively integrating the external quantum efficiency EQE(λ) of the first region, the second region, and the third region with the AM1.5G spectrum through the following formula in the 900 - 1200 nm band to respectively calculate and obtain the integrated current density values J of the first region, the second region, and the third region: In the formula, EQE(λ) is the external quantum efficiency, AM1.5G is the standard solar spectrum at an air mass of 1.5, q is the elementary charge with a value of 1.6×10 -19 C; h is the Planck constant with a value of 6.6×10 -34 J·s, c is the speed of light in vacuum with a value of 3.0×10 8 m / s, λ is the wavelength, and the integration range is 900 - 1200 nm.

3. A method for testing free carrier absorption loss according to claim 1, characterized in that, The said first heavily doped layer and / or the second heavily doped layer is a homojunction structure.

4. The method for testing free carrier absorption loss according to claim 3, characterized in that, The said homojunction structure is a single-crystal doped layer with a conduction type of N-type or P-type formed by thermal diffusion, ion implantation, or printing doping paste; The sheet resistance of the said single-crystal doped layer is 10 - 500 Ω / sq, and the junction depth is 0.3 - 3 μm.

5. A method for testing free carrier absorption loss according to claim 1, characterized in that The said first heavily doped layer and / or the second heavily doped layer is a passivated contact structure.

6. The method for testing free carrier absorption loss according to claim 5, wherein The said passivated contact structure includes a tunneling oxide layer and a heavily doped polysilicon layer arranged in a stack; The thickness of the said tunneling oxide layer is 0.5 - 3.0 nm; The conductivity type of the heavily doped polysilicon layer is N-type or P-type, the thickness is 30 to 600 nm, and the doping concentration is 0.1 to 8.0E+20 cm -3 .

7. A method for testing the free carrier absorption loss according to any one of claims 1-6, characterized in that, In the said step S1, the preparation steps of the battery sample include: Step S11, respectively forming a front heavily doped layer and a back heavily doped layer with opposite conduction types on the front surface and the back surface of the silicon wafer; Step S12: Locally remove the front heavy doping layer on the front surface of the silicon wafer to obtain the first heavy doping layer, and locally remove the back heavy doping layer on the back surface of the silicon wafer to obtain the second heavy doping layer, so that the undoped regions and the doped regions of the first heavy doping layer on the front surface of the silicon wafer are alternately arranged, the undoped regions and the doped regions of the second heavy doping layer on the back surface of the silicon wafer are alternately arranged, and the first heavy doping layer and the second heavy doping layer are arranged in a staggered manner up and down, so that the second region and the third region exist in the corresponding local parts of the front surface and the back surface, and the undoped region on the front surface of the silicon wafer and the undoped region on the back surface of the silicon wafer have the first region that is locally overlapped up and down; Step S13: Deposit a first antireflection film and a second antireflection film on the front surface and the back surface of the silicon wafer respectively; Step S14: Prepare a first metal gate line on the front surface of the silicon wafer, so that the end of the first metal gate line passes through the first antireflection film and is located on the first heavy doping layer; prepare a second metal gate line on the back surface of the silicon wafer, so that the end of the second metal gate line passes through the second antireflection film and is located on the second heavy doping layer.

8. A method for testing free carrier absorption loss according to claim 7, characterized in that, Before the step S11, it further includes: cleaning the silicon wafer to remove the damaged layer, and then performing a texturing or polishing step on the silicon wafer.

9. The method for testing the free carrier absorption loss according to claim 1, characterized in that, The conductivity type of the silicon wafer is N-type or P-type, the resistivity is 5-100 Ω·cm, and the thickness is 150-200 μm.

10. A battery sample for testing free carrier absorption loss, characterized in that, The battery sample is prepared by using the step S1 of a method for testing the free carrier absorption loss according to any one of claims 1-9; the battery sample includes: a silicon wafer, and the front surface and the back surface of the silicon wafer are respectively locally provided with a first heavy doping layer and a second heavy doping layer with opposite conductivity types, the first heavy doping layer and the second heavy doping layer are arranged in a staggered manner up and down, and the undoped region on the front surface of the silicon wafer and the undoped region on the back surface of the silicon wafer are locally overlapped up and down; so that the battery sample includes a first region where there is no doping in the corresponding local parts of the front surface and the back surface, a second region where there is a first heavy doping layer in the corresponding local part of the front surface and no doping in the corresponding local part of the back surface, and a third region where there is no doping in the corresponding local part of the front surface and a second heavy doping layer in the corresponding local part of the back surface; The first antireflection film is provided on the undoped region and the doped region on the front surface of the silicon wafer, and the second antireflection film is provided on the undoped region and the doped region on the back surface of the silicon wafer; the first metal gate line with the end located on the first heavy doping layer is provided on the front surface of the silicon wafer, and the second metal gate line with the end located on the second heavy doping layer is provided on the back surface of the silicon wafer.

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