A task processing method and device

Abstract

Embodiments of the present application disclose a task processing method and device, which are used for loading instructions required by a task from a memory to a cache before a processor executes the task, so as to improve the speed of the processor executing the task. The task processing method comprises the following steps: a processor acquires a task, the task being a task waiting for execution; the processor determines instructions required in a process of executing the task according to the task; the processor triggers the cache to load the required instructions from the memory to the cache; and the processor executes the task according to the required instructions in the cache.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a task processing method and apparatus. Background Technology

[0002] During task execution, the processor can obtain corresponding data and instructions based on the received task, and then execute the task according to the instructions. An instruction is a command that directs the processor to perform a certain operation or processing function. Clearly, assuming the processor's processing power remains constant, the faster the processor can obtain instructions, the faster it can execute the task. In traditional technology, instructions are stored in memory. Therefore, the processor can obtain instructions from memory when executing a task.

[0003] To improve the speed at which a processor fetches instructions, some instructions stored in memory can be loaded into a cache. A cache is a storage device whose data exchange speed is faster than that of main memory. When executing a task, the processor can fetch instructions from the cache. Because the cache has a faster data exchange speed, the processor's instruction fetching time is shorter. Therefore, storing instructions in the cache can improve the processor's instruction fetching speed, thereby improving the speed of task execution.

[0004] However, during task execution, if the cache does not contain the instructions required for the task, the cache needs to load the instructions from memory. Because memory data exchange is slow, loading instructions from memory takes a considerable amount of time. During this time, the processor has no executable instructions and cannot continue executing the task, resulting in a slower task execution speed. Summary of the Invention

[0005] This application provides a task processing method and apparatus, which enables the cache to load the instructions required for executing the task into the cache before the processor executes the task, thereby improving the speed of the processor executing the task.

[0006] Firstly, embodiments of this application provide a task processing method applied to a processor. Before executing a task, the processor can first acquire the task awaiting execution and determine the instructions required to execute the task, i.e., the instructions the processor needs to read during task execution. Then, the processor can trigger a cache to load the instructions required for task execution from memory into the cache, thereby executing the task according to the instructions stored in the cache. The data exchange speed of the cache is faster than that of the memory. In this way, any instruction required by the processor to execute a task is loaded into the cache before execution. During task execution, every instruction required by the processor can be found in the cache, eliminating the need for the cache to load instructions from memory during task execution. Compared to traditional technologies, because the cache does not need to read instructions from memory with a slower data exchange speed, the processor can read instructions from the cache much faster. This ensures that the processor can quickly acquire instructions during task execution, thereby improving the processor's task execution speed.

[0007] In one possible implementation, when the processor triggers the cache to load instructions, it can first obtain the addresses of the instructions required for executing the task stored in memory, send these addresses to the cache, and trigger the cache to load the required instructions from memory into the cache based on the addresses. In this way, the cache can determine whether the instruction exists in the cache based on its memory address, and then load the instruction from memory if the cache does not contain the required instructions.

[0008] In one possible implementation, the instructions required to execute a task can be determined by the cache. The processor can send a task waiting to be executed to the cache, triggering the cache to determine the instructions needed to execute the task based on the task.

[0009] In one possible implementation, when the instructions for executing a task are determined by the cache, the cache, triggered by the processor, can determine the addresses in memory where the instructions required to execute the task are stored, based on the task awaiting execution, and thus determine whether these instructions have been loaded into the cache. If the cache does not contain any instructions for executing the task, the processor can trigger the cache to load the instructions required to execute the task from memory according to the addresses.

[0010] In one possible implementation, the tasks awaiting execution can be pre-configured. The processor can obtain task configuration information, i.e., information about the pre-configured tasks, such as task table entries. Then, when determining the instructions to execute a task, the processor can use this task information to determine the instructions required during task execution.

[0011] In one possible implementation, the processor can determine the tasks awaiting execution based on information required for processing the tasks. The processor can receive information necessary for processing the tasks awaiting execution. This information may include, for example, context information of a message, including parameters that may be used when processing the message. The processor can predict the tasks awaiting execution based on this required information.

[0012] In one possible implementation, the processor can read the instructions needed to execute a task from the cache and execute the task accordingly. After reading the instructions from the cache, the processor can release the cache space occupied by the read instructions, thereby improving cache space utilization.

[0013] In one possible implementation, the cache may include at least one sub-cell. Then, when the processor triggers the cache to load instructions from memory required to execute a task, it can trigger the cache to load the required instructions from memory into one or more cache sub-cells. Correspondingly, when the processor reads instructions from the cache, it can load instructions from one or more cache sub-cells storing the instructions required to execute the task.

[0014] In one possible implementation, when the cache includes at least one cache sub-unit, the processor can set a counter for each of the at least one cache sub-units. After the cache loads the instructions required to execute a task from memory, the processor can determine a target value based on the number of times the instructions stored in each of the at least one cache sub-units need to be read during task execution, and increment the counter of the corresponding cache sub-unit by the target value. Correspondingly, after the processor reads instructions from a cache sub-unit, the processor can decrement the counter of that cache sub-unit based on the number of times the instructions have been read. Then, after the processor has read all the instructions required to execute the task, the processor can subtract the target value from the counter of each of the at least one cache sub-units. This allows the counter to record the number of times the instructions stored in the cache sub-units have been read. If the read count for a cache sub-unit is exhausted, it means the processor no longer needs to read the instructions stored in that cache sub-unit, and the processor can release the cache space of that cache sub-unit. In this way, cache space occupied by instructions can be released in a timely manner.

[0015] In some possible implementations, before the processor triggers the cache to load instructions from memory into the cache, the processor may check if the instructions required to perform the task exist in the cache. If the instructions are in the cache, the processor can read them from the cache and execute the task. If the instructions are not in the cache, the processor may trigger the cache to load the necessary instructions from memory.

[0016] In some possible implementations, the tasks waiting to be performed may include any one or more of message forwarding, tunnel establishment, and message inspection.

[0017] Secondly, embodiments of this application provide an integrated circuit, the integrated circuit processor chip including a control circuit and an interface circuit; wherein, the interface circuit is used to acquire a task, the task being a task waiting to be executed; the control circuit is used to determine, according to the task, the instructions required for executing the task, trigger a cache to load the required instructions from memory into the cache, and execute the task according to the required instructions in the cache.

[0018] In some possible implementations, the control circuitry is configured to obtain the address of the required instruction stored in the memory and trigger the cache to load the required instruction from the memory into the cache according to the address.

[0019] In some possible implementations, the control circuitry is used to trigger the cache to determine the instructions required to execute the task based on the task.

[0020] In some possible implementations, the control circuitry is configured to trigger the cache to retrieve the address of the required instruction stored in the memory according to the task; and trigger the cache to load the required instruction from the memory into the cache according to the address.

[0021] In some possible implementations, the interface circuit is used to acquire task configuration information, which is information about the pre-configured task; the control circuit is used to determine the instructions required to execute the task based on the task configuration information.

[0022] In some possible implementations, the interface circuit is used to acquire information required to process the task and to predict the task based on the required information.

[0023] In some possible implementations, the control circuitry is configured to read the required instructions from the cache and execute the task according to the required instructions; after reading the required instructions from the cache, it is configured to release the cache space occupied by the required instructions.

[0024] In some possible implementations, the cache includes at least one cache sub-unit; the control circuitry is configured to trigger the cache to load the required instruction from memory into the at least one cache sub-unit; and after reading the required instruction from the cache, to read the required instruction from the at least one cache sub-unit.

[0025] In some possible implementations, the control circuitry is configured to control the counter of each cache sub-unit in the at least one cache sub-unit to increment by a target value, the target value being equal to the number of reads of the required instruction cached by the cache sub-unit; after the required instruction is read from the cache, the value of the counter of each cache sub-unit is decremented by the target value according to the number of reads of the required instruction.

[0026] In some possible implementations, the control circuitry is configured to confirm that the required instruction does not exist in the cache before triggering the cache to load the required instruction from memory into the cache.

[0027] In some possible implementations, the task includes at least one of the following: message forwarding, tunnel establishment, and message detection.

[0028] Thirdly, embodiments of this application provide a message processing apparatus, which includes an acquisition unit and a processing unit; the acquisition unit is used to acquire a task, the task being a task waiting to be executed; the processing unit is used to determine, based on the task, instructions required for executing the task; trigger a cache to load the required instructions from memory into the cache; and execute the task based on the required instructions in the cache.

[0029] Fourthly, embodiments of this application provide a chip, the chip including a memory and a processor, the memory for storing instructions or program code, and the processor for calling and running the instructions or program code from the memory to perform the task processing method as described in the first aspect above.

[0030] Fifthly, embodiments of this application provide an apparatus comprising a processor chip and a memory, the memory being used to store instructions or program code, and the processor chip being used to call and run the instructions or program code from the memory to perform the task processing method as described in the first aspect above.

[0031] In a sixth aspect, embodiments of this application provide a computer-readable storage medium including instructions, programs, or code that, when executed on a computer, cause the computer to perform the task processing method as described in the first aspect above. Attached Figure Description

[0032] Figure 1 A schematic diagram of the structure of a processor provided in an embodiment of this application;

[0033] Figure 2 A schematic diagram of the device provided in an embodiment of this application;

[0034] Figure 3The method flow of the task processing method provided in the embodiments of this application;

[0035] Figure 4 A schematic diagram of the structure of a network device provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram illustrating the data interaction process within a network device as provided in an embodiment of this application.

[0037] Figure 6 A schematic diagram of the structure of an integrated circuit 600 provided in an embodiment of this application;

[0038] Figure 7 A schematic diagram of a message processing apparatus 700 provided in an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of the structure of a chip 800 provided in an embodiment of this application;

[0040] Figure 9 This is a schematic diagram of the structure of a device 900 provided in an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of the structure of a device 1000 provided in an embodiment of this application. Detailed Implementation

[0042] The following description, in conjunction with the accompanying drawings, introduces the conventional techniques and the task processing methods and apparatus provided by the embodiments of this application.

[0043] First, the basic architecture of a processor will be introduced. (See also...) Figure 1 The figure shows a schematic diagram of a processor 100. The processor 100 includes a processor core 110 and a processor core 120. The processor core 110 includes a processing unit 111 and a cache 112. Similarly, the processor core 120 may include a processing unit 121 and a cache. The cache 112 is used to load instructions from other memory (such as RAM) within the computer, and the processing unit 111 is used to read instructions from the cache 112 and perform tasks such as data processing and message forwarding according to the instructions. If the processor 100 is packaged into a chip, the resulting chip can be called a central processing unit (CPU).

[0044] exist Figure 1In the illustrated embodiment, processor 100 includes two processor cores, each of which includes a processing unit and a cache. The cache is encapsulated within the processor core of the processor chip. In some other implementations, the processor may include one processor core or more than two processor cores. The cache may be encapsulated inside the processor chip, outside the processor core, or as a storage device independent of the processor. This application does not limit the number of processor cores or the location of the cache encapsulation.

[0045] A cache, short for high-speed buffer memory, is mostly composed of storage devices with high data exchange speeds. In the embodiments of this application, a cache may also be referred to as temporary memory or temporary storage. The cache is connected to both the processing unit inside the processor and the external memory, and can store some or all of the instructions stored in the memory. When executing a task, the processing unit can send a read request to the cache, which includes an identifier of the instruction required by the processing unit to execute the task. Based on the instruction identifier, the cache can determine the instruction required by the processing unit to execute the task and send the corresponding instruction to the processing unit. After receiving the instruction, the processing unit can execute the task according to the instruction. In some possible implementations, the cache may include one or more cache sub-units. Any one of these cache sub-units can be used to store instructions. Optionally, a cache sub-unit can store one instruction or multiple instructions.

[0046] Memory can be divided into external storage and main memory. External storage includes devices such as hard disk drives (HHDs), while main memory includes devices such as synchronous dynamic random-access memory (SDRAM) or double data rate SDRAM (DDR). Cache, on the other hand, includes devices such as static random access memory (SRAM). During data exchange with the processor, SRAM has a faster data exchange speed than DDR (or SDRAM), and DDR has a faster data exchange speed than hard disks. Therefore, the processing unit takes less time to fetch instructions from the cache than from memory. It is evident that by placing a cache between memory and the processing unit, the speed at which the processing unit fetches instructions can be improved, thereby increasing the speed at which the processor executes tasks.

[0047] However, during task execution by the processing unit, if the cache does not contain the instructions needed to execute the task, the cache needs to load the instructions from memory and then send them to the processing unit. Since reading data from memory is slow, the time it takes to load instructions from the cache is long, and the time it takes for the processing unit to fetch instructions is also long, resulting in a decrease in the processor's task execution speed. Furthermore, during the time the cache loads instructions from memory, the processing unit has no executable instructions and remains in a waiting state. Therefore, due to the limited storage space of the cache, when the cache does not contain the instructions needed by the processor, both the processor's task execution speed and processor utilization will decrease.

[0048] To address the aforementioned problems, embodiments of this application provide a task processing method that pre-loads the instructions required for task execution into a cache before execution. Thus, when a task is executed, the necessary instructions are already stored in the cache. This allows the processing unit to quickly retrieve the required instructions, improving the processor's task execution speed and increasing processor utilization.

[0049] To facilitate understanding, the application scenarios of the embodiments of this application will be introduced first. See [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of the architecture of a device provided in an embodiment of this application. The device includes a processor 100 and a memory 200. The processor 100 includes a cache 112 and a processor unit 111, and the memory 200 is connected to the cache 112. For a description of the processor 100, please refer to the preceding text; it will not be repeated here.

[0050] In this embodiment of the application, the device to which the processor 100 belongs can be a terminal device or a network device. A terminal device, also known as user equipment (UE), mobile station (MS), mobile terminal (MT), terminal, etc., is a device that provides voice and / or data connectivity to a user, or a chip set in the device, such as a handheld device or vehicle-mounted device with wireless connectivity. Currently, examples of terminal devices include: mobile phones, desktop computers, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and 5G-residential gateways (5G-RG) supporting 5G access. When the device to which processor 100 belongs is a network device, this device can be a physical device such as a router or switch, or a server that deploys a virtual router or virtual switch, used to transmit messages between other network devices and / or terminal devices. Accordingly, processor 100 can be referred to as a forwarding chip.

[0051] In this embodiment, the processing unit 111 can be a data processing unit within the central processing unit 100, such as a data processing unit within a processor core. The cache 112 can be a high-speed storage device such as SRAM. The memory 200 can include any one or more of main memory and secondary storage. When the memory 200 includes both main memory and secondary storage, the processor 100 can pre-load the instructions required for program execution from secondary storage into main memory so that the cache 112 can retrieve instructions from main memory.

[0052] It should be noted that, Figure 2The cache 112 belongs to the processor core 110 of the processor 100, but this does not mean that the cache provided in this embodiment is necessarily encapsulated in the processor core. In some possible implementations, the cache can also be an independent storage device outside the processor. Furthermore, in... Figure 2 In the illustrated embodiment, processor 110 includes two processor cores. Each processor core 110 includes a processing unit 111 and a cache 112. This does not mean that the processor provided in this embodiment can only include two processor cores, and each processor core can only include one processor and one cache. In some possible implementations, the processor may include one or more processing units and one or more caches. One cache may correspond to one or more processing units, and one processing unit may also correspond to one or more caches. This embodiment does not limit the specific architecture of the processor.

[0053] In some possible implementations, the device may have a multi-level cache structure, that is, multiple caches of different levels are built using various storage media. The higher the level of the cache, the faster the data exchange speed and the smaller the size. Therefore, for a computer with a multi-level cache structure, the cache in the embodiments of this application can be a level 1 cache (the level 1 cache is the highest level cache), and the memory can include other caches with lower levels than the level 1 cache, such as level 2 cache, level 3 cache, etc.

[0054] See Figure 3 ,Should Figure 3 A flowchart illustrating a task processing method provided in this application embodiment. The task processing method provided in this application embodiment includes the following steps:

[0055] S301: The processor acquires tasks waiting to be executed.

[0056] In this embodiment of the application, the processor may be Figure 2 Processor 100. Optionally, when the processor includes multiple processor cores, different steps in the task processing method provided in this application embodiment can be executed by different processor cores. Taking a processor including core 110 and processor core 120 as an example, S201 and S202 can be executed by processor core 110, and S203, S204 and S205 can be executed by processor core 120.

[0057] Before executing a task, the processor first acquires the tasks waiting to be executed, i.e., the tasks that the processor needs to perform. When the processor is the central processing unit of the terminal device, this task can be a data processing task triggered by user operations. The processor can then determine the tasks waiting to be executed based on the user's actions. Of course, the task may not be triggered by the user; this application does not impose specific limitations on this embodiment.

[0058] When the processor is a forwarding chip in a network device, the task can be any one or more of tasks such as packet forwarding, packet inspection, and tunnel establishment. This task awaiting execution can be triggered by input from the network device. Packet forwarding refers to the processor forwarding received packets to other devices; packet inspection refers to the processor processing and inspecting fields included in the packet; and tunnel establishment refers to the processor establishing a tunnel to other devices based on received announcement messages. For example, suppose a network device receives a data packet that needs to be forwarded to another network device; then the processor can determine that the task awaiting execution is packet forwarding.

[0059] In this embodiment, the processor can determine the tasks waiting to be executed based on task configuration information, or it can predict the tasks waiting to be executed based on the information required to execute the tasks. The two methods for obtaining tasks waiting to be executed are described in detail below.

[0060] In the first implementation, the processor can determine the tasks waiting to be executed based on task configuration information. This task configuration information consists of pre-configured task information. Before executing a task, the processor can obtain the pre-configured task configuration information and then determine the tasks waiting to be executed based on this information.

[0061] In the second implementation, the processor can predict the tasks waiting to be executed based on task information. Specifically, the processor can obtain the information required to execute the task through the data interface or network interface of the computer device it is connected to, and predict the tasks waiting to be executed based on the required information.

[0062] The following section uses the processor as the forwarding chip in a network device as an example to explain the two implementation methods.

[0063] In the first implementation, technicians can configure task entries in the network device. These task entries include information about one or more tasks, i.e., task configuration information. The processor can then retrieve the task entries and determine the tasks awaiting execution based on the task configuration information within them. Specifically, the processor can retrieve information about all tasks in the task entries and identify the task corresponding to each piece of information as the task awaiting execution. For a detailed introduction to task entries, please refer to [link to relevant documentation]. Figure 5 The description of step S501 in the illustrated embodiment will not be repeated here.

[0064] Optionally, the processor may first determine the set of tasks that may need to be executed based on the task table entries, and then determine whether each task in the task set needs to be executed based on the message and / or the message's context information. For example, suppose the task table entries include the task configuration information for task 1, and task 1 is "count the number of messages from device A". Then the processor can determine whether the message comes from device A. If the message comes from device A, the processor can determine that task 1 is a task waiting to be executed; if the message comes from another device, the processor can determine that task 1 is not a task waiting to be executed.

[0065] In the second implementation, the processor can obtain the context information of the packet and predict the tasks awaiting execution based on this context information. The context information includes information that may be used when processing the packet. Based on the packet's context information, the processor can predict the tasks that need to be executed. For example, assuming the packet's context information includes the IP address of the destination device used for packet forwarding, the processor determines that the tasks awaiting execution include packet forwarding.

[0066] S302: The processor determines the instructions required to execute the task based on the task.

[0067] After identifying the tasks awaiting execution, the processor can determine the instructions required to execute those tasks. Optionally, the instructions required to execute the tasks can be determined based on a pre-generated mapping. This mapping represents the correspondence between tasks and the instructions required by the processor to execute those tasks. Optionally, the mapping can be a correspondence between task information and the storage addresses of the instructions required to execute the task. The task information can be a task identifier or information used to execute the task, etc. The storage address of the instructions can be the address where the instructions are stored in memory (e.g., main memory).

[0068] In the embodiments of this application, the processor can determine the instructions required for executing a task based on a correspondence, or the cache can determine the task based on a correspondence. The two methods of determining the instructions required for executing a task are described in detail below.

[0069] In the first implementation, the processor can determine the memory address of the instruction corresponding to the task based on the correspondence. Optionally, if executing a task requires multiple instructions, and these instructions are stored at adjacent addresses in memory, the processor can determine the memory addresses of the first and last instructions to obtain the address range of the required instructions.

[0070] Optionally, when the processor determines the task to be executed based on the task configuration information, the processor can also determine the memory address of the instruction based on the task configuration information and the corresponding relationship.

[0071] In the second implementation, the processor can send information about tasks waiting to be executed to the cache, and the cache can determine the storage address of the instructions required to execute the task based on the received task information and the corresponding relationship.

[0072] S303: The processor triggers the cache to load the required instructions from memory into the cache.

[0073] After determining the instructions needed to execute a task, the processor triggers the cache to load the required instructions from memory into the cache. In other words, the processor stores the necessary instructions in the cache before executing the task, so that it can retrieve instructions from the cache during task execution. The cache is a storage device located between memory and the processor; for example, it could be... Figure 2 The processor 100 contains an internal cache 112. Alternatively, the cache can also be other storage devices external to the processor. The memory can be an external storage device, for example, it could be... Figure 2 The memory 200 in the memory. When the memory is a storage device other than the processor, the memory can be RAM or external storage such as a hard disk.

[0074] In this embodiment, the cache can be loaded based on the address where the instruction is stored in memory. Specifically, as described in step 302, the storage address of the instruction required to execute the task can be determined by the processor or by the cache. Depending on the device that determines the storage address, the processor triggers the cache loading instruction in different ways. The two implementation methods are described below.

[0075] In the first implementation, the instruction's storage address is determined by the processor based on a correspondence, corresponding to the first implementation of step 302. The processor can then send the instruction's storage address to the cache, allowing the cache to determine whether the instruction corresponding to that address is already stored in the cache. The cache can also determine whether the received instruction's storage address has been loaded into the cache. If the instruction is not loaded into the cache, the cache can load the required instruction from memory based on the storage address.

[0076] In the second implementation, the instruction's storage address is determined by the cache according to a correspondence, corresponding to the second implementation of step 302. The processor can then trigger the cache to determine the storage address of the instruction required to execute the task based on the received task information. After determining the instruction's storage address, the cache can determine whether the instruction has already been loaded into the cache based on its storage address. If the instruction is not loaded into the cache, the cache can load the required instruction from memory based on its storage address.

[0077] The above describes how the processor triggers cache loading instructions. The following section will further explain the methods of cache loading instructions.

[0078] As described above, the storage address of an instruction is the address where the instruction is stored in memory. Therefore, a cache can record the correspondence between the addresses of instructions stored in memory and the addresses of instructions stored in the cache, and thus determine whether the instructions required to execute the task have been loaded into the cache based on this correspondence. Specifically, the cache can record the address of each instruction stored in memory during the instruction loading process. After determining the storage address of an instruction, the cache can check if the stored instructions include an instruction whose storage address matches the storage address of the instruction required to execute the task. If it does, it means that the instruction required for the task execution has been loaded into the cache. If it does not, the cache can retrieve the instruction from the corresponding storage location in memory based on the received storage address and store the instruction in the cache.

[0079] In this embodiment, the task may require multiple instructions. The processor can then trigger the cache to load the required instructions from memory into the cache. Optionally, the processor can send the memory address of each of the multiple instructions to the cache, so that the cache loads each instruction from memory into the cache. Alternatively, the processor can send a range of addresses for the multiple instructions to the cache, so that the cache loads instructions according to the address range. For a detailed explanation of address ranges and loading instructions, please refer to the above text; it will not be repeated here.

[0080] As described above, a cache can include one or more cache sub-units. Therefore, when a cache load instruction is triggered, the processor can instruct the cache to load the required instructions from memory into at least one cache sub-unit. When executing a task requires multiple instructions, the cache can load these instructions into the same cache sub-unit or into different cache sub-units.

[0081] Optionally, the processor can set a counter for each cache sub-cell in the cache. The value of the counter represents the total number of times the instruction stored in the corresponding cache sub-cell can be read. Then, after the processor triggers the cache to load instructions into the cache sub-cell, the processor can determine the target value for that cache sub-cell as the number of times the instructions stored in the cache sub-cell can be read. That is, the target value is equal to the number of times the processor needs to read the instructions stored in the cache sub-cell during the execution of the task. The processor can increment the counter of each cache sub-cell by the corresponding target value.

[0082] For example, suppose the cache includes cache sub-unit A and cache sub-unit B. Executing task X requires executing instruction 1 once, instruction 2 twice, and instruction 3 three times. The processor triggers the cache to load instruction 1 and instruction 2 into cache sub-unit A, and instruction 3 into cache sub-unit B. Then, the processor can increment the counter corresponding to cache sub-unit A by 3, and increment the counter corresponding to cache sub-unit B by 3.

[0083] Suppose that before executing task Y, the processor needs to execute task Z, and executing task Z requires executing instruction 1 three times and instruction 3 once. Then, the processor can increment the counter of cache subunit C by 3 and the counter of cache subunit B by 1, on top of the existing increments.

[0084] S304: The processor executes the task according to the required instructions in the cache.

[0085] After loading the instructions required to execute a task into the cache, the processor can execute the task based on the instructions stored in the cache. Specifically, after determining that all the instructions required to process the task have been loaded into the cache, the cache can send these instructions to the processor so that the processor can execute the task according to the instructions. Optionally, the processor can also read the instructions required to execute the task from the cache and execute the task according to the instructions. In some possible implementations, to save cache storage space, after the processor reads instructions from the cache, or after the cache sends instructions to the processor, the processor can release the cache space occupied by the instructions. For example, it can control the cache to delete the instructions required to execute the task or overwrite the instructions with other instructions to improve cache utilization.

[0086] Similar to S303, when the cache comprises one or more cache sub-units, the processor can read the required instructions from each of these sub-units. Optionally, when a cache sub-unit has a corresponding counter, the processor can adjust the counter of the cache sub-unit after reading the instruction. Each time the processor reads an instruction from the cache, it decrements the value of the counter of the cache sub-unit containing that instruction by one. Then, after the processor completes the task, the required number of instruction reads is exhausted, and the value of the counter for each cache sub-unit is equal to the difference between the counter value before task execution and the target value. Thus, by increasing the target value before reading instructions and decreasing it after reading instructions, the counter value reflects the number of times the instructions stored in the cache sub-unit need to be read. The processor can then determine whether the cache space of a cache sub-unit can be released based on the counter value. For example, if the initial value of the counter is 0, then when the counter value of a cache sub-unit is 0, the processor can release the cache space of that cache sub-unit.

[0087] Let's continue with the S303 example. Assume the initial values ​​of the counters in cache sub-units A and B are both 0. After loading instructions, the counter value of cache sub-unit A is 3, and the counter value of cache sub-unit B is also 3. After the processor reads instructions 1 and 2 from cache sub-unit A, it can decrement the counter of cache sub-unit A by 2, bringing its counter value to 1, indicating that executing the task still requires reading one more instruction from cache sub-unit A. After the processor reads instruction 3 three times from cache sub-unit B, its counter becomes 0, allowing the processor to release the cache space in cache sub-unit A. Therefore, by adjusting the counter values, the processor can determine which cache sub-unit can release its cache space from at least one cache sub-unit.

[0088] In some possible implementations, the processor can add the instructions required to execute a task to a cache sub-unit. The processor can then increment a counter for that cache sub-unit. After reading all the instructions required to execute the task, the processor can decrement the counter of the cache sub-unit from at least one cache sub-unit that can free up cache space. In this way, although there is no need to add or subtract a target value, the processor can still determine the cache sub-unit that can free up cache space based on the counter value.

[0089] In this embodiment, the processor can determine the instructions needed to execute the task before execution and trigger the cache to load these instructions from memory into the cache. In this way, all the instructions needed by the processor during task execution are stored in the cache. Therefore, by loading the required instructions into the cache before task execution, the cache does not need to load data from memory during task execution. Since the processor can read data from the cache quickly, it can obtain the instructions needed to execute the task at a faster speed. This ensures that the processor can quickly obtain instructions during task execution, thereby improving the processor's task execution speed.

[0090] Furthermore, most tasks require multiple instructions, and processors typically fetch and execute instructions one by one. That is, during task execution, the processor first reads an instruction from the cache and processes the data according to that instruction. After this instruction is executed, the processor then reads the next instruction for the task from the cache and processes the data according to the new instruction. Therefore, in conventional technology, when the cache does not contain a specific instruction required by the processor to execute a task, the cache needs to read that instruction from memory. During the process of the cache reading instructions from memory, the processor has no executable instructions and is in a waiting state. Because the cache reads data from memory slowly, the processor is in a waiting state for a long time. This reduces both the speed of task execution and the utilization rate of the processor. In the embodiments of this application, the processor loads all the instructions required for task execution into the cache before executing the task, so that all the instructions needed by the processor during task execution can be fetched from the cache, eliminating the need for the cache to read instructions from memory. This improves both the speed of task execution and the utilization rate of the processor.

[0091] The task processing method provided in the embodiments of this application has been described above. The following detailed explanation uses network devices such as routers and switches as examples.

[0092] See Figure 4 , Figure 4 This is a schematic diagram of a network device provided in an embodiment of this application. The network device includes a forwarding chip 400 and a memory 500. The forwarding chip 400 includes a processor core 410 and a processor core 420. The processor core 420 includes at least one processing unit 421 and at least one cache 422. The processor core 410 is connected to both the processing unit 421 and the cache 422, the processing unit 421 is connected to the cache 422, and the memory 500 is connected to the cache 422.

[0093] In this embodiment, the memory 500 can be RAM or a storage module composed of RAM and secondary storage. The forwarding chip 400 can be a central processing unit (CPU) or other chips used for data processing. Processor core 410 and processor core 420 can be two different processor cores in the forwarding chip 400. Processor core 410 can be the processor core in the forwarding chip 400 used to determine instructions, and processor core 420 can be the processor core in the forwarding chip 400 used to execute tasks. The cache 422 can be a high-speed storage device such as SRAM.

[0094] Optionally, the processor core 420 may include a processing unit 421 and a cache 422, and may include multiple processing units and / or multiple caches. The cache 422 may be encapsulated in the processor core 420, or it may be encapsulated in other locations within the forwarding chip 400, or it may be a separate storage device outside the forwarding chip 400.

[0095] exist Figure 4 The network device shown performs Figure 3 In the task processing method shown, the data interaction process between the processor core 420, processing unit 321, cache 422, and memory 500 can be as follows: Figure 5 As shown, it includes the following steps:

[0096] S501: Processor core 410 acquires the task waiting to be executed and determines the storage address of the instructions required during the execution of the task.

[0097] The processor core 410 in the forwarding chip 400 can acquire tasks waiting to be executed and determine the instructions required to execute those tasks. As described in step S301, the processor core 410 can acquire tasks waiting to be executed based on task configuration information and / or information required to execute the task. For network devices, the task configuration information can be carried in a task table entry, and the information required to execute the task can be carried in the context information of the packet.

[0098] Task entries can be pre-configured by technicians and include one or more task configuration information, which can be task enable bits or parameters required to execute the task. The value of the enable bit indicates whether the task corresponding to that enable bit needs to be executed. For example, an enable bit value of 1 indicates that the task corresponding to that enable bit needs to be executed, and an enable bit value of 1 indicates that the task corresponding to that enable bit does not need to be executed. Therefore, the processor core 410 can determine the tasks waiting to be executed based on the values ​​of the enable bits or the parameters required to execute the tasks. Specifically, if the value of the enable bit indicates that the task needs to be executed, the processor core 410 can determine that the value corresponding to that enable bit is a task waiting to be executed; if the task entry contains parameters required to execute a task, the processor core 410 can determine that the task is a task that needs to be executed.

[0099] For example, see Table 1, which is a schematic diagram of one possible structure for task entries.

[0100] Table 1

[0101] FunA_En FunB_Para

[0102] In Table 1, the element FunA_En in the first row and first column is the enable bit for task A. The value of FunA_En indicates whether the forwarding chip 400 needs to execute task A. The element FunB_Para in the first row and second column of Table 1 is the parameter for task B. The value of FunB_Para is the parameter used by the forwarding chip 400 when executing task B. Task A can be tasks such as counting the number of packets or forwarding packets.

[0103] Therefore, processor core 410 can determine whether task A needs to be executed based on the value of FunA_En, and whether task B needs to be executed based on the value of FunB_Para. For example, assuming the value of FunA_En is 1, processor core 410 can determine that task A is a task that needs to be executed; assuming the value of FunA_En is 0, processor core 410 can determine that task A is not a task that needs to be executed. Assuming the value of FunB_Para is empty (NULL), processor core 410 can determine that task B is not a task that needs to be executed; assuming FunB_Para includes the parameters required to execute task B, processor core 410 can determine that task B is a task that needs to be executed.

[0104] In some possible implementations, a task table entry may include one or more mutually exclusive task groups, each containing multiple tasks. Tasks belonging to the same mutually exclusive task group are mutually exclusive. That is, if the forwarding chip 400 executes a task in a mutually exclusive task group, then the forwarding chip 400 cannot execute other tasks in that group. Therefore, when a task table entry includes mutually exclusive task groups, the task configuration information may include type information, indicating which task in the mutually exclusive task group the forwarding chip 400 needs to execute.

[0105] For example, see Table 2, which is a possible structural diagram of task table items.

[0106] Table 2

[0107]

[0108] In the embodiment shown in Table 2, tasks C, D, and E constitute a mutually exclusive task group. The element FunC_Para in the first row and fourth column of Table 2 represents the parameter of task C; the element FunD_Para in the second row and fourth column represents the parameter of task D; and the element FunE_Para in the first row and fourth column represents the parameter of task E. The element type in the third column of Table 2 is the type information of the entry; the value of type indicates which of the three tasks (C, D, and E) the forwarding chip 400 needs to execute. Descriptions of FunA_En and FunB_Para can be found above and will not be repeated here.

[0109] Then, the processor core 410 can determine the task waiting to be executed from tasks C, D, and E based on the value of type. Assuming the value of type is 0, the processor core 410 can determine that task C is the task waiting to be executed, and thus execute task C according to the value of FunC_Para; assuming the value of type is 1, the processor core 410 can determine that task D is the task waiting to be executed, and thus execute task D according to the value of FunD_Para; assuming the value of type is 2, the processor core 410 can determine that task E is the task waiting to be executed, and thus execute task E according to the value of FunE_Para.

[0110] The above describes how processor core 410 determines tasks waiting to be executed based on task table entries (i.e., task configuration information). The following describes how processor core 410 determines tasks waiting to be executed based on context information (i.e., information required by the task).

[0111] While receiving a message, the network device can also obtain the message's context information. This context information includes all the information needed for any task that can be performed on the message; that is, the information needed for each of all possible tasks the network device might perform on the message. Therefore, after obtaining the message's context information, the processor core 410 can predict the processing the network device might perform on the message based on this context information, thereby determining the task that the forwarding chip 400 might execute. For example, assuming the message's context information includes the parameters required to execute task A, the processor core 410 can identify task A as the task waiting to be executed.

[0112] Optionally, the processor core 410 can also combine task table entries and context information to determine the tasks waiting to be executed. Specifically, the processor core 410 can first determine the tasks that may be executed based on the task table entries, and then determine whether the tasks that may be executed are needed based on the context information of the message.

[0113] For example, suppose task A is to count the number of packets, and the network device is configured with a rule "do not count packets from device X". When determining the task to be executed, the processor core 410 can first determine whether task A is possible based on the value of the enable bit of task A in the task table entry, and then determine whether the packet comes from device X based on the packet's context information. If the packet comes from device X, the processor core 410 can determine that task A is not a task waiting to be executed; if the packet comes from a device other than device X, the processor core 410 can determine that task A is a task waiting to be executed.

[0114] After identifying the task awaiting execution, the processor core 410 can determine the memory addresses of the instructions required to execute that task. Optionally, the processor core 410 can determine the address range of instructions required to execute the task based on a mapping relationship. This mapping relationship is between task information and instruction memory addresses, and can be obtained during task compilation. The instruction address range can include the memory addresses of multiple instructions. In some possible implementations, the memory 500 includes main memory, and all instructions required to execute the task are pre-stored in main memory; in this case, the instruction range can be the addresses where the instructions are stored in main memory.

[0115] For details on the specific method of determining instructions based on tasks awaiting execution, please refer to the description of step S302, which will not be repeated here.

[0116] S502: Processor core 410 sends the memory address of the required instructions to cache 422.

[0117] After determining the instructions required to execute the task, the processor core 410 can send the storage addresses of the required instructions to the cache 422. Optionally, the processor core 410 can send a request to the cache 422, which includes the storage address of each of one or more instructions required to execute the task.

[0118] In some possible implementations, executing different tasks may require the same one or more instructions. These instructions common to different tasks can be called common instructions. In the embodiments of this application, the address range of instructions that the processor core 410 can send to the cache 422 may also include the storage address of common instructions.

[0119] S503: Cache 422 determines whether an instruction needs to be loaded from memory 500 based on the instruction's storage address.

[0120] Upon receiving the storage address of the instruction, cache 422 can determine whether the instruction has already been loaded into cache 422 based on the storage address. If the instruction has not been loaded into cache 422, cache 422 determines that the instruction needs to be loaded from memory 500, and thus executes step S504. If the instruction has already been loaded into cache 422, cache 422 can skip step S504 and execute step S505.

[0121] Specifically, cache 422 can record the storage address of each instruction in memory 500 when loading instructions. Therefore, after receiving the storage address sent by processor core 410, cache 422 can determine whether its stored instructions include instructions whose storage address in memory 500 matches the storage address sent by processor core 410. If the storage address of an instruction stored in cache 422 in memory 500 is the same as the received storage address, it means that the instruction corresponding to that storage address has been loaded into cache 422, and cache 422 can skip step S504 and proceed to step S505. If the storage addresses of all instructions stored in cache 422 in memory 500 are different from the storage addresses sent by processor core 410, it means that the instruction corresponding to that storage address has not yet been loaded into cache 422, and cache 422 can proceed to step S504.

[0122] Optionally, when the processor core 410 sends the memory addresses of multiple instructions to the cache 422, the cache 422 can determine one by one whether the multiple instructions have been loaded. If any one of the instructions has not been loaded, the cache 422 can execute step S504 to load the instruction from the memory 500.

[0123] S504: Cache 422 loads instructions from memory 500.

[0124] If cache 422 determines that one or more instructions required to execute a task have not yet been loaded into cache 422, cache 422 can load instructions from memory 500 according to the storage address of the instructions. Optionally, when the storage address of an instruction is the address where the instruction is stored in memory, cache 422 can load the instruction from memory. In this embodiment, cache 422 can read the instruction corresponding to the storage address from memory 500, and can send the storage address of the instruction to be loaded to memory 500, so that memory 500 can send the instruction to be loaded to cache 422 for execution.

[0125] S505: Cache 422 sends an acknowledgment message to processor core 410.

[0126] After confirming that all instructions required to execute the task have been loaded into cache 422, cache 422 can send confirmation information to processor core 410 so that processor core 410 can execute subsequent steps.

[0127] S506: Processor core 410 sends a task to processing unit 421 to be executed.

[0128] After receiving the confirmation message from cache 422, processor core 410 confirms that all instructions required to execute the task have been loaded into cache 422, meaning the aforementioned task awaiting execution can enter the execution phase. Then, processor core 410 can send the task awaiting execution to processing unit 421 so that processing unit 421 can execute the task.

[0129] Optionally, the processor core 410 may also send information required for executing the task to the processing unit 421, such as the context information of the aforementioned message, the address range of the instruction, etc., so that the processing unit 421 can execute the task according to the received information.

[0130] S507: Processing unit 421 retrieves instructions from cache 422 according to the task waiting to be executed.

[0131] Upon receiving a task awaiting execution, processing unit 421 can retrieve the instructions required to execute the task from cache 422. Optionally, processing unit 421 can send an instruction retrieval request to cache 422, which includes the storage address of the instruction currently being executed by processing unit 421. Cache 422 can determine the storage address of the instruction required by processing unit 421 in cache 422 based on the instruction retrieval request, and then send the instruction to processing unit 421.

[0132] Optionally, after the processing unit 421 retrieves an instruction from the cache 422, the cache 422 can delete the instruction retrieved by the processing unit 421, thereby releasing the cache space occupied by the instruction.

[0133] S508: Processing unit 421 executes tasks according to instructions.

[0134] After receiving the instruction, the processing unit 421 can execute the task according to the instruction.

[0135] In some possible implementations, processing unit 421 can fetch instructions from cache 422 one by one. That is, processing unit 421 fetches only one instruction at a time. After this instruction is executed, processing unit 421 can fetch the next instruction from cache 422. Thus, by repeatedly executing steps S507 and S508, processing unit 421 can execute the instructions required for the task one by one.

[0136] In this embodiment, when the processor core 410 receives a new task, it does not directly send the task to the processing unit 421. Instead, it determines the storage address of the instructions required for task execution based on the task and triggers the cache 422 to load the required instructions from the memory 500 into the cache 422. Only after ensuring that all instructions required for task execution are loaded into the cache 422 does the processor core 410 send the task and the information required for task execution to the processing unit 421. Thus, during task execution, every instruction required by the processor 321 can be found in the cache 422. Therefore, every instruction that the processing unit 421 can obtain during task execution is stored in the cache 422. By loading instructions into the cache 422 before task execution, the cache 422 avoids loading instructions from the memory 500 during task execution, thereby improving the speed of task execution by the processing unit 421. Furthermore, since the processing unit 421 does not need to wait for the cache 422 to load instructions from the memory 500, the waiting time of the processing unit 421 is shorter, which also improves the utilization rate of the processing unit 421.

[0137] See Figure 6 This application embodiment also provides an integrated circuit 600, which can implement... Figure 3 The processor in the illustrated embodiment has the following functions. The integrated circuit includes an interface circuit 601 and a control circuit 602. The control circuit 601 and the interface circuit 602 are connected via a communication line 603. The interface circuit 602 enables the chip 600 to connect to other devices via the communication link.

[0138] Among them, interface circuit 601 is used to implement Figure 3 In step S301 of the illustrated embodiment, the control circuit 602 is used to implement... Figure 3 Steps S302, S303, and S304 in the illustrated embodiment.

[0139] Specifically, interface circuit 601 is used to acquire a task, which is a task waiting to be executed.

[0140] The control circuit 602 is configured to determine the instructions required for executing the task based on the task, trigger the cache to load the required instructions from the memory into the cache, and execute the task according to the required instructions in the cache.

[0141] Please refer to the above for the specific execution process. Figure 3 The detailed descriptions of the corresponding steps in the illustrated embodiments will not be repeated here.

[0142] Optionally, the integrated circuit 600 provided in this embodiment may further include a cache. The interface circuit 601 and control circuit 602 in the integrated circuit 600 may be one or more.

[0143] For example, the integrated circuit 600 may be an FPGA, an ASIC, a system-on-a-chip (SoC), a CPU, an NP, a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0144] See Figure 7 This application embodiment also provides a task processing device 700, which can realize... Figure 3 The processor in the illustrated embodiment has the following functions. The message sending device 700 includes an acquisition unit 701 and a processing unit 702. The acquisition unit 701 is used to implement... Figure 3 In step S301 of the illustrated embodiment, the processing unit 702 is used to implement... Figure 3 Steps S302, S303, and S304 in the illustrated embodiment.

[0145] Specifically, the acquisition unit 701 acquires a task, which is a task waiting to be executed.

[0146] The processing unit 702 is configured to determine the instructions required for executing the task based on the task, trigger the cache to load the required instructions from the memory into the cache, and execute the task based on the required instructions in the cache.

[0147] Please refer to the above for the specific execution process. Figure 3 The detailed descriptions of the corresponding steps in the illustrated embodiments will not be repeated here.

[0148] It should be noted that the division of units in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. The functional units in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. For example, in the above embodiment, the acquisition unit and the processing unit can be the same unit or different units. The integrated unit can be implemented in hardware or as a software functional unit.

[0149] See Figure 8 This application also provides a chip 800, which can achieve... Figure 3 The processor in the illustrated embodiment functions as follows. The chip includes a memory 801 and a processor 802. The memory 801 stores instructions or program code, and the processor 802 retrieves and executes the instructions or program code from the memory 801 to achieve... Figure 3 Steps S301, S302, S303, and S304 in the illustrated embodiment.

[0150] Optionally, the processor 802 may be Figure 6 The integrated circuit 600 shown. The processor 802 may include a cache. When the processor 802 does not include a cache, the memory 801 may include a cache.

[0151] Figure 9 This is a schematic diagram of the structure of a device 900 provided in an embodiment of this application. The integrated circuit 600, task processing device 700, or chip 800 mentioned above can be located at... Figure 9 This is achieved using the device shown. See also Figure 9 The device 900 includes at least one processor chip 901 and at least one memory 902. Optionally, the device 900 may also include a communication bus 903 and at least one network interface 904.

[0152] The processor chip 901 can be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits (ICs) used to control the execution of the program in this application. The processor chip 901 can be used to implement the task processing method provided in the embodiments of this application.

[0153] For example, when Figure 2 The equipment in the middle through Figure 9When implemented using the device shown, the processor can be used to: acquire a task, which is a task waiting to be executed; determine, based on the task, the instructions required to execute the task; determine, based on the task, that the required instructions are not included in the cache; and execute the task based on the required instructions in the cache.

[0154] Alternatively, the processor chip 901 can be Figure 8 The chip 800 in the illustrated embodiment can also be... Figure 6 The integrated circuit 600 is shown in the embodiment. When the processor chip 801 does not include a cache, the memory 902 may include a cache, main memory, and secondary storage; when the processor chip 901 includes a cache, the memory 902 may include main memory and secondary storage.

[0155] Memory 902 may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions. Memory 902 may also be random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions. It may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 902 may exist independently and be connected to processor 901 via communication bus 903. Memory 902 may also be integrated with processor 901. Optionally, memory 902 may include a cache.

[0156] Optionally, the memory 902 stores program code or instructions for executing the present application's solution, and the processor 901 controls the execution of these instructions. The processor 901 executes the program code or instructions stored in the memory 902. The program code may include one or more software modules. Optionally, the processor 901 may also store program code or instructions for executing the present application's solution, in which case the processor 901 does not need to read the program code or instructions from the memory 902.

[0157] Optionally, memory 902 can be used to implement Figure 2 The function of memory 200 in the device shown.

[0158] The communication bus 903 is used to transfer information between the processor chip 901, the network interface 904, and the memory 902.

[0159] Network interface 904 can be a transceiver or similar device used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), or Wireless Local Area Network (WLAN). In this embodiment, network interface 904 can be used to receive messages sent by other nodes in the segmented routing network, and can also send messages to other nodes in the segmented routing network. Network interface 904 can be an Ethernet interface, a Fast Ethernet (FE) interface, or a Gigabit Ethernet (GE) interface, etc.

[0160] In a specific implementation, as one example, device 900 may include multiple processor chips, for example... Figure 9 The processor chips 901 and 905 are shown. Each of these processor chips can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Optionally, Figure 3 The different steps in the task processing method shown can be executed by different processor chips. Here, a processor chip can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0161] Figure 10 This is a schematic diagram of the structure of a device 1000 provided in an embodiment of this application. Figure 2 The device in can be Figure 10 This is achieved using the device shown. See also Figure 10The illustrated device structure diagram shows that device 1000 includes a main control board and one or more interface boards. The main control board is communicatively connected to the interface boards. The main control board, also called a main processing unit (MPU) or route processor card, includes a CPU and memory. It is responsible for controlling and managing the various components in device 1000, including routing calculations, device management, and maintenance functions. The interface boards, also called line processing units (LPUs) or line cards, are used to receive and send messages. In some embodiments, the main control board and interface boards, or interface boards themselves, communicate via a bus. In some embodiments, the interface boards communicate via a switch fabric unit (SFU). In this case, device 1000 also includes a switch fabric unit, which is communicatively connected to the main control board and interface boards. The switch fabric unit is used to forward data between the interface boards and can also be called a switch fabric unit (SFU). Each interface board includes a CPU, memory, a forwarding engine, and an interface card (IC), where the interface card may include one or more network interfaces. The network interface can be an Ethernet interface, FE interface, or GE interface, etc. The CPU communicates with the memory, forwarding engine, and interface card respectively. The memory stores the forwarding table. The forwarding engine forwards received packets based on the forwarding table stored in the memory. If the destination address of the received packet is the IP address of device 1000, the packet is sent to the CPU of the main control board or interface board for processing; if the destination address of the received packet is not the IP address of device 1000, the forwarding table is consulted based on the destination. If the next hop and outgoing interface corresponding to the destination address are found in the forwarding table, the packet is forwarded to the outgoing interface corresponding to the destination address. The forwarding engine can be a network processor (NP). The interface card, also called a daughter card, can be installed on the interface board and is responsible for converting photoelectric signals into data frames, performing validity checks on the data frames, and forwarding them to the forwarding engine for processing or the interface board CPU. In some embodiments, the CPU can also perform the functions of the forwarding engine, such as implementing soft forwarding based on a general-purpose CPU, thus eliminating the need for a forwarding engine on the interface board. In some embodiments, the forwarding engine can be implemented using an ASIC or a field-programmable gate array (FPGA). In some embodiments, the memory storing the forwarding table can also be integrated into the forwarding engine as part of the forwarding engine.

[0162] Optionally, the chip system may include one or more processors. These processors can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Optionally, the chip system may also include one or more memories. These memories can be integrated with the processor or separated from it; this application does not limit this. For example, the memory can be a non-transient processor, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or disposed on different chips. This application does not specifically limit the type of memory or the arrangement of the memory and processor.

[0163] For example, the chip system can be an FPGA, an ASIC, a system on-chip (SoC), a CPU, an NP, a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0164] It should be understood that each step in the above method embodiments can be completed by integrated logic circuits in the processor hardware or by instructions in software form. The method steps disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.

[0165] This application also provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to perform the task processing method provided in the above method embodiments, which is executed by a processor.

[0166] This application also provides a computer program product containing instructions that, when run on a computer, causes the computer to execute the task processing method provided in the above method embodiments, which is executed by a processor.

[0167] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0168] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical module division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0170] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be obtained according to actual needs to achieve the purpose of this embodiment.

[0171] Furthermore, the module units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software module unit.

[0172] If the integrated unit is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0173] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0174] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention.

[0175] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A task processing method, characterized in that, The method includes: The processor acquires a task, which is a task waiting to be executed; The processor determines the instructions required to execute the task based on the task. The processor triggers the cache to load the required instructions from memory into the cache; The processor executes the task according to the required instructions in the cache; The processor determines the instructions required to execute the task based on the task, including: The processor determines the instructions required to execute the task based on a pre-generated correspondence, wherein the correspondence represents the relationship between the task and the instructions required by the processor to execute the task; The processor acquires tasks, including: The processor obtains the task based on task entries and context information. The task entries include information about one or more tasks and one or more mutually exclusive task groups. Each mutually exclusive task group includes multiple tasks, and the multiple tasks belonging to the same mutually exclusive task group are mutually exclusive.

2. The method according to claim 1, characterized in that, The processor triggering the cache to load the required instructions from memory into the cache includes: The processor obtains the address where the required instruction is stored in the memory; The processor triggers the cache to load the required instructions from memory into the cache according to the address.

3. The method according to claim 1, characterized in that, The processor determines, based on the task, the instructions required to execute the task, including: The processor triggers the cache to determine the instructions required to execute the task based on the task.

4. The method according to claim 3, characterized in that, The processor triggers the cache to determine, based on the task, the instructions required to execute the task, including: The processor triggers the cache to retrieve the address of the required instruction stored in the memory according to the task; The processor triggers the cache to load the required instructions from memory into the cache according to the address.

5. The method according to claim 4, characterized in that, The processor executes the task according to the required instructions in the cache, including: The processor reads the required instructions from the cache and executes the task according to the required instructions; After the processor reads the required instructions from the cache, the method further includes: The processor releases the cache space occupied by the required instructions.

6. The method according to claim 5, characterized in that, The cache includes at least one cache sub-unit; The processor triggering the cache to load the required instructions from memory into the cache includes: The processor triggers the cache to load the required instructions from memory into the at least one cache sub-unit; The processor reads the required instructions from the cache, including: The processor reads the required instructions from the at least one cache subunit.

7. The method according to claim 6, characterized in that, After the processor triggers the cache to load the required instructions from memory into the at least one cache sub-unit, the method further includes: The processor controls the counter of each cache sub-unit in the at least one cache sub-unit to increment by a target value, the target value being equal to the number of reads of the required instructions cached by the cache sub-unit; After the processor reads the required instruction from the cache and before the processor releases the cache space occupied by the required instruction, the method further includes: The processor reduces the value of the counter in each cache subunit by the target value based on the number of reads required for the instruction.

8. The method according to any one of claims 1-7, characterized in that, Before the processor triggers the cache to load the required instructions from memory into the cache, the method further includes: The processor confirms that the required instruction does not exist in the cache.

9. The method according to any one of claims 1-7, characterized in that, The task includes at least one of the following: Message forwarding, tunnel establishment, and message detection.

10. An integrated circuit, characterized in that, The integrated circuit includes an interface circuit and a control circuit; The interface circuit is used to acquire a task, which is a task waiting to be executed. The control circuit is configured to determine the instructions required for executing the task based on the task, trigger the cache to load the required instructions from the memory into the cache, and execute the task based on the required instructions in the cache; When the control circuit determines the instructions required to execute the task based on the task, it is specifically used for: The instructions required to execute the task are determined based on a pre-generated correspondence, wherein the correspondence represents the relationship between the task and the instructions required by the processor to execute the task; The interface circuit is specifically used for: The task is obtained based on the task table entry and context information. The task table entry includes information on one or more tasks and one or more mutually exclusive task groups. Each mutually exclusive task group includes multiple tasks, and the multiple tasks belonging to the same mutually exclusive task group are mutually exclusive.

11. The integrated circuit according to claim 10, characterized in that, The control circuit is used to obtain the address where the required instruction is stored in the memory, and trigger the cache to load the required instruction from the memory into the cache according to the address.

12. The integrated circuit according to claim 10, characterized in that, The control circuit is used to trigger the cache to determine the instructions required to execute the task based on the task.

13. The integrated circuit according to claim 12, characterized in that, The control circuit is used to trigger the cache to obtain the address of the required instruction stored in the memory according to the task; and to trigger the cache to load the required instruction from the memory into the cache according to the address.

14. The integrated circuit according to claim 13, characterized in that, The control circuit is configured to read the required instructions from the cache and execute the task according to the required instructions; after reading the required instructions from the cache, it is configured to release the cache space occupied by the required instructions.

15. The integrated circuit according to claim 14, characterized in that, The cache includes at least one cache sub-unit; The control circuit is configured to trigger the cache to load the required instruction from memory into the at least one cache sub-unit; and after reading the required instruction from the cache, to read the required instruction from the at least one cache sub-unit.

16. The integrated circuit according to claim 15, characterized in that, The control circuit is used to control the counter of each cache sub-unit in the at least one cache sub-unit to increment by a target value, the target value being equal to the number of reads of the required instruction cached by the cache sub-unit; After reading the required instruction from the cache, the value of the counter of each cache sub-unit is reduced by the target value according to the number of times the required instruction has been read.

17. The integrated circuit according to any one of claims 10-16, characterized in that, The control circuit is configured to confirm that the required instruction does not exist in the cache before triggering the cache to load the required instruction from memory into the cache.

18. The integrated circuit according to any one of claims 10-16, characterized in that, The task includes at least one of the following: Message forwarding, tunnel establishment, and message detection.

19. A chip, characterized in that, The chip includes a memory and a processor. The memory is used to store instructions or program code, and the processor is used to call and run the instructions or program code from the memory to perform the task processing method as described in any one of claims 1-9.

20. A device, characterized in that, The device includes a processor chip and a memory, the memory being used to store instructions or program code, and the processor chip being used to call and run the instructions or program code from the memory to perform the task processing method as described in any one of claims 1-9.

21. A computer-readable storage medium, characterized in that, Includes instructions, programs, or code that, when executed on a computer, cause the computer to perform the task processing method as described in any one of claims 1-9.

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