Active matrix substrate and method for manufacturing the same

Abstract

Provided is an active matrix substrate having a plurality of oxide semiconductor TFTs having a top gate structure and different characteristics. The active matrix substrate has a first TFT and a second TFT, the oxide semiconductor layer of each TFT includes a high-resistance region and a low-resistance region, the high-resistance region includes a channel region overlapping the gate electrode when viewed in the normal direction of the substrate and an offset region overlapping the gate insulating layer and not overlapping the gate electrode, the low-resistance region includes a source contact region, a drain contact region, and an intervening region between these contact regions and the high-resistance region, the gate insulating layer of the first TFT includes a first insulating film and a second insulating film disposed on the first insulating film, the gate insulating layer of the second TFT includes the second insulating film and does not include the first insulating film, and the total length L1 of the channel length direction of the offset region of the first TFT is greater than the total length L2 of the channel length direction of the offset region of the second TFT.

Description

TECHNICAL FIELD

[0001] The present application relates to an active matrix substrate and a manufacturing method thereof. BACKGROUND

[0002] An active matrix substrate used for liquid crystal display devices, organic electroluminescence (EL) display devices, and the like has a display region having a plurality of pixels and a region other than the display region (a non-display region or a frame region). In the display region, a switching element such as a thin film transistor (hereinafter, referred to as "TFT") is provided per pixel. As such a switching element, a TFT using an amorphous silicon film as an active layer (hereinafter, referred to as "amorphous silicon TFT") and a TFT using a polycrystal silicon film as an active layer (hereinafter, referred to as "polycrystal silicon TFT") have been widely used since old times.

[0003] As a material of an active layer of a TFT, use of an oxide semiconductor instead of amorphous silicon and polycrystal silicon has been proposed. Such a TFT is referred to as an "oxide semiconductor TFT". An oxide semiconductor has a higher mobility than amorphous silicon. Therefore, an oxide semiconductor TFT can operate at a higher speed than an amorphous silicon TFT.

[0004] A structure of a TFT is roughly classified into a bottom gate structure and a top gate structure. At present, an oxide semiconductor TFT is mostly adopted in the bottom gate structure, but use of the top gate structure has also been proposed (for example, Patent Document 1). In the top gate structure, it is possible to make a gate insulating layer thin, and thus a high current supply performance can be obtained.

[0005] In a non-display region of an active matrix substrate, a peripheral circuit such as a drive circuit is sometimes formed monolithically (integrally). By forming a drive circuit monolithically, it is possible to achieve a narrow and small non-display region and a cost reduction due to a simplification of a mounting process. For example, in a non-display region, a gate driver circuit is sometimes formed monolithically, and a source driver circuit is mounted in a COG (Chip on Glass) manner.

[0006] In a device in which a narrow frame is required such as a smartphone, a multiplexing circuit such as a source shared driving (SSD) circuit is sometimes formed monolithically in addition to a gate driver. An SSD circuit is a circuit that distributes video data from one video signal line of each terminal of a source driver to a plurality of source wirings. By mounting an SSD circuit, it is possible to make a region in which a terminal portion and a wiring are arranged (a terminal portion / wiring formation region) in a non-display region narrower. In addition, the number of outputs from a source driver is reduced, and it is possible to reduce a circuit scale, and thus it is possible to reduce a cost of a drive IC.

[0007] The periphery circuit such as a driver circuit and an SSD circuit includes a TFT. In this specification, a TFT arranged as a switching element in each pixel of a display region is referred to as a "pixel TFT" or a "pixel transistor", and a TFT included in a periphery circuit is referred to as a "circuit TFT" or a "circuit transistor". Note that a TFT included in a circuit TFT and functioning as a driver circuit is referred to as a "driver-circuit TFT", and a TFT included in an SSD circuit is referred to as an "SSD-circuit TFT".

[0008] In an active matrix substrate in which an oxide semiconductor TFT is used as a pixel TFT, from the viewpoint of a manufacturing process, it is preferable that a circuit TFT also use the same oxide semiconductor film as a pixel TFT and be formed by a common process. Thus, a circuit TFT and a pixel TFT generally have the same structure. The characteristics of these TFTs are also substantially the same.

[0009] Prior Art Documents

[0010] Patent Documents

[0011] Patent Document 1: Japanese Published Patent Application No. 2015-109315 SUMMARY

[0012] Problems to be Solved by the Invention

[0013] However, the characteristics required for a pixel TFT and a circuit TFT are different from each other. Further, even among circuit TFTs, the characteristics required for a driver-circuit TFT and an SSD-circuit TFT are different, for example. In recent years, the types of circuit TFTs monolithically formed in an active matrix substrate have been increasing, and along with this, the performance required for a circuit TFT has further diversified.

[0014] Thus, in an active matrix substrate including a plurality of TFTs having different uses, in order for each TFT to have a characteristic required depending on the use, it is required to separately produce a plurality of oxide semiconductor TFTs having different characteristics.

[0015] An embodiment of the present application is made in view of the above-described circumstances, and an object thereof is to provide an active matrix substrate including a plurality of oxide semiconductor TFTs having a top-gate structure and different characteristics from each other.

[0016] Means for Solving the Problems

[0017] An active matrix substrate and a method for manufacturing an active matrix substrate disclosed in the following items are described in this specification.

[0018] [Item 1] An active matrix substrate including a substrate and a plurality of oxide semiconductor TFTs supported on a main surface of the substrate and including a first TFT and a second TFT, wherein

[0019] Each of the oxide semiconductor TFTs includes an oxide semiconductor layer, a gate insulating layer disposed on a portion of the oxide semiconductor layer, a gate electrode disposed on a portion of the gate insulating layer, and a source electrode and a drain electrode,

[0020] The oxide semiconductor layer of the first TFT is formed of a first oxide semiconductor film, the oxide semiconductor layer of the second TFT is a different layer from the oxide semiconductor layer of the first TFT, and the oxide semiconductor layer of the second TFT is formed of a second oxide semiconductor film having a higher mobility than the first oxide semiconductor film,

[0021] The oxide semiconductor layer of each of the first and second TFTs includes a high-resistance region covered with the gate insulating layer and low-resistance regions located on both sides of the high-resistance region and not covered with the gate insulating layer, the low-resistance regions having a smaller specific resistance than the high-resistance region,

[0022] The high-resistance region includes a channel region overlapping the gate electrode when viewed in a normal direction of the main surface of the substrate and an offset region overlapping the gate insulating layer and not overlapping the gate electrode, the offset region including a source-side offset region and a drain-side offset region located on both sides of the channel region, respectively,

[0023] The low-resistance region includes a source contact region electrically connected to the source electrode, a drain contact region located on an opposite side of the source contact region across the high-resistance region and electrically connected to the drain electrode, and a source-side intervening region and a drain-side intervening region intervening between the source contact region and the high-resistance region and between the drain contact region and the high-resistance region, respectively,

[0024] The gate insulating layer of the first TFT includes a first insulating film and a second insulating film disposed on the first insulating film, and the gate insulating layer of the second TFT includes the second insulating film and does not include the first insulating film,

[0025] A total length L1 of the offset region of the first TFT in a channel length direction is greater than a total length L2 of the offset region of the second TFT in the channel length direction.

[0026] [Item 2] The active matrix substrate according to Item 1, wherein

[0027] The active matrix substrate described above further includes a first insulating layer between the oxide semiconductor layer of the second TFT and the substrate, and the first insulating layer includes the first insulating film.

[0028] [Item 3] The active matrix substrate according to any one of items 1 or 2, wherein

[0029] The side surface of the first insulating film and the second insulating film in the gate insulating layer of the first TFT and the side surface of the second insulating film in the gate insulating layer of the second TFT each have a tapered shape.

[0030] [Item 4] The active matrix substrate according to item 3, wherein

[0031] The side surface of the first insulating film and the side surface of the second insulating film in the gate insulating layer of the first TFT are aligned with each other.

[0032] [Item 5] The active matrix substrate according to any one of items 1 or 2, wherein

[0033] In the gate insulating layer of the first TFT, the second insulating film covers only a part of the upper surface of the first insulating film, and the side surface of the second insulating film is located inward of the side surface of the first insulating film when viewed from the normal direction of the substrate.

[0034] [Item 6] The active matrix substrate according to any one of items 3 to 5, wherein

[0035] The distance d1 between the edge of the second insulating film in the first TFT and the edge of the gate electrode is substantially equal to the distance d2 between the edge of the second insulating film in the second TFT and the edge of the gate electrode when viewed from the normal direction of the substrate, and the distance d3 between the edge of the first insulating film in the first TFT and the edge of the gate electrode is greater than the distance d1 and the distance d2.

[0036] [Item 7] The active matrix substrate according to any one of items 1 to 6, wherein

[0037] The first insulating film and the second insulating film include the same insulating material.

[0038] [Item 8] The active matrix substrate according to any one of items 1 to 7, wherein

[0039] The first TFT has a threshold voltage that is shifted in the positive direction from the threshold voltage of the second TFT.

[0040] [Item 9] The active matrix substrate according to Item 8, wherein

[0041] The first TFT has an enhancement characteristic, and the second TFT has a depletion characteristic.

[0042] [Item 10] The active matrix substrate according to any one of Items 1 to 9, wherein

[0043] The active matrix substrate has a display region including a plurality of pixel regions, and a non-display region provided at a periphery of the display region,

[0044] The plurality of oxide semiconductor TFTs include a plurality of pixel TFTs each disposed in one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit disposed in the non-display region,

[0045] Each of the pixel TFTs is the first TFT,

[0046] The plurality of circuit TFTs include the second TFT.

[0047] [Item 11] The active matrix substrate according to any one of Items 1 to 9, wherein

[0048] The active matrix substrate has a display region including a plurality of pixel regions, and a non-display region provided at a periphery of the display region,

[0049] The plurality of oxide semiconductor TFTs include a plurality of pixel TFTs each disposed in one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit disposed in the non-display region,

[0050] The plurality of circuit TFTs include the first TFT and the second TFT.

[0051] [Item 12] The active matrix substrate according to Item 10 or 11, wherein

[0052] The active matrix substrate further includes a plurality of source bus lines and a plurality of gate bus lines, the source electrode of each of the pixel TFTs is electrically connected to one of the plurality of source bus lines, and the gate electrode of each of the pixel TFTs is electrically connected to one of the plurality of gate bus lines,

[0053] The peripheral circuit includes an SSD circuit that distributes a display signal to n source bus lines among the plurality of source bus lines,

[0054] The SSD circuit includes a plurality of TFTs for the SSD circuit, each of the TFTs for the SSD circuit being the second TFT.

[0055] [Item 13] The active matrix substrate according to any one of Items 1 to 12, wherein

[0056] The first oxide semiconductor film and the second oxide semiconductor film each contain In and / or Sn,

[0057] The total of the atomic ratios of In and Sn with respect to all metal elements in the second oxide semiconductor film is larger than the total of the atomic ratios of In and Sn with respect to all metal elements in the first oxide semiconductor film.

[0058] [Item 14] The active matrix substrate according to any one of Items 1 to 12, wherein

[0059] The second oxide semiconductor film contains Sn, the first oxide semiconductor film does not contain Sn, or contains Sn at a lower concentration than the second oxide semiconductor film.

[0060] [Item 15] The active matrix substrate according to Item 13, wherein

[0061] The first oxide semiconductor film and the second oxide semiconductor film are each an In-Ga-Zn-O-based semiconductor film,

[0062] The total of the atomic ratios of In with respect to all metal elements in the second oxide semiconductor film is larger than the total of the atomic ratios of In with respect to all metal elements in the first oxide semiconductor film.

[0063] [Item 16] The active matrix substrate according to any one of Items 1 to 15, wherein

[0064] At least one of the first oxide semiconductor film and the second oxide semiconductor film is an In-Ga-Zn-O-based semiconductor film containing a crystalline portion.

[0065] [Item 17] A method for manufacturing an active matrix substrate, the method for manufacturing an active matrix substrate according to Item 2, comprising:

[0066] (A) forming the oxide semiconductor layer of the first TFT on the substrate;

[0067] (B) forming an insulating film to be the first insulating film so as to cover the oxide semiconductor layer of the first TFT;

[0068] (C) forming the oxide semiconductor layer of the second TFT on the insulating film;

[0069] Process (D) forming another insulating film to be the second insulating film so as to cover the oxide semiconductor layer of the second TFT;

[0070] Process (E) forming the gate electrode of the first TFT and the second TFT on the other insulating film;

[0071] Process (F) after the process (E), patterning the insulating film and the other insulating film, thereby obtaining the first insulating film and the second insulating film from the insulating film and the other insulating film, respectively, thereby forming the gate insulating layer of the first TFT and the gate insulating layer of the second TFT, and forming the first insulating layer on the substrate side of the oxide semiconductor layer of the second TFT; and

[0072] Process (G) in the first TFT and the second TFT, respectively, performing a low-resistance treatment of making the resistivity of the part of the oxide semiconductor layer not covered by the gate insulating layer lower than the part covered by the gate insulating layer, thereby forming the low-resistance region in the part of the oxide semiconductor layer not covered by the gate insulating layer.

[0073] [Item 18] The method of manufacturing an active matrix substrate according to item 17, wherein

[0074] In the process (F), dry etching of the insulating film and the other insulating film is performed with the same resist layer as a mask, thereby forming the gate insulating layer of the first TFT, the gate insulating layer of the second TFT, and the first insulating layer,

[0075] The dry etching is performed with the condition that a tapered shape is formed in the side surface of the first insulating film and the second insulating film in the gate insulating layer of the first TFT and the side surface of the second insulating film in the gate insulating layer of the second TFT, thereby making the width of the channel length direction of the gate insulating layer of the first TFT larger than the width of the channel length direction of the gate insulating layer of the second TFT.

[0076] [Item 19] The method of manufacturing an active matrix substrate according to item 17, wherein

[0077] The process (F) includes:

[0078] A first etching process (fl) performing etching of the other insulating film with a first resist layer as a mask; and

[0079] In the second etching process (f2), after the above process (f1), the insulating film is etched using a second resist layer, which is different from the first resist layer, as a mask.

[0080] [Item 20] The manufacturing method of the active matrix substrate according to Item 17, wherein,

[0081] The above process (F) includes:

[0082] In the third etching process (f3), the third resist layer is used as a mask to pattern the aforementioned insulating film and the other insulating films, thereby forming the gate insulating layer and the first insulating layer of the second TFT in the region where the second TFT is formed; and

[0083] In the fourth etching process (f4), before or after the above process (f3), a fourth resist layer, different from the third resist layer, is used as a mask to pattern the above insulating film and the other above insulating films, thereby forming the gate insulating layer of the first TFT in the region where the first TFT is formed.

[0084] Effects of the Invention

[0085] According to one embodiment of the present invention, an active matrix substrate is provided, which includes a plurality of oxide semiconductor TFTs having top gate structures and different characteristics. Furthermore, according to another embodiment of the present invention, a method for manufacturing an active matrix substrate capable of separately fabricating a plurality of oxide semiconductor TFTs with different characteristics using the same oxide semiconductor film is provided. Attached Figure Description

[0086] FIG. 1 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 1000 of the first embodiment.

[0087] FIG. 2A This is a top view illustrating the first TFT 100 and the second TFT 200 formed on the active matrix substrate 1000.

[0088] FIG. 2B It is along the first TFT100 and the second TFT200 FIG. 2A The cross-sectional view of line IIb-IIb' shown.

[0089] FIG. 3 This is a diagram illustrating the Vg-Id characteristics of the first TFT100 and the second TFT200.

[0090] FIG. 4A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0091] FIG. 4Bis a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0092] FIG. 4C is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0093] FIG. 4D is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0094] FIG. 4E is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0095] FIG. 4F is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0096] FIG. 4G is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0097] FIG. 4H is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0098] FIG. 4I is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0099] FIG. 4J is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0100] FIG. 4K is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0101] FIG. 4L is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0102] FIG. 4M is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0103] FIG. 4N is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0104] FIG. 4O is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0105] FIG. 4P is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0106] FIG. 5A is a cross-sectional view showing a process of a manufacturing method of the active matrix substrate 1000.

[0107] FIG. 5B FIG. 10B is a cross-sectional view of a process of a manufacturing method of the active matrix substrate 1000.

[0108] FIG. 5C FIG. 11B is a cross-sectional view of a process of a manufacturing method of the active matrix substrate 1000.

[0109] FIG. 6A FIG. 12B is a cross-sectional view of a process of another manufacturing method of the active matrix substrate 1000.

[0110] FIG. 6B FIG. 13B is a cross-sectional view of a process of another manufacturing method of the active matrix substrate 1000.

[0111] FIG. 6C FIG. 14B is a cross-sectional view of a process of another manufacturing method of the active matrix substrate 1000.

[0112] FIG. 6D FIG. 15B is a cross-sectional view of a process of another manufacturing method of the active matrix substrate 1000.

[0113] FIG. 7A FIG. 16B is a cross-sectional view of a process of still another manufacturing method of the active matrix substrate 1000.

[0114] FIG. 7B FIG. 17B is a cross-sectional view of a process of still another manufacturing method of the active matrix substrate 1000.

[0115] FIG. 7C FIG. 18B is a cross-sectional view of a process of still another manufacturing method of the active matrix substrate 1000.

[0116] FIG. 7D FIG. 19B is a cross-sectional view of a process of still another manufacturing method of the active matrix substrate 1000.

[0117] FIG. 8 FIG. 20 is a diagram illustrating a shift register circuit in a gate driver circuit.

[0118] FIG. 9 FIG. 21 is a diagram illustrating a unit shift register circuit SR.

[0119] FIG. 10 FIG. 22 is a diagram illustrating an SSD circuit.

[0120] Explanation of Reference Numerals

[0121] 1 substrate

[0122] 2A, 2B lower conductive layer

[0123] 3 lower insulating layer

[0124] 4 first oxide semiconductor layer

[0125] 4a first high-resistance region

[0126] 4b first low-resistance region

[0127] 41 first channel region

[0128] 42 first offset region

[0129] 6 second oxide semiconductor layer

[0130] 6a second high-resistance region

[0131] 6b second low-resistance region

[0132] 61 second channel region

[0133] 62 second offset region

[0134] 42s, 62s source side offset region

[0135] 42d, 62d drain side offset region

[0136] 43s, 63s source side intervening region

[0137] 43d, 64d drain side intervening region

[0138] 44s, 64d source contact region

[0139] 44d, 64d drain contact region

[0140] 5A, 5B gate insulating layer

[0141] 7A, 7B gate electrode

[0142] 8A, 8B source electrode

[0143] 9A, 9B drain electrode

[0144] 10 interlayer insulating layer

[0145] 11 inorganic insulating layer

[0146] 12 organic insulating layer

[0147] 13 upper insulating layer

[0148] 17 dielectric layer

[0149] 51 first insulating film

[0150] 52 second insulating film

[0151] 100 first TFT

[0152] 200 2nd TFT

[0153] 1000 Active matrix substrate

[0154] CE Common electrode

[0155] PE Pixel electrode

[0156] GL Gate bus line

[0157] SL Source bus line

[0158] L1 Length of 1st offset region

[0159] L1 Length of 2nd offset region

[0160] m1, m2, m3, m4, m5, m6, m7, m8 Mask portion of resist layer DETAILED DESCRIPTION

[0161] As described above, the characteristics required for the TFT provided in the active matrix substrate differ depending on each use thereof. Hereinafter, one example of the preferred TFT characteristics will be described with reference to the active matrix substrate used in a liquid crystal display device.

[0162] In the SSD circuit TFT used in the SSD circuit, a relatively large on current is required to flow therethrough, and a high current driving force is required. If a TFT having a small current driving force is used, it is sometimes difficult to charge the source bus line within a prescribed time. In addition, if the channel width of the TFT is increased in order to secure the desired current driving force, the size of the TFT increases, and it can be impossible to achieve narrow frame design. Therefore, in the SSD circuit TFT, it is preferred to lower the threshold voltage to further increase the on current. The SSD circuit TFT can have, for example, a depletion characteristic having a negative threshold voltage.

[0163] In contrast to this, in the driving circuit TFT used in the driving circuit such as a gate driver, it is preferred to shift the threshold voltage of the driving circuit TFT in the positive direction from the threshold voltage of the SSD circuit TFT to reduce the off-leakage current. If the off-leakage current is large, it can be a cause of an increase in power consumption, malfunction of the driving circuit, erroneous operation, and the like. The driving circuit TFT can have, for example, an enhancement characteristic having a positive threshold voltage.

[0164] In addition, as the pixel TFT used in the liquid crystal display device, it is preferred to use a TFT having a small off-leakage current. Thereby, it is possible to suppress a decrease in the contrast of the display. The pixel TFT can have a depletion characteristic, or can have an enhancement characteristic.

[0165] Furthermore, the use and required characteristics of the TFT are not limited to the above-described examples, and are diversified.

[0166] Through research by the inventors of the present application, it was difficult to form multiple TFTs having different characteristics using the same oxide semiconductor film. For example, although a TFT for an SSD circuit preferably uses an oxide semiconductor having a high mobility, with the increase in the mobility of the oxide semiconductor, the threshold voltage of the TFT shifts to the negative direction, and becomes a depletion characteristic. A TFT having a depletion characteristic is not always suitable for a TFT for a driver circuit. On the other hand, a TFT for a driver circuit preferably has an enhancement characteristic, but in a TFT having an enhancement characteristic, it is difficult to further increase the on-current, and thus it can not be suitable for another peripheral circuit such as an SSD circuit.

[0167] In this case, it is possible to consider forming multiple TFTs having different characteristics by using oxide semiconductor films different from each other as active layers. However, by merely making the materials of the oxide semiconductor films different, it is sometimes difficult to achieve the characteristics required according to the use of each of the multiple TFTs.

[0168] The inventors of the present application found a method for separately manufacturing multiple top-gate TFTs each of which can have characteristics required according to the use, based on the above-described insight. According to one embodiment of the present application, by making not only the materials of the active layers different from each other but also the structures of the gate insulating layers and the active layers different from each other, the characteristics of each TFT can be controlled independently of each other. In addition, it is possible to suppress an increase in the number of manufacturing steps and manufacturing cost, and separately manufacture the TFTs.

[0169] (First Embodiment)

[0170] Hereinafter, an active matrix substrate according to the first embodiment will be described with reference to the drawings, taking an active matrix substrate used for a liquid crystal display device as an example.

[0171] <Basic Structure of Active Matrix Substrate 1000>

[0172] FIG. 1 is a schematic view illustrating an example of a planar structure of the active matrix substrate 1000 according to the present embodiment.

[0173] The active matrix substrate 1000 has a display region DR and a region other than the display region DR (a non-display region or a frame region) FR. The display region DR includes pixel regions PIX arranged in a matrix. The pixel region PIX (sometimes simply referred to as a "pixel") is a region corresponding to a pixel of a display device. The non-display region FR is a region located at the periphery of the display region DR and not contributing to display.

[0174] In the non-display region FR, a gate driver, a demultiplexer circuit functioning as an SSD circuit, and the like are provided integrally (monolithically), for example. The source driver is mounted on the active matrix substrate 1000, for example.

[0175] In the display region DR, a plurality of gate bus lines GL extending in the row direction and a plurality of source bus lines SL extending in the column direction are formed. Each pixel region PIX is defined by the gate bus line GL and the source bus line SL, for example. The gate bus lines GL are connected to the respective terminals of the gate driver. The source bus lines SL are connected to the respective terminals of the source driver.

[0176] Each pixel region PIX has a pixel transistor (pixel TFT) Tp and a pixel electrode PE. The gate electrode of the pixel transistor Tp is electrically connected to the corresponding gate bus line GL, and the source electrode is electrically connected to the corresponding source bus line SL. The drain electrode is electrically connected to the pixel electrode PE. In the case where the active matrix substrate 1000 is applied to a display device of a lateral electric field mode such as an FFS (Fringe Field Switching) mode, although not shown, an electrode (common electrode) shared by a plurality of pixels is provided in the active matrix substrate 1000. In the case where the active matrix substrate is applied to a display device of a longitudinal electric field mode, the common electrode CE can also be provided in a counter substrate arranged opposite to the active matrix substrate with a liquid crystal layer interposed therebetween.

[0177] In the non-display region of the active matrix substrate 1000, a plurality of circuit TFTs constituting a peripheral circuit are formed. The circuit TFTs include a TFT for a drive circuit constituting the gate driver, a TFT for an SSD circuit constituting the SSD circuit, and the like.

[0178] <Structure of TFT in Active Matrix Substrate 1000>

[0179] Next, the structure of a plurality of top-gate TFTs included in the active matrix substrate 1000 will be described.

[0180] The active matrix substrate 1000 of the present embodiment includes a plurality of oxide semiconductor TFTs having a top-gate structure. Each oxide semiconductor TFT has an oxide semiconductor layer and a gate electrode arranged on a part of the oxide semiconductor layer with a gate insulating layer interposed therebetween.

[0181] The plurality of oxide semiconductor TFTs include at least one first TFT and one second TFT having mutually different characteristics. The oxide semiconductor layer that becomes an active layer of the first TFT is referred to as a "first oxide semiconductor layer", and the oxide semiconductor layer that becomes an active layer of the second TFT is referred to as a "second oxide semiconductor layer". The first TFT and the second TFT differ in the following aspects.

[0182] (i) Oxide semiconductor material

[0183] The first oxide semiconductor layer and the second oxide semiconductor layer are different layers (i.e., formed of different oxide semiconductor films). In this embodiment, the first oxide semiconductor layer is formed of a first oxide semiconductor film (hereinafter referred to as a "low-mobility oxide semiconductor film") whose mobility is relatively low, and the second oxide semiconductor layer is formed of a second oxide semiconductor film (hereinafter referred to as a "high-mobility oxide semiconductor film") whose mobility is higher than that of the low-mobility oxide semiconductor film.

[0184] (ii) Structure of gate insulating layer

[0185] The gate insulating layer of the first TFT is thicker than that of the second TFT. Specifically, the gate insulating layer of the first TFT includes a first insulating film and a second insulating film provided over the first insulating film. On the other hand, in the second TFT, the second oxide semiconductor layer is positioned between the first insulating film and the second insulating film. Thus, the gate insulating layer of the second TFT includes the second insulating film but does not include the first insulating film. Thus, the capacitance of the gate insulating layer per unit area (gate capacitance) of the second TFT can be made higher than that of the first TFT. Thus, the on-state current (drain current Id) of the second TFT can be made larger than that of the first TFT in the case where the voltage Vdg applied between the gate and the drain is the same.

[0186] (iii) Length of offset region

[0187] The first oxide semiconductor layer and the second oxide semiconductor layer each include a high-resistance region forming a channel and a low-resistance region positioned on both sides of the high-resistance region and having a resistivity lower than that of the high-resistance region. The high-resistance region includes a channel region overlapping with the gate electrode with the gate insulating layer interposed therebetween and an offset region which does not overlap with the gate electrode when viewed in the direction normal to the substrate 1. When the offset region is provided in the active layer of the TFT, the off-state leakage current can be reduced. However, the offset region is a region which is not opposite to the gate electrode, and thus is not reduced in resistance when the TFT is turned on due to application of voltage to the gate electrode. Thus, if the length of the offset region in the channel length direction (offset length) is increased, the on-state current is reduced.

[0188] In this embodiment, the length L1 of the offset region of the first oxide semiconductor layer (hereinafter referred to as the "first offset region") in the channel length direction is larger than the length L2 of the offset region of the second oxide semiconductor layer (hereinafter referred to as the "second offset region") in the channel length direction. Thus, the first TFT can have superior off-state leakage characteristics to the second TFT. The second TFT can have superior on-state characteristics to the first TFT because the reduction in on-state current due to the offset region is suppressed.

[0189] Further, typically, each of the oxide semiconductor layers of the TFTs can have offset regions on both sides of the channel region (the source side and the drain side). In that case, the "length L1 of the first offset region" refers to the total length in the channel length direction of the offset regions on the source side and the drain side in the first oxide semiconductor layer. Similarly, the "length L2 of the second offset region" refers to the total length in the channel length direction of the offset regions on the source side and the drain side in the second oxide semiconductor layer.

[0190] As described in (i) to (iii) above, in the first TFT and the second TFT, the structures of the gate insulating layers are made different from each other by not only making the active layers different layers but also forming the second oxide semiconductor layer as the active layer of the second TFT between the first insulating film and the second insulating film which are the gate insulating layers of the first TFT. Further, the lengths L1 and L2 of the offset regions of the first TFT and the second TFT are made different from each other, for example, by the difference in the thickness of the gate insulating layer. According to this embodiment, the material of the oxide semiconductor film, the thickness of the gate insulating layer, and the length of the offset region of each TFT can be controlled independently, and thus the characteristics of each TFT can be controlled depending on the use. Specifically, in this embodiment, the second TFT can have a higher mobility (TFT mobility) than the first TFT. As described later, the first TFT can have a threshold voltage which is offset in the positive direction from the threshold voltage of the second TFT. Note that in this specification, the mobility in an actual TFT is referred to as "TFT mobility" to be distinguished from the mobility of the oxide semiconductor material itself.

[0191] The structure of the first TFT and the second TFT according to this embodiment will be described in more detail below with reference to the drawings.

[0192] FIG. 2A is a top view of the first TFT 100 and the second TFT 200 of the active matrix substrate 1000, FIG. 2B is FIG. 2A a cross-sectional view at the line IIb-IIb' of FIG. 1 Ib. The active matrix substrate 1000 can have a plurality of first TFTs 100 and a plurality of second TFTs 200, but only a single first TFT 100 and a single second TFT 200 are illustrated and described.

[0193] The first TFT 100 and the second TFT 200 are top-gate type TFTs which are supported by the substrate 1 and have an oxide semiconductor layer as an active layer.

[0194] The first TFT 100 has the first oxide semiconductor layer 4 as an active layer, and the second TFT has the second oxide semiconductor layer 6 as an active layer. The first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 are different layers. The first oxide semiconductor layer 4 is formed of a low-mobility oxide semiconductor film. The second oxide semiconductor layer 6 is formed of a high-mobility oxide semiconductor film having a higher mobility than the low-mobility oxide semiconductor film.

[0195] The first TFT 100 includes the first oxide semiconductor layer 4 provided over the main surface of the substrate 1, the gate insulating layer 5A provided over part of the first oxide semiconductor layer 4, the gate electrode 7A provided over part of the gate insulating layer 5A, and the source electrode 8A and the drain electrode 9A. The gate electrode 7A is provided so as to cover part of the first oxide semiconductor layer 4 with the gate insulating layer 5A interposed therebetween.

[0196] The first oxide semiconductor layer 4 includes the first high-resistance region 4a and the first low-resistance region 4b which is located on both sides of the first high-resistance region 4a and has a smaller resistivity than the first high-resistance region 4a. The first high-resistance region 4a can be a semiconductor region, and the first low-resistance region 4b can be a conductor region. In this embodiment, the first high-resistance region 4a is covered with the gate insulating layer 5A, and the first low-resistance region 4b is not covered with the gate insulating layer 5A. Such a structure can be obtained, for example, by performing a low-resistance treatment of the first oxide semiconductor layer 4 using the gate insulating layer 5A and the gate electrode 7A as masks.

[0197] The first high-resistance region 4a includes the first channel region 41 which overlaps with the gate electrode 7A with the gate insulating layer 5A interposed therebetween and the first offset region 42 which is located on both sides of the first channel region 41, when viewed in the normal line direction of the main surface of the substrate 1 (hereinafter, simply referred to as the "normal line direction of the substrate 1"). The first offset region 42 is a region which overlaps with the gate insulating layer 5A and does not overlap with the gate electrode 7A when viewed in the normal line direction of the substrate 1. In this example, the first offset region 42 includes a source side offset region 42s and a drain side offset region 42d which are located on both sides of the first channel region 41, respectively.

[0198] The first offset region 42 has a length LI in the channel length direction. In this example, the length LI is a length in which a length LIs in the channel length direction of the source side offset region 42s and a length LId in the channel length direction of the drain side offset region 42d are added together. The length LIs of the source side offset region 42s is defined by a length in the channel length direction from the edge portion of the source side of the gate electrode 7A to the edge portion of the source side of the gate insulating layer 5A when viewed from the normal direction of the substrate 1. Similarly, the length LId of the drain side offset region 42d is defined by a length in the channel length direction from the edge portion of the drain side of the gate electrode 7A to the edge portion of the drain side of the gate insulating layer 5A when viewed from the normal direction of the substrate 1.

[0199] The first low-resistance region 4b includes a source contact region 44s electrically connected to the source electrode 8A and a drain contact region 44d electrically connected to the drain electrode 9A. The drain contact region 44d is located on the opposite side of the source contact region 44s with the first high-resistance region 4a interposed therebetween when viewed from the normal direction of the substrate 1. The first low-resistance region 4b further includes a source side interposed region 43s interposed between the source contact region 44s and the first high-resistance region 4a and a drain side interposed region 43d interposed between the drain contact region 44d and the first high-resistance region 4a.

[0200] The gate insulating layer 5A is provided over part of the first oxide semiconductor layer 4. The gate insulating layer 5A includes a first insulating film 51 and a second insulating film 52 provided over the first insulating film 51. In this example, the gate insulating layer 5A has a layered structure in which the first insulating film 51 is the lower layer and the second insulating film 52 is the upper layer.

[0201] The materials of the first insulating film 51 and the second insulating film 52 can be the same. For example, the first insulating film 51 and the second insulating film 52 can each be a SiO2 film. In that case, the boundary of these insulating films can be confirmed by a cross-sectional photograph or the like. Alternatively, the materials of the first insulating film 51 and the second insulating film 52 can be different from each other. For example, the first insulating film 51 can be a SiO2 film and the second insulating film 52 can be a SiO x N y film.

[0202] As illustrated in the drawing, the first insulating film 51 of the gate insulating layer 5A can be in direct contact with the upper surface of the first high-resistance region 4a of the first oxide semiconductor layer 4. Further, the second insulating film 52 of the gate insulating layer 5A can be in direct contact with the upper surface of the first insulating film 51. In the gate insulating layer 5A, the side surface of the first insulating film 51 and the side surface of the second insulating film 52 can be aligned with each other. Such a structure can be formed by patterning the first insulating film 51 and the second insulating film 52 using the same mask.

[0203] The first oxide semiconductor layer 4, the gate insulating layer 5A, and the gate electrode 7A are covered by an interlayer insulating layer 10. The interlayer insulating layer 10 may also be in direct contact with the upper surface of the first low-resistance region 4b of the first oxide semiconductor layer 4.

[0204] The source electrode 8A and drain electrode 9A are disposed, for example, on the interlayer insulating layer 10. In this example, the interlayer insulating layer 10 has: a first opening 10As that exposes the source contact region 44s of the first oxide semiconductor layer 4; and a second opening 10Ad that exposes the drain contact region 44d. The source electrode 8A is disposed on the interlayer insulating layer 10 and within the first opening 10As, and is connected to the source contact region 44s within the first opening 10As. The drain electrode 9A is disposed on the interlayer insulating layer 10 and within the second opening 10Ad, and is connected to the drain contact region 44d within the second opening 10Ad.

[0205] The first TFT 100 may also have a lower conductive layer 2A functioning as a light-shielding layer between the first oxide semiconductor layer 4 and the substrate 1. The lower conductive layer 2A is covered by a lower insulating layer 3. The first oxide semiconductor layer 4 is disposed on the lower conductive layer 2A with respect to the lower insulating layer 3. The lower conductive layer 2A may be configured to overlap at least the first channel region 41 of the first oxide semiconductor layer 4 when viewed from the normal direction of the substrate 1. This can suppress the degradation of the characteristics of the first oxide semiconductor layer 4 caused by light (backlight light) from the substrate 1 side. The lower conductive layer 2A may also overlap at least partially with the first offset region 42 of the first oxide semiconductor layer 4 when viewed from the normal direction of the substrate 1, for example, it may overlap entirely with the first high-resistance region 4a. By shielding part or all of the first offset region 42, it is possible to suppress the first offset region 42 from becoming low-resistance due to light degradation. Therefore, it is possible to suppress the increase of cutoff leakage current.

[0206] When using the first TFT100 as FIG. 1 In the case of the pixel transistor Tp (pixel TFT) shown, the gate electrode 7A is electrically connected to the corresponding gate bus GL. The gate electrode 7A can be integrally formed with the corresponding gate bus GL using the same conductive film. The source electrode 8A is electrically connected to the corresponding source bus SL. The source electrode 8A can be integrally formed with the corresponding source bus SL using the same conductive film. The drain electrode 9A is electrically connected to the corresponding pixel electrode PE.

[0207] On the other hand, like the first TFT 100, the second TFT 200 includes a second oxide semiconductor layer 6, a gate insulating layer 5B provided over a part of the second oxide semiconductor layer 6, a gate electrode 7B provided over a part of the gate insulating layer 5B, and a source electrode 8B and a drain electrode 9B.

[0208] The gate insulating layer 5B of the second TFT 200 includes the second insulating film 52 but does not include the first insulating film 51, unlike the gate insulating layer 5A of the first TFT 100. In this example, the gate insulating layer 5B is thinner than the gate insulating layer 5A by the thickness of the first insulating film 51. The gate insulating layer 5B can be composed of only the second insulating film 52. The second insulating film 52 of the gate insulating layer 5B can be in direct contact with a part of the upper surface of the first oxide semiconductor layer 4 (the upper surface of the first high-resistance region 4a).

[0209] A first insulating layer 5C including the first insulating film 51 can be provided between the second oxide semiconductor layer 6 and the substrate 1. That is, the second oxide semiconductor layer 6 can be positioned between the first insulating layer 5C and the gate insulating layer 5B. In other words, the second oxide semiconductor layer 6 can be positioned between the first insulating film 51 and the second insulating film 52. The side surface of the first insulating layer 5C can be aligned with the side surface of the second oxide semiconductor layer 6. This configuration enables patterning of the first insulating film 51 using the second oxide semiconductor layer 6 as a mask.

[0210] Further, in this specification, the second insulating film 52 serving as the upper layer of the gate insulating layer 5A of the first TFT 100 and the second insulating film 52 included in the gate insulating layer 5B of the second TFT 200 are formed of the same insulating film (i.e., are the same layer). Similarly, the first insulating film 51 serving as the lower layer of the gate insulating layer 5A of the first TFT 100 and the first insulating film 51 included in the first insulating layer 5C on the substrate 1 side of the second oxide semiconductor layer 6 are the same layer.

[0211] The second oxide semiconductor layer 6, like the first oxide semiconductor layer 4 of the first TFT 100, includes a second high-resistance region 6a covered with the gate insulating layer 5B and second low-resistance regions 6b positioned on both sides of the second high-resistance region 6a and not covered with the gate insulating layer 5B.

[0212] The second high-resistance region 6a includes a second channel region 61 overlapping the gate electrode 7B when viewed from the normal direction of the substrate 1, and a second offset region 62 overlapping the gate insulating layer 5B and not overlapping the gate electrode 7B. The second offset region 62 includes a source side offset region 62s and a drain side offset region 62d. On the other hand, the second low-resistance region 6b includes a source contact region 64s electrically connected to the source electrode 8B, a drain contact region 64d electrically connected to the drain electrode 9B, a source side intervening region 63s intervening between the source contact region 64s and the second high-resistance region 6a, and a drain side intervening region 63d intervening between the drain contact region 64d and the second high-resistance region 6a.

[0213] The second offset region 62 has a length L2 in the channel length direction. In this example, the length L2 is a length in which a length L2s in the channel length direction of the source side offset region 62s and a length L2d in the channel length direction of the drain side offset region 62d are added together. The length L2s of the source side offset region 62s is defined by a length in the channel length direction from the edge on the source side of the gate electrode 7B to the edge on the source side of the gate insulating layer 5B when viewed from the normal direction of the substrate 1. Similarly, the length L2d of the drain side offset region 62d is defined by a length in the channel length direction from the edge on the drain side of the gate electrode 7B to the edge on the drain side of the gate insulating layer 5B when viewed from the normal direction of the substrate 1.

[0214] In this embodiment, the length L2 of the second offset region 62 in the second TFT 200 is smaller than the length L1 of the first offset region 42 in the first TFT 100. As shown in the figure, the lengths L2s, L2d of the offset regions on the source side and the drain side of the second TFT 200 can be respectively smaller than the lengths L1s, L1d of the offset regions on the source side and the drain side of the first TFT 100.

[0215] The second oxide semiconductor layer 6, the gate insulating layer 5B, and the gate electrode 7B are covered with an interlayer insulating layer 10. The interlayer insulating layer 10 can be in direct contact with the upper surface of the second low-resistance region 6b of the second oxide semiconductor layer 6.

[0216] The source electrode 8B and the drain electrode 9B are provided, for example, on the interlayer insulating layer 10. As with the first TFT 100, in this example, the source electrode 8B is connected to the source contact region 64s within a first opening portion 10Bs formed in the interlayer insulating layer 10. The drain electrode 9B is connected to the drain contact region 64d within a second opening portion 10Bd formed in the interlayer insulating layer 10.

[0217] As with the 1st TFT 100, the 2nd TFT 200 can also have the lower conductive layer 2B functioning as a light-blocking layer between the 2nd oxide semiconductor layer 6 and the substrate 1. The lower conductive layer 2B is covered with the lower insulating layer 3. As shown in the drawing, the 1st insulating layer 5C can be provided on the lower insulating layer 3, and the 2nd oxide semiconductor layer 6 can be provided on the 1st insulating layer 5C. As with the light-blocking layer of the 1st TFT 100, the lower conductive layer 2B can be provided so as to overlap at least the 2nd channel region 61 of the 2nd oxide semiconductor layer 6 when viewed from the normal line direction of the substrate 1. The lower conductive layer 2B can also at least partially overlap the 2nd offset region 62 of the 2nd oxide semiconductor layer 6, for example, can overlap the entire 2nd high-resistance region 6a when viewed from the normal line direction of the substrate 1.

[0218] The gate electrodes 7A, 7B of the 1st TFT 100 and the 2nd TFT 200 can be formed of the same conductive film (gate conductive film), and the source electrodes 8A, 8B and the drain electrodes 9A, 9B can be formed of the same conductive film (source conductive film). In addition, the lower conductive layers 2A, 2B can each be formed of the same conductive film (lower conductive film).

[0219] The structures of the 1st TFT 100 and the 2nd TFT 200 are not limited to the structures shown in FIGS. 1A and IB. FIG. 2A and FIG. 2B

[0220] In the illustrated example, in the 1st TFT 100, the length L1s of the source side offset region 42s and the length L1d of the drain side offset region 42d are substantially the same, but they can also be different from each other (asymmetrical structure). Similarly, in the 2nd TFT 200, the lengths L2s, L2d of the source side offset region 62s and the drain side offset region 62d can also be different from each other.

[0221] In the 1st TFT 100 and the 2nd TFT 200, the lower conductive layers 2A, 2B can be in an electrically floating state, or can be fixed to the GND potential (0 V). Alternatively, the lower conductive layers 2A, 2B can also function as lower gate electrodes by electrically connecting the lower conductive layers 2A, 2B to the gate electrodes 7A, 7B, respectively, with connection portions not shown (double-gate structure). Thereby, the on-current can be further increased. For example, in the 2nd TFT 200, the lower conductive layer 2B can be provided so as to at least partially overlap the 2nd offset region 62 when viewed from the normal line direction of the substrate 1, and the lower conductive layer 2B can be caused to function as a lower gate electrode. Thereby, by applying a prescribed voltage to the lower gate electrode also when the 2nd TFT 200 is turned on, the 2nd offset region 62 is made low in resistance. Thus, the on-current can be further increased.

[0222] ​In addition, in the 1st TFT 100 and / or the 2nd TFT 200, at least one of the source electrode and the drain electrode can be provided on the substrate 1 side than the 1st oxide semiconductor layer 4 and the 2nd oxide semiconductor layer 6. For example, at least one of the source electrode and the drain electrode can be formed using the same conductive film as the lower conductive layers 2A, 2B, and electrically connected to the corresponding oxide semiconductor layer in the opening portion formed in the lower insulating layer 3.

[0223] Further, the planar shape, size, channel length, channel width, and the like of each layer of the 1st TFT 100 and the 2nd TFT 200 can be set according to the use of each TFT, and can be different from each other.

[0224] <Effects>

[0225] As shown in Table 1, in the present embodiment, the (i) oxide semiconductor material, the (ii) structure of the gate insulating layer, and the (iii) length of the offset region of the 1st TFT 100 and the 2nd TFT 200 are different from each other. Thereby, the characteristics of the 1st TFT 100 and the 2nd TFT 200 can be made different from each other. In this example, the 2nd TFT 200 can have a higher TFT mobility than the 1st TFT 100. In addition, "large", "small", "high", and "low" in Table 1 indicate a relative size relationship when compared with the other TFT.

[0226] [Table 1]

[0227]

[0228] FIG. 3 is a graph illustrating the Vg-Id characteristics of the 1st TFT 100 and the 2nd TFT 200. The horizontal axis of the coordinate graph indicates the potential of the gate electrode (gate-drain voltage) Vg with the potential of the drain electrode as a reference, and the vertical axis of the coordinate graph indicates the drain current Id.

[0229] According to FIG. 3 As can be seen, the 2nd TFT 200 has a threshold voltage higher than that of the 1st TFT 100 in the positive direction. It is considered that this is because, as described above, the TFT mobility of the 2nd TFT 200 is higher than that of the 1st TFT 100 due to the difference in the material and structure shown in Table 1, and the threshold voltage is shifted in the positive direction.

[0230] The first TFT 100 is suitable for use as a pixel TFT because of its small off-state current. The pixel TFT can have an enhancement characteristic with a positive threshold voltage or a depletion characteristic with a negative threshold voltage. In addition, in the case where the first TFT 100 has an enhancement characteristic, it can be suitably used for a circuit TFT such as a TFT for a driver circuit. Thus, power consumption can be reduced. In addition, malfunction of a circuit can be suppressed, and reduction in yield can be suppressed. Furthermore, the first TFT 100 can be used as a TFT for inspection or a TFT for ESD protection.

[0231] The second TFT 200 is suitable for use as a circuit TFT such as a TFT for an SSD circuit, for example. The second TFT 200 has higher TFT mobility than the first TFT 100, and is excellent in current driving force (on-state current). In addition, short channeling can be achieved, and the area of a circuit can be reduced.

[0232] Alternatively, the first TFT 100 and the second TFT 200 can be mixed in a driver circuit. For example, the second TFT 200 with high mobility can be used as at least a TFT referred to as an "output transistor (also referred to as a buffer transistor)" (which will be described later) included in a gate driver circuit, and the first TFT 100 can be used as any other TFT. FIG. 9

[0233] Preferred characteristics of a pixel TFT, a TFT for a driver circuit, and a TFT for an SSD circuit in a liquid crystal display device are exemplified in Table 2. The characteristics and the range of values described in Table 2 are examples, and do not limit the characteristics of each TFT.

[0234] [Table 2]

[0235]

[0236] According to this embodiment, the characteristics of the first TFT 100 and the second TFT 200 can be controlled independently of each other. First, in the first TFT 100 and the second TFT 200, a preferred oxide semiconductor material can be separately selected. Second, the thickness of the gate insulating layer 5A and 5B of each TFT can be controlled independently of each other. Specifically, the thickness of the gate insulating layer 5B of the second TFT 200 can be controlled by the thickness of the second insulating film 52. The thickness of the gate insulating layer 5A of the first TFT 100 is the total thickness of the first insulating film 51 and the second insulating film 52, and thus can be controlled by adjusting the thickness of the first insulating film 51. Third, the length L1 and L2 of the offset region of each TFT can be controlled, for example, by the thickness of the first insulating film 51 and the second insulating film 52, etching conditions of these insulating films, and the like.

[0237] ​Further, according to the present embodiment, it is possible to suppress an increase in the number of manufacturing steps and to separately produce TFTs having different characteristics. Specifically, as described later in detail, after the first oxide semiconductor layer 4 of the first TFT 100 is formed, the first insulating film, the second oxide semiconductor layer 6 of the second TFT 200, and the second insulating film are sequentially formed. Thereafter, the first insulating film and the second insulating film are patterned. Thus, on the first oxide semiconductor layer 4, the gate insulating layer 5A including the first insulating film and the second insulating film is formed. On the second oxide semiconductor layer 6, the gate insulating layer 5B including the second insulating film and not including the first insulating film is formed. The gate insulating layers 5A and 5B can be formed by patterning the first insulating film and the second insulating film using the same etching mask. In this case, the gate insulating layer 5A is thicker than the gate insulating layer 5B, and thus the length of the taper shape in the channel length direction (taper length) formed on the side surface of the gate insulating layer 5A becomes larger than that of the gate insulating layer 5B. As a result, it is possible to make the length LI of the offset region of the first TFT 100 larger than the length L2 of the offset region of the second TFT 200 by an amount of the difference in the taper length of the gate insulating layers 5A and 5B.

[0238] Further, in the conventional method, in the case where oxide semiconductor layers of two TFTs are formed in different layers, the oxide semiconductor layer formed first can be damaged in a process of forming another oxide semiconductor layer later. In contrast, according to the above method, the formation of the second oxide semiconductor layer 6 (deposition and patterning of the high-mobility oxide semiconductor film) can be performed with the entire first oxide semiconductor layer 4 covered with the first insulating film 51. Thus, it is possible to reduce damage to the first oxide semiconductor layer 4 in later processes.

[0239] <Concerning High-mobility Oxide Semiconductor Film and Low-mobility Oxide Semiconductor Film>

[0240] The composition, thickness, crystal structure, formation method, and the like of the low-mobility oxide semiconductor film used for the first oxide semiconductor layer 4 of the first TFT 100 and the high-mobility oxide semiconductor film used for the second oxide semiconductor layer 6 of the second TFT 200 are not particularly limited. The high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film can each be a single-layer film or a stacked film including a plurality of oxide semiconductor films. It is only necessary that the mobility of the high-mobility oxide semiconductor film (the mobility of the entire stacked film in the case where the high-mobility oxide semiconductor film is a stacked film) be higher than that of the low-mobility oxide semiconductor film.

[0241] The compositions of the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film can be different from each other. By "different compositions" is meant that the types or composition ratios of metal elements included in each layer are different. As one example, the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film can each include In and / or Sn, and the total of the atomic ratios of In and Sn with respect to all metal elements in the high-mobility oxide semiconductor film is greater than the total of the atomic ratios of In and Sn with respect to all metal elements in the low-mobility oxide semiconductor film.

[0242] For example, the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film can each be an In-Ga-Zn-O-based oxide semiconductor layer, and the atomic ratio of In in the low-mobility oxide semiconductor film can be less than the atomic ratio of In in the high-mobility oxide semiconductor film. Alternatively, the atomic ratio of Ga in the low-mobility oxide semiconductor film can be greater than the atomic ratio of Ga in the high-mobility oxide semiconductor film.

[0243] Alternatively, the high-mobility oxide semiconductor film can include Sn and the low-mobility oxide semiconductor film can not include Sn. Alternatively, the low-mobility oxide semiconductor film can include Sn at a lower concentration than the high-mobility oxide semiconductor film. That is, the atomic ratio of Sn with respect to all metal elements in the low-mobility oxide semiconductor film can be less than the atomic ratio of Sn with respect to all metal elements in the high-mobility oxide semiconductor film.

[0244] As the low-mobility oxide semiconductor film, for example, an In-Ga-Zn-O-based semiconductor film (In:Ga:Zn = 1:1:1 or the like) can be used. As the high-mobility oxide semiconductor film, for example, an In-Ga-Zn-O-based semiconductor film (In:Ga:Zn = 5:1:4 or the like), an In-Sn-Zn-O-based semiconductor film, an In-Al-Sn-Zn-O-based semiconductor film, an In-W-Zn-O-based semiconductor film, an In-Sn-O-based semiconductor film, an In-Zn-O-based semiconductor film, an In-Ga-Sn-O-based semiconductor film, an In-Sn-Ti-Zn-O-based semiconductor film, or the like can be used.

[0245] Alternatively, the low-mobility oxide semiconductor film and the high-mobility oxide semiconductor film can have different crystal structures from each other. For example, one of these oxide semiconductor films can be an amorphous oxide semiconductor film and the other can be a crystalline oxide semiconductor film including a crystalline portion.

[0246] Further, even when the proportion of each metal element is the same, the mobility of the oxide semiconductor film can be changed by changing the film formation method or the film formation conditions. For example, the atmosphere in a chamber when the oxide semiconductor film is formed by a sputtering method (e.g., the flow ratio of oxygen and Ar supplied to the chamber) can be changed. Specifically, the flow ratio of oxygen to Ar can be set to be large (e.g., 80 %) when a low-mobility oxide semiconductor film is formed, and the flow ratio of oxygen to Ar can be set to be smaller than that when the low-mobility oxide semiconductor film is formed (e.g., 20 %) when a high-mobility oxide semiconductor film is formed.

[0247] The thickness of the low-mobility oxide semiconductor film and the high-mobility oxide semiconductor film can be substantially the same or can be different. The high-mobility oxide semiconductor film can be thinner than the low-mobility oxide semiconductor film. Alternatively, the high-mobility oxide semiconductor film can be thicker than the low-mobility oxide semiconductor film. The thickness of the high-mobility oxide semiconductor film is, for example, greater than or equal to 5 nm and less than or equal to 50 nm. The thickness of the low-mobility oxide semiconductor film is, for example, greater than or equal to 10 nm and less than or equal to 100 nm.

[0248] <Method for manufacturing active matrix substrate 1000>

[0249] Hereinafter, an example of a method for manufacturing an active matrix substrate will be described with reference to an active matrix substrate for a liquid crystal display device of an FFS mode.

[0250] FIG. 4A to FIG. 4P and FIG. 5A to FIG. 5C are cross-sectional views each illustrating a step of the method for manufacturing the active matrix substrate 1000.

[0251] Here, an example in which the first TFT 100 is formed as a pixel TFT and the second TFT 200 is formed as a circuit TFT included in a peripheral circuit in each pixel region PIX is shown. The second TFT 200 is used for an SSD circuit, for example. Note that the use of each TFT is not limited to the example shown in the drawings. In the following description, a region where the first TFT 100 (pixel TFT) is formed is referred to as a "first TFT formation region r1", and a region where the second TFT 200 (circuit TFT) is formed is referred to as a "second TFT formation region r2". The active matrix substrate 1000 includes a plurality of pixel TFTs and a plurality of circuit TFTs, and here, only a single pixel TFT and a single circuit TFT are shown.

[0252] • STEP 1: Formation of a lower conductive layer FIG. 4A

[0253] A lower conductive film (thickness: greater than or equal to 50 nm and less than or equal to 500 nm, for example) is formed over the substrate 1 by a sputtering method, for example. Next, patterning of the lower conductive film is performed by a known photolithography process. Thus, as shown in FIG. 1A, a lower conductive layer 110 is formed in the first TFT formation region r1 and the second TFT formation region r2.​FIG. 4A As shown, a lower conductive layer 2A is formed in the first TFT forming region r1, and a lower conductive layer 2B is formed in the second TFT forming region r2.

[0254] As substrate 1, transparent and insulating substrates such as glass substrates, silicon substrates, and heat-resistant plastic substrates (resin substrates) can be used.

[0255] The material of the lower conductive film is not particularly limited, and films containing metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or their alloys, or metal nitrides, can be used. Alternatively, a laminated film formed by stacking multiple such films can also be used.

[0256] Here, a single-layer film containing a metal film (including an alloy film) of Cu or Al is used as the lower conductive film. Alternatively, a multilayer film with a metal film containing Cu or Al as the uppermost layer can also be used.

[0257] STEP 2: Formation of the lower insulating layer 3 FIG. 4B )

[0258] Next, as FIG. 4B As shown, a lower insulating layer 3 (thickness: for example, 200nm or more and 600nm or less) is formed in such a way as to cover the lower conductive layers 2A and 2B.

[0259] The lower insulating layer 3 is formed, for example, by a CVD method. As the lower insulating layer 3, silicon oxide (SiOx) layers, silicon nitride (SiNx) layers, silicon oxynitride (SiOxNy; x>y) layers, and silicon oxynitride (SiNxOy; x>y) layers can be appropriately used. The lower insulating layer 3 can be a single layer or have a stacked structure. For example, to prevent impurities from diffusing from the substrate 1, a silicon nitride (SiNx) layer or a silicon oxynitride layer can be formed on the substrate side (lower layer), and to ensure insulation, a silicon oxide (SiO2) layer or a silicon oxynitride layer can be formed on top of it (upper layer).

[0260] STEP 3: Formation of the first oxide semiconductor layer 4 FIG. 4C )

[0261] Next, a low-mobility oxide semiconductor film is formed on the lower insulating layer 3, and the low-mobility oxide semiconductor film is patterned. Thus, as... FIG. 4C As shown, a first oxide semiconductor layer 4, which serves as the active layer of the first TFT, is formed in the first TFT formation region r1. The portion of the low-mobility oxide semiconductor film located in the second TFT formation region r2 is removed.

[0262] Low-mobility oxide semiconductor films can be formed, for example, by sputtering. Here, an In-Ga-Zn-O semiconductor film (e.g., In:Ga:Zn = 1:1:1 or 4:2:4) with a thickness of 40 nm is formed as a low-mobility oxide semiconductor film.

[0263] Patterning of low-mobility oxide semiconductor films can be performed using either dry etching or wet etching. In the case of wet etching, if the low-mobility oxide semiconductor film is an In-Ga-Zn-O based semiconductor film, PAN-based or oxalic acid-based etching solutions can be used.

[0264] STEP 4: Formation of insulating film 510 ( FIG. 4D )

[0265] Next, as FIG. 4D As shown, an insulating film 510 is formed as a first insulating film in a manner that covers the first oxide semiconductor layer 4. The insulating film 510 can be formed, for example, by a CVD method.

[0266] An insulating film identical to the lower insulating layer 3 (exemplified as the lower insulating layer 3) can be used as the insulating film 510. Here, a silicon oxide (SiO2) film is formed as the insulating film 510. When an oxide film such as silicon oxide is used as the insulating film 510, oxidation defects generated in the channel region of each TFT can be reduced by the oxide film, thus suppressing the low resistance of the channel region. The thickness of the insulating film 510 can be, for example, 20 nm or more and 200 nm or less. The thickness of the insulating film 510 can be set, for example, such that the thickness of the gate insulating layer of the first TFT (the total thickness of the first insulating film and the second insulating film) is 100 nm or more and 450 nm or less.

[0267] STEP 5: Formation of the second oxide semiconductor layer 6 FIG. 4E )

[0268] Next, as FIG. 4E As shown, a high-mobility oxide semiconductor film is formed on the insulating film 510, and the high-mobility oxide semiconductor film is patterned. Thus, as... FIG. 4E As shown, a second oxide semiconductor layer 6 is formed as the active layer of the second TFT in the second TFT formation region r2. The portion of the high-mobility oxide semiconductor film located in the first TFT formation region r1 is removed.

[0269] High-mobility oxide semiconductor films can be formed, for example, by sputtering. Here, an In-Ga-Zn-O semiconductor film (e.g., In:Ga:Zn = 5:1:4) with a thickness of 35 nm is formed as the high-mobility oxide semiconductor film 60. Alternatively, an In-Sn-Zn-O semiconductor film (e.g., In₂O₃-SnO₂-ZnO) containing Sn can be formed with a thickness of 35 nm. The high-mobility oxide semiconductor film can also be a multilayer film containing a high-mobility material.

[0270] Patterning of high-mobility oxide semiconductor films can be performed using either dry etching or wet etching. In the case of wet etching, if the high-mobility oxide semiconductor film is an In-Ga-Zn-O based semiconductor film, a PAN-based etchant or an oxalic acid-based etchant can be used. If the high-mobility oxide semiconductor film is an In-Sn-Zn-O based semiconductor film, an oxalic acid-based etchant can be used.

[0271] Annealing of these oxide semiconductor films can also be performed before or after patterning of high-mobility and low-mobility oxide semiconductor films.

[0272] STEP 6: Formation of insulating film 520 ( FIG. 4F )

[0273] Next, as FIG. 4F As shown, an insulating film (sometimes referred to as "other insulating film") 520, which serves as the second insulating film, is formed on the second oxide semiconductor layer 6 and the insulating film 510. The insulating film 520 can be formed, for example, by a CVD method.

[0274] Similar to insulating film 510, insulating film 520 can also be the same as that used in lower insulating layer 3 (exemplified by the insulating film in lower insulating layer 3). Insulating film 520 can be an insulating film comprising the same material as insulating film 510. Here, a silicon oxide (SiO2) film is formed as insulating film 520. The thickness of insulating film 520 can be, for example, 80 nm or more and 250 nm or less. The thickness of insulating film 520 defines the thickness of the gate insulating layer of the second TFT.

[0275] Furthermore, the material of the insulating film 520 can be different from that of the insulating film 510. For example, it could be a SiO2 film formed as the insulating film 510, or a SiO2 film formed as the insulating film. x N y The film serves as an insulating film 520. This allows for further improvement of the gate capacitance of the second TFT.

[0276] STEP 7: Formation of the conductive film 70 for the gate ( FIG. 4G )

[0277] Next, as FIG. 4G As shown, a gate conductive film 70 (thickness: for example, 50 nm or more and 500 nm or less) is formed on the insulating film 520.

[0278] For example, metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), and tantalum (Ta), or their alloys, can be used as the gate conductive film 70. The gate conductive film 70 can also have a stacked structure comprising multiple layers formed of different conductive materials. Here, a Cu / Cu alloy stacked film with a Cu alloy film as the lower layer and a Cu film as the upper layer is used as the gate conductive film. Alternatively, a Cu / Ti stacked film or a Cu / Mo stacked film can be used.

[0279] STEP 8: Formation of gate electrodes 7A and 7B FIG. 4H )

[0280] Next, a first resist layer R1 is formed on a portion of the gate conductive film 70. Specifically, firstly, a resist film is formed on the gate conductive film 70. Then, the resist film is exposed using a gate metal photomask and developed to obtain the first resist layer R1. The first resist layer R1 includes a mask portion m1 located in the first TFT formation region r1 and a mask portion m2 located in the second TFT formation region r2.

[0281] Next, the first resist layer R1 is used as a mask for etching the gate conductive film 70. Thus, as... FIG. 4H As shown, a gate electrode 7A is formed in the first TFT forming region r1, and a gate electrode 7B is formed in the second TFT forming region r2. Although not shown, a gate bus is also formed using a gate conductive film 70. When viewed from the normal direction of the substrate 1, the portion of the first oxide semiconductor layer 4 that overlaps with the gate electrode 7A is called the "first channel region 41", and the portion of the second oxide semiconductor layer 6 that overlaps with the gate electrode 7B is called the "second channel region 61".

[0282] The etching of the gate conductive film 70 can be performed using, for example, a hydrogen peroxide-based etchant. In this example, the etching time is set to be relatively long (such as over-etching) so that the widths (lengths in the channel length direction) of the gate electrodes 7A and 7B become smaller than the widths of the mask portions m1 and m2, respectively.

[0283] STEP 9: Patterning of insulating films 510 and 520 ( FIG. 4I , FIG. 5A to FIG. 5C )

[0284] Next, the insulating films 510 and 520 are patterned, thereby obtaining the second insulating film 52 from the insulating film 520 and the first insulating film 51 from the insulating film 510. Thus, as...FIG. 4I The gate insulating layer 5A of the 1st TFT, the gate insulating layer 5B of the 2nd TFT, and the 1st insulating layer 5C are formed as shown. The portion of the 1st oxide semiconductor layer 4 that is adjacent to the 1st channel region 41 and covered with the gate insulating layer 5A becomes a "1st offset region 42", and the portion of the 2nd oxide semiconductor layer 6 that is adjacent to the 2nd channel region 61 and covered with the gate insulating layer 5B becomes a "2nd offset region 62".

[0285] Here, reference is made to FIG. 5A to FIG. 5C The patterning method of the insulating films 510, 520 will be described in more detail. In this example, the etching of the insulating film 520 and the insulating film 510 is performed using the same 1st resist layer R1 as the etching of the gate conductive film 70, to form the gate insulating layers 5A, 5B. Thereby, the number of manufacturing processes and the manufacturing cost can be reduced.

[0286] FIG. 5A A state before the patterning of the insulating films 510, 520 is shown after the patterning of the gate conductive film 70. As shown, the mask portions m1, m2 have widths w1, w2 in the channel length direction. As described above, the widths w1, w2 of the mask portions m1, m2 are each larger than the width of the gate electrode 7A, 7B. That is, the positions e1, e2 of the edges of the mask portions m1, m2 are outside the edge portions of the gate electrodes 7A, 7B when viewed from the normal direction of the substrate 1.

[0287] Next, dry etching of the insulating films 510, 520 is performed using the 1st resist layer R1. The conditions of the dry etching are set so that the edges of the mask portions m1, m2 of the 1st resist layer R1 retreat as the etching of the etched film proceeds. For example, an etching gas containing carbon tetrafluoride (CF4) gas can be used. Thereby, a tapered shape is formed on the side wall (side surface) of the etched film. In this etching, the 1st oxide semiconductor layer 4 and the 2nd oxide semiconductor layer 6 function as etching stoppers.

[0288] FIG. 5B and FIG. 5C are drawings showing this etching process, and show the timing at which the etching of the insulating film 520 is completed and the timing at which the etching of the insulating film 51 is completed (Just Etching timing), respectively.

[0289] As FIG. 5BAs shown, in the first TFT formation region r1 and the second TFT formation region r2, etching is performed on the insulating film 520, which serves as the etched film, and the portions of the insulating film 520 not covered by the mask portions m1 and m2 are removed. In the second TFT formation region r2, the insulating film 520 is removed, thereby exposing a portion of the upper surface of the second oxide semiconductor layer 6. Furthermore, along with the etching, the mask portions m1 and m2 of the first resist layer R1 are also etched. As a result, the edges of the mask portions m1 and m2 recede from their positions e1 and e2 before the start of this etching process in the direction indicated by the arrow Ra. Thus, a tapered shape is formed on the sidewalls of the patterned insulating film 520.

[0290] like FIG. 5C As shown, during further etching, the portion of the insulating film 510 exposed by the removal of the insulating film 520 is removed. Furthermore, as etching proceeds, the edges of the mask portions m1 and m2 further recede in the direction indicated by arrow Ra. Consequently, in the first TFT formation region r1, the portion of the insulating film 510 not covered by the mask portion m1 is removed, exposing a portion of the first oxide semiconductor layer 4. With the receding of the edges of the mask portion m1, the sidewalls of the patterned insulating film 510 have a tapered shape. On the other hand, in the second TFT formation region r2, the portion of the insulating film 510 not covered by the second oxide semiconductor layer 6 is etched. Additionally, in each TFT formation region r1 and r2, the portion of the insulating film 520 exposed due to the receding edges of the mask portions m1 and m2 is further etched, thus reducing the width of the insulating film 520.

[0291] Thus, the first insulating film 51 is obtained from the insulating film 510, and the second insulating film 52 is obtained from the insulating film 520. In the first TFT forming region r1, a gate insulating layer 5A comprising the first insulating film 51 and the second insulating film 52 is formed. The side surfaces of the first insulating film 51 and the second insulating film 52 in the gate insulating layer 5A have a tapered shape. The side surfaces of the first insulating film 51 and the second insulating film 52 can be aligned with each other on the side surfaces of the gate insulating layer 5A.

[0292] On the other hand, in the second TFT formation region r2, a gate insulating layer 5B including a second insulating film 52 is formed. The gate insulating layer 5B (here, the second insulating film 52) has a tapered shape. Additionally, on the substrate 1 side of the second oxide semiconductor layer 6, a first insulating layer 5C including a first insulating film 51 is formed. Since the first insulating layer 5C is patterned using the second oxide semiconductor layer 6 as an etching mask, the side surface of the first insulating layer 5C can be aligned with the side surface of the second oxide semiconductor layer 6.

[0293] The thickness of the insulating film that becomes the gate insulating layer 5A (here, the total thickness of the first insulating film 51 and the second insulating film 52) is greater than the thickness of the insulating film that becomes the gate insulating layer 5B (here, the thickness of the second insulating film 52). Therefore, the length of the channel length direction of the portion having a tapered shape (hereinafter, referred to as "tapered length") tl in the gate insulating layer 5A becomes greater than the tapered length t2 of the gate insulating layer 5B (tl > t2). Therefore, the lengths Lls, Lld of the respective offset regions of the first TFT 100 respectively become greater than the lengths L2s, L2d of the respective offset regions of the second TFT 200 by the amount of the difference Δt (= tl - t2) of the tapered lengths. As a result, the length Ll of the first offset region 42 can be made greater than the length L2 of the second offset region 62.

[0294] The difference Δt varies depending on the thicknesses of the insulating films 510, 520 and the tapered angle. The tapered angle can be controlled, for example, by etching conditions or the like. The tapered angle of the gate insulating layer 5A and the gate insulating layer 5B is not particularly limited and can be, for example, 10° or greater and less than 75°.

[0295] In this example, the gate conductive film 70 and the insulating film 520 in the first TFT formation region r1 are etched using the same mask under the same conditions as the gate conductive film 70 and the insulating film 520 in the second TFT formation region r2. Therefore, when viewed from the normal direction of the substrate 1, the overhang amount (the distance between the edge of the second insulating film 52 and the edge of the gate electrode 7A) dl of the second insulating film 52 as the upper layer of the gate insulating layer 5A can be substantially equal to the overhang amount (the distance between the edge of the second insulating film 52 and the edge of the gate electrode 7B) d2 of the second insulating film 52 as the gate insulating layer 5B. The overhang amount d3 of the first insulating film 51 in the gate insulating layer 5A is greater than the overhang amounts dl, d2. Further, the overhang amount d3 is the lengths Lls, Lld of the respective offset regions of the first TFT. The overhang amount d2 is the lengths L2s, L2d of the respective offset regions of the second TFT.

[0296] In FIG. 5C At the appropriate etching timing shown in FIG. 6, the width of the gate insulating layer 5A in the channel length direction is the same as the width wl of the mask portion ml before the start of the present etching, but when over-etching is performed, the width of the gate insulating layer 5A becomes smaller than the width wl of the mask portion ml.

[0297] The above describes an example in which the first resist layer R1 used for patterning the conductive film 70 for the gate electrode is used to etch the insulating films 510 and 520, but the etching of the insulating films 510 and 520 can be performed using a resist layer different from the first resist layer R1. For example, after the etching of the conductive film 70 for the gate electrode, the first resist layer R1 can be removed, and another resist layer can be provided over the insulating film 520 and the gate electrodes 7A and 7B. The other resist layer includes a first mask portion having a width larger than that of the gate electrode 7A and covering the entire gate electrode 7A, and a second mask portion having a width larger than that of the gate electrode 7B and covering the entire gate electrode 7B. Thus, in each TFT, a shift region having a desired width (length in the channel length direction) can be formed adjacent to the channel region. Further, the other resist layer can be formed using the same photomask (photomask for the gate electrode) as the first resist layer R1. For example, the line width of the other resist layer can be made larger than the width defined by the photomask for the gate electrode by adjusting the exposure amount to the resist film when the other resist layer is formed.

[0298] • STEP 10: Low-resistance treatment of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 FIG. 4J

[0299] Next, low-resistance treatment of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 is performed. For example, plasma treatment can be performed as the low-resistance treatment. In the plasma treatment, exposed regions of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 exposed from the gate insulating layers 5A and 5B can be exposed to a reducing plasma or a plasma containing a doping element (e.g., an argon plasma). Thus, the resistance of the exposed regions of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 is reduced, and the exposed regions become a first low-resistance region 4b and a second low-resistance region 6b, respectively, when viewed in the direction normal to the substrate 1. The first low-resistance region 4b can be a conductor region (e.g., a sheet resistance of 200 Ω / □ or less). On the other hand, a region of the first oxide semiconductor layer 4 covered with the gate insulating layer 5A becomes a first high-resistance region (semiconductor region) 4a having a higher resistivity than that of the first low-resistance region 4b. Similarly, a region of the second oxide semiconductor layer 6 covered with the gate insulating layer 5B becomes a high-resistance region (semiconductor region) 6a having a higher resistivity than that of the second low-resistance region 6b.

[0300] The method of the low-resistance treatment (plasma treatment) is not limited to the above description. The method and conditions of the plasma treatment are described in, for example, Japanese Published Patent Application No. 2008-40343. For reference, the entire disclosure of Japanese Published Patent Application No. 2008-40343 is incorporated herein by reference. ​

[0301] Furthermore, the method for reducing resistance is not limited to plasma processing. For example, when the interlayer insulating layer 10 includes an insulating layer (e.g., a SiNx layer) that has the property of reducing oxide semiconductors, the exposed regions can also be made to have low resistance by contacting the interlayer insulating layer 10 with the exposed regions of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6.

[0302] • STEP 11: Formation of interlayer insulation layer 10 ( FIG. 4K )

[0303] Next, an interlayer insulating layer 10 is formed covering the first oxide semiconductor layer 4, the second oxide semiconductor layer 6, the gate insulating layers 5A and 5B, and the gate electrodes 7A and 7B. Then, the interlayer insulating layer 10 is patterned using a known photolithography process. Thus, as... FIG. 4K As shown, first openings 10As and 10Bs and second openings 10Ad and 10Bd are formed in the interlayer insulating layer 10. The first opening 10As exposes the portion of the first low-resistance region 4b of the first oxide semiconductor layer 4 located on the source side of the first channel region 41 (source contact region 44s), and the second opening 10Ad exposes the portion of the first low-resistance region 4b of the first oxide semiconductor layer 4 located on the drain side of the first channel region 41 (drain contact region 44d). Similarly, the first opening 10Bs exposes the portion of the second low-resistance region 6b of the second oxide semiconductor layer 6 located on the source side of the second channel region 61 (source contact region 64s), and the second opening 10Bd exposes the portion of the second low-resistance region 6b of the second oxide semiconductor layer 6 located on the drain side of the second channel region 61 (drain contact region 64d).

[0304] Inorganic insulating layers such as silicon oxide films, silicon nitride films, silicon oxynitride films, and silicon oxynitride films can be formed as single layers or stacked layers as interlayer insulating layers 10. The thickness of the inorganic insulating layer can be 100 nm or more and 500 nm or less. When an insulating film such as a silicon nitride film that reduces oxide semiconductors is used to form the interlayer insulating layer 10, it is preferable to maintain a low resistivity in the regions of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 that are in contact with the interlayer insulating layer 10 (here, the first low-resistance region 4b and the second low-resistance region 6b). Here, for example, a SiNx layer (thickness: 300 nm) is formed by CVD as the interlayer insulating layer 10.

[0305] In a case where an insulating layer (for example, a silicon nitride layer or the like, a hydrogen supply layer) that can reduce the oxide semiconductor is used as the interlayer insulating layer 10, even if the above-described low-resistance treatment is not performed, the portions of the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 that are in contact with the interlayer insulating layer 10 can be made lower in resistance than the portions that are not in contact with the interlayer insulating layer 10.

[0306] • STEP 12: Formation of source electrodes 8A, 8B and drain electrodes 9A, 9B FIG. 4L

[0307] Next, on the interlayer insulating layer 10, a source conductive film (thickness: for example, 50 nm or more and 500 nm or less) that is not shown is formed, and the source conductive film is patterned. Thus, as shown in FIG. 1, the source electrodes 8A, 8B and the drain electrodes 9A, 9B are formed. Although not shown, a source bus line is also formed from the source conductive film. FIG. 4L

[0308] In the first TFT formation region r1, the source electrode 8A and the drain electrode 9A are disposed on the interlayer insulating layer 10 and in the opening portions 10As, 10Ad, respectively, and are connected to the source contact region 44s and the drain contact region 44d of the first oxide semiconductor layer 4 in the opening portions 10As, 10Ad. Similarly, in the second TFT formation region r2, the source electrode 8B and the drain electrode 9B are disposed on the interlayer insulating layer 10 and in the opening portions 10Bs, 10Bd, respectively, and are connected to the source contact region 64s and the drain contact region 64d of the second oxide semiconductor layer 6 in the opening portions 10Bs, 10Bd. In this way, the first TFT 100 that becomes a pixel transistor is formed in the first TFT formation region r1, and the second TFT 200 that becomes a circuit transistor is formed in the second TFT formation region r2.

[0309] As the source conductive film, for example, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy or the like that includes these elements as components can be used. For example, a three-layer structure of a titanium film-aluminum film-titanium film, a three-layer structure of a molybdenum film-aluminum film-molybdenum film, or the like can be used. Further, the source conductive film is not limited to a three-layer structure, and can have a single-layer or two-layer structure, or a stacked structure of four or more layers. Here, a stacked film in which a Ti film (thickness: 15 to 70 nm) is a lower layer and a Cu film (thickness: 50 to 400 nm) is an upper layer is used. When a stacked film in which an ohmic conductive film such as a Ti film is a lowermost layer is used, the contact resistance with the first oxide semiconductor layer 4 and the second oxide semiconductor layer 6 can be more effectively reduced.

[0310] • STEP 13: Formation of inorganic insulating layer 11 and organic insulating layer 12 FIG. 4M ​​)

[0311] Next, as shown in FIG. 4M , an upper insulating layer 13 is formed so as to cover the interlayer insulating layer 10 and the TFTs 100, 200. Here, an inorganic insulating layer 11 (thickness: for example, 100 nm or more and 500 nm or less) and an organic insulating layer 12 (thickness: for example, 1 to 4 μm, preferably 2 to 3 μm) are sequentially formed as the upper insulating layer 13.

[0312] The same inorganic insulating film as the interlayer insulating layer 10 can be used as the inorganic insulating layer 11. Here, for example, a SiNx layer (thickness: 300 nm) is formed as the inorganic insulating layer 11 by a CVD method. The organic insulating layer 12 can be, for example, an organic insulating film (for example, an acrylic resin film) containing a photosensitive resin material.

[0313] After that, patterning of the organic insulating layer 12 is performed. Thereby, in each pixel region, an opening portion 12p which exposes a part of the inorganic insulating layer 11 is formed in the organic insulating layer 12. The opening portion 12p is disposed so as to overlap the drain electrode 9A of the TFT 100 when viewed from the normal direction of the substrate 1. In this patterning, the entire portion of the organic insulating layer 12 located in the non-display region can also be removed.

[0314] • STEP 14: Formation of Common Electrode CE FIG. 4N

[0315] Next, as shown in FIG. 4N , a common electrode CE is formed on the upper insulating layer 13.

[0316] First, a first transparent conductive film (thickness: 20 to 300 nm) which is not shown is formed on the upper insulating layer 13 and in the opening portion 12p. Here, for example, an indium-zinc oxide film is formed as the first transparent conductive film by a sputtering method. As the material of the first transparent conductive film, a metal oxide such as indium-tin oxide (ITO), indium-zinc oxide, ZnO, or the like can be used. After that, patterning of the first transparent conductive film is performed. In the patterning, for example, wet etching can be performed using an oxalic acid-based etching solution. Thereby, the common electrode CE is obtained. The common electrode CE can have an opening portion, for example, on a region where a pixel contact hole is formed.

[0317] • STEP 15: Formation of Dielectric Layer 17 FIG. 4O

[0318] Next, as shown in FIG. 4O , a dielectric layer 17 (thickness: 50 to 500 nm) is formed so as to cover the common electrode CE, and patterning of the dielectric layer 17 and the inorganic insulating layer 11 is performed.

[0319] ​​The dielectric layer 17 is formed in the pixel region on the organic insulating layer 12 and the common electrode CE and in the opening portion 12p. The material of the dielectric layer 17 can be the same as the materials exemplified as the material of the inorganic insulating layer 11. Here, for example, a SiN film is formed as the dielectric layer 17 by a CVD method.

[0320] After that, by a known photolithography process, etching of the dielectric layer 17 and the inorganic insulating layer 11 is performed, and a pixel contact hole CHp is formed which exposes the drain electrode 9A of the TFT 100. In this example, the pixel contact hole CHp includes an opening portion 17p of the dielectric layer 17, an opening portion 12p of the organic insulating layer 12, and an opening portion 11p of the inorganic insulating layer 11. The opening portion 17p can at least partially overlap the opening portion 12p when viewed from the normal direction of the substrate 1. The opening portion 11p is etched with the resist layer (not shown) on the dielectric layer 17 and the organic insulating layer 12 as masks.

[0321] • STEP 16: Formation of the pixel electrode PE FIG. 4P

[0322] Next, a second transparent conductive film (thickness: 20 to 300 nm) which is not shown is formed on the dielectric layer 17 and in the pixel contact hole CHp. The second transparent conductive film can be formed using the same material as the first transparent conductive film.

[0323] After that, patterning of the second transparent conductive film is performed. Here, for example, wet etching of the second transparent conductive film is performed using an oxalic acid-based etching solution. Thus, as shown in FIG. 1C, the pixel electrode PE is formed in each pixel region. The pixel electrode PE is connected to the drain electrode 9A of the TFT 100 in the pixel contact hole CHp. In this way, the active matrix substrate 1000 is manufactured. FIG. 4P

[0324] The structure of the active matrix substrate 1000 is not limited to the structure shown in the drawing. It is only necessary that the pixel electrode PE and the common electrode CE be arranged so as to face each other with the dielectric layer 17 interposed therebetween. Here, an example is shown in which the common electrode CE is arranged on the pixel electrode PE with the dielectric layer 17 interposed therebetween, but the common electrode CE can also be arranged on the substrate 1 side of the pixel electrode PE.

[0325] In addition, the source electrode of the pixel TFT and a source bus line which is not shown can be formed in the same layer as the lower conductive layers 2A and 2B (i.e., formed using the same conductive film as the lower conductive layers 2A and 2B). Furthermore, the pixel electrode PE can be directly connected to the oxide semiconductor layer (drain contact region) of the pixel TFT. In this case, the portion of the pixel electrode PE which contacts the oxide semiconductor layer of the pixel TFT is sometimes referred to as a "drain electrode".

[0326] ​​The method of manufacturing the active matrix substrate is not limited to the above-described method. For example, the patterning method of the insulating film 510 and the insulating film 520 in STEP 9 is not limited to the method described with reference to FIG. 5A to FIG. 5C The following describes a modification example of the patterning method of the insulating film 510 and the insulating film 520 with reference to the drawings.

[0327] <Modification Example 1>

[0328] In Modification Example 1, the insulating film 510 and the insulating film 520 are patterned using different resist masks, respectively.

[0329] FIG. 6A to FIG. 6D The following describes a modification example of the patterning method of the insulating film 510 and the insulating film 520 with reference to the drawings. As for the material, thickness, formation process, and the like of each layer, if they are the same as those described with reference to FIG. 4A to FIG. 4P and FIG. 5A to FIG. 5C , the description is omitted.

[0330] First, the formation process of the gate electrodes 7A, 7B is performed in the same manner as that described with reference to FIG. 4A to FIG. 4H . In STEP 8, the patterning of the conductive film 70 for gate electrode is performed using the first resist layer Rl, and the gate electrodes 7A, 7B are formed. FIG. 6A The state before the patterning of the insulating films 510, 520 is performed after the formation of the gate electrodes 7A, 7B is shown.

[0331] Next, as shown in FIG. 6B , the dry etching of the insulating film 520 (referred to as "first etching") is performed using the first resist layer Rl used in the etching of the conductive film 70 for gate electrode, and the second insulating film 52 is obtained. FIG. 6B The point in time at which the etching of the insulating film 520 is completed (the point in time at which the etching is appropriately performed) is shown. The conditions of the first etching can be the same as those described with reference to FIG. 5B and FIG. 5C except that the etching time is shortened.

[0332] By the first etching, the second insulating film 52 that becomes the upper layer of the gate insulating layer of the first TFT is formed in the first TFT formation region r1, and the second insulating film 52 that becomes the gate insulating layer 5B of the second TFT is formed in the second TFT formation region r2. Thereafter, the first resist layer Rl is removed.

[0333] Further, at the point in time at which the etching is appropriately performed shown in FIG. 6B , the width of the second insulating film 52 is the same as the width wl, w2 of the mask portions ml, m2 before the first etching is started, but when over-etching is performed, the width of the second insulating film 52 becomes smaller than the width wl, w2 of the mask portions ml, m2.

[0334] Next, as shown in FIG. 5B, a second resist layer R2 is formed over the insulating film 520, the gate insulating layer 5B, and the gate electrodes 7A and 7B. The second resist layer R2 includes a mask portion m3 and a mask portion m4. FIG. 6C

[0335] The mask portion m3 covers the entire gate insulating layer 5A and gate electrode 7A in the first TFT formation region r1. In this example, the width w3 of the mask portion m3 in the channel length direction is larger than the width of the second insulating film 52 which is the upper layer of the gate insulating layer 5A, and is smaller than the width of the first oxide semiconductor layer 4. That is, the position e3 of the edge of the mask portion m3 is set to be outside the side surface of the second insulating film 52 and inside the side surface of the first oxide semiconductor layer 4 when viewed from the normal direction of the substrate 1. The width of the mask portion m3 can be set to be sufficiently larger than the width of the second insulating film 52 so that the second insulating film 52 is not etched even if the edge of the mask portion m3 recedes in the second etching to be described later.

[0336] The mask portion m4 covers the entire gate insulating layer 5B and gate electrode 7B in the second TFT formation region r2. In this example, the width w4 of the mask portion m4 in the channel length direction is larger than the width of the gate insulating layer 5B, and is smaller than the width of the second oxide semiconductor layer 6. That is, the position e4 of the edge of the mask portion m4 is set to be outside the side surface of the gate insulating layer 5B and inside the side surface of the second oxide semiconductor layer 6 when viewed from the normal direction of the substrate 1. The width of the mask portion m4 can be set to be sufficiently larger than the width of the gate insulating layer 5B so that the gate insulating layer 5B (second insulating film 52) is not etched even if the edge of the mask portion m4 recedes in the etching to be described later.

[0337] Further, the width w4 of the mask portion m4 in the channel length direction can be set to be larger than the width of the second oxide semiconductor layer 6. Thus, the portion of the insulating film 510 which is located in the vicinity of the edge portion of the second oxide semiconductor layer 6 (particularly, below the edge portion) can be inhibited from being etched.

[0338] ​The second resist layer R2 can be formed using the same gate metal photomask as the first resist layer R1. Since the linewidths of the mask portions m1 and m2 of the first resist layer R1 are reduced by the first etching, mask portions m3 and m4 with widths larger than the mask portions m1 and m2 after the first etching can be formed even using the same photomask. By using the same photomask as the first resist layer R1 and adjusting the exposure amount, the linewidths of the mask portions m3 and m4 can be further increased. By forming the first resist layer R1 and the second resist layer R2 using the same photomask, the increase in manufacturing cost can be suppressed. Alternatively, the second resist layer R2 can use a different photomask than the first resist layer R1.

[0339] Next, as FIG. 6D As shown, the first insulating film 510 is dry-etched (referred to as "second etching") using the second resist layer R2 as a mask to obtain the first insulating film 51. FIG. 6D The etching point of insulating film 510 is shown (appropriate etching point). The conditions for the second etching, except for shortening the etching time, are the same as previously mentioned. FIG. 5B and FIG. 5C The conditions described are the same.

[0340] In the second etching, in the first TFT formation region r1, when viewed from the normal direction of the substrate 1, the portion of the insulating film 510 not covered by the mask portion m3 is removed. Thus, in the first TFT formation region r1, the insulating film 51 is formed from the insulating film 510 to become the lower layer of the gate insulating layer 5A. The side surface of the first insulating film 51 may have a tapered shape. In the illustrated example, when viewed from the normal direction of the substrate 1, in the gate insulating layer 5A, the side surface of the second insulating film 52 is located further inward than the side surface of the first insulating film 51. That is, the second insulating film 52 only covers a portion of the upper surface of the first insulating film 51, and a step is formed on the side surface of the gate insulating layer 5A. In the gate insulating layer 5A, the portion of the upper surface of the first insulating film 51 located further outward than the side surface of the second insulating film 52 (the portion not covered by the second insulating film 52) may be in direct contact with the interlayer insulating layer 10. Furthermore, in FIG. 6D At the positive edge point shown, the width of the first insulating film 51 is the same as the width w3 of the mask portion m3 before the second etching begins. However, when over-etching is performed, the width of the first insulating film 51 becomes smaller than the width w3 of the mask portion m3.

[0341] Furthermore, in the second TFT formation region r2, the portion of the insulating film 510 not covered by the second oxide semiconductor layer 6 is removed by the second etching. Thus, a first insulating layer 5C is formed from the insulating film 510. The first insulating layer 5C is located on the substrate 1 side of the second oxide semiconductor layer 6. The side surface of the first insulating layer 5C may be aligned with the side surface of the second oxide semiconductor layer 6.

[0342] Furthermore, in this example, during the second etching, the second insulating film 52, which is the upper layer of the gate insulating layer 5A, is covered by the mask portion m3 and therefore is not etched. Similarly, the gate insulating layer 5B is covered by the mask portion m4 and therefore is not etched.

[0343] Although not illustrated, the subsequent procedures are the same as those in the reference. FIG. 4J to FIG. 4P The procedures described are the same.

[0344] In this modified example, the width of the mask portion m3 of the second resist layer R2 is set such that the width of the lower layer of the gate insulating layer 5A of the first TFT is greater than the width of the gate insulating layer 5B of the second TFT. This allows the length L1 of the first offset region 42 to be greater than the length L2 of the second offset region 62.

[0345] In addition, with FIG. 5A to FIG. 5C Similarly, in this modified example, the gate conductive film 70 and insulating film 520 in the first TFT forming region r1 are etched using the same mask and under the same conditions as the gate conductive film 70 and insulating film 520 in the second TFT forming region r2. Therefore, the protrusion d1 of the second insulating film 52, which is the upper layer of the gate insulating layer 5A, is approximately equal to the protrusion d2 of the second insulating film 52, which is the gate insulating layer 5B. The protrusion d3 of the first insulating film 51 in the gate insulating layer 5A is greater than the protrusions d1 and d2.

[0346] According to this modified example, the width of the mask portion m2 of the first resist layer R1 used in the first etching can control the width of the gate insulating layer 5B of the second TFT 200 and the length L2 of the second offset region 62. Furthermore, the width of the mask portion m3 of the second resist layer R2 used in the second etching can control the width of the gate insulating layer 5A of the first TFT 100 and the length L1 of the first offset region 42. Thus, the lengths L1 of the first offset region 42 and L2 of the second offset region 62 can be controlled independently, allowing for the setting of these lengths L1 and L2 with a high degree of freedom. Moreover, even when the first and second etchings are performed under conditions where it is difficult to form a tapered shape on the sides of the second insulating film 52 and the first insulating film 51, the length L1 of the first offset region 42 can be made greater than the length L2 of the second offset region 62.

[0347]

[0348] In the modification example 2, the gate insulating layer 5A of the 1st TFT 100 and the gate insulating layer 5B of the 2nd TFT 200 are formed using different resist masks, respectively.

[0349] FIG. 7A to FIG. 7D Fig. 16 is a cross-sectional view of another modification example of a patterning method of the insulating film 510 and the insulating film 520, respectively. As for the materials, thicknesses, formation processes, and the like of the layers, if they are the same as those described with reference to Figs. 1 to 15, the description thereof is omitted. FIG. 4A to FIG. 4P and FIG. 5A to FIG. 5C The description thereof is omitted if the method is the same as that described above.

[0350] The process proceeds to a formation process of the gate electrodes 7A, 7B (STEP 8) by the method described above with reference to Figs. 1 to 15. In STEP 8, the patterning of the conductive film 70 for gate electrodes is performed using the 1st resist layer R1, and the gate electrodes 7A, 7B are formed. Thereafter, the 1st resist layer R1 is removed. FIG. 4A to FIG. 4H Next, as shown in Fig. 16, the 3rd resist layer R3 is formed on the insulating film 520 and the gate electrodes 7A, 7B. The 3rd resist layer R3 includes a mask portion m5 and a mask portion m6. The mask portion m5 is disposed so as to cover the 1st TFT formation region r1. On the other hand, in the 2nd TFT formation region r2, the mask portion m6 is disposed so as to cover a part of the gate electrode 7B and the insulating film 520. The width w6 of the mask portion m6 is larger than the width of the gate electrode 7B and smaller than the width of the 2nd oxide semiconductor layer 6.

[0351] FIG. 7A Next, as shown in Fig. 16, the 3rd resist layer R3 is formed on the insulating film 520 and the gate electrodes 7A, 7B. The 3rd resist layer R3 includes a mask portion m5 and a mask portion m6. The mask portion m5 is disposed so as to cover the 1st TFT formation region r1. On the other hand, in the 2nd TFT formation region r2, the mask portion m6 is disposed so as to cover a part of the gate electrode 7B and the insulating film 520. The width w6 of the mask portion m6 is larger than the width of the gate electrode 7B and smaller than the width of the 2nd oxide semiconductor layer 6.

[0352] Next, as shown in Fig. 16, the 3rd resist layer R3 is formed on the insulating film 520 and the gate electrodes 7A, 7B. The 3rd resist layer R3 includes a mask portion m5 and a mask portion m6. The mask portion m5 is disposed so as to cover the 1st TFT formation region r1. On the other hand, in the 2nd TFT formation region r2, the mask portion m6 is disposed so as to cover a part of the gate electrode 7B and the insulating film 520. The width w6 of the mask portion m6 is larger than the width of the gate electrode 7B and smaller than the width of the 2nd oxide semiconductor layer 6. FIG. 7B FIG. 5B FIG. 5C In the 3rd etching, the etching of the insulating films 510, 520 is performed using the 3rd resist layer R3 as a mask. The 3rd etching conditions can be the same as those described above with reference to Figs. 1 to 15. In the present embodiment, the etching of the insulating films 510, 520 is performed until the insulating films 510, 520 are completely etched (until the point of time of the appropriate etching amount), but over-etching can be performed. FIG. 7B

[0353] By the 3rd etching, in the 2nd TFT formation region r2, the 2nd insulating film 52 which becomes the gate insulating layer 5B is formed from the insulating film 520. The 2nd insulating film 52 can have a tapered shape. In addition, on the substrate 1 side of the 2nd oxide semiconductor layer 6, the 1st insulating layer 5C is formed from the insulating film 510. In the 1st TFT formation region r1, the insulating film 510 and the insulating film 520 are covered by the mask portion m5, and thus are not etched. Thereafter, the 3rd resist layer R3 is removed.

[0354] ​​​​​Next, as FIG. 7C As shown, a fourth resist layer R4 is formed on the insulating film 520, the gate insulating layer 5B, and the gate electrodes 7A and 7B. The fourth resist layer R4 includes a mask portion m7 and a mask portion m8. In the first TFT formation region r1, the mask portion m7 covers a portion of the gate electrode 7A and the insulating film 520. The width w7 of the mask portion m7 is greater than the width of the gate electrode 7A and less than the width of the first oxide semiconductor layer 4. On the other hand, the mask portion m8 is configured to cover the second TFT formation region r2.

[0355] Next, as FIG. 7D As shown, the fourth resist layer R4 is used as a mask for dry etching of the insulating film 520 and the insulating film 510 (hereinafter referred to as "the fourth dry etching"). The fourth etching conditions can be the same as those previously referred to. FIG. 5B and FIG. 5C The conditions described are the same. FIG. 7D The etching points of insulating films 510 and 520 are shown as completion points (appropriate etching points), but over-etching is also possible.

[0356] In the fourth etching, in the first TFT formation region r1, a second insulating film 52 is formed from insulating film 520 as the upper layer of the gate insulating layer 5A, and a first insulating film 51 is formed from insulating film 510 as the lower layer of the gate insulating layer 5A. The side surfaces of the second insulating film 52 and the first insulating film 51 may each have a tapered shape. In the second TFT formation region r2, the first insulating layer 5C and the gate insulating layer 5B are covered by the mask portion m8 and therefore are not etched. Afterwards, the fourth resist layer R4 is removed.

[0357] Although not illustrated, the subsequent procedures are similar to those in the diagram. FIG. 4J to FIG. 4P The procedures described are the same.

[0358] In this modified example, the width w7 of the mask portion m7 of the fourth resist layer R4 is set such that the width of the gate insulating layer 5A of the first TFT is greater than the width of the gate insulating layer 5B of the second TFT. This allows the length L1 of the first offset region 42 to be greater than the length L2 of the second offset region 62. Furthermore, a fourth etching can be performed before the third etching.

[0359] According to the present modification example, the width of the gate insulating layer 5B of the second TFT 200 and the length L2 of the second offset region 62 are controlled by the width w6 of the mask portion m6 of the third resist layer R3 used in the third etching, and the width of the gate insulating layer 5A of the first TFT 100 and the length Ll of the first offset region 42 are controlled by the width w7 of the mask portion m7 of the fourth resist layer R4 used in the fourth etching. Thus, the length Ll of the first offset region 42 and the length L2 of the second offset region 62 can be controlled independently of each other, and therefore these lengths Ll, L2 can be set with high degrees of freedom, respectively. Further, even if the third etching and the fourth etching are performed under conditions in which it is difficult to form a tapered shape at the side surface of the gate insulating layer 5A and the gate insulating layer 5B, the length Ll of the first offset region 42 can be made larger than the length L2 of the second offset region 62.

[0360] <Configuration and operation of gate driver circuit>

[0361] The circuit configuration and operation of a gate driver monolithically formed on an active matrix substrate will be described. The gate driver includes a shift register. The shift register includes a plurality of unit shift register circuits connected in multiple stages.

[0362] FIG. 8 is a diagram illustrating a shift register circuit.

[0363] The shift register circuit has a plurality of unit shift register circuits SR1 to SRz (z: an integer of 2 or more) (hereinafter collectively referred to as "unit shift register circuits SR"). Each stage of the unit shift register circuits SR has a set terminal S that receives a set signal, an output terminal Z that outputs an output signal, a reset terminal R that receives a reset signal, and clock input terminals CK1, CK2 that receive clock signals GCK1, GCK2. In the unit shift register circuit SRa (a ≥ 2), the set terminal S is input with the output signal of the unit shift register circuit SR of the previous stage. The set terminal S of the unit shift register circuit SR1 of the first stage is input with a gate start pulse signal GSP. In addition, each stage of the unit shift register circuits SR outputs the output signal to the corresponding gate bus line GL disposed in the display region. The reset terminal R is input with the output signal of the unit shift register circuit of the next stage. The reset terminal R of the unit shift register circuit SRz of the last stage is input with a clear signal.

[0364] Two clock input terminals are provided as the two-phase clock signals GCK1, GCK2. One of the clock input terminals is input with the clock signal GCK1, and the other clock input terminal is input with the clock signal GCK2. The clock signals input to the clock input terminals are configured to be alternately switched between adjacent stages.

[0365] FIG. 9 Fig. 9 is a diagram showing one example of a unit shift register circuit SR. In this example, the unit shift register circuit SR has four TFTs 31 to 34 and a capacitor section Cap.

[0366] The TFT 31 is an input transistor. The gate and drain of the TFT 31 are connected to a set terminal, and the source of the TFT 31 is connected to the gate of the TFT 34. The TFT 34 is an output transistor. The drain of the TFT 34 is connected to a clock input terminal CK1, and the source is connected to an output terminal Z. That is, the TFT 34 functions as a transmission gate to pass or block a clock signal input to the clock input terminal CK1.

[0367] The capacitor section Cap is connected between the gate and source of the TFT 34 which is an output transistor. In this specification, a node connected to the gate of the TFT 34 is referred to as "node netA", and a node connected to the output terminal Z is referred to as "node Z". One electrode of the capacitor section Cap is connected to the gate of the TFT 34 and the node netA, and the other electrode is connected to the source of the TFT 34 and the node Z.

[0368] The TFT 32 is arranged between a Low power input terminal and the node netA. The TFT 32 is a pull-down transistor for lowering the potential of the node netA. The gate of the TFT 32 is connected to a reset terminal, the drain is connected to the node netA, and the source is connected to the Low power input terminal.

[0369] The node Z is connected to the TFT 33. The gate of the TFT 33 is connected to a clock signal input terminal CK2, the drain is connected to the node Z, and the source is connected to the Low power input terminal.

[0370] In this embodiment, the first TFT can be used as the TFTs 31 to 34. Alternatively, the second TFT having a large current driving force (high mobility) can be used at least for the TFT 34 which is an output transistor, and the first TFT can be used for the other TFTs. Thus, two kinds of TFTs having different characteristics can be mixed in the drive circuit according to the use. Further, the TFTs 31 to 34 are preferably enhanced characteristics regardless of the TFT structure.

[0371] Further, the configuration of the drive circuit is not limited to the illustrated configuration. For example, the unit shift register circuit can have five or more TFTs including an output transistor.

[0372] <Configuration and operation of SSD circuit>

[0373] The circuit configuration and operation of the SSD formed monolithically on the active matrix substrate will be described.

[0374] FIG. 10is a view for explaining the configuration and operation of the SSD circuit.

[0375] The SSD circuit 600 is arranged between the source driver SD and the display region DR. The SSD circuit 600 includes a plurality of SSD unit circuits 500(1) to 500(i) (i is an integer of 2 or more) (sometimes collectively referred to as "SSD unit circuits 500") and control signal trunks SW1 to SWn (n is an integer of 2 or more, and here n = 3). The SSD circuit 600 and the source driver SD are controlled by a control circuit provided in the non-display region FR. The control signal trunks SW1 to SWn are connected to the control circuit.

[0376] The output terminals V(1) to V(i) (hereinafter, sometimes collectively referred to as "V terminals") of the source driver SD are each connected to any one of a plurality of video signal lines DO(1) to DO(i) (sometimes collectively referred to as "video signal lines DO"). The n source buses SL after grouping correspond to one video signal line DO. The SSD unit circuits 500 are provided between the video signal lines and the source buses SL after grouping in units of video signal lines. The SSD unit circuits 500 distribute video data from one video signal line DO to n source buses SL.

[0377] In the present embodiment, the Nth video signal line of the plurality of video signal lines DO(1) to DO(i) is set to DO(N) (N is an integer of 1 to i), and the SSD unit circuit 500 and the source buses SL corresponding to the video signal line DO(N) are set to 500(N) and SL(N-1) to SL(N-n), respectively. The source buses SL(N-1) to SL(N-n) may, for example, correspond to R, G, and B pixels (i.e., n = 3).

[0378] Each of the SSD unit circuits 500(N) has at least n (here, 3) thin film transistors (SSD circuit TFTs) 40(1) to 40(n) (sometimes collectively referred to as "SSD circuit TFTs 40").

[0379] The SSD circuit TFT 40 functions as a selection switch. The gate electrode of the SSD circuit TFT 40 is electrically connected to the corresponding one of the n control signal trunks SW1 to SWn. The source electrode of the SSD circuit TFT 40 is electrically connected to the branch line of the video signal line DO(N). The drain electrode of the SSD circuit TFT 40 is connected to the corresponding one of the source buses SL(N-1) to SL(N-3).

[0380] A selection signal (control signal) is supplied to the gate electrode of the TFT 40 for the SSD circuit from one of the control signal trunks SW1 to SW3. The control signal specifies the on period of the selection switch within the same group and is synchronized with the time-series signal output from the source driver SD. The SSD unit circuit 500(N) writes the data potential obtained by time-division driving of the output to the video signal line DO(N) in time series to the plurality of source buses SL(N-1) to SL(N-n) (time-division driving). Thus, the number of V terminals of the source driver SD can be reduced, and thus, the area of the non-display region FR (narrow frame) can be further reduced.

[0381] In this embodiment, as the TFT 40 for the SSD circuit, a TFT having a higher mobility (current driving force) than the other circuit TFTs or the pixel TFTs can be used. For example, a second TFT having a high mobility can be suitably used as the TFT 40 for the SSD circuit. The second TFT can also have a depletion characteristic.

[0382] Note that the configuration of the SSD circuit is not limited to the configuration illustrated in the drawing. The configuration, operation, and the like of the SSD circuit are disclosed in, for example, Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Publication No. 2011 / 118079. In this specification, the entire contents of Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Publication No. 2011 / 118079 are incorporated by reference for reference.

[0383] <oxide semiconductor>

[0384] The oxide semiconductor included in the oxide semiconductor layer of each TFT in this embodiment (also referred to as a metal oxide or an oxide material) can be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. As the crystalline oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a crystalline oxide semiconductor in which a c-axis is aligned substantially perpendicular to a layer surface, or the like can be given.

[0385] The oxide semiconductor layer can have a stacked structure of two or more layers. In the case where the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer can include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures can be included. Further, a plurality of amorphous oxide semiconductor layers can be included. In the case where the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the layer on the side of the gate electrode (the lower layer in the case of a bottom-gate structure, or the upper layer in the case of a top-gate structure) can be smaller than the energy gap of the oxide semiconductor included in the layer on the side opposite to the gate electrode (the upper layer in the case of a bottom-gate structure, or the lower layer in the case of a top-gate structure). However, in the case where the difference between the energy gaps of these layers is small, the energy gap of the oxide semiconductor of the layer on the side of the gate electrode can be larger than the energy gap of the oxide semiconductor of the layer on the side opposite to the gate electrode.

[0386] The material, structure, film formation method, and the like of the amorphous oxide semiconductor and each of the above-described crystalline oxide semiconductors, and the configuration of the oxide semiconductor layer having a stacked structure are described in, for example, Japanese Patent Application Publication No. 2014-007399. For reference, the entire disclosure of Japanese Patent Application Publication No. 2014-007399 is hereby incorporated by reference into the present specification.

[0387] The oxide semiconductor layer can include at least one metal element among In, Ga, and Zn, for example. In this embodiment, the oxide semiconductor layer includes an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide), for example. Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited, and the oxide semiconductor layer includes In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or the like, for example. Such an oxide semiconductor layer can be formed of an oxide semiconductor film including an In-Ga-Zn-O-based semiconductor.

[0388] The In-Ga-Zn-O-based semiconductor can be amorphous or crystalline. As the crystalline In-Ga-Zn-O-based semiconductor, a crystalline In-Ga-Zn-O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer plane is preferable.

[0389] Further, the crystal structure of the crystalline In-Ga-Zn-O-based semiconductor is disclosed in, for example, the above-mentioned Japanese Patent Application Laid-Open No. 2014-007399, Japanese Patent Application Laid-Open No. 2012-134475, Japanese Patent Application Laid-Open No. 2014-209727, and the like. For reference, the entire contents of Japanese Patent Application Laid-Open No. 2012-134475 and Japanese Patent Application Laid-Open No. 2014-209727 are incorporated into the specification of the present application. The TFT having the In-Ga-Zn-O-based semiconductor layer has a high mobility (more than 20 times as high as that of a-Si TFT) and a low off current (less than one hundredth as low as that of a-Si TFT), and thus is suitable for use as a driver TFT (e.g., a TFT included in a driver circuit provided on the same substrate as a display region in the periphery of a display region including a plurality of pixels) and a pixel TFT (a TFT provided in a pixel).

[0390] The oxide semiconductor layer can also include another oxide semiconductor instead of the In-Ga-Zn-O-based semiconductor. For example, an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO) can be included. The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer can include an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), a Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, a Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, an In-W-Zn-O-based semiconductor, or the like.

[0391] Industrial Applicability

[0392] Embodiments of the present application can be suitably used for an active matrix substrate having a peripheral circuit formed monolithically. Such an active matrix substrate is applied to a display device such as a liquid crystal display device, an organic electroluminescence (EL) display device, and an inorganic electroluminescence display device, an imaging device such as an image sensor device, an image input device, a fingerprint reading device, a variety of electronic devices such as a semiconductor memory, and the like.

Claims

1. An active matrix substrate comprising a substrate and a plurality of oxide semiconductor TFTs supported on a main surface of the substrate and including a first TFT and a second TFT, characterized by each oxide semiconductor TFT having: an oxide semiconductor layer; a gate insulating layer disposed on a part of the oxide semiconductor layer; a gate electrode disposed on a part of the gate insulating layer; and a source electrode and a drain electrode, the oxide semiconductor layer of the first TFT being formed of a first oxide semiconductor film, the oxide semiconductor layer of the second TFT being a different layer from the oxide semiconductor layer of the first TFT, and the oxide semiconductor layer of the second TFT being formed of a second oxide semiconductor film having a higher mobility than the first oxide semiconductor film, the oxide semiconductor layers of the first and second TFTs each including a high-resistance region covered with the gate insulating layer and low-resistance regions located on both sides of the high-resistance region and not covered with the gate insulating layer, the low-resistance regions having a smaller specific resistance than the high-resistance region, the high-resistance region including a channel region overlapping the gate electrode when viewed in a normal direction to the main surface of the substrate and an offset region overlapping the gate insulating layer and not overlapping the gate electrode, the offset region including a source-side offset region and a drain-side offset region located on both sides of the channel region, respectively, a length in a channel length direction of the source-side offset region being defined by a length in the channel length direction from a rim of the gate electrode on the source electrode side to a rim of the gate insulating layer on the source electrode side when viewed in the normal direction to the substrate, a length in the channel length direction of the drain-side offset region being defined by a length in the channel length direction from a rim of the gate electrode on the drain electrode side to a rim of the gate insulating layer on the drain electrode side when viewed in the normal direction to the substrate, the low-resistance region including: a source contact region electrically connected to the source electrode; a drain contact region located on an opposite side of the source contact region through the high-resistance region and electrically connected to the drain electrode; and a source-side intervening region and a drain-side intervening region intervening between the source contact region and the high-resistance region and between the drain contact region and the high-resistance region, respectively, the gate insulating layer of the first TFT including a first insulating film and a second insulating film disposed on the first insulating film, the gate insulating layer of the second TFT including the second insulating film and not including the first insulating film, a total length LI in the channel length direction of the offset region of the first TFT being greater than a total length L2 in the channel length direction of the offset region of the second TFT.

2. The active matrix substrate according to claim 1, wherein ​ ​ The active matrix substrate described above further includes a first insulating layer between the oxide semiconductor layer of the second TFT and the substrate, and the first insulating layer includes the first insulating film.

3. The active matrix substrate according to claim 1 or 2, wherein The side surface of the first insulating film and the second insulating film in the gate insulating layer of the first TFT and the side surface of the second insulating film in the gate insulating layer of the second TFT each have a tapered shape.

4. The active matrix substrate according to claim 3, wherein The side surface of the first insulating film and the side surface of the second insulating film in the gate insulating layer of the first TFT are aligned with each other.

5. The active matrix substrate according to claim 1 or 2, wherein In the gate insulating layer of the first TFT, the second insulating film covers only a part of the upper surface of the first insulating film, and the side surface of the second insulating film is located inward of the side surface of the first insulating film when viewed from the normal direction of the substrate.

6. The active matrix substrate according to claim 3, wherein The distance d1 between the edge of the second insulating film and the edge of the gate electrode in the first TFT is equal to the distance d2 between the edge of the second insulating film and the edge of the gate electrode in the second TFT, and the distance d3 between the edge of the first insulating film and the edge of the gate electrode in the first TFT is greater than the distance d1 and the distance d2 when viewed from the normal direction of the substrate.

7. The active matrix substrate according to any one of claims 1, 2, 4, and 6, wherein The first insulating film and the second insulating film include the same insulating material.

8. The active matrix substrate according to any one of claims 1, 2, 4, and 6, wherein The first TFT has a threshold voltage that is shifted in the positive direction from the threshold voltage of the second TFT.

9. The active matrix substrate according to claim 8, wherein The first TFT has an enhancement characteristic, and the second TFT has a depletion characteristic.

10. The active matrix substrate according to any one of claims 1, 2, 4, 6, and 9, wherein The active matrix substrate has a display region including a plurality of pixel regions and a non-display region provided around the display region, The plurality of oxide semiconductor TFTs include a plurality of pixel TFTs each disposed in one of the plurality of pixel regions and a plurality of circuit TFTs that constitute a peripheral circuit disposed in the non-display region, Each pixel TFT is the first TFT, The plurality of circuit TFTs include the second TFT.

11. The active matrix substrate according to any one of claims 1, 2, 4, 6, and 9, wherein The active matrix substrate has a display region including a plurality of pixel regions and a non-display region provided around the display region, The plurality of oxide semiconductor TFTs includes a plurality of pixel TFTs each arranged in one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit arranged in the non-display region, The plurality of circuit TFTs includes the first TFT and the second TFT.

12. The active matrix substrate according to claim 10, wherein The active matrix substrate further includes a plurality of source bus lines and a plurality of gate bus lines, the source electrode of each of the pixel TFTs is electrically connected to one of the plurality of source bus lines, and the gate electrode of each of the pixel TFTs is electrically connected to one of the plurality of gate bus lines. The peripheral circuit includes an SSD circuit that distributes a display signal to n source bus lines among the plurality of source bus lines. The SSD circuit includes a plurality of SSD circuit TFTs, each of which is the second TFT.

13. The active matrix substrate according to any one of claims 1, 2, 4, 6, 9, 12, wherein Each of the first oxide semiconductor film and the second oxide semiconductor film includes In and / or Sn. The total of the atomic ratios of In and Sn with respect to all metal elements in the second oxide semiconductor film is larger than the total of the atomic ratios of In and Sn with respect to all metal elements in the first oxide semiconductor film.

14. The active matrix substrate according to any one of claims 1, 2, 4, 6, 9, 12, wherein The second oxide semiconductor film includes Sn, and the first oxide semiconductor film does not include Sn or includes Sn at a lower concentration than the second oxide semiconductor film.

15. The active matrix substrate according to claim 13, wherein Each of the first oxide semiconductor film and the second oxide semiconductor film is an In-Ga-Zn-O-based semiconductor film, The total of the atomic ratios of In with respect to all metal elements in the second oxide semiconductor film is larger than the total of the atomic ratios of In with respect to all metal elements in the first oxide semiconductor film.

16. The active matrix substrate according to any one of claims 1, 2, 4, 6, 9, 12, 15, wherein At least one of the first oxide semiconductor film and the second oxide semiconductor film is an In-Ga-Zn-O-based semiconductor film including a crystalline portion.

17. A method for manufacturing an active matrix substrate, the method being the method for manufacturing the active matrix substrate according to claim 2, comprising: a step (A) of forming the oxide semiconductor layer of the first TFT on the substrate; a step (B) of forming an insulating film to be the first insulating film so as to cover the oxide semiconductor layer of the first TFT; a step (C) of forming the oxide semiconductor layer of the second TFT on the insulating film; a step (D) of forming another insulating film to be the second insulating film so as to cover the oxide semiconductor layer of the second TFT; (E) forming the gate electrode of the first TFT and the second TFT on the other insulating film; (F) after the step (E), patterning the insulating film and the other insulating film to obtain the first insulating film and the second insulating film from the insulating film and the other insulating film, respectively, thereby forming the gate insulating layer of the first TFT and the gate insulating layer of the second TFT, and forming the first insulating layer on the substrate side of the oxide semiconductor layer of the second TFT; and (G) in the first TFT and the second TFT, respectively, performing a low-resistance treatment of making the resistivity of a portion of the oxide semiconductor layer not covered by the gate insulating layer lower than that of a portion covered by the gate insulating layer, thereby forming the low-resistance region in the portion of the oxide semiconductor layer not covered by the gate insulating layer.

18. The method for manufacturing an active matrix substrate according to claim 17, wherein in the step (F), dry etching of the insulating film and the other insulating film is performed using the same resist layer as a mask, thereby forming the gate insulating layer of the first TFT, the gate insulating layer of the second TFT, and the first insulating layer, the dry etching is performed under a condition that a tapered shape is formed in side surfaces of the first insulating film and the second insulating film in the gate insulating layer of the first TFT and in a side surface of the second insulating film in the gate insulating layer of the second TFT, thereby making the width of the channel length direction of the gate insulating layer of the first TFT larger than the width of the channel length direction of the gate insulating layer of the second TFT.

19. The method for manufacturing an active matrix substrate according to claim 17, wherein the step (F) includes: a first etching step (fl) of performing etching of the other insulating film using a first resist layer as a mask; and a second etching step (f2) of performing etching of the insulating film using a second resist layer different from the first resist layer as a mask after the step (fl).

20. The method for manufacturing an active matrix substrate according to claim 17, wherein the step (F) includes: a third etching step (f3) of performing patterning of the insulating film and the other insulating film using a third resist layer as a mask, thereby forming the gate insulating layer of the second TFT and the first insulating layer in a region where the second TFT is formed; and a fourth etching step (f4) of performing patterning of the insulating film and the other insulating film using a fourth resist layer different from the third resist layer as a mask before or after the step (f3), thereby forming the gate insulating layer of the first TFT in a region where the first TFT is formed.

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