Array substrate and display panel
By changing the connection point between the data line and the active P-Si layer and adopting a dual-gate thin-film transistor design, the display crosstalk and mura problems caused by data voltage jumps in the array substrate were solved, achieving a more stable display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YUNGU GUAN TECH CO LTD
- Filing Date
- 2022-02-17
- Publication Date
- 2026-06-02
AI Technical Summary
In existing array substrates, the parasitic capacitance between the data lines and the driving TFTs is relatively large, which makes it easy for display crosstalk to occur when the data voltage jumps.
The connection point between the data line and the active P-Si layer is changed, moving it from above to below the second scan line Scan2, and a dual-gate thin-film transistor design is adopted, especially the first thin-film transistor T1, which is a dual-gate transistor, combined with an optimized wiring structure.
The parasitic capacitance of the driving transistors in the data lines and pixel circuits was reduced, which decreased the probability of display crosstalk and improved the display mura problem.
Smart Images
Figure CN114678379B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to array substrates and display panels. Background Technology
[0002] Existing display devices generally use thin-film transistor (TFT) array substrates as driving substrates. A TFT array substrate typically includes multiple scan lines, multiple data lines, and multiple pixel circuits. Each pixel circuit includes multiple TFTs, and each pixel circuit is electrically connected to its corresponding scan line and data line. In existing array substrate wiring designs, the parasitic capacitance between the data lines and the driving TFTs is relatively large. When the data voltage changes abruptly, crosstalk can easily occur, causing display defects. Summary of the Invention
[0003] The main technical problem solved by this invention is to provide an array substrate and a display panel that can reduce the probability of display crosstalk caused by data voltage jumps.
[0004] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: providing an array substrate, the array substrate including a substrate, multiple pixel circuits, multiple scan lines, and multiple data lines, each pixel circuit including a thin film transistor; each pixel circuit is electrically connected to at least one corresponding scan line; each pixel circuit is electrically connected to at least one corresponding data line; the scan line includes at least a first scan line and a second scan line electrically connected to a pixel circuit, and the data line includes at least a first data line electrically connected to a pixel circuit, the orthographic projection of the connection point of the first data line and the active layer of the thin film transistor on the substrate is located on the side of the orthographic projection of the second scan line on the substrate away from the orthographic projection of the first scan line on the substrate.
[0005] The array substrate includes a light-emitting enable signal line. Each pixel circuit is electrically connected to at least one corresponding light-emitting enable signal line. The light-emitting enable signal line includes at least a first light-emitting enable signal line electrically connected to a pixel circuit. The orthographic projection of the connection point between the first data line and the active layer of the thin-film transistor on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the first enable signal line on the substrate.
[0006] The pixel circuit includes a power supply unit, a data writing unit, a driving unit, and an initialization unit. The power supply unit is connected to the light-emitting enable signal line to provide a power signal to the pixel circuit. The data writing unit is used to receive the scan signal and includes at least one thin-film transistor for writing the data signal into the driving unit according to the scan signal and saving it. The driving unit is connected to the data writing unit and the power supply unit. The driving unit includes at least one thin-film transistor for receiving the power signal and driving the light-emitting unit to emit light according to the data signal. The initialization unit is used to initialize the gate of the thin-film transistor in the driving unit.
[0007] The data writing unit includes a first thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the first thin-film transistor is connected to the second scan line, the first channel terminal of the first thin-film transistor is connected to the first data line, and the second channel terminal of the first thin-film transistor is connected to the driving unit. The first thin-film transistor is a dual-gate transistor.
[0008] The second scan line includes a first gate portion and a second gate portion. The orthographic projection of the first gate portion onto the substrate is at least partially located in the orthographic projection of the first channel region of the active layer of the first thin-film transistor onto the substrate, so that the first gate portion serves as the first gate of the first thin-film transistor. The orthographic projection of the second gate portion onto the substrate is at least partially located in the orthographic projection of the second channel region of the active layer of the first thin-film transistor onto the substrate, so that the second gate portion serves as the second gate of the first thin-film transistor, forming a dual-gate transistor. The first gate and the second gate of the first thin-film transistor are connected on the same scan line.
[0009] The driving unit includes a second thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the second thin-film transistor is connected to the initialization unit, the first channel terminal of the second thin-film transistor is connected to the second channel terminal of the first thin-film transistor, and the second channel terminal of the second thin-film transistor is connected to the light-emitting unit of the display panel.
[0010] The data writing unit also includes a third thin-film transistor, which includes a control terminal, a first channel terminal and a second channel terminal. The control terminal of the third thin-film transistor is connected to the second scan line, the first channel terminal of the third thin-film transistor is connected to the initialization unit, and the second channel terminal of the third thin-film transistor is connected to the second channel terminal of the second thin-film transistor. The third thin-film transistor is a dual-gate transistor.
[0011] The array substrate includes a first reference voltage line; the initialization unit includes a fourth thin-film transistor, which includes a control terminal, a first channel terminal and a second channel terminal. The control terminal of the fourth thin-film transistor is connected to the first scan line, the first channel terminal of the fourth thin-film transistor is connected to the first reference voltage line, and the second channel terminal of the fourth thin-film transistor is connected to the control terminal of the second thin-film transistor. The fourth thin-film transistor is a dual-gate transistor.
[0012] The array substrate includes a high-potential power supply voltage line; the power supply unit includes a fifth thin-film transistor and a sixth thin-film transistor. The fifth thin-film transistor includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the fifth thin-film transistor is connected to the light-emitting enable signal line, the first path terminal of the fifth thin-film transistor is connected to the high-potential power supply voltage line, and the second path terminal of the fifth thin-film transistor is connected to the first path terminal of the second thin-film transistor. The sixth thin-film transistor includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the sixth thin-film transistor is connected to the light-emitting enable signal line, the first path terminal of the sixth thin-film transistor is connected to the second path terminal of the second thin-film transistor, and the second path terminal of the sixth thin-film transistor is connected to the light-emitting unit of the display panel.
[0013] The scan line includes a third scan line electrically connected to a pixel circuit; the array substrate includes a second reference voltage line; the initialization unit also includes a seventh thin-film transistor, which includes a control terminal, a first path terminal and a second path terminal. The control terminal of the seventh thin-film transistor is connected to the third scan line, the first path terminal of the seventh thin-film transistor is connected to the second reference voltage line, and the second path terminal of the seventh thin-film transistor is connected to the light-emitting unit of the display panel.
[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a display panel, the display panel including a light-emitting unit and an array substrate of any one of the above, the array substrate being used to provide a driving circuit for the light-emitting unit.
[0015] The beneficial effects of the present invention are as follows: Unlike the prior art, the technical solution provided by the present invention changes the position of the connection point between the data line and the active P-Si layer, moving the connection point from above the second scan line Scan2 to below the second scan line Scan2. This can reduce the parasitic capacitance of the driving transistors of the data line and the pixel circuit, thereby reducing the probability of display crosstalk caused by data voltage jumps. Attached Figure Description
[0016] Figure 1 This is a top perspective view of the circuit structure of an array substrate in a conventional embodiment;
[0017] Figure 2This is a top perspective view of the circuit structure of an array substrate in an embodiment of this application;
[0018] Figure 3 This is an equivalent circuit diagram of the driving circuit of an array substrate in an embodiment of this application. Detailed Implementation
[0019] To make the purpose, technical solution and effects of this application clearer and more explicit, the following describes this application in further detail with reference to the accompanying drawings and embodiments.
[0020] Please refer to the following: Figure 2 and Figure 3 , Figure 2 This is a top perspective view of the circuit structure of an array substrate according to an embodiment of this application. Figure 3 This is an equivalent circuit diagram of a driving circuit for an array substrate according to an embodiment of this application. In this embodiment, the array substrate includes a substrate (not shown), multiple pixel circuits (one pixel circuit is shown as an example in the figure), multiple scan lines (Scan), and multiple data lines (Data). Each pixel circuit includes at least one thin-film transistor (TFT), each pixel unit is electrically connected to at least one corresponding scan line (Scan), and each pixel unit is electrically connected to at least one corresponding data line (Data).
[0021] The substrate can be a rigid substrate or a flexible substrate. Rigid substrates can be glass substrates, silicon substrates, etc.; flexible substrates can be polyimide substrates, etc.
[0022] like Figure 2 As shown, the scan line Scan includes at least a first scan line Scan1 and a second scan line Scan2 electrically connected to a pixel circuit, and the data line Data includes at least a first data line Data1 electrically connected to a pixel circuit. The orthographic projection of the connection point N1 between the first data line Data1 and the active layer P-Si layer of the thin-film transistor TFT on the substrate is located on the side of the orthographic projection of the second scan line Scan2 on the substrate that is far from the orthographic projection of the first scan line Scan1 on the substrate. Figure 2 As shown, connection point N1 is located below the second scan line Scan2, that is, connection point N1 is located on the side of the second scan line Scan2 away from the first scan line Scan1.
[0023] Please refer to the following: Figure 1 and Figure 2 , Figure 1This is a top perspective view of the circuit structure of an array substrate in the prior art. Compared with the prior art, this application changes the position of the connection point between the data line Data and the active layer P-Si layer, moving the connection point from above the second scan line Scan2 to below the second scan line Scan2. This reduces the parasitic capacitance between the data line Data and the driving transistor of the pixel circuit, thereby reducing the probability of display crosstalk caused by data voltage jumps.
[0024] In one embodiment, this application adjusts the wiring method of the active P-Si layer by folding the originally upward-extending active P-Si layer downward, thereby changing the position of the connection point between the data line Data and the active P-Si layer. This makes the connection point N1 far away from the active P-Si layer of the driving transistor of the pixel circuit, which can reduce the parasitic capacitance between the data line Data and the driving transistor of the pixel circuit and reduce the probability of display crosstalk caused by data voltage jumps.
[0025] In one embodiment, the array substrate further includes a light-emitting enable signal line EM. Each pixel circuit is electrically connected to at least one corresponding light-emitting enable signal line EM. The light-emitting enable signal line EM includes at least a first light-emitting enable signal line EM1 electrically connected to a pixel circuit. The orthographic projection of the connection point N1 between the first data line Data1 and the active layer P-Si layer of the thin-film transistor on the substrate is located between the orthographic projection of the second scan line Scan2 on the substrate and the orthographic projection of the first enable signal line EM1 on the substrate. Figure 2 As shown, connection point N1 is located between the second scan line Scan2 and the first enable signal line EM1.
[0026] In one embodiment, the pixel circuit includes at least a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst (i.e., the pixel circuit has a 2T1C structure), used to drive the light-emitting unit to emit light. The first thin-film transistor T1 is a switching thin-film transistor used to control the on / off state of the data voltage, providing a path for the energy storage capacitor Cst; the second thin-film transistor T2 is a driving thin-film transistor used to control the current flowing through the light-emitting unit, controlling the light emission. In existing solutions, the first thin-film transistor T1 is generally a single-gate structure. When process fluctuations cause a shift in TFT characteristics, it can easily lead to leakage current in the pixel circuit, resulting in display mura. For example, when there are black blocks in the display image and multi-pulse driving is used, the single-gate structure of the first thin-film transistor T1 has a large leakage current. The leakage current of the first thin-film transistor T1 may cause the data signal Vdata to be written to the gate potential of the second thin-film transistor T2, resulting in display mura defects.
[0027] Therefore, in the solution provided in this application, the first thin-film transistor T1 adopts a dual-gate structure, that is, the first thin-film transistor T1 is a dual-gate transistor. By adopting a dual-gate transistor, the display mura caused by leakage current of the first thin-film transistor T1 can be improved.
[0028] like Figure 3 As shown, the first thin-film transistor T1 includes thin-film transistors T1a and T1b connected in series. The active P-Si layers of thin-film transistors T1a and T1b respectively include a channel region, a source region, and a drain region. The drain region of thin-film transistor T1a is connected to the source region of thin-film transistor T1b, thereby connecting thin-film transistors T1a and T1b together. The drain region of thin-film transistor T1a and the source region of thin-film transistor T1b constitute the dual-gate node of the first thin-film transistor T1.
[0029] The first thin-film transistor T1 is electrically connected to the second scan line Scan2. The corresponding scan line (such as the second scan line Scan2) includes a first gate portion and a second gate portion. The orthographic projection of the first gate portion onto the substrate is at least partially located within the orthographic projection of the first channel region of the thin-film transistor T1a onto the substrate, so that the first gate portion serves as the gate of the thin-film transistor T1a. The orthographic projection of the second gate portion onto the substrate is at least partially located within the orthographic projection of the second channel region of the thin-film transistor T1b onto the substrate, so that the second gate portion serves as the gate of the thin-film transistor T1b. Thus, the gates of the thin-film transistors T1a and T1b are connected to the same scan line Scan2.
[0030] In this embodiment, by setting the first thin-film transistor T1 to a dual-gate structure, the leakage current of the first thin-film transistor T1 can be significantly reduced, improving display mura. Furthermore, by changing the position of the connection point N1 between the data line Data and the active P-Si layer, making the connection point N1 farther away from the active P-Si layer of the driving transistor of the pixel circuit, the parasitic capacitance between the data line Data and the driving transistor of the pixel circuit can be reduced, lowering the probability of display crosstalk caused by data voltage jumps. Furthermore, by changing the wiring structure of the active P-Si layer, sufficient space can be provided to set up the first thin-film transistor T1 with a dual-gate structure while changing the position of the connection point N1, thereby simultaneously solving both the display mura problem and the crosstalk problem.
[0031] Please continue reading. Figure 2 and Figure 3The array substrate provided in this application includes pixel circuits and signal lines. The pixel circuit includes a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, and a storage capacitor Cst, i.e., the pixel circuit has a 7T1C structure. The signal lines include scan lines Scan, data lines Data, reference voltage lines Vref, high-potential power supply voltage lines Elvdd and Elvss, etc.
[0032] Specifically, each pixel circuit includes a power supply unit, a data writing unit, a driving unit, and an initialization unit.
[0033] The power supply unit is connected to the light-emitting enable signal line EM. Through EM, it receives the light-emitting enable signal EM1, which indicates whether the pixel circuit is emitting light. The power supply unit then provides a power signal Vdd to the light-emitting element of the pixel circuit based on EM1. The power supply unit includes a fifth thin-film transistor T5 and a sixth thin-film transistor T6. The fifth thin-film transistor T5 includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the fifth thin-film transistor T5 is connected to the light-emitting enable signal line EM1, the first path terminal of the fifth thin-film transistor T5 is connected to the high-potential power supply voltage line Elvdd, and the second path terminal of the fifth thin-film transistor T5 is connected to the driving unit of the pixel circuit. The sixth thin-film transistor T6 also includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the sixth thin-film transistor T6 is connected to the light-emitting enable signal line EM1, the first path terminal of the sixth thin-film transistor T6 is connected to the driving unit of the pixel circuit, and the second path terminal of the sixth thin-film transistor T6 is connected to the light-emitting unit.
[0034] The data writing unit receives the scan signal Scan2 and, driven by Scan2, writes the data signal Vdata to the driving unit of the pixel circuit and saves it. The data writing unit includes a first thin-film transistor T1 and a third thin-film transistor T3. The first thin-film transistor T1 includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the first thin-film transistor T1 is connected to the second scan line Scan2, the first path terminal of the first thin-film transistor T1 is connected to the first data line Data1, and the second path terminal of the first thin-film transistor T1 is connected to the driving unit of the pixel circuit. The first thin-film transistor T1 is a dual-gate transistor. The third thin-film transistor T3 includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the third thin-film transistor T3 is connected to the second scan line Scan2, the first path terminal of the third thin-film transistor T3 is connected to the initialization unit of the pixel circuit, and the second path terminal of the third thin-film transistor T3 is connected to the driving unit of the pixel circuit. In one embodiment, the third thin-film transistor is a dual-gate transistor.
[0035] The driving unit connects the data writing unit and the power supply unit, and is used to receive the power signal Vdd and adjust the driving current according to the data signal Vdata, thereby driving the light-emitting unit to emit light. The driving unit includes a second thin-film transistor T2, which includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the second thin-film transistor T2 is connected to the initialization unit of the pixel circuit, the first path terminal of the second thin-film transistor T2 is connected to the second path terminal of the first thin-film transistor T1, and the second path terminal of the second thin-film transistor T2 is connected to the light-emitting unit.
[0036] The initialization unit is connected to the reference signal line Vref, and also to the light-emitting unit and the driving unit. It is used to initialize the gate of the second thin-film transistor T2 in the driving unit and the anode of the light-emitting unit.
[0037] The initialization unit includes a fourth thin-film transistor (TFT) T4, which includes a control terminal, a first pass terminal, and a second pass terminal. The control terminal of TFT T4 is connected to the first scan line Scan1, the first pass terminal of TFT T4 is connected to the first reference voltage line Vref1, and the second pass terminal of TFT T4 is connected to the control terminal of the second thin-film transistor T2, for initializing the gate of the second thin-film transistor T2. In one embodiment, the fourth thin-film transistor T4 is a dual-gate transistor.
[0038] The initialization unit also includes a seventh thin-film transistor T7, which includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the seventh thin-film transistor T7 is connected to the third scan line Scan3, the first path terminal of the seventh thin-film transistor T7 is connected to the second reference voltage line Vref2, and the second path terminal of the seventh thin-film transistor T7 is connected to the light-emitting unit for initializing the anode of the light-emitting unit.
[0039] In one embodiment, the array substrate includes a first metal layer M1, a second metal layer M2, and a third metal layer M3 stacked on an active P-Si layer. The first metal layer M1 includes at least gate electrodes of multiple transistors, a first capacitor plate of a storage capacitor, and multiple scan lines Scan extending along a first direction, and a light-emitting enable signal line EM extending along the first direction. The second metal layer M2 includes at least a second capacitor plate of the storage capacitor and a reference voltage line Vref extending along the first direction. The third metal layer M3 includes at least source and drain electrodes of multiple transistors, multiple data lines Data extending along a second direction, and a high-potential power supply voltage line Elvdd extending along the second direction. The extension direction of the scan lines Scan intersects the extension direction of the data lines Data. For example, the extension direction of the scan lines Scan is perpendicular to the extension direction of the data lines Data. The scan lines Scan extend horizontally, and the data lines Data extend vertically. Other signal lines and peripheral circuits for driving are also disposed on the first metal layer M1, the second metal layer M2, and the third metal layer M3, which will not be described in detail here.
[0040] This application also provides a display panel, which includes a light-emitting unit and an array substrate as described in any of the above embodiments. The array substrate is used to provide a driving circuit for the light-emitting unit. The array substrate can be used to drive various display devices to emit light, such as OLED displays, quantum dot displays, Micro-LED displays, etc., but is not limited to these, and can also be other display devices.
[0041] In the above embodiments, by changing the position of the connection point N1 between the data line Data and the active P-Si layer, making the connection point N1 farther away from the active P-Si layer of the driving transistor of the pixel circuit, the parasitic capacitance between the data line Data and the driving transistor of the pixel circuit can be reduced, thus reducing the probability of display crosstalk caused by data voltage jumps. Furthermore, the first thin-film transistor T1 is configured with a dual-gate structure. The dual-gate structure can significantly reduce the leakage current of the first thin-film transistor T1, improving display mura. In other words, by changing the wiring structure of the active P-Si layer, sufficient space can be provided to accommodate the first thin-film transistor T1 with a dual-gate structure while changing the position of the connection point N1, thereby simultaneously solving both the display mura problem and the crosstalk problem.
[0042] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this invention.
Claims
1. An array substrate, characterized in that, include: Substrate; Multiple pixel circuits, each of the pixel circuits including a thin-film transistor; Multiple scan lines, each pixel circuit being electrically connected to at least one corresponding scan line; Multiple data lines, with each pixel circuit electrically connected to at least one corresponding data line; The scan line includes at least a first scan line and a second scan line electrically connected to a pixel circuit, and the data line includes at least a first data line electrically connected to a pixel circuit. The orthographic projection of the connection point of the first data line and the active layer of the thin film transistor on the substrate is located on the side of the orthographic projection of the second scan line on the substrate that is away from the orthographic projection of the first scan line on the substrate. The array substrate further includes: a light-emitting enable signal line, each pixel circuit being electrically connected to at least one corresponding light-emitting enable signal line, the light-emitting enable signal line including at least a first light-emitting enable signal line electrically connected to a pixel circuit, the orthographic projection of the connection point of the first data line and the active layer of the thin film transistor on the substrate being located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the first light-emitting enable signal line on the substrate.
2. The array substrate according to claim 1, characterized in that, The pixel circuit includes a power supply unit, a data writing unit, a driving unit, and an initialization unit. The power supply unit is connected to the light emission enable signal line and provides a power signal to the pixel circuit. The data writing unit is used to receive a scan signal and includes at least one thin-film transistor for writing a data signal into the driving unit according to the scan signal and storing it. The driving unit is connected to the data writing unit and the power supply unit and includes at least one thin-film transistor for receiving the power signal and driving the light emission unit to emit light according to the data signal. The initialization unit is used to initialize at least the gate of the thin-film transistor in the driving unit.
3. The array substrate according to claim 2, characterized in that, The data writing unit includes a first thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the first thin-film transistor is connected to the second scan line, the first channel terminal of the first thin-film transistor is connected to the first data line, and the second channel terminal of the first thin-film transistor is connected to the driving unit. The first thin-film transistor is a dual-gate transistor.
4. The array substrate according to claim 3, characterized in that, The second scan line includes a first gate portion and a second gate portion, wherein the orthographic projection of the first gate portion on the substrate is at least partially located in the orthographic projection of the first channel region of the active layer of the first thin-film transistor on the substrate, so that the first gate portion serves as the first gate of the first thin-film transistor; the orthographic projection of the second gate portion on the substrate is at least partially located in the orthographic projection of the second channel region of the active layer of the first thin-film transistor on the substrate, so that the second gate portion serves as the second gate of the first thin-film transistor, forming a dual-gate transistor, and the first gate and the second gate of the first thin-film transistor are connected on the same scan line.
5. The array substrate according to claim 3, characterized in that, The driving unit includes a second thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the second thin-film transistor is connected to the initialization unit, the first channel terminal of the second thin-film transistor is connected to the second channel terminal of the first thin-film transistor, and the second channel terminal of the second thin-film transistor is connected to the light-emitting unit of the display panel.
6. The array substrate according to claim 5, characterized in that, The data writing unit further includes a third thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the third thin-film transistor is connected to the second scan line, the first channel terminal of the third thin-film transistor is connected to the initialization unit, and the second channel terminal of the third thin-film transistor is connected to the second channel terminal of the second thin-film transistor. The third thin-film transistor is a dual-gate transistor.
7. The array substrate according to claim 5, characterized in that, The initialization unit includes a fourth thin-film transistor, which includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal of the fourth thin-film transistor is connected to the first scan line, the first channel terminal of the fourth thin-film transistor is connected to the first reference voltage line of the array substrate, and the second channel terminal of the fourth thin-film transistor is connected to the control terminal of the second thin-film transistor. The fourth thin-film transistor is a dual-gate transistor.
8. The array substrate according to claim 7, characterized in that, The initialization unit further includes a seventh thin-film transistor, which includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the seventh thin-film transistor is connected to the third scan line of the array substrate, the first path terminal of the seventh thin-film transistor is connected to the second reference voltage line of the array substrate, and the second path terminal of the seventh thin-film transistor is connected to the light-emitting unit of the display panel.
9. The array substrate according to claim 5, characterized in that, The power supply unit includes a fifth thin-film transistor and a sixth thin-film transistor. The fifth thin-film transistor includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the fifth thin-film transistor is connected to the light-emitting enable signal line. The first path terminal of the fifth thin-film transistor is connected to the high-potential power supply voltage line of the array substrate. The second path terminal of the fifth thin-film transistor is connected to the first path terminal of the second thin-film transistor. The sixth thin-film transistor includes a control terminal, a first path terminal, and a second path terminal. The control terminal of the sixth thin-film transistor is connected to the light-emitting enable signal line. The first path terminal of the sixth thin-film transistor is connected to the second path terminal of the second thin-film transistor. The second path terminal of the sixth thin-film transistor is connected to the light-emitting unit of the display panel.
10. A display panel, characterized in that, It includes a light-emitting unit and an array substrate as described in any one of claims 1-9.