Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes providing a substrate, forming a plurality of source-drain structures in the substrate, forming a first dielectric layer on the substrate and on surfaces of the plurality of source-drain structures, forming a first conductive structure on the surfaces of the plurality of source-drain structures in the first dielectric layer, forming a sacrificial layer on a top surface of the first conductive structure using a selective deposition process after forming the first conductive structure, and forming a second dielectric layer on a surface of the first dielectric layer after forming the sacrificial layer, wherein the sacrificial layer is different from a material of the second dielectric layer. The performance and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits is constantly shrinking, which effectively improves the operating speed of the entire integrated circuit. As the size requirements of components become smaller and smaller, the size of the conductive structures formed to connect with semiconductor devices also becomes smaller and smaller.

[0003] However, the performance and reliability of existing semiconductor structures still need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance and reliability of the formed semiconductor structure while realizing a self-aligned etching process.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of source / drain structures located within the substrate; a first dielectric layer located on the substrate and the surfaces of the plurality of source / drain structures; a first conductive structure located within the first dielectric layer and on the surfaces of the source / drain structures, wherein the top surface of the first conductive structure is flush with the surface of the first dielectric layer; a conductive protective structure located on the top surface of the first conductive structure; and a second dielectric layer located on the surface of the first dielectric layer, wherein the second dielectric layer is also located on the sidewall of the conductive protective structure, and the material of the second dielectric layer is different from the material of the conductive protective structure.

[0006] Optionally, the material of the first conductive structure includes cobalt, ruthenium, or tungsten.

[0007] Optionally, the thickness of the conductive protective structure ranges from 50 angstroms to 200 angstroms.

[0008] Optionally, the material of the conductive protective structure includes dielectric materials or metal compounds.

[0009] Optionally, the second dielectric layer and the conductive protection structure further have a first conductive opening, the first conductive opening exposing a portion of the top surface of the first conductive structure; the semiconductor structure further includes a second conductive structure located within the first conductive opening.

[0010] Optionally, it further includes: a plurality of gate structures located on the surface of the substrate, a gate protection structure located on the top surface of the gate structures, and sidewalls located on the sidewalls of the gate structures and the gate protection structure, wherein the first dielectric layer is also located on the sidewalls of the sidewalls, and the conductive protection structure and the gate protection structure are made of the same material.

[0011] Optionally, the thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.

[0012] Optionally, in the direction perpendicular to the extension direction of the gate structure, the second dielectric layer further has a second conductive opening, the second conductive opening exposing a portion of the top surface of the gate structure; and a third conductive structure located within the second conductive opening.

[0013] Optionally, the substrate includes a substrate and a plurality of fin structures located on the substrate, the gate structure spanning the fin structures.

[0014] Optionally, it may also include a third dielectric layer located on the surface of the second dielectric layer and the surface of the conductive protective structure.

[0015] The present invention also provides a semiconductor structure, comprising: a substrate; a plurality of source / drain structures located within the substrate; a first dielectric layer located on the substrate and the surfaces of the plurality of source / drain structures; a first conductive structure located within the first dielectric layer and on the surfaces of the source / drain structures, wherein the top surface of the first conductive structure is flush with the surface of the first dielectric layer; a sacrificial layer located on the top surface of the first conductive structure; and a second dielectric layer located on the surface of the first dielectric layer, wherein the second dielectric layer is also located on the sidewall of the sacrificial layer, and the material of the second dielectric layer is different from the material of the sacrificial layer.

[0016] Optionally, the material of the first conductive structure includes cobalt, ruthenium, or tungsten.

[0017] Optionally, the material of the sacrificial layer includes titanium nitride or a metallic material.

[0018] Optionally, the metallic material includes tungsten, ruthenium, or platinum.

[0019] Optionally, the material of the sacrificial layer may include a dielectric material.

[0020] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of source / drain structures within the substrate; forming a first dielectric layer on the substrate and the surfaces of the plurality of source / drain structures; forming a first conductive structure located on the surface of the source / drain structures within the first dielectric layer; after forming the first conductive structure, forming a sacrificial layer on the top surface of the first conductive structure using a selective film deposition process; and after forming the sacrificial layer, forming a second dielectric layer on the surface of the first dielectric layer, wherein the sacrificial layer and the second dielectric layer are made of different materials.

[0021] Optionally, the material of the first conductive structure includes cobalt, ruthenium, or tungsten.

[0022] Optionally, the material of the second dielectric layer includes a dielectric material or a metal compound.

[0023] Optionally, the material of the sacrificial layer is a dielectric material; the method of forming the semiconductor structure further includes: etching a portion of the sacrificial layer until a first conductive opening is formed in the second dielectric layer, the first conductive opening exposing a portion of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.

[0024] Optionally, the material of the sacrificial layer includes titanium nitride or a metallic material, and the selective film formation process includes a selective metal electroless plating process.

[0025] Optionally, the metallic material includes tungsten, ruthenium, or platinum.

[0026] Optionally, the process parameters of the selective metal electroless plating process include: a pressure range of 20 Pa to 100 Pa; gases used including: SiH4, H2, and WF6, wherein the gas flow rate of WF6 ranges from 2 sccm to 50 sccm; and a temperature range of 100°C to 400°C.

[0027] Optionally, it further includes: after forming the second dielectric layer, etching back and removing the sacrificial layer to form a first opening in the second dielectric layer, the first opening exposing the top surface of the first conductive structure; and forming a conductive protective structure in the first opening, the conductive protective structure being made of a different material than the second dielectric layer.

[0028] Optionally, the process for re-etching the sacrificial layer includes a plasma etching process, wherein the process parameters of the plasma etching process include: a pressure range of 40 mTorr to 300 mTorr; a source power range of 500 W to 1500 W; and the gas used includes one or more of SiH4, HBr, and SF6.

[0029] Optionally, the material of the conductive protective structure includes dielectric materials or metal compounds.

[0030] Optionally, it further includes: forming a conductive opening mask layer on the second dielectric layer and the conductive protective structure, the conductive opening mask layer having a first conductive mask opening, the first conductive mask opening exposing a portion of the surface of the conductive protective structure and a portion of the surface of the second dielectric layer adjacent to the conductive protective structure; using the conductive opening mask layer and the second dielectric layer as masks, etching a portion of the conductive protective structure until a first conductive opening is formed in the second dielectric layer and the conductive protective structure, the first conductive opening exposing a portion of the top surface of the first conductive structure; and forming a second conductive structure within the first conductive opening.

[0031] Optionally, in the etching process of the conductive protective structure, the etching ratio of the conductive protective structure to the second dielectric layer is greater than 5:1.

[0032] Optionally, it may also include forming a third dielectric layer on the surface of the second dielectric layer and the surface of the conductive protective structure before etching the portion of the conductive protective structure.

[0033] Optionally, it further includes: before forming the first conductive structure, forming a plurality of gate structures, a gate protection structure located on the top surface of the gate structures, and sidewalls located on the sidewalls of the gate structures and the gate protection structure, wherein the first dielectric layer is also located on the sidewalls of the sidewalls, and the conductive protection structure and the gate protection structure are made of the same material.

[0034] Optionally, the thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.

[0035] Optionally, the conductive opening mask layer further includes a plurality of second conductive mask openings, the second conductive mask openings exposing a portion of the gate protection structure; the method for forming the semiconductor structure further includes: etching the gate protection structure while etching the conductive protection structure, until a second conductive opening is formed in the second dielectric layer and the gate protection structure, the second conductive opening exposing a portion of the top surface of the gate structure; and forming a third conductive structure in the second conductive opening.

[0036] Optionally, the substrate includes a substrate and a plurality of fin structures located on the substrate, the gate structure spanning the fin structures.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] In the semiconductor structure formation method provided by the technical solution of the present invention, after forming the first conductive structure, a sacrificial layer is formed on the top surface of the first conductive structure using a selective film deposition process. Therefore, the sacrificial layer can be located only on the top surface of the first conductive structure. At the same time, after forming the sacrificial layer, a second dielectric layer of a different material from the sacrificial layer is formed on the surface of the first dielectric layer. Therefore, in the subsequent etching process of the sacrificial layer, the second dielectric layer and the sacrificial layer can be etched at different rates. Thus, on the one hand, when the material of the sacrificial layer is a dielectric material, the sacrificial layer can directly serve as a conductive protective structure. Furthermore, by using the different etching rates, a self-aligned etching process can be achieved when a portion of the sacrificial layer is etched to form a conductive opening that exposes the first conductive structure. On the other hand, when the sacrificial layer is a non-dielectric material, after the sacrificial layer is easily removed by different etching rates, space can be provided for forming a conductive protective structure on the top surface of the first conductive structure, which is made of a different material than the second dielectric layer and is a dielectric material. Therefore, in the subsequent etching process of the conductive protective structure, different etching rates can be applied to the second dielectric layer and the conductive protective structure. Furthermore, when etching a portion of the conductive protective structure to form a conductive opening exposing the first conductive structure, a self-aligned etching process can be achieved. Based on this, since there is no etching process on the material of the first conductive structure during the formation of the sacrificial layer or the conductive protective structure, the etching process has a smaller impact on the first conductive structure after its formation. Consequently, the electrical characteristics of the first conductive structures in different regions of the semiconductor structure are highly consistent, thereby improving the stability of the electrical characteristics of the semiconductor structure and enhancing its performance and reliability. In summary, the semiconductor structure can improve the stability of its electrical characteristics and enhance its performance and reliability while simultaneously achieving a self-aligned etching process to form the conductive opening. Attached Figure Description

[0039] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0040] Figures 4 to 14 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0041] As described in the background section, the performance and reliability of existing semiconductor structures still need to be improved.

[0042] The following detailed explanation, in conjunction with the accompanying drawings, explains why the performance and reliability of semiconductor structures still need improvement.

[0043] Figures 1 to 3This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0044] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a substrate (not shown) and a plurality of fin structures (not shown) disposed on the substrate and disposed therebetween; a first dielectric layer (not shown) is formed on the surface of the substrate 100, the first dielectric layer covering a portion of the sidewalls of the fin structures.

[0045] Please continue to refer to this. Figure 1 A second dielectric layer 110 is formed on the surface of the first dielectric layer. The second dielectric layer 110 has a plurality of gate openings (not shown) that span the fin structure. The gate openings expose the surface and part of the sidewall of the fin structure. A gate structure 120, a gate protection structure 130 located on the top surface of the gate structure 120, and sidewalls 140 located on the sidewalls of the gate structure 120 and the sidewalls of the gate protection structure 130 are formed in the gate openings.

[0046] Please refer to Figure 2 A first conductive opening mask layer (not shown) is formed on the top surface of the gate protection structure 130, the top surface of the sidewall 140, and the surface of the second dielectric layer 110. The first conductive opening mask layer has a plurality of first conductive mask openings (not shown). Using the first conductive opening mask layer as a mask, the second dielectric layer 110 is etched until the surface of the substrate 100 is exposed, forming a first conductive opening (not shown). An initial conductive structure 150 is formed in the first conductive opening.

[0047] The initial conductive structure 150 is made of cobalt, and thus, due to the material properties of cobalt, the parasitic resistance of the subsequently formed conductive structure is relatively small.

[0048] Please refer to Figure 3 The initial conductive structure 150 is etched back to form a first conductive structure 151, and a conductive protective structure opening (not shown) is formed in the second dielectric layer 110 on the first conductive structure 151; a conductive protective structure 160 is formed in the conductive protective structure opening.

[0049] Next, a second conductive opening mask layer (not shown) is formed on the surface of the conductive protection structure 160 and the surface of the second dielectric layer 110. The second conductive opening mask layer has a plurality of second conductive mask openings (not shown). The second conductive mask openings expose a portion of the conductive protection structure 160 and the top surface of the sidewall 140. Using the second conductive opening mask layer as a mask, a portion of the conductive protection structure 160 is etched until the top surface of the first conductive structure 151 is exposed, forming a second conductive opening (not shown) in the conductive protection structure 160 and the second dielectric layer 110. A second conductive structure (not shown) is formed in the second conductive opening, and the second conductive structure is electrically connected to the first conductive structure 151.

[0050] In the above embodiments, by etching back the initial conductive structure 150 to form a conductive protective structure opening, a conductive protective structure 160 with a critical dimension (CD) smaller than the limit of existing photolithography processes can be formed. Furthermore, since the material of the formed conductive protective structure 160 is different from the material of the sidewalls 140, by using different etching rates for the materials of the conductive protective structure 160 and the sidewalls 140, a self-aligned etching process can be achieved during the formation of the second conductive opening.

[0051] Specifically, in the direction perpendicular to the extension direction of the gate structure 120, the width of the second conductive mask opening is greater than the width of the second conductive opening (the second conductive mask opening exposes not only the top surface of the conductive protection structure 160 but also part of the top surface of the sidewall 140), thereby increasing the process window for the etching process forming the second conductive opening and reducing the difficulty of the photolithography process. Simultaneously, through the self-aligned etching process, a second conductive opening with a critical dimension smaller than the width of the second conductive mask opening can be formed.

[0052] However, while achieving the self-aligned etching process, due to the poor chemical stability of cobalt, the chemical reaction during the re-etching of the initial conductive structure 150 is highly reactive. This results in poor uniformity in the thickness and other properties of the etching byproducts formed on the surface of the initial conductive structure 150. Consequently, controlling the re-etching process of the initial conductive structure 150 is difficult, leading to poor consistency between the conductive structures 151 in different regions of the formed semiconductor structure. For example, the surface roughness of the conductive structures 151 in different regions is inconsistent, and the height H of the conductive structures 151 in different regions (e.g., ...) is also inconsistent. Figure 3 Inconsistencies, such as those shown, result in poor electrical characteristic consistency among the conductive structures 151 in different regions of the semiconductor structure, leading to unstable electrical characteristics and consequently poor performance and reliability of the semiconductor structure.

[0053] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. After forming a first conductive structure, a sacrificial layer is formed on the top surface of the first conductive structure using a selective film deposition process. Furthermore, after forming the sacrificial layer, a second dielectric layer is formed on the surface of the first dielectric layer. The sacrificial layer and the second dielectric layer are made of different materials. This method achieves a self-aligned etching process while simultaneously improving the performance and reliability of the formed semiconductor structure.

[0054] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0055] Figures 4 to 14 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0056] Please refer to Figure 4 Provides a base.

[0057] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200.

[0058] The substrate 200 is made of semiconductor materials.

[0059] In this embodiment, the substrate 200 is made of silicon.

[0060] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0061] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0062] Please refer to Figure 5 A plurality of source / drain structures 202 are formed within the substrate.

[0063] In this embodiment, the method for forming a plurality of source / drain structures 202 includes: forming a plurality of mutually discrete pseudo-gate structures 209 on the substrate surface; forming sidewalls 210 on the sidewalls of the pseudo-gate structures 209; forming source / drain openings (not shown) in the fin structures 201 on both sides of the pseudo-gate structures 209; and forming source / drain structures 202 in the source / drain openings using an epitaxial growth process.

[0064] In the process of forming the source-drain structure 202, the sidewall 210 is used to define the formation position of the source-drain structure 202.

[0065] In this embodiment, the material of the pseudo-gate structure 209 includes polycrystalline silicon.

[0066] In this embodiment, the pseudo-gate structure 209 is also used to define the pattern of the gate structure during the subsequent formation of the gate structure.

[0067] In other embodiments, the pseudo-gate structure is directly used as the gate structure.

[0068] In this embodiment, the method for forming the pseudo-gate structure 209 includes: forming a pseudo-gate material film (not shown) covering the surface of the fin structure 201 on the substrate; patterning the pseudo-gate material film until the substrate surface is exposed, so as to form a plurality of mutually discrete pseudo-gate structures 209 on the substrate, the pseudo-gate structures 209 spanning the fin structure 201, and the top surface of the pseudo-gate structure 209 being higher than the top surface of the fin structure 201.

[0069] The formation process of the pseudogate material film includes epitaxial growth or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0070] In this embodiment, the method for forming the sidewall 210 includes: depositing a sidewall material film (not shown) on the substrate surface and the surface of the dummy gate structure 209; using an anisotropic etching process to etch back the sidewall material film until the sidewall material film on the substrate surface and the top surface of the dummy gate structure 209 is removed, thereby forming the sidewall 210 on the sidewall of the dummy gate structure 209.

[0071] The sidewall 210 is made of a low-k dielectric material (k less than 3.9) or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiBCN, etc.

[0072] Please refer to Figure 6 A first dielectric layer 220 is formed on the substrate and the surface of the plurality of source / drain structures 202, and the first dielectric layer 220 is also located on the sidewall surface of the sidewall 210.

[0073] The first dielectric layer 220 provides support for the subsequent formation of the gate structure and the first conductive structure.

[0074] In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0075] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0076] In this embodiment, the method for forming the first dielectric layer 220 includes: forming a first dielectric material layer (not shown) on the surface of the dummy gate structure 209 and the substrate, wherein the surface of the first dielectric material layer is higher than the top surface of the dummy gate structure 209; and planarizing the first dielectric material layer until the top surface of the dummy gate structure 209 is exposed.

[0077] The formation process of the first dielectric material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0078] The process for planarizing the first dielectric material layer includes: etch-back process or chemical mechanical polishing process, etc.

[0079] In this embodiment, before forming the first dielectric material layer, an etching stop layer (not shown) is formed on the substrate surface, the source / drain structure 202 surface, and the sidewall of the sidewall 210.

[0080] The etching stop layer can protect the sidewall 210 and source / drain structure 202 during the subsequent etching process to form the first conductive opening, thereby reducing the damage to the surface of the sidewall 210 and source / drain structure 202 caused by the etching process and improving the performance of the semiconductor structure.

[0081] In this embodiment, the material of the etch stop layer includes silicon nitride.

[0082] In this embodiment, before forming the dummy gate structure 209, a substrate dielectric layer (not shown) is also formed on the surface of the substrate 200. The substrate dielectric layer is also located on a portion of the sidewall of the fin structure 201. The function of the substrate dielectric layer is to provide electrical insulation between adjacent fin structures 201 and between the semiconductor device and the substrate.

[0083] Please continue to refer to this. Figure 6 After forming the first dielectric layer 220, the dummy gate structure 209 is removed, and a plurality of gate openings (not shown) are formed in the first dielectric layer 220. The gate openings are filled with the material of the gate structure to form a plurality of initial gate structures 211 located in the first dielectric layer 220 on the substrate. The initial gate structures 211 span the fin structure 201, the sidewalls 210 are located on the sidewalls of the initial gate structures 211, and the source / drain structures 202 are located in the substrate on both sides of the initial gate structures 211.

[0084] In this embodiment, the method for forming the initial gate structure 211 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric layer 220 and the inner wall surface of the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer fills the gate opening; planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric layer 220 is exposed, thereby forming the initial gate structure 211.

[0085] Please refer to Figure 7 The initial gate structure 211 is etched back to form a gate structure 212. At the same time, a gate protection structure opening (not shown) is formed in the first dielectric layer 220, and the gate protection structure opening exposes the top surface of the gate structure 212. A gate protection structure 213 is formed in the gate protection structure opening, and the gate protection structure 213 is located on the top surface of the gate structure 212.

[0086] In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0087] The gate dielectric layer is made of a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0088] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0089] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0090] Specifically, since the gate structure 212 is formed by etching back the initial gate structure 211, a plurality of the gate structures 212 are located on the substrate, and a plurality of the gate structures 212 are also located within the first dielectric layer 220. Furthermore, the gate structure 212 spans the fin structure 201, the source / drain structure 202 is located within the substrate on both sides of the gate structure 212, and the sidewall 210 is located on the sidewall surface of the gate structure 212.

[0091] In this embodiment, the sidewall 210 is also located on the sidewall of the grid protection structure 213.

[0092] In this embodiment, on one hand, the gate protection structure 213 is used to define the position of the sacrificial layer during the subsequent formation of the sacrificial layer. Specifically, by forming the gate protection structure 213, the first dielectric layer 220, and the sidewall 210, the sacrificial layer can be formed only on the top surface of the first conductive structure in conjunction with the subsequent sacrificial layer formation process, i.e., in conjunction with the selective film deposition process. On the other hand, the gate protection structure 213 can protect the gate structure 212 in subsequent etching and other processes, reducing the damage to the gate structure 212 caused by the etching and other processes, thereby improving the performance of the semiconductor structure.

[0093] Furthermore, by selecting a different material from the sidewall 210 to form the gate protection structure 213, different etching rates can be applied to the sidewall 210 and the gate protection structure 213 during the subsequent etching process to form the second conductive opening. This allows for self-alignment of the conductive opening pattern during the subsequent formation of the second conductive opening.

[0094] In this embodiment, the material of the gate protection structure 213 includes silicon nitride.

[0095] In this embodiment, the process of etching back the initial gate structure 211 includes at least one of dry etching or wet etching.

[0096] In this embodiment, the method for forming the gate protection structure 213 further includes: forming a gate protection structure material layer (not shown) inside the opening of the gate protection structure and on the surface of the first dielectric layer 220; planarizing the gate protection structure material layer until the surface of the first dielectric layer 220 is exposed.

[0097] The process for forming the protective structure material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0098] The process for planarizing the gate protection structure material layer includes chemical mechanical polishing, dry etching, or wet etching.

[0099] In this embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.

[0100] If the gate protection structure 213 is too thin, on the one hand, the process of forming the gate protection structure 213 is more difficult; on the other hand, it is not conducive to the protection of the gate structure 212 in subsequent etching processes, resulting in a deterioration in the performance of the semiconductor structure. If the gate protection structure 213 is too thick, the aspect ratio of the subsequently formed second conductive opening is increased, which not only increases the difficulty of the etching process to form the second conductive opening, resulting in a poor morphology of the formed second conductive opening, but also makes it difficult to fill the material of the third conductive structure within the second conductive opening, increasing the risk of defects such as voids in the formed third conductive structure, which also leads to a deterioration in the performance of the semiconductor structure. Therefore, selecting an appropriate thickness range, i.e., when the thickness of the gate protection structure 213 is between 50 angstroms and 200 angstroms, can reduce the process difficulty of subsequently forming the second conductive opening and the third conductive structure, while also improving the morphology and quality of the third conductive structure and reducing defects within the third conductive structure, thereby improving the performance of the semiconductor structure.

[0101] Please refer to Figure 8 After the gate protection structure 213 is formed, a first conductive structure 230 is formed within the first dielectric layer 220 on the surface of the source / drain structure 202.

[0102] In this embodiment, the material of the first conductive structure 230 includes cobalt. Therefore, due to the low resistivity of cobalt, the parasitic resistance of the formed first conductive structure 230 is relatively low, which is beneficial for improving the performance of the semiconductor structure.

[0103] In other embodiments, the material of the first conductive structure includes ruthenium or tungsten.

[0104] Specifically, the method for forming the first conductive structure 230 includes: etching a first dielectric layer 220 between adjacent gate structures 212 until the surface of the source / drain structure 202 is exposed, forming an opening (not shown) in the first dielectric layer 220; forming a first conductive structure material layer in the opening, on the surface of the first dielectric layer 220, on the top surface of the gate protection structure 213, and on the top surface of the sidewall 210; and planarizing the first conductive structure material layer until the surface of the first dielectric layer 220, the top surface of the gate protection structure 213, and the top surface of the sidewall 210 are exposed, thus forming the first conductive structure 230.

[0105] Please refer to Figure 9 After the first conductive structure 230 is formed, a sacrificial layer 240 is formed on the top surface of the first conductive structure 230 using a selective film deposition process.

[0106] In this embodiment, the sacrificial layer 240 is made of a metallic material, and the selective film formation process includes a selective metal electroless plating process.

[0107] In this embodiment, the sacrificial layer 240 is used to define the shape and location of the subsequently formed conductive protective structure. Specifically, in this embodiment, space can be provided for the formation of the conductive protective structure by subsequently removing the sacrificial layer 240.

[0108] Specifically, in this embodiment, a selective metal electroless plating process is used to form a sacrificial layer 240 on the top surface of the first conductive structure 230.

[0109] In this embodiment, since the sacrificial layer 240 is subsequently removed to provide space for the formation of a conductive protection structure, the requirements for the pattern accuracy and quality of the formed sacrificial layer 240 are relatively low, thus reducing the process difficulty of forming the sacrificial layer 240.

[0110] In this embodiment, the process parameters of the selective metal electroless plating process include: a pressure range of 20 Pa to 100 Pa; gases used include: SiH4, H2, and WF6, wherein the gas flow rate of WF6 ranges from 2 sccm to 50 sccm; and a temperature range of 100°C to 400°C.

[0111] In this embodiment, the sacrificial layer 240 is made of tungsten. Therefore, due to the high material stability of tungsten, the sacrificial layer 240 has high material stability, which helps reduce the difficulty of etching the sacrificial layer 240 and further reduces the impact of the etching process on the first conductive structure 230, thereby improving the performance of the semiconductor structure.

[0112] In other embodiments, the metallic material includes ruthenium or platinum.

[0113] In other embodiments, the material of the sacrificial layer includes titanium nitride.

[0114] The thickness of the sacrificial layer 240 ranges from 50 angstroms to 200 angstroms. Specifically, in this embodiment, the thickness of the sacrificial layer 240 is used to define the thickness of the subsequently formed conductive protective structure.

[0115] In another embodiment, the sacrificial layer is made of a dielectric material. Specifically, in another embodiment, the sacrificial layer directly serves as a conductive protective structure.

[0116] Please refer to Figure 10 After the sacrificial layer 240 is formed, a second dielectric layer 250 is formed on the surface of the first dielectric layer 220, and the sacrificial layer 240 and the second dielectric layer 250 are made of different materials.

[0117] Since a sacrificial layer is formed on the top surface of the first conductive structure 230 after the formation of the first conductive structure 230, the sacrificial layer can be located only on the top surface of the first conductive structure 230. At the same time, since a second dielectric layer 250 of a different material than the sacrificial layer is formed on the surface of the first dielectric layer 220 after the formation of the sacrificial layer, the second dielectric layer 250 and the sacrificial layer can be etched at different rates in the subsequent etching process of the sacrificial layer.

[0118] Specifically, in this embodiment, the sacrificial layer 240 is made of a non-dielectric material. By using different etching rates, the non-dielectric sacrificial layer 240 can be easily removed, providing space on the top surface of the first conductive structure 230 for forming a conductive protective structure made of a dielectric material different from the second dielectric layer 250. Based on this, in the subsequent etching process of the conductive protective structure, different etching rates can be applied to the second dielectric layer 250 and the conductive protective structure. Furthermore, when etching a portion of the conductive protective structure to form a conductive opening exposing the first conductive structure 230, a self-aligned etching process can be achieved.

[0119] In another embodiment, the sacrificial layer is made of a dielectric material and can directly serve as a conductive protective structure. By using the different etching rates, a self-aligned etching process can be achieved when a portion of the sacrificial layer is subsequently etched to form a conductive opening exposing the first conductive structure.

[0120] Based on this, since there is no etching process on the material of the first conductive structure 230 during the formation of the sacrificial layer 240 (in this embodiment) or the conductive protection structure (in another embodiment), the etching process has a smaller impact on the first conductive structure 230 after its formation. Consequently, the electrical characteristics of the first conductive structures 230 in each region of the semiconductor structure are highly consistent, thereby improving the stability of the electrical characteristics of the semiconductor structure and enhancing its performance and reliability. In summary, the semiconductor structure can improve the stability of its electrical characteristics and enhance its performance and reliability while simultaneously implementing a self-aligned etching process to form the conductive opening.

[0121] In this embodiment, the method for forming the second dielectric layer 250 includes: forming a second dielectric material layer on the surface of the first dielectric layer 220, the top surface of the gate protection structure 213, the top surface of the sidewall 210, and the surface of the sacrificial layer 240; planarizing the second dielectric material layer until the top surface of the sacrificial layer 240 is exposed.

[0122] The process for forming the second dielectric material layer includes spin coating or deposition, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0123] The process for planarizing the second dielectric material layer includes dry etching, wet etching, or chemical mechanical polishing.

[0124] In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound includes TiN, AlN, TiO, or AlO.

[0125] Specifically, in this embodiment, the second dielectric layer 250 is SiCO.

[0126] Please refer to Figure 11 After the second dielectric layer 250 is formed, the sacrificial layer 240 is etched back and removed, and a first opening 251 is formed in the second dielectric layer 250, the first opening 251 exposing the top surface of the first conductive structure 230.

[0127] The first opening 251 provides space for forming a conductive protective structure.

[0128] In this embodiment, the process of etching back the sacrificial layer 240 includes a plasma etching process. The process parameters of the plasma etching process include: a pressure range of 40 mTorr to 300 mTorr; a source power range of 500 W to 1500 W; and the gas used includes one or more of SiH4, HBr, and SF6.

[0129] Please refer to Figure 12 A conductive protective structure 260 is formed within the first opening 251, and the conductive protective structure 260 is made of a different material than the second dielectric layer 250.

[0130] Specifically, the conductive protection structure 260 is located on the top surface of the first conductive structure 230.

[0131] Since the conductive protection structure 260 is located on the top surface of the first conductive structure 230, the spacing between the subsequently formed second conductive structure and the top surface of the gate structure 213 is relatively large, reducing the risk of short circuit between the second conductive structure and the gate structure 213. This allows for the formation of a thinner gate protection structure 213. Because the gate protection structure 213 can be thinner, a smaller dummy gate structure 209 and a smaller first conductive structure 230 can be formed. This facilitates material filling during the formation of the dummy gate structure 209 and the first conductive structure 230, thereby increasing the process window for forming the dummy gate structure 209 and the first conductive structure 230 and reducing the process difficulty of forming the semiconductor structure.

[0132] The conductive protective structure 260 is made of a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound includes TiN, AlN, TiO, or AlO.

[0133] In this embodiment, the material of the conductive protection structure 260 is the same as the material of the gate protection structure 213. That is, the material of the conductive protection structure 260 is silicon nitride.

[0134] Since the conductive protection structure 260 is made of the same material as the gate protection structure 213, the conductive protection structure 260 and the gate protection structure 213 can be etched simultaneously to form the first conductive opening and the second conductive opening. This reduces the process steps and time required to form the semiconductor structure and improves the efficiency of forming the semiconductor structure.

[0135] In this embodiment, the method for forming the conductive protection structure 260 includes: forming a conductive protection structure material layer on the surface of the second dielectric layer 250 and within the first opening 251; planarizing the conductive protection structure material layer until the surface of the second dielectric layer 250 is exposed.

[0136] The process of forming a conductive protective structural material layer includes spin coating or deposition, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0137] The process for planarizing the conductive protective structural material layer includes dry etching, wet etching, or chemical mechanical polishing.

[0138] Please refer to Figure 13A conductive opening mask layer 280 is formed on the second dielectric layer 250 and the conductive protection structure 260. The conductive opening mask layer 280 has a first conductive mask opening 281, which exposes a portion of the surface of the conductive protection structure 260 and a portion of the surface of the second dielectric layer 250 adjacent to the conductive protection structure 260. Using the conductive opening mask layer 280 and the second dielectric layer 250 as masks, a portion of the conductive protection structure 260 is etched until a first conductive opening 271 is formed in the second dielectric layer 250 and the conductive protection structure 260. The first conductive opening 271 exposes a portion of the top surface of the first conductive structure 230.

[0139] Since the first conductive mask opening 281 exposes not only part of the surface of the conductive protection structure 260, but also part of the surface of the second dielectric layer 250 adjacent to the conductive protection structure 260, the process window for the photolithography process that forms the first conductive mask opening 281 is increased, thus reducing the process difficulty.

[0140] The first conductive opening 271 provides space for the subsequent formation of the second conductive structure.

[0141] In this embodiment, during the etching process of the conductive protection structure 260, the etching selectivity ratio between the conductive protection structure 260 and the second dielectric layer 250 is greater than 5:1. Therefore, by using this larger etching selectivity ratio, a self-aligned etching process can be achieved when forming the first conductive opening 271.

[0142] In this embodiment, the conductive opening mask layer 280 also has a plurality of second conductive mask openings 282, the second conductive mask openings 282 exposing part of the gate protection structure 213.

[0143] In this embodiment, the method for forming the semiconductor structure further includes: etching the gate protection structure 213 while etching the conductive protection structure 260, until a second conductive opening 272 is formed in the second dielectric layer 250 and the gate protection structure 213, wherein the second conductive opening 272 exposes a portion of the top surface of the gate structure 212.

[0144] The second conductive opening 272 provides space for the subsequent formation of the third conductive structure.

[0145] In other embodiments, portions of the conductive protection structure 260 and portions of the gate protection structure 213 are etched respectively.

[0146] In another embodiment, the sacrificial layer directly serves as a conductive protective structure. The method of forming the semiconductor structure further includes: etching a portion of the sacrificial layer until a first conductive opening is formed within the second dielectric layer, the first conductive opening exposing a portion of the top surface of the first conductive structure.

[0147] In this embodiment, before etching the conductive protection structure 260, a third dielectric layer 270 is formed on the surface of the second dielectric layer 250 and the surface of the conductive protection structure 260.

[0148] In this embodiment, after the first conductive opening 271 is formed, the conductive opening mask layer 280 is removed.

[0149] Please refer to Figure 14 A second conductive structure 291 is formed within the first conductive opening 271.

[0150] In this embodiment, while forming the second conductive structure 291, a third conductive structure 292 is formed within the second conductive opening 272.

[0151] The method of forming the second conductive structure 291 and the third conductive structure 292 includes: forming a conductive material layer (not shown) in the first conductive opening 271, the second conductive opening 272, and on the surface of the third dielectric layer 270; planarizing the conductive material layer until the surface of the third dielectric layer 270 is exposed.

[0152] The process of forming a conductive material layer includes spin coating or deposition, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0153] The process of planarizing conductive material layers includes dry etching, wet etching, or chemical mechanical polishing.

[0154] Accordingly, the present invention also provides a semiconductor structure formed by the above method. Please refer to [link / reference needed]. Figure 10 The system includes: a substrate 200; a plurality of source / drain structures 202 located within the substrate 200; a first dielectric layer 220 located on the surface of the substrate 200 and the plurality of source / drain structures 202; a first conductive structure 230 located within the first dielectric layer 220 and on the surface of the source / drain structures 202, the top surface of the first conductive structure 230 being flush with the surface of the first dielectric layer 220; a sacrificial layer 240 located on the top surface of the first conductive structure 230; and a second dielectric layer 250 located on the surface of the first dielectric layer 220, the second dielectric layer 250 also being located on the sidewall of the sacrificial layer 240, and the material of the second dielectric layer 250 being different from the material of the sacrificial layer 240.

[0155] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200.

[0156] The substrate 200 is made of semiconductor materials.

[0157] In this embodiment, the substrate 200 is made of silicon.

[0158] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0159] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0160] In this embodiment, the material of the first conductive structure 230 includes cobalt.

[0161] In other embodiments, the material of the first conductive structure includes ruthenium or tungsten.

[0162] In this embodiment, the material of the sacrificial layer 240 includes tungsten.

[0163] In other embodiments, the material of the sacrificial layer includes titanium nitride, ruthenium, or platinum.

[0164] In another embodiment, the sacrificial layer is made of a dielectric material. Specifically, in another embodiment, the sacrificial layer directly serves as a conductive protective structure.

[0165] In this embodiment, the thickness of the sacrificial layer 240 ranges from 50 angstroms to 200 angstroms.

[0166] In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0167] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0168] In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound includes TiN, AlN, TiO, or AlO.

[0169] Specifically, in this embodiment, the second dielectric layer 250 is SiCO.

[0170] In this embodiment, the semiconductor structure further includes: a plurality of gate structures 212 located on the surface of the substrate 200, a gate protection structure 213 located on the top surface of the gate structure 212, and sidewalls 210 located on the sidewalls of the gate structure 212 and the gate protection structure 213. The first dielectric layer 220 is also located on the sidewall of the sidewall 210. The gate structure 212 spans the fin structure 202, and the source / drain structure 202 is located in the substrate 200 on both sides of the gate structure 212.

[0171] In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) located on the surface of the substrate 200 and within the first dielectric layer 220, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0172] The gate dielectric layer is made of a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0173] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0174] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0175] In other embodiments, the gate structure 212 is made of polycrystalline silicon.

[0176] In this embodiment, the material of the gate protection structure 213 includes silicon nitride.

[0177] In this embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.

[0178] In this embodiment, the material of the sidewall 210 includes a low-k dielectric material or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiBCN, etc.

[0179] In this embodiment, the semiconductor structure further includes an etch stop layer (not shown) located on the sidewall of the sidewall 210.

[0180] In this embodiment, the material of the etch stop layer includes silicon nitride.

[0181] Accordingly, the present invention also provides a semiconductor structure formed by the above method. Please refer to [link / reference needed]. Figure 14 The system includes: a substrate 200; a plurality of source / drain structures 202 located within the substrate 200; a first dielectric layer 220 located on the substrate 200 and the surfaces of the plurality of source / drain structures 202; a first conductive structure 230 located within the first dielectric layer 220 and on the surfaces of the source / drain structures 202, the top surface of the first conductive structure 230 being flush with the surface of the first dielectric layer 220; a conductive protective structure 260 located on the top surface of the first conductive structure 230; and a second dielectric layer 250 located on the surface of the first dielectric layer 220, the second dielectric layer 250 also being located on the sidewall of the conductive protective structure 260, and the material of the second dielectric layer 250 being different from the material of the conductive protective structure 260.

[0182] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200.

[0183] The substrate 200 is made of semiconductor materials.

[0184] In this embodiment, the substrate 200 is made of silicon.

[0185] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0186] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0187] In this embodiment, the material of the first conductive structure 230 includes cobalt.

[0188] In other embodiments, the material of the first conductive structure includes ruthenium or tungsten.

[0189] In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0190] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0191] In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound includes TiN, AlN, TiO, or AlO.

[0192] Specifically, in this embodiment, the second dielectric layer 250 is SiCO.

[0193] In this embodiment, the second dielectric layer 250 and the conductive protection structure 260 also have a first conductive opening 271 (e.g., Figure 13 As shown), the first conductive opening 271 exposes part of the top surface of the first conductive structure 230.

[0194] In this embodiment, the semiconductor structure further includes a second conductive structure 291 located within the first conductive opening 271.

[0195] In this embodiment, the semiconductor structure further includes: a plurality of gate structures 212 located on the surface of the substrate 200, a gate protection structure 213 located on the top surface of the gate structure 212, and sidewalls 210 located on the sidewalls of the gate structure 212 and the gate protection structure 213. The first dielectric layer 220 is also located on the sidewall of the sidewall 210. The gate structure 212 spans the fin structure 202, and the source / drain structure 202 is located in the substrate 200 on both sides of the gate structure 212.

[0196] In this embodiment, the material of the gate protection structure 213 includes silicon nitride.

[0197] The conductive protective structure 260 is made of a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound includes TiN, AlN, TiO, or AlO.

[0198] In this embodiment, the material of the conductive protection structure 260 is the same as the material of the gate protection structure 213. That is, the material of the conductive protection structure 260 is silicon nitride.

[0199] In this embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.

[0200] In this embodiment, the thickness of the conductive protective structure 260 ranges from 50 angstroms to 200 angstroms.

[0201] In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) located on the surface of the substrate 200 and within the first dielectric layer 220, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0202] The gate dielectric layer is made of a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0203] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0204] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0205] In other embodiments, the gate structure 212 is made of polycrystalline silicon.

[0206] In this embodiment, the material of the sidewall 210 includes a low-k dielectric material or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiBCN, etc.

[0207] In this embodiment, the semiconductor structure further includes an etch stop layer (not shown) located on the sidewall of the sidewall 210.

[0208] In this embodiment, the material of the etch stop layer includes silicon nitride.

[0209] In this embodiment, the semiconductor structure further includes a substrate dielectric layer (not shown) located on the surface of the substrate 200, and the substrate dielectric layer is also located on a portion of the sidewall of the fin structure 201.

[0210] In this embodiment, in the direction perpendicular to the extending direction of the gate structure 212, the second dielectric layer 250 further has a second conductive opening 272 (e.g., ...). Figure 13 As shown in the figure, the second conductive opening 272 exposes a portion of the top surface of the gate structure 212.

[0211] In this embodiment, the semiconductor structure further includes a third conductive structure 292 located within the second conductive opening 272.

[0212] In this embodiment, the semiconductor structure further includes a third dielectric layer 270 located on the surface of the second dielectric layer 250 and the surface of the conductive protective structure 260.

[0213] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Several source / drain structures located within the substrate; A first dielectric layer located on the substrate and the surfaces of the plurality of source / drain structures; Several gate structures located on the surface of the substrate; A gate protection structure located on the top surface of the gate structure, wherein the first dielectric layer is located on the sidewalls of the gate structure and the gate protection structure, and the top surface of the first dielectric layer is flush with the top surface of the gate protection structure; A first conductive structure located within the first dielectric layer and on the surface of the source / drain structure, wherein the top surface of the first conductive structure is flush with the surface of the first dielectric layer; A conductive protective structure located on the top surface of the first conductive structure; A second dielectric layer is located on the surface of the first dielectric layer, and the second dielectric layer is also located on the side wall of the conductive protective structure. Furthermore, the material of the second dielectric layer is different from the material of the conductive protective structure.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the first conductive structure includes cobalt, ruthenium, or tungsten.

3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the conductive protective structure ranges from 50 angstroms to 200 angstroms.

4. The semiconductor structure as described in claim 1, characterized in that, The materials of the conductive protective structure include dielectric materials or metal compounds.

5. The semiconductor structure as described in claim 1, characterized in that, The second dielectric layer and the conductive protective structure also have a first conductive opening, which exposes a portion of the top surface of the first conductive structure. The semiconductor structure further includes a second conductive structure located within the first conductive opening.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: The first dielectric layer is also located on the sidewall of the gate structure and the gate protection structure, and the conductive protection structure and the gate protection structure are made of the same material.

7. The semiconductor structure as described in claim 6, characterized in that, The thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.

8. The semiconductor structure as described in claim 6, characterized in that, In the direction perpendicular to the extension direction of the gate structure, the second dielectric layer also has a second conductive opening, which exposes a portion of the top surface of the gate structure; A third conductive structure located within the second conductive opening.

9. The semiconductor structure as described in claim 6, characterized in that, The substrate includes a substrate and a plurality of fin structures located on the substrate, the gate structure spanning the fin structures.

10. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A third dielectric layer located on the surface of the second dielectric layer and the surface of the conductive protective structure.

11. A semiconductor structure, characterized in that, include: Base; Several source / drain structures located within the substrate; A first dielectric layer located on the substrate and the surfaces of the plurality of source / drain structures; Several gate structures located on the surface of the substrate; A gate protection structure located on the top surface of the gate structure, wherein the first dielectric layer is located on the sidewalls of the gate structure and the gate protection structure, and the top surface of the first dielectric layer is flush with the top surface of the gate protection structure; A first conductive structure located within the first dielectric layer and on the surface of the source / drain structure, wherein the top surface of the first conductive structure is flush with the surface of the first dielectric layer; A sacrificial layer located on the top surface of the first conductive structure; A second dielectric layer is located on the surface of the first dielectric layer, and the second dielectric layer is also located on the sidewall of the sacrificial layer, and the material of the second dielectric layer is different from the material of the sacrificial layer.

12. The semiconductor structure as claimed in claim 11, characterized in that, The material of the first conductive structure includes cobalt, ruthenium, or tungsten.

13. The semiconductor structure as described in claim 11, characterized in that, The material of the sacrificial layer includes titanium nitride or metallic materials.

14. The semiconductor structure as described in claim 13, characterized in that, The metallic material includes tungsten, ruthenium, or platinum.

15. The semiconductor structure as claimed in claim 11, characterized in that, The material of the sacrificial layer includes a dielectric material.

16. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Several source / drain structures are formed within the substrate; A first dielectric layer is formed on the substrate and on the surfaces of the plurality of source and drain structures; A plurality of gate structures and a gate protection structure are formed on the surface of the substrate. The first dielectric layer is located on the sidewalls of the gate structures and the gate protection structure, and the top surface of the first dielectric layer is flush with the top surface of the gate protection structure. After forming a plurality of the gate structures, a first conductive structure is formed within the first dielectric layer on the surface of the source / drain structure, the top surface of the first conductive structure being flush with the surface of the first dielectric layer. After the first conductive structure is formed, a sacrificial layer is formed on the top surface of the first conductive structure; After the sacrificial layer is formed, a second dielectric layer is formed on the surface of the first dielectric layer. The second dielectric layer is also located on the sidewall of the sacrificial layer, and the sacrificial layer is made of a different material than the second dielectric layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the first conductive structure includes cobalt, ruthenium, or tungsten.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the second dielectric layer includes dielectric materials or metal compounds.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the sacrificial layer is a dielectric material; the method of forming the semiconductor structure further includes: etching a portion of the sacrificial layer until a first conductive opening is formed in the second dielectric layer, the first conductive opening exposing a portion of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The sacrificial layer is made of titanium nitride or a metallic material, and the sacrificial layer is formed by a selective film deposition process, which includes a selective metal electroless plating process.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The metallic material includes tungsten, ruthenium, or platinum.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The process parameters of the selective metal electroless plating process include: a pressure range of 20 Pa to 100 Pa; gases used include: SiH4, H2, and WF6, wherein the gas flow rate of WF6 ranges from 2 sccm to 50 sccm; and a temperature range of 100℃ to 400℃.

23. The method for forming a semiconductor structure as described in claim 20, characterized in that, Also includes: After the second dielectric layer is formed, the sacrificial layer is etched back and removed, forming a first opening in the second dielectric layer, the first opening exposing the top surface of the first conductive structure; a conductive protective structure is formed in the first opening, the conductive protective structure being made of a different material than the second dielectric layer.

24. The method for forming a semiconductor structure as described in claim 21, characterized in that, The process of etching back the sacrificial layer includes a plasma etching process, the process parameters of which include: a pressure range of 40 mTorr to 300 mTorr; a source power range of 500 W to 1500 W; and the gas used includes one or more of SiH4, HBr and SF6.

25. The method for forming a semiconductor structure as described in claim 23, characterized in that, The materials of the conductive protective structure include dielectric materials or metal compounds.

26. The method for forming a semiconductor structure as described in claim 21, characterized in that, Also includes: A conductive opening mask layer is formed on the second dielectric layer and the conductive protective structure. The conductive opening mask layer has a first conductive mask opening, which exposes a portion of the surface of the conductive protective structure and a portion of the surface of the second dielectric layer adjacent to the conductive protective structure. Using the conductive opening mask layer and the second dielectric layer as masks, a portion of the conductive protection structure is etched until a first conductive opening is formed within the second dielectric layer and the conductive protection structure, and the first conductive opening exposes a portion of the top surface of the first conductive structure. A second conductive structure is formed within the first conductive opening.

27. The method for forming a semiconductor structure as described in claim 26, characterized in that, In the etching process of the conductive protective structure, the etching ratio of the conductive protective structure to the second dielectric layer is greater than 5:

1.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, Also includes: Before etching the conductive protective structure, a third dielectric layer is formed on the surface of the second dielectric layer and the surface of the conductive protective structure.

29. The method for forming a semiconductor structure as described in claim 26, characterized in that, Also includes: Sidewalls are formed on the sidewalls of the gate structure and the gate protection structure, the first dielectric layer is also located on the sidewalls of the sidewalls, and the conductive protection structure and the gate protection structure are made of the same material.

30. The method for forming a semiconductor structure as described in claim 29, characterized in that, The thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.

31. The method for forming a semiconductor structure as described in claim 29, characterized in that, The conductive opening mask layer also has several second conductive mask openings, which expose part of the gate protection structure. The method for forming the semiconductor structure further includes: etching the gate protection structure while etching the conductive protection structure, until a second conductive opening is formed in the second dielectric layer and the gate protection structure, the second conductive opening exposing a portion of the top surface of the gate structure; A third conductive structure is formed within the second conductive opening.

32. The method for forming a semiconductor structure as described in claim 31, characterized in that, The substrate includes a substrate and a plurality of fin structures located on the substrate, the gate structure spanning the fin structures.

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