Multiplier circuits, chips, electronic devices and computer-readable storage media

Abstract

This disclosure presents a multiplier circuit, a chip, an electronic device, and a computer-readable storage medium. The multiplier circuit includes a calculation circuit, a data reading circuit, a format selection circuit, and a storage circuit. The format selection circuit determines an operation mode based on a format selection signal, wherein the operation mode indicates the format of the input data. The data reading circuit reads input data corresponding to the operation mode from the storage circuit. The calculation circuit performs a multiplication operation based on the operation mode and the input data to obtain a calculation result. By determining the format of the input data through the format selection circuit, the multiplier circuit can perform calculations on input data of multiple formats using a single multiplier circuit, solving the technical problem of wasted chip area in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of multipliers, and more particularly to a multiplier circuit, chip, electronic device, and computer-readable storage medium. Background Technology

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. A key characteristic of the intelligent era is the increasing variety and volume of data people acquire, coupled with ever-growing demands for faster data processing. Chips are the cornerstone of task scheduling, fundamentally determining our data processing capabilities. From an application perspective, chips mainly follow two paths: one is the general-purpose chip path, such as CPUs (Central Processing Units), which offer great flexibility but have relatively low effective computing power when processing algorithms in specific domains; the other is the dedicated chip path, such as TPUs (Tensor Processing Units), which can exert high effective computing power in certain specific domains, but their processing capabilities are relatively poor or even incapable of handling more general and flexible domains. Because the data in the intelligent era is diverse in type and enormous in quantity, chips are required to possess both extremely high flexibility to handle different and rapidly evolving algorithms in various domains, and extremely strong processing capabilities to quickly process massive and rapidly increasing amounts of data.

[0003] In processor design, various floating-point multiplier circuits are often required to meet the requirements of floating-point operations with different precisions and data formats. For example, for scenarios with high precision requirements, a 32-bit floating-point multiplier circuit is needed to meet the precision requirements of 32-bit floating-point calculations; while for scenarios with lower precision requirements, a 16-bit floating-point multiplier circuit is needed to meet the precision requirements of 16-bit floating-point calculations. Therefore, in existing technologies, traditional multipliers cannot implement multiplication of two precisions with a single multiplier, so they are designed separately, resulting in wasted chip area and increased cost. Summary of the Invention

[0004] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] To address the technical problems of inflexible task scheduling and complex control in existing technologies for processing kernels, this disclosure proposes the following technical solution:

[0006] In a first aspect, embodiments of this disclosure provide a multiplier circuit, including:

[0007] The system includes a calculation circuit, a data reading circuit, a format selection circuit, and a storage circuit; wherein the format selection circuit is used to determine an operation mode based on a format selection signal; wherein the operation mode indicates the format of the input data; the data reading circuit is used to read the input data corresponding to the operation mode from the storage circuit according to the operation mode; and the calculation circuit performs a multiplication operation based on the operation mode and the input data to obtain a calculation result.

[0008] Furthermore, the data reading circuit includes:

[0009] The first input data reading circuit is used to read the sign bit, exponent bit and mantissa bit of the first input data from the storage circuit according to the operation mode;

[0010] The second input data reading circuit is used to read the sign bit, exponent bit, and mantissa bit of the second input data from the storage circuit according to the operation mode.

[0011] Furthermore, the data reading circuit includes:

[0012] A switching circuit is used to determine the state of a switch in the switching circuit according to the format of the data indicated by the operation mode, so as to read the corresponding data from the storage circuit by turning on the switch.

[0013] Furthermore, the data reading circuit includes:

[0014] The circuit includes a sign reading circuit, an exponent reading circuit, and a mantissa reading circuit; among them,

[0015] The symbol reading circuit is used to read the symbol bit of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0016] The exponent reading circuit is used to read the exponent bits of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0017] The mantissa reading circuit is used to read the mantissa of the input data corresponding to the operation mode from the storage circuit according to the operation mode.

[0018] Furthermore, the computing circuit includes:

[0019] The circuit includes a sign bit calculation circuit, a multiplication circuit, and an addition circuit; among them,

[0020] The sign bit calculation circuit is used to calculate the sign bit of the output data based on the sign bit of the first input data and the sign bit of the second input data.

[0021] The multiplication circuit is used to calculate the mantissa of the output data according to the operation mode, the mantissa of the first input data and the mantissa of the second input data, and to generate an exponent adjustment signal.

[0022] The addition circuit is used to calculate the exponent of the output data based on the operation mode, the exponent of the first input data, the exponent of the second input data, and the exponent adjustment signal.

[0023] Furthermore, the multiplication circuit includes:

[0024] Basic multiplication calculation circuit and rounding normalization circuit; among which,

[0025] The basic multiplication calculation circuit is used to perform multiplication calculations on the mantissa of the first data and the mantissa of the second data according to the width of the mantissa of the input data corresponding to the operation mode to obtain the initial mantissa of the output data.

[0026] The rounding normalization circuit is used to normalize and round the initial mantissa based on the width of the input data to obtain the mantissa of the output data and the exponent adjustment signal.

[0027] Furthermore, the adder circuit includes:

[0028] Basic addition calculation circuit and exponent adjustment circuit; among which,

[0029] The basic addition calculation circuit is used to perform addition calculation on the exponent bits of the first data and the exponent bits of the second data according to the width of the exponent of the input data corresponding to the operation mode to obtain the initial exponent bits of the output data.

[0030] The exponent adjustment circuit is used to adjust the initial exponent bit according to the exponent adjustment signal to obtain the exponent bit of the output data.

[0031] Furthermore, the sign bit calculation circuit, multiplication circuit, and addition circuit sequentially store the sign bit, exponent bit, and mantissa bit of the output data into the storage circuit to obtain the output data.

[0032] Furthermore, the width of the computing circuit, the width of the data reading circuit, and the width of the storage circuit are the maximum widths in the format of the input data indicated by the operation mode.

[0033] Secondly, embodiments of this disclosure provide a floating-point multiplication calculation method, including:

[0034] Get the operation mode;

[0035] The first input data and the second input data are obtained according to the input data format corresponding to the operation mode;

[0036] The first input data and the second data are multiplied according to the operation mode to obtain the output data.

[0037] Thirdly, embodiments of this disclosure provide a chip including at least one multiplier circuit as described in the first aspect.

[0038] Fourthly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the floating-point multiplication calculation methods described in the second aspect above.

[0039] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the floating-point multiplication calculation methods described in the second aspect above.

[0040] In a sixth aspect, embodiments of this disclosure provide a computer program product, characterized in that: it includes computer instructions, which, when executed by a computing device, enable the computing device to execute any of the floating-point multiplication calculation methods described in the second aspect above.

[0041] In a seventh aspect, embodiments of this disclosure provide a computing device, characterized in that it includes any of the chips described in the third aspect.

[0042] This disclosure presents a multiplier circuit, a chip, an electronic device, and a computer-readable storage medium. The multiplier circuit includes a calculation circuit, a data reading circuit, a format selection circuit, and a storage circuit. The format selection circuit determines an operation mode based on a format selection signal, wherein the operation mode indicates the format of the input data. The data reading circuit reads input data corresponding to the operation mode from the storage circuit. The calculation circuit performs a multiplication operation based on the operation mode and the input data to obtain a calculation result. By determining the format of the input data through the format selection circuit, the multiplier circuit can perform calculations on input data of multiple formats using a single multiplier circuit, solving the technical problem of wasted chip area in the prior art.

[0043] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0044] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0045] Figure 1a This is a schematic diagram of the multiplier circuit provided in an embodiment of the present disclosure;

[0046] Figure 1b This is a structural example of a multiplier circuit provided in an embodiment of the present disclosure;

[0047] Figure 1c A schematic diagram illustrating the storage format of floating-point numbers provided in embodiments of this disclosure;

[0048] Figure 2 This is a schematic diagram of the structure of the multiplication circuit and the addition circuit provided in the embodiments of this disclosure;

[0049] Figure 3 The diagram provided for embodiments of this disclosure shows an adjustable-width addition calculation circuit and a multiplication calculation circuit;

[0050] Figure 4 A flowchart of a floating-point multiplication calculation method is also provided in this embodiment of the disclosure;

[0051] Figure 5a A schematic diagram of a specific example of a multiplier circuit provided in an embodiment of this disclosure;

[0052] Figure 5b A schematic diagram of a multiplier circuit providing an embodiment of this disclosure performing multiplication calculations in fp32 data format;

[0053] Figure 5c This is a schematic diagram of a multiplier circuit provided in an embodiment of the present disclosure performing multiplication calculations in fp16 data format. Detailed Implementation

[0054] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0055] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0056] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0057] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0058] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0059] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0060] Figure 1a This is a schematic diagram of a multiplier circuit provided in an embodiment of the present disclosure. The multiplier circuit 100 includes:

[0061] The circuit comprises a calculation circuit 101, a data reading circuit 102, a format selection circuit 103, and a storage circuit 104; wherein,

[0062] The format selection circuit 103 is used to determine the operation mode according to the format selection signal; wherein, the operation mode indicates the format of the input data;

[0063] The data reading circuit 102 is used to read input data corresponding to the operation mode from the storage circuit 104 according to the operation mode;

[0064] The calculation circuit 101 performs a multiplication operation based on the operation mode and the input data to obtain the calculation result.

[0065] The format selection circuit 103 receives a format selection signal, which is used to indicate the operation mode of the computing circuit. The operation mode refers to the operation of the input data format. In this disclosure, the input data format is the precision of a floating-point number. The precision of the floating-point number can be fp16, fp32, or any other custom precision.

[0066] Optionally, the format selection circuit can be implemented as a register. The size of the register is determined by the number of operation modes supported by the multiplier circuit. For example, if the multiplier circuit supports multiplication of floating-point numbers in two formats, the register needs 1 bit. If the multiplier circuit supports multiplication of floating-point numbers in three formats, the register needs at least 2 bits. In this implementation, the format selection signal is used to set the value of each bit of the register in the format selection circuit. Each different value corresponds to a preset operation mode.

[0067] The storage circuit 104 is used to store the two input data required for the multiplication operation and the calculation result. The data reading circuit determines the format of the data to be read according to the operation mode, and reads the data of the corresponding format from the storage circuit 104 as the input data of the calculation circuit 101. After obtaining the input data, the calculation circuit 101 performs a multiplication operation to obtain the calculation result, and then writes it into the storage circuit 104.

[0068] Thus, due to the presence of the format selection circuit 103, the multiplier circuit 100 can support multiplication operations of input data in multiple formats, which saves chip area compared to the existing technology that requires a separate multiplier circuit for each data format.

[0069] Optionally, the data reading circuit 102 includes a first input data reading circuit and a second input data reading circuit, wherein:

[0070] The first input data reading circuit is used to read the sign bit, exponent bit and mantissa bit of the first input data from the storage circuit according to the operation mode;

[0071] The second input data reading circuit is used to read the sign bit, exponent bit, and mantissa bit of the second input data from the storage circuit according to the operation mode.

[0072] Optionally, the first input data and the second input data are stored in different areas of the storage circuit, or in different storage cells within the storage circuit. For example... Figure 1b The diagram shows a specific example of the multiplier circuit. The storage circuit consists of three different storage units: Reg_a, Reg_b, and Reg_c. Reg_a stores the first input data 'a', Reg_b stores the second input data 'b', and Reg_c stores the output data 'c'. The first input data reading circuit determines the position of the most significant bit of 'a' in Reg_a according to the operation mode and reads the data between the least significant bit and the most significant bit in Reg_a as the first input data 'a'. The second input data reading circuit determines the position of the most significant bit of 'b' in Reg_b according to the operation mode and reads the data between the least significant bit and the most significant bit in Reg_b as the second input data 'b'. Floating-point numbers are generally stored as sign bits, exponent bits, and mantissa bits, such as... Figure 1c The diagram shows the storage format of a floating-point number. S represents the sign bit, E represents the exponent, and M represents the mantissa. A floating-point number can be represented as: X = (-1) s *2 E *M. Thus, the input data can be divided into three parts by the number of bits in the sign bit, exponent bit, and mantissa bit in each predefined format.

[0073] Optional, such as Figure 1b As shown, the data reading circuit 102 includes a symbol reading circuit S. i _adj, Exponent Reading Circuit E i _adj and mantissa reading circuit M i _adj; where,

[0074] The symbol reading circuit S i _adj is used to read the sign bit of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0075] The index reading circuit E i _adj is used to read the exponent of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0076] The mantissa reading circuit M i _adj is used to read the mantissa of the input data corresponding to the operation mode from the storage circuit according to the operation mode.

[0077] Optionally, the symbol reading circuit S i _adj, Exponent Reading Circuit E i _adj and mantissa reading circuit Mi The number of _adj can be 1, that is, a sign reading circuit reads the sign bit of the first input data and the second input data respectively, an exponent reading circuit reads the exponent bit of the first input data and the second input data respectively, and a mantissa reading circuit reads the mantissa bit of the first input data and the second input data respectively.

[0078] Optional, such as Figure 1b As shown, the symbol reading circuit S i _adj, Exponent Reading Circuit E i _adj and mantissa reading circuit M i Since there are two `_adj` values ​​(i = 1 or 2), the first input data is read by `S1_adj`, `E1_adj`, and `M1_adj`, and the second input data is read by `S2_adj`, `E2_adj`, and `M2_adj`. Taking the first input data as an example, during reading, `S1_adj` determines the position of the sign bit in `Reg_a` according to the floating-point precision in the data format indicated by the operation mode, and reads the sign bit of `a` from that position. Similarly, the exponent and mantissa bits of `a` are read through `E1_adj` and `M1_adj` respectively.

[0079] Optionally, the data reading circuit is implemented as a switching circuit. The switching circuit determines the state of the switches in the switching circuit according to the data format indicated by the operation mode, so as to read the corresponding data from the storage circuit by turning on the open switches. For each different data format, different numbers of switches are turned on to achieve reading of different data formats. For example, the data reading circuit is implemented as a 32-bit switching circuit. When reading a floating-point number of fp32, all switches are turned on; when reading a floating-point number of fp16, only the lower 16 bits of the switching circuit are turned on. It is understood that the sub-circuit symbol reading circuit S in the above data reading circuit... i _adj, Exponent Reading Circuit E i _adj and mantissa reading circuit M i _adj can also be implemented as a switching circuit with the corresponding number of bits, which will not be elaborated here.

[0080] Optional, such as Figure 1b As shown, the computing circuit specifically includes:

[0081] The circuit includes a sign bit calculation circuit, a multiplication circuit, and an addition circuit; among them,

[0082] The sign bit calculation circuit is used to calculate the sign bit of the output data based on the sign bit of the first input data and the sign bit of the second input data.

[0083] The multiplication circuit is used to calculate the mantissa of the output data according to the operation mode, the mantissa of the first input data and the mantissa of the second input data, and to generate an exponent adjustment signal.

[0084] The addition circuit is used to calculate the exponent of the output data based on the operation mode, the exponent of the first input data, the exponent of the second input data, and the exponent adjustment signal.

[0085] like Figure 1b As shown, the sign bit calculation circuit is an XOR circuit. Since the sign bit is 1 bit, the sign bit S1 of the first input data obtained by S1_adj is calculated by XOR, and the sign bit S2 of the second input data obtained by S2_adj is calculated by XOR. An XOR operation is then performed on S1 and S2. That is, when S1 and S2 are the same, the sign bit S of the output data is 0; when S1 and S2 are different, the sign bit S of the output data is 1. Here, 0 represents a positive floating-point number, and 1 represents a negative floating-point number.

[0086] The multiplication circuit calculates the product of the mantissa bits of a floating-point number. The multiplication circuit determines the number of mantissa bits involved in the calculation based on the operation mode, then performs the multiplication operation based on the number of bits and generates an exponent adjustment signal. Since the result of the multiplication may involve a carry, an exponent adjustment signal needs to be generated based on the calculation result of the multiplication circuit to adjust the exponent bits obtained in the adder circuit.

[0087] The adder circuit calculates the sum of the exponent bits of the floating-point number. Since carry may be involved, the adder circuit also receives an exponent adjustment signal generated by the multiplication circuit and adjusts the sum according to the exponent adjustment signal. If a carry is needed, the sum is added with the number of carry bits.

[0088] In this disclosure, the widths of the computing circuit, the data reading circuit, and the storage circuit are the maximum widths in the format of the input data indicated by the operation mode. The widths of the computing circuit, the data reading circuit, the format selection circuit, and the storage circuit are all designed to support the maximum precision of floating-point numbers that the multiplier needs to support. For example, if the multiplier circuit supports multiplication of fp32 and fp16 floating-point numbers, then all circuits in the multiplier are designed with widths that can support fp32 floating-point calculations. Similarly, if the storage circuit is designed to be 32 bits wide, the computing circuit is also designed to be able to calculate 32-bit floating-point numbers.

[0089] In this disclosure, both the multiplication circuit and the addition circuit in the computing circuit are circuits with adjustable widths. For example... Figure 2 As shown, the multiplication circuit includes:

[0090] The basic multiplication calculation circuit 201 and the rounding normalization circuit 202; wherein,

[0091] The basic multiplication calculation circuit 201 is used to perform multiplication calculation on the mantissa of the first data and the mantissa of the second data according to the width of the mantissa of the input data corresponding to the operation mode to obtain the initial mantissa of the output data.

[0092] The rounding normalization circuit 202 is used to normalize and round the initial mantissa based on the width of the input data to obtain the mantissa of the output data and the exponent adjustment signal.

[0093] The basic multiplication calculation circuit 201 first determines the mantissa width of the floating-point number in this operation based on the width control signal Adj. Adj is determined by the operation mode and is sent to the multiplication circuit through the format selection circuit or the data reading circuit. The basic multiplication calculation circuit Basic_mul multiplies the two mantissas M1 and M2 to obtain the initial mantissa M_prm. The width of M_prm is twice the width of M1 (which is also M2). M_prm is sent to the rounding and normalization circuit Round&Norm (this circuit supports both normalized and non-normalized numbers). Round&Norm performs rounding and mantissa normalization on M_prm to generate the mantissa M and the exponent adjustment signal E_adj of the output data.

[0094] In machines, to ensure the uniqueness of floating-point representations, floating-point numbers are stored in normalized form. For IEEE 754 standard floating-point numbers, this means the mantissa must be in the form of 1.M. Since the mantissa may be in a denormalized form after adding or subtracting the mantissas of two fixed-point decimals, normalization is necessary. Normalization includes left normalization and right normalization. Left normalization involves shifting the mantissa to the left while decrementing the exponent until the mantissa is in the form of 1.M. For example, the floating-point number 0.0011 * 2... 25 Since it's in a denormalized form, a left normalization operation is needed. This involves shifting the mantissa three bits to the left and decreasing the exponent by three, resulting in 1.1100 * 2. 22 This is the normalized form. Right normalization operation: Shift the mantissa one bit to the right while incrementing the exponent by 1, resulting in the normalized form. Note that right normalization only requires shifting the mantissa one bit to the right. This occurs when a carry-over occurs in the highest bit of the mantissa (the bit before the decimal point), making the mantissa appear as 10.xxxx or 11.xxxx. For example, 10.0011 * 2 25 After right-aligning by one bit, it becomes 1.00011*2 26 It has become a standardized form.

[0095] In floating-point operations, during exponent alignment (aligning the exponents of two floating-point numbers) or right normalization, the mantissa needs to be shifted to the right. The shifted-out bits are discarded, resulting in a loss of precision in the calculation result. To reduce this precision loss, a certain number of shifted-out bits, called guard bits, can be retained and used for rounding after normalization. The IEEE 754 standard lists four optional rounding methods: round to nearest (the default rounding method listed in the standard); round toward +∞; round toward -∞; and round toward 0.

[0096] Custom floating-point numbers are also normalized and rounded according to the rules for normalization and rounding operations described above.

[0097] like Figure 2 As shown, the adder circuit includes:

[0098] The basic addition calculation circuit 203 and the exponent adjustment circuit 204; wherein,

[0099] The basic addition calculation circuit 203 is used to perform addition calculation on the exponent bits of the first data and the exponent bits of the second data according to the width of the exponent of the input data corresponding to the operation mode to obtain the initial exponent bits of the output data.

[0100] The exponent adjustment circuit 204 is used to adjust the initial exponent bit according to the exponent adjustment signal to obtain the exponent bit of the output data.

[0101] The basic addition calculation circuit 203 first determines the floating-point exponent width for this operation based on the width control signal Adj. Adj is determined by the operation mode and is sent to the multiplication circuit through a format selection circuit or a data reading circuit. The basic addition calculation circuit Basic_adder adds the two exponents E1 and E2 to obtain an initial exponent E_prm. The width of E_prm is the width of E1 (which is also E2) plus one bit. Because there may be a carry, E_prm is sent to the exponent adjustment circuit Exp_adj. Exp_adj adjusts the obtained E_prm according to the exponent adjustment signal E_adj generated by the multiplication circuit 201 to obtain the exponent E of the output data.

[0102] Since both addition and multiplication circuits have adjustable widths, the specific operational circuits and registers within them must be designed according to the maximum possible width. For example, in the addition circuit, `Basic_adder` needs to have enough addition units to satisfy the maximum possible width of E (i.e., W_E_max units), and can select all or some units to operate based on the `Adj` control signal. The width of its output result `E_prm` also needs to satisfy the maximum possible width of E plus one bit, and its width is adjustable. Similarly, in the multiplication circuit, `Basic_mul` needs to have enough multiplication units to satisfy the maximum possible width of M (i.e., W_M_max units), and can select all or some units to operate based on the `Adj` control signal. The width of its output result `M_prm` also needs to be twice the maximum possible width of E (W_M_max), and its length is adjustable.

[0103] like Figure 3 The diagram shows a schematic of an adjustable-width addition and multiplication circuit. Depending on the adjustable width range, the values ​​of W_E_max and W_M_max differ, and their sum, plus the 1-bit sign bit, exceeds the maximum supported width of the floating-point number, a difference from other existing solutions. For example, if the multiplier circuit supports three floating-point widths simultaneously: standard fp16 (1 sign bit, 5 exponent bits, and 10 mantissa bits), standard fp32 (1 sign bit, 8 exponent bits, and 23 mantissa bits), and a custom fp32 (1 sign bit, 10 exponent bits, and 21 mantissa bits), then in the design, W_E_max = max(5,8,10) = 10; W_M_max = max(10,23,21) = 23.

[0104] Furthermore, after obtaining the output result, the sign bit calculation circuit, multiplication circuit, and addition circuit sequentially store the sign bit, exponent bit, and mantissa bit of the output data into the storage circuit to obtain the output data. For example... Figure 1b As shown, after the sign bit calculation circuit, multiplication circuit and addition circuit obtain the sign bit, exponent bit and mantissa bit of the output data, the sign bit, exponent bit and mantissa bit are sequentially output to the corresponding positions of Reg_c to obtain the output data.

[0105] The above embodiment discloses a multiplier circuit, which includes a calculation circuit, a data reading circuit, a format selection circuit, and a storage circuit. The format selection circuit determines an operation mode based on a format selection signal, wherein the operation mode indicates the format of the input data. The data reading circuit reads input data corresponding to the operation mode from the storage circuit according to the operation mode. The calculation circuit performs a multiplication operation based on the operation mode and the input data to obtain a calculation result. This multiplier circuit determines the format of the input data through the format selection circuit, enabling the calculation of input data in multiple formats using a single multiplier circuit, thus solving the technical problem of wasted chip area in the prior art.

[0106] Furthermore, such as Figure 4 As shown, this disclosure also provides a floating-point multiplication calculation method for use in the multiplier circuit described in the above embodiments, including:

[0107] Step S401: Obtain the operation mode;

[0108] Step S402: Obtain the first input data and the second input data according to the input data format corresponding to the operation mode;

[0109] Step S403: Perform a multiplication operation on the first input data and the second data according to the operation mode to obtain the output data.

[0110] In step S401, the data format selection circuit of the multiplier circuit acquires the operation mode selection signal;

[0111] In step S402, the data reading circuit of the multiplier circuit determines the format of the input data according to the operation mode indicated by the data format selection circuit, and then obtains the first input data and the second input data according to the format of the input data, wherein the format of the first input data and the second input data is the same as the format of the input data determined by the operation mode.

[0112] In step S403, the calculation circuit of the multiplier circuit determines the calculation accuracy according to the operation mode, and performs multiplication operation on the first input data and the second input data to obtain the output data.

[0113] Furthermore, step S402 includes:

[0114] The first input data reading circuit of the multiplier circuit reads the sign bit, exponent bit, and mantissa bit of the first input data from the storage circuit according to the operation mode;

[0115] The second input data reading circuit of the multiplier circuit reads the sign bit, exponent bit, and mantissa bit of the second input data from the storage circuit according to the operation mode.

[0116] Furthermore, step S402 includes:

[0117] The sign reading circuit of the data reading circuit reads the sign bit of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0118] The exponent reading circuit of the data reading circuit reads the exponent bits of the input data corresponding to the operation mode from the storage circuit according to the operation mode;

[0119] The mantissa reading circuit of the data reading circuit reads the mantissa of the input data corresponding to the operation mode from the storage circuit according to the operation mode.

[0120] Furthermore, step S403 includes:

[0121] The sign bit calculation circuit of the calculation circuit calculates the sign bit of the output data based on the sign bit of the first input data and the sign bit of the second input data;

[0122] The multiplication circuit of the calculation circuit calculates the mantissa of the output data according to the operation mode, the mantissa of the first input data and the mantissa of the second input data, and generates an exponent adjustment signal.

[0123] The addition circuit of the calculation circuit calculates the exponent of the output data according to the operation mode, the exponent of the first input data, the exponent of the second input data, and the exponent adjustment signal.

[0124] Furthermore, step S403 includes:

[0125] The basic multiplication calculation circuit in the multiplication circuit performs multiplication calculations on the mantissa of the first data and the mantissa of the second data according to the width of the mantissa of the input data corresponding to the operation mode to obtain the initial mantissa of the output data.

[0126] The rounding normalization circuit in the multiplication circuit performs normalization and rounding operations on the initial mantissa based on the width of the input data to obtain the mantissa of the output data and the exponent adjustment signal.

[0127] Furthermore, step S403 includes:

[0128] The basic addition calculation circuit in the addition circuit performs addition calculation on the exponent bits of the first data and the exponent bits of the second data according to the width of the exponent of the input data corresponding to the operation mode to obtain the initial exponent bits of the output data;

[0129] The exponent adjustment circuit in the adder circuit adjusts the initial exponent bit according to the exponent adjustment signal to obtain the exponent bit of the output data.

[0130] Furthermore, after step S403, the following steps are also included:

[0131] The sign bit calculation circuit, multiplication circuit, and addition circuit store the sign bit, exponent bit, and mantissa bit of the output data in the storage circuit in sequence to obtain the output data.

[0132] Figure 5a This is an example of a multiplier circuit in an embodiment of this disclosure. For example... Figure 5a As shown, the multiplier circuit 500 supports multiplication operations of both fp16 and fp32.

[0133] The widths of registers Reg_a, Reg_b, and Reg_c are the maximum widths of the two floating-point formats, i.e., 32 bits. The format used for multiplication operations in the multiplier circuit is controlled by the data format selection signal Format.

[0134] When Format = '0', the value of Format is stored in the data format selection circuit, and the current operation is performed in fp32 format. During the operation, both the input and output data are in fp32 format. The adjustable-width multiplication circuit M_adj and the adjustable-width addition circuit A_adj are both set to perform operations corresponding to the mantissa and exponent in fp32, and their circuit diagrams are shown in Figure 5b. At this time, S i_adj will select the highest bit of Reg_a and Reg_b, i.e., b

[31] , as the value of the sign bit of the input data according to the fp32 format floating-point number, and send it to the sign calculation circuit XOR to obtain the value of the sign bit of the output data c; Ex_adj will select the value of b[30:23] of Reg_a and Reg_b as the exponent of the input data and send it to the width adjustable addition calculation circuit configured for 8-bit operation for operation; Mx_adj will select the value of b[22:0] of Reg_a and Reg_b as the mantissa of the input data and send it to the width adjustable multiplication calculation circuit configured for 23-bit operation for operation. The multiplication calculation circuit calculates the value of the mantissa bit of the output data and the exponent adjustment signal. The above addition calculation circuit adjusts the result of the addition calculation according to the exponent adjustment signal to obtain the value of the exponent bit of the output data. Finally, the calculation circuit outputs the values ​​obtained by the sign calculation circuit, the addition calculation circuit and the multiplication calculation circuit to Reg_c in the order of sign bit, exponent bit and mantissa bit to obtain the result of the multiplication operation. This enables floating-point multiplication operations on the fp32.

[0135] When Format = '1', the value of Format is stored in the data format selection circuit, and the current operation is performed in fp16 format. During the operation, both the input and output data are in fp16 format. The adjustable-width multiplication circuit M_adj and the adjustable-width addition circuit A_adj are both set to perform operations corresponding to the mantissa and exponent in fp16. Figure 5c As shown. At this time, S i _adj will select the highest bit of Reg_a and Reg_b, i.e., b

[15] , as the value of the sign bit of the input data according to the fp16 format floating-point number, and send it to the sign calculation circuit XOR to obtain the value of the sign bit of the output data c; Ex_adj will select the values ​​of b[14:10] of Reg_a and Reg_b as the exponent of the input data and send it to the width adjustable addition calculation circuit configured for 5-bit operation for operation; Mx_adj will select the values ​​of b[9:0] of Reg_a and Reg_b as the mantissa of the input data and send it to the width adjustable multiplication calculation circuit configured for 10-bit operation for operation. The multiplication calculation circuit calculates the value of the mantissa bit of the output data and the exponent adjustment signal. The above addition calculation circuit adjusts the result of the addition calculation according to the exponent adjustment signal to obtain the value of the exponent bit of the output data. Finally, the calculation circuit outputs the values ​​obtained by the sign calculation circuit, the addition calculation circuit and the multiplication calculation circuit to Reg_c in the order of sign bit, exponent bit and mantissa bit to obtain the result of the multiplication operation. This enables floating-point multiplication operations for fp16.

[0136] Understandably, the multiplier circuit can also support floating-point calculations with higher precision. In this case, more Format values ​​need to be defined. Each Format corresponds to a data format, and each data format corresponds to a configuration of the data reading circuit and the calculation circuit, so as to support multiplication calculations of floating-point numbers with multiple precisions in a single multiplier circuit.

[0137] This disclosure also provides a chip including at least one multiplier circuit as described in the above embodiments.

[0138] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the floating-point multiplication calculation methods described in the embodiments.

[0139] This disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the floating-point multiplication calculation methods described in the foregoing embodiments.

[0140] This disclosure also provides a computer program product, characterized in that it includes computer instructions, which, when executed by a computing device, can execute any of the floating-point multiplication calculation methods described in the foregoing embodiments.

[0141] This disclosure also provides a computing device, characterized in that it includes any of the chips described in the embodiments.

[0142] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0143] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0144] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0145] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A multiplier circuit, characterized in that, include: Computation circuit, data reading circuit, format selection circuit, and storage circuit; The format selection circuit is used to determine the operation mode based on the format selection signal; wherein the operation mode indicates the format of the input data; The data reading circuit is used to read input data corresponding to the operation mode from the storage circuit according to the operation mode; The computing circuit performs a multiplication operation based on the operation mode and the input data to obtain the calculation result; The data reading circuit includes a switching circuit. The switching circuit is used to determine the state of the switches in the switching circuit according to the data format indicated by the operation mode, so as to read the corresponding data from the storage circuit by turning on the switches. Different numbers of switches are turned on correspond to different data formats.

2. The multiplier circuit as described in claim 1, characterized in that, The data reading circuit includes: The first input data reading circuit is used to read the sign bit, exponent bit and mantissa bit of the first input data from the storage circuit according to the operation mode; The second input data reading circuit is used to read the sign bit, exponent bit, and mantissa bit of the second input data from the storage circuit according to the operation mode.

3. The multiplier circuit as described in claim 1 or 2, characterized in that, The data reading circuit includes: The circuit includes a sign reading circuit, an exponent reading circuit, and a mantissa reading circuit; among them, The symbol reading circuit is used to read the symbol bit of the input data corresponding to the operation mode from the storage circuit according to the operation mode; The exponent reading circuit is used to read the exponent bits of the input data corresponding to the operation mode from the storage circuit according to the operation mode; The mantissa reading circuit is used to read the mantissa of the input data corresponding to the operation mode from the storage circuit according to the operation mode.

4. The multiplier circuit as described in claim 2, characterized in that, The computing circuit includes: The circuit includes a sign bit calculation circuit, a multiplication circuit, and an addition circuit; among them, The sign bit calculation circuit is used to calculate the sign bit of the output data based on the sign bit of the first input data and the sign bit of the second input data. The multiplication circuit is used to calculate the mantissa of the output data according to the operation mode, the mantissa of the first input data and the mantissa of the second input data, and to generate an exponent adjustment signal. The addition circuit is used to calculate the exponent of the output data based on the operation mode, the exponent of the first input data, the exponent of the second input data, and the exponent adjustment signal.

5. The multiplier circuit as described in claim 4, characterized in that, The multiplication circuit includes: Basic multiplication calculation circuit and rounding normalization circuit; among which, The basic multiplication calculation circuit is used to perform multiplication calculations on the mantissa of the first input data and the mantissa of the second input data according to the width of the mantissa of the input data corresponding to the operation mode to obtain the initial mantissa of the output data. The rounding normalization circuit is used to normalize and round the initial mantissa based on the width of the input data to obtain the mantissa of the output data and the exponent adjustment signal.

6. The multiplier circuit as described in claim 4 or 5, characterized in that, The adder circuit includes: Basic addition calculation circuit and exponent adjustment circuit; among which, The basic addition calculation circuit is used to perform addition calculation on the exponent bits of the first input data and the exponent bits of the second input data according to the width of the exponent of the input data corresponding to the operation mode to obtain the initial exponent bits of the output data. The exponent adjustment circuit is used to adjust the initial exponent bit according to the exponent adjustment signal to obtain the exponent bit of the output data.

7. The multiplier circuit as described in claim 4 or 5, characterized in that: The sign bit calculation circuit, multiplication circuit, and addition circuit store the sign bit, exponent bit, and mantissa bit of the output data in the storage circuit in sequence to obtain the output data.

8. The multiplier circuit as described in claim 1, characterized in that, The width of the computing circuit, the width of the data reading circuit, and the width of the storage circuit are the maximum widths in the format of the input data indicated by the operation mode.

9. A floating-point multiplication calculation method, used in the multiplier circuit as described in any one of claims 1-8, characterized in that, include: Get the operation mode; The first input data and the second input data are obtained according to the input data format corresponding to the operation mode; The first input data and the second input data are multiplied according to the operation mode to obtain the output data.

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