Programming method for storage device

Abstract

The present invention discloses a programming method for a storage device, wherein the storage device comprises a plurality of storage cells, a bit line and a plurality of word lines. When the storage device is in a programming operation, the storage cells comprise a selected storage cell and a plurality of unselected storage cells. The programming method comprises performing a plurality of precharging steps, performing a plurality of programming steps, and performing a verification step on the selected storage cell after the precharging step and the programming step. Each precharging step comprises applying a precharging voltage to a bit line for driving an unselected storage cell. Each programming step comprises applying a programming voltage to a word line for driving a selected storage cell.

Description

Technical Field

[0001] The present disclosure belongs to the field of storage technology and relates to a programming method for a storage device, and more particularly to a programming method for a three-dimensional storage device. Background Art

[0002] As the critical dimensions of components in integrated circuits are gradually reduced to the limits of process technology, designers have begun to seek technologies that can achieve greater memory density, thereby achieving lower costs per bit. However, as the technology trend moves towards reducing the size and spacing of memory cells, the problem of program disturbance during the programming operation of memory cells becomes more and more serious.

[0003] Therefore, it is very important to reduce the program disturbance problem when the memory device is programmed. Summary of the invention

[0004] The present disclosure relates to a programming method for a storage device.

[0005] According to one aspect of the present disclosure, a programming method for a storage device is provided. The storage device includes a plurality of storage cells, a bit line, and a plurality of word lines. When the storage device is in a programming operation, the plurality of storage cells include a selected storage cell and a plurality of unselected storage cells. The programming method includes: performing a plurality of precharging steps, performing a plurality of programming steps, and performing a verification step on the selected storage cell after the precharging step and the programming step. Each precharging step includes applying a precharging voltage to a bit line used to drive the unselected storage cell. Each programming step includes applying a programming voltage to a word line used to drive the selected storage cell among the plurality of word lines.

[0006] According to another aspect of the present disclosure, a programming method for a storage device is provided. The storage device includes a plurality of storage cells, a bit line and a plurality of word lines. When the storage device is in a programming operation, the plurality of storage cells include a selected storage cell and a plurality of unselected storage cells. The programming method includes: performing a first precharge step, performing a first programming step, performing a plurality of second precharge steps and performing a plurality of second programming steps. The first precharge step includes applying a precharge voltage to a bit line for driving an unselected storage cell. The first programming step includes applying a first programming voltage to a word line for driving a selected storage cell among a plurality of word lines. Each second precharge step includes applying a precharge voltage to a bit line for driving an unselected storage cell. Each second programming step includes applying a second programming voltage to a word line for driving a selected storage cell among a plurality of word lines. The second programming voltage is different from the first programming voltage.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 depicting a storage device;

[0009] Figure 2A A programming method for a storage device according to an embodiment is illustrated;

[0010] Figure 2B A voltage timing diagram of a programming method for a memory device according to an embodiment is shown;

[0011] Figure 3 A programming method for a storage device according to an embodiment is illustrated;

[0012] Figure 4 The test results of the memory cells programmed by the programming method of an embodiment are shown;

[0013] Figure 5 The test results of the memory cells programmed by the programming method of an embodiment are shown;

[0014] Figure 6 A programming method for a storage device according to an embodiment is illustrated; and

[0015] Figure 7 A programming method for a memory device according to an embodiment is shown.

[0016]

Explanation of symbols

[0017] 101: First memory serial

[0018] 102: Second memory serial

[0019] 201,202,301~303,604,609,613,618,622,626: Pre-charge steps

[0020] 211, 212, 311~313, 601, 606, 611, 615, 620, 624, 628: Programming steps

[0021] 231~234,331~336,602,605,607,610,612,614,616,619,621,623,625,627,629: Processing steps

[0022] 222,322,603,608,617,630: Verification steps

[0023] BL_1, BL_2: bit lines

[0024] CSL: Common Source Line

[0025] DWLB0, DWLB1, DWLT0, DWLT1: dummy word lines

[0026] GSL: Ground Select Line

[0027] MC_01, MC_11, MC_231, MC_241, MC_251, MC_461, MC_471, MC_02, MC_12, MC_232, MC_242, MC_252, MC_462, MC_472: Memory cell

[0028] S1, S1_1, S2, S2_1, S3, S3_1, S4, S4_1: Programming stage

[0029] SSL 1, SSL 2: Serial select lines

[0030] T1~T8: Time point

[0031] V a : Pulse voltage

[0032] V dmy1 , V dmy2 :Virtual voltage

[0033] V pass : Pass voltage

[0034] V pgm , V pgm 1. V pgm 2. V pgm 3. V pgm 4: Programming voltage

[0035] V pgm 1_1, V pgm 2_1, V pgm 3_1, V pgm 4_1: Programming voltage

[0036] V pre : Precharge voltage

[0037] WL0~WL47:Word line DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0039] In an embodiment of the present disclosure, a programming method for a storage device is provided, which can reduce program disturbance of the storage device. The programming method can be used for a three-dimensional storage device, such as a three-dimensional NAND flash memory.

[0040] It should be noted that the present disclosure does not show all possible embodiments, and other embodiments not proposed in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual products. Therefore, the description and illustrations are only used to describe the embodiments, and are not used to limit the scope of protection of the present disclosure. In addition, the descriptions in the embodiments, such as detailed structures, process steps, and material applications, are only for illustrative purposes and are not intended to limit the scope of protection of the present disclosure. The details of the steps and structures of the embodiments may be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following is an explanation of the same / similar elements represented by the same / similar symbols.

[0041] Furthermore, the ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., are intended to modify the elements or steps of the claims. They themselves do not imply or represent any previous ordinal numbers of the claimed elements or steps, nor do they represent the order of one claimed element or step and another claimed element or step, or the order of implementation. The use of these ordinals is only used to clearly distinguish a described element or step with a certain name from another described element or step with the same name.

[0042] A storage device suitable for performing the programming method of the present disclosure may include a plurality of memory strings, a plurality of bit lines, a plurality of string selection lines, a plurality of word lines, a plurality of ground selection lines, and a plurality of common source lines. For ease of description, Figure 1 Only two memory chains are shown by way of example.

[0043] Figure 1 The memory device includes a first memory string 101, a second memory string 102, a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of word lines WL, a ground selection line GSL, and a common source line CSL. The first memory string 101 is different from the second memory string 102, and the first memory string 101 is adjacent to the second memory string 102.

[0044] The first memory string 101 includes a plurality of memory cells MC (MC_01, MC_11 ... MC_231, MC_241, MC_251 ... MC_461, MC_471). The second memory string 102 includes a plurality of memory cells MC (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472). The plurality of word lines WL include a word line WL0 for driving memory cells MC_01 and MC_02, a word line WL47 for driving memory cells MC_471 and MC_472, and a plurality of word lines WL1-WL46 sequentially arranged between the word line WL0 and the word line WL47. The memory cells MC_01 and MC_02 are respectively arranged at the lower ends of the first memory series 101 and the second memory series 102, and the memory cells MC_471 and MC_472 are respectively arranged at the upper ends of the first memory series 101 and the second memory series 102. Each of the word lines WL1-WL46 is respectively used to drive each of the memory cells MC_11 ... MC_231, MC_241, MC_251 ... MC_461 of the first memory series 101. Each of the word lines WL1-WL46 is used to drive each of the memory cells MC_12 ... MC_232, MC_242, MC_252 ... MC_462 of the second memory string 102. The word line used to drive the memory cell mentioned here may mean that when the voltage value applied to any word line WL changes, the electric field value acting on the memory cell MC driven by the word line WL may change accordingly. For example, when the voltage value applied to the word line WL0 changes, the electric field value acting on the memory cell MC_01 and the memory cell MC_02 may change accordingly.

[0045] The first memory string 101 is electrically connected between the bit line BL_1 and the common source line CSL. The second memory string 102 is electrically connected between the bit line BL_2 and the common source line CSL. Specifically, the channel line of the first memory string 101 is electrically connected between the bit line BL_1 and the common source line CSL, and the channel line of the second memory string 102 is electrically connected between the bit line BL_2 and the common source line CSL. The bit line BL_1 can be used to drive a plurality of memory cells MC (MC_01, MC_11 ... MC_231, MC_241, MC_251 ... MC_461, MC_471) in the first memory string 101. The bit line BL_2 can be used to drive a plurality of memory cells MC (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) in the second memory string 102. In one embodiment, the first memory string 101 and the second memory string may be electrically connected to the same bit line. The bit line used to drive the memory cell described herein may represent that when the voltage value applied to any bit line BL changes, the electric field value acting on the memory cell MC driven by the bit line BL may change accordingly. For example, when the voltage value applied to the bit line BL_2 changes, the electric field value acting on the memory cells MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472 of the second memory string 102 may change accordingly.

[0046] The serial selection line SSL_1 and the ground selection line GSL are coupled to opposite ends of the first memory string 101. The serial selection line SSL_2 and the ground selection line GSL are coupled to opposite ends of the second memory string 102. Specifically, the serial selection line SSL_1 is coupled between the bit line BL_1 and the memory cell MC_471 of the first memory string 101; the serial selection line SSL_2 is coupled between the bit line BL_2 and the memory cell MC_472 of the second memory string 102; the ground selection line GSL is coupled between the common source line CSL and the memory cell MC_01 of the first memory string 101 and between the common source line CSL and the memory cell MC_02 of the second memory string 102. In one embodiment, the memory device may include a plurality of serial selection lines SSL coupled between the bit line BL_1 and the memory cell MC_471 and / or between the bit line BL_2 and the memory cell MC_472. The memory device may further include dummy word lines DWLT0 , DWLT1 disposed between the word line WL47 and the bit line BL, and dummy word lines DWLB0 , DWLB1 disposed between the word line WL0 and the common source line CSL.

[0047] when Figure 1When the storage device shown is in a programming operation, one of the plurality of storage cells MC is selected for programming, and the other storage cells MC can be understood as unselected storage cells. For example, storage cell MC_241 is selected and can be understood as a selected storage cell, the other storage cells (i.e., storage cells MC_01, MC_11 ... MC_231, MC_251 ... MC_461, MC_471 and MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) can be understood as unselected storage cells, the first memory series 101 including the selected storage cell (MC_241) can be understood as a selected storage series, and the second memory series 102 including the unselected storage cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) can be understood as an unselected storage series.

[0048] During the programming operation, the programming method of the present disclosure includes performing one or more precharging steps on the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102 to turn off the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102 and inhibiting programming of the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102. During the programming operation, the programming method also includes performing one or more programming steps on the selected memory cells (MC_241) of the first memory string 101 to program the selected memory cells (MC_241). Each precharging step is performed before each programming step. During the programming operation, the programming method further includes performing a verification step on the selected memory cell (MC_241) after the precharging step and the programming step to verify whether the selected memory cell (MC_241) is properly programmed.

[0049] Please also refer to Figure 1 , Figure 2A and Figure 2B picture. Figure 2A A programming method for a memory device according to an embodiment is shown. Figure 2B Figure 1 Figure 2A 2 is a voltage (or bias) timing diagram for a programming method for a memory device. Figure 2BThe vertical axis represents the voltage (or bias) provided to the word line WL24 for driving the selected memory cell (MC_241), the word lines WL0-WL23, WL25-WL47 for driving the unselected memory cells (MC_01, MC_11...MC_231, MC_251...MC_461, MC_471 and MC_02, MC_12...MC_232, MC_252...MC_462, MC_472), the dummy word lines DWLT0, DWLT1, DWLB0, DWLB1, the serial selection line SSL_2 coupled to the unselected memory cells in the second memory serial 102, and the bit line BL_2. Figure 2B The horizontal axis represents time, which may include time point T1, time point T2, ... to time point T8 in sequence.

[0050] The programming method for a memory device includes performing a plurality of precharge steps 201, 202, performing a plurality of programming steps 211, 212, and performing a verification step 222 after the plurality of precharge steps 201, 202 and the plurality of programming steps 211, 212 during a programming operation. The programming method may further include performing a processing step 231 between the precharge step 201 and the programming step 211, performing a processing step 232 between the programming step 211 and the precharge step 202, performing a processing step 233 between the precharge step 202 and the programming step 212, and performing a processing step 234 between the programming step 212 and the verification step 222 during a programming operation. Specifically, the precharge step 201, the processing step 231, the programming step 211, the processing step 232, the precharge step 202, the processing step 233, the programming step 212, the processing step 234, and the verification step 222 may be performed in sequence.

[0051] For example, the precharge step 201 may include applying a precharge voltage V to the bit line BL_2 for driving the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102 during a period from the time point T1 to the time point T2 (a first precharge period). pre , to increase the channel voltage of the second memory string 102, and apply a pulse voltage V to the string selection line SSL_2 during the period from time point T1 to time point T2. a , so that the second memory string 102 is connected to the bit line BL_2. In the precharge step 201, the word lines WL0-WL47 and the dummy word lines DWLT0, DWLT1, DWLB0, DWLB1 may be 0 volts (V). The programming step 211 may include applying a programming voltage V to the word line WL24 used to drive the selected memory cell (MC_241) during a period from time point T3 to time point T4 (a first programming period).pgm , to program the selected memory cell (MC_241), and to apply a pass voltage V to the word lines WL0-WL23, WL25-WL47 during the period from time point T3 to time point T4. pass In one embodiment, the voltage V pass Less than the programming voltage V pgm In the programming step 211, a dummy voltage V is applied to the dummy word lines DWLT0 and DWLB1. dmy1 , and apply a dummy voltage V to the dummy word lines DWLT1 and DWLB0 dmy2 In the programming step 211, the serial selection line SSL_2 and the bit line BL_2 may be at 0 volts.

[0052] The precharge step 202 may include applying a precharge voltage V to the bit line BL_2 for driving the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102 during a period from the time point T5 to the time point T6 (a second precharge period). pre , to increase the channel voltage of the second memory string 102, and apply a pulse voltage V to the string selection line SSL_2 during the period from time point T5 to time point T6. a , so that the second memory string 102 is connected to the bit line BL_2. In the precharge step 202, the word lines WL0-WL47 and the dummy word lines DWLT0, DWLT1, DWLB0, DWLB1 may be 0 volts. The programming step 212 may include applying a programming voltage V to the word line WL24 used to drive the selected memory cell (MC_241) during a period from time point T7 to time point T8 (a second programming period). pgm , to program the selected memory cell (MC_241), and to apply a pass voltage V to the word lines WL0-WL23, WL25-WL47 during the period from time point T7 to time point T8. pass In the programming step 212, a dummy voltage V is applied to the dummy word lines DWLT0 and DWLB1. dmy1 , and apply a dummy voltage V to the dummy word lines DWLT1 and DWLB0 dmy2 In the programming step 212, the serial selection line SSL_2 and the bit line BL_2 may be 0 volts. dmy1 Can be greater than the virtual voltage V dmy2 . Virtual voltage V dmy1 With virtual voltage V dmy2 The value of the pulse voltage V a The value of the voltage V pass between the values ​​of .

[0053] Processing step 231 may be performed during a period from time point T2 to time point T3. Processing step 232 may be performed during a period from time point T4 to time point T5. Processing step 233 may be performed during a period from time point T6 to time point T7. Processing step 234 may be performed after time point T8. Verification step 222 may be performed after time point T8 and after processing step 234.

[0054] In one embodiment, the precharge voltage V pre Can be 4V, pulse voltage V a Can be 3V, programming voltage V pgm Can be 24V, through the voltage V pass Can be 8V, virtual voltage V dmy1 With virtual voltage V dmy2 The first precharge period may be equal to the second precharge period, for example, the first precharge period and the second precharge period may be 6 microseconds (μs). The first precharge period may be different from the second precharge period, for example, the first precharge period may be 7 μs, and the second precharge period may be 5 μs. In one embodiment, the precharge voltage V used for different precharge steps is pre Can be a fixed value.

[0055] Figure 2A and Figure 2B A programming method is shown that includes two precharge steps and two programming steps before a verification step during a programming operation, however, the programming method may include more verification steps and more programming steps. For example, the programming method may include N precharge steps and N programming steps, each of the N precharge steps is performed before each of the N programming steps, and N is greater than 1. In one embodiment, each of the N precharge steps may include applying a precharge voltage V to the bit line BL_2 during a precharge period. pre Each of the N programming steps may include applying a programming voltage V to the word line WL24 used to drive the selected memory cell (MC_241) during a programming period. pgm. The precharge period decreases as the N value increases, and the programming period decreases as the N value increases. In one embodiment, the precharge period is inversely proportional to the N value, and the programming period is inversely proportional to the N value. For example, when the N value is equal to 2, the precharge period may be 6 microseconds, and the programming period may be 6 microseconds; when the N value is equal to 3, the precharge period may be 4 microseconds, and the programming period may be 4 microseconds; when the N value is equal to 6, the precharge period may be 2 microseconds, and the programming period may be 2 microseconds. The present disclosure is not limited to this. In one embodiment, no verification step may be included between the N precharge steps, and / or no verification step may be included between the N programming steps. For example, no verification step is included between the precharge step 201 and the precharge step 202, and / or no verification step is included between the programming step 211 and the programming step 212.

[0056] Figure 3 A programming method for a memory device according to another embodiment is shown. The programming method may include, during a programming operation, performing three precharge steps 301, 302, 303 and three programming steps 311, 312, 313 (N=3) before a verification step 322. Figure 3 In the programming method shown, precharge step 301, process step 331, programming step 311, process step 332, precharge step 302, process step 333, programming step 312, process step 334, precharge step 303, process step 335, programming step 313, process step 336, and verification step 322 may be performed in sequence. Precharge steps 301, 302, 303 may be similar to Figure 2A and Figure 2B The precharge steps 201, 202 are shown, except that the precharge period is different. The programming steps 311, 312, 313 can be similar to Figure 2A and Figure 2B The programming steps 211, 212 are shown to be different except for the programming period. In one embodiment, the precharge steps 301, 302, 303 can be performed during a precharge period of 4 microseconds, and the programming steps 311, 312, 313 can be performed during a programming period of 4 microseconds.

[0057] Figure 4The test results of the memory cells programmed by the programming method of one embodiment are shown. In the comparative example, during the programming operation, the programming method includes only one precharge step (N=1), which is performed before a verification step, and the precharge step is performed with a precharge period of 12 microseconds. In Example 1, during the programming operation, the programming method includes two precharge steps (N=2), which are performed before a verification step, and each precharge step is performed with a precharge period of 6 microseconds. In Example 2, during the programming operation, the programming method includes three precharge steps (N=3), which are performed before a verification step, and each precharge step is performed with a precharge period of 4 microseconds. In Example 3, during the programming operation, the programming method includes six precharge steps (N=6), which are performed before a verification step, and each precharge step is performed with a precharge period of 2 microseconds. As Figure 4 As shown, compared with the comparative example, the program disturbance suppression of embodiments 1 to 3 is better. Specifically, the program disturbance suppression of embodiment 3 is better than that of embodiment 2, and the program disturbance suppression of embodiment 2 is better than that of embodiment 1.

[0058] Figure 5 The test results of the memory cells programmed by the programming methods of the comparative example and embodiments 1 to 3 are shown. Figure 5 As shown, the programming capabilities of the comparative example and embodiments 1 to 3 are similar. That is, the programming method provided by the present disclosure can enhance the suppression effect of program disturbance while still maintaining the programming capability.

[0059] Please also refer to Figure 1 and Figure 6 . Figure 6 A programming method for a storage device according to another embodiment is shown. Figure 1When the storage device shown is in a programming operation, one of the plurality of storage cells MC is selected for programming, and the other storage cells MC can be understood as unselected storage cells. For example, storage cell MC_241 is selected and can be understood as a selected storage cell, the other storage cells (i.e., storage cells MC_01, MC_11 ... MC_231, MC_251 ... MC_461, MC_471 and MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) can be understood as unselected storage cells, the first memory series 101 including the selected storage cell (MC_241) can be understood as a selected storage series, and the second memory series 102 including the unselected storage cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) can be understood as an unselected storage series.

[0060] The programming method may include applying a series of increasing programming voltages during the programming operation to program the selected memory cell (MC_241). In the series of programming voltages, the programming voltage may (but is not limited to) increase stepwise; that is, the programming voltage may increase by a fixed difference. The programming method may include multiple programming stages. Each programming stage corresponds to a programming voltage in the series of programming voltages. Each programming stage includes a verification step for the selected memory cell (MC_241), and at least one programming step earlier than the verification step, the programming step including applying a corresponding programming voltage to the word line WL24 used to drive the selected memory cell (MC_241). For ease of explanation, Figure 6 Only four programming phases are shown by way of example.

[0061] exist Figure 6 In the programming method, the programming method includes sequentially performed programming stages S1, S2, S3, and S4. Each programming stage S1, S2, S3, and S4 corresponds to each programming voltage V pgm 1. V pgm 2. V pgm 3. V pgm 4. In this embodiment, the programming voltage can be increased by a difference of x volts (x is greater than 0). In other words, the programming voltage V pgm 2 can be understood as V pgm 1+x, programming voltage V pgm 3 can be understood as V pgm 1+2x, programming voltage V pgm 4 can be understood as V pgm 1+3x.

[0062] The programming phase S1 includes performing a programming step 601 and performing a verification step 603 after the programming step 601. The programming phase S1 may further include a processing step 602 performed between the programming step 601 and the verification step 603. The programming step 601 may include applying a programming voltage V to the word line WL24 for driving the selected memory cell (MC_241). pgm 1, to program the selected memory cell (MC_241). A verification step 603 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed.

[0063] If the verification step 603 of the programming phase S1 fails (indicating that the selected memory cell has not been successfully programmed), the programming phase S2 will proceed, and the programming phase S2 includes increasing the programming voltage V pgm 2 and a precharge step. The programming phase S2 may include sequentially performing a precharge step 604, a processing step 605, a programming step 606, a processing step 607, and a verification step 608. The precharge step 604 may include applying a precharge voltage V to the bit line BL_2 for driving the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102. pre , to turn off the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102 and inhibit programming of the unselected memory cells (MC_02, MC_12 ... MC_232, MC_242, MC_252 ... MC_462, MC_472) of the second memory string 102. The programming step 606 may include applying a programming voltage V to the word line WL24. pgm 2, to program the selected memory cell (MC_241). A verification step 608 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed.

[0064] If the verification step 608 of the programming phase S2 fails (indicating that the selected memory cell has not been successfully programmed), the programming phase S3 will be performed next, and the programming phase S3 includes an increased programming voltage V compared to the programming phase S2. pgm 3 and more precharge steps. The programming stage S3 may include sequentially performing a precharge step 609, a processing step 610, a programming step 611, a processing step 612, a precharge step 613, a processing step 614, a programming step 615, a processing step 616, and a verification step 617. The precharge step 609 may include applying a precharge voltage V to the bit line BL_2. preThe programming step 611 may include applying a programming voltage V to word line WL24. pgm 3. Precharge step 615 may be similar to precharge step 609. Programming step 615 may be similar to programming step 611. Verification step 617 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed. Programming stage S3 may be similar to Figure 2A and Figure 2B The operation method is shown in the figure.

[0065] If the verification step 617 of the programming phase S3 fails (indicating that the selected memory cell has not been successfully programmed), the programming phase S4 will be performed next, and the programming phase S4 includes an increased programming voltage V compared to the programming phase S3. pgm 4 and more precharge steps. The programming stage S4 may include sequentially performing a precharge step 618, a processing step 619, a programming step 620, a processing step 621, a precharge step 622, a processing step 623, a programming step 624, a processing step 625, a precharge step 626, a processing step 627, a programming step 628, a processing step 629, and a verification step 630. Each precharge step 618, 622, 626 may include applying a precharge voltage V to the bit line BL_2. pre Each programming step 620, 624, 628 may include applying a programming voltage V to word line WL24. pgm 4. A verification step 630 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed. The programming stage S4 may be similar to Figure 3 The operation method shown.

[0066] exist Figure 6 In the embodiment, the programming method includes four programming phases, however, the programming method may include more than four programming phases or less than four programming phases. In one embodiment, the programming method may include performing more programming phases after programming phase S4 and using a more increased programming voltage. The programming voltage V pgm It may be incrementally increased in the above manner until the selected memory cell (MC_241) is properly programmed, or until the selected memory cell (MC_241) reaches a predetermined threshold voltage. In one embodiment, in a programming phase, no verification step may be included between precharge steps, and / or no verification step may be included between programming steps. In another embodiment, a programming phase includes only one verification step, which is performed after all programming steps of the programming phase are completed.

[0067] exist Figure 6In the precharge step 604, the precharge voltage V is applied to the bit line BL_2 during the first precharge period. pre Each precharge step 609, 613 may include applying a precharge voltage V to the bit line BL_2 during the second precharge period. pre Each precharge step 618, 622, 626 may include applying a precharge voltage V to the bit line BL_2 during the third precharge period. pre . The first precharge period may be greater than the second precharge period, and the second precharge period may be greater than the third precharge period. In one embodiment, the first precharge period may be 12 microseconds, the second precharge period may be 6 microseconds, and the third precharge period may be 4 microseconds. In one embodiment, in a programming stage, the precharge period depends on the number of precharge steps. Specifically, the precharge period decreases as the number of precharge steps increases. In one embodiment, the precharge voltage V used for different programming stages is pre Can be a fixed value.

[0068] exist Figure 6 In the first programming period, the programming step 606 may include applying a programming voltage V to the word line WL24. pgm 2, each programming step 611, 615 may include applying a programming voltage V to word line WL24 during the second programming period. pgm 3. Each programming step 620, 624, 628 may include applying a programming voltage V to word line WL24 during the third programming period. pgm 4. The first programming period may be greater than the second programming period, and the second programming period may be greater than the third programming period. In one embodiment, the first programming period may be 12 microseconds, the second programming period may be 6 microseconds, and the third programming period may be 4 microseconds. In one embodiment, in a programming stage, the programming period depends on the number of programming steps. Specifically, the programming period decreases as the number of programming steps increases.

[0069] When the programming voltage is low, the program disturb may be slight. Therefore, when the programming voltage is low, the precharge step may be unnecessary. Figure 6 In the programming phase S1, there is no precharge step, because the programming voltage V pgm 1 is low.

[0070] In one embodiment, the number of programming steps in each programming phase can be adjusted according to the programming voltage V pgm The programming period in each programming stage can be increased with the programming voltage V pgm In one embodiment, the number of precharge steps in each programming phase can be increased with the programming voltage V pgm The precharge period in each programming phase can be increased with the programming voltage V pgmThe number of precharge steps may be equal to the number of programming steps.

[0071] Figure 7 A programming method for a memory device according to an embodiment is shown. Figure 7 The programming method shown and Figure 6 The difference between the programming methods shown is that Figure 7 The programming method shown may include more programming stages between the programming stages S1, S2, S3, S4. For example, Figure 7 The programming method shown may include a programming phase S11 between the programming phase S1 and the programming phase S2. In addition to the programming voltage V pgm 1_1 and the programming voltage V for programming phase S1 pgm 1, programming phase S1_1 is similar to programming phase S1. Programming voltage V pgm 1_1 is greater than the programming voltage V used in programming phase S1 pgm 1, and is less than the programming voltage V used in programming stage S2 pgm 2. The programming method may include a programming phase S2_1 between the programming phase S2 and the programming phase S3. In addition to the programming voltage V used in the programming phase S2_1 pgm 2_1 and the programming voltage V for programming stage S2 pgm 2, programming phase S2_1 is similar to programming phase S2. pgm 2_1 is greater than the programming voltage V used in programming stage S2 pgm 2, and is less than the programming voltage V used in programming stage S3 pgm 3. The programming method may include a programming phase S3_1 between the programming phase S3 and the programming phase S4. In addition to the programming voltage V pgm 3_1 and the programming voltage V for programming stage S3 pgm 3, programming stage S3_1 is similar to programming stage S3. pgm 3_1 is greater than the programming voltage V used in programming stage S3 pgm 3, and is less than the programming voltage V used in programming stage S4 pgm 4. The programming method may include a programming phase S4_1 after the programming phase S4. In addition to the programming voltage V used in the programming phase S4_1, pgm 4_1 and the programming voltage V used in the programming phase S4 pgm 4, programming stage S4_1 is similar to programming stage S4. pgm 4_1 is greater than the programming voltage V used in the programming stage S4 pgm 4.

[0072] In one embodiment, the programming method may include more than one programming phase between programming phase S1 and programming phase S2, and / or between programming phase S2 and programming phase S3, and / or between programming phase S3 and programming phase S4, and / or after programming phase S4. The programming voltage V for multiple programming phases pgm Increases with each programming stage.

[0073] In one embodiment, the number of precharge steps in each programming phase may correspond to the programming voltage range, that is, when the programming voltage V used in a programming phase is pgm When the programming voltage V is within the programming voltage range, the number of precharge steps in the programming phase can be constant. pgm When the voltage is increased to a certain value, the number of precharge steps in the programming phase will increase. Figure 7 As shown, when the programming voltage V pgm 2, the number of precharge steps in each of the programming stages S1, S1_1, ... is maintained at 0; when the programming voltage V pgm 2, the number of precharge steps in programming phase S2 is increased to 1. For example, Figure 7 As shown, when the programming voltage V pgm 3, the number of precharge steps in each of the programming stages S2, S2_1, ... is maintained at 1; when the programming voltage V pgm 3. The number of precharge steps in programming phase S3 is increased to 2.

[0074] In this embodiment, the number of programming steps in each programming phase may correspond to the programming voltage range, that is, when the programming voltage V used in a programming phase is pgm When the programming voltage V is within the programming voltage range, the number of programming steps in the programming phase can be constant. pgm When the voltage is increased to a certain value, the number of programming steps in the programming phase will increase. Figure 7 As shown, when the programming voltage V pgm 3, the number of programming steps in each of the programming stages S2, S21, ... is maintained at 1; when the programming voltage V pgm 3, the number of programming steps in the programming stage S3 is increased to 2. The number of precharge steps may be equal to the number of programming steps.

[0075] In a comparative example, the programming method includes only one precharge step and only one programming step. Since the potential difference between the unselected memory cells may induce band to band leakage, the local self-boosting phenomenon (local self-boosting) occurring in the channel of the unselected memory cell in the unselected memory string may collapse in the programming step. In addition, as the programming period of the programming step increases, the collapse of the local self-boosting phenomenon will become more serious. The collapse of the local self-boosting phenomenon may reduce the potential difference (control gate-to-channel potential differences) between the control gate and the channel of the unselected memory cell, thereby causing serious programming interference. In contrast, the programming method provided by the present disclosure includes more than one precharge step. Performing more than one precharge step in a programming operation is beneficial to establishing a stable local self-boosting phenomenon, and can reduce or avoid the collapse of the local self-boosting phenomenon, thereby reducing or suppressing programming interference. Moreover, compared to a programming method comparison example including only one precharge step and only one programming step, the precharge step of the programming method disclosed herein is performed with a short precharge period, and the programming step of the programming method disclosed herein is performed with a short programming period. In a programming operation, a large number of precharge steps and a short precharge period for each precharge step are beneficial to efficiently establish a local self-boosting phenomenon and put unselected memory cells in a strong off state. A short programming period is also beneficial to establish a local self-boosting phenomenon and can reduce or suppress programming interference. Therefore, through the programming method disclosed herein, the program interference suppression effect of the storage device can be improved, and the programming window can be increased while maintaining the programming capability of the storage device.

[0076] The concepts of the present disclosure may also be extended and applied to other variations.

[0077] The memory string may be a vertical channel structure, or may use a single gate vertical channel structure, or a vertical gate structure, etc. The memory cell may be a floating gate memory cell or a nitride trapping memory cell, etc. The memory cell may be a single-level memory cell, a multi-level memory cell, or a triple-level memory cell, etc.

[0078] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art with common knowledge in the technical field to which the present invention belongs may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined by the claims.

[0079] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for programming a storage device, characterized in that: The storage device includes a plurality of storage cells, a bit line and a plurality of word lines. When the storage device is in a programming operation, the plurality of storage cells include a selected storage cell and a plurality of unselected storage cells. The programming method includes: Performing a plurality of precharge steps, each of the precharge steps comprising applying a precharge voltage to the bit line for driving the unselected memory cells; wherein the programming method comprises N precharge steps, each of the N precharge steps comprising applying the precharge voltage to the bit line for a precharge period, the precharge period decreasing as the N increases; Performing a plurality of programming steps, each of the programming steps comprising applying a programming voltage to a word line of the word lines for driving the selected memory cell; as well as After the precharge steps and the programming steps, a verification step is performed on the selected memory cell.

2. The programming method according to claim 1, wherein the precharge steps include a first precharge step and a second precharge step, the second precharge step is performed after the first precharge step, the programming steps include a first programming step and a second programming step, the second programming step is performed after the first programming step, and the first programming step is performed between the first precharge step and the second precharge step. 3 . The programming method according to claim 2 , wherein the second programming step is performed between the second precharge step and the verification step. 4 . The programming method according to claim 1 , wherein the programming method comprises N programming steps, each of the N programming steps comprises applying the programming voltage to the word line for a programming period, and the programming period decreases as the N increases.

5. A method for programming a storage device, characterized in that: The storage device includes a plurality of storage cells, a bit line and a plurality of word lines. When the storage device is in a programming operation, the plurality of storage cells include a selected storage cell and a plurality of unselected storage cells. The programming method includes: Performing a first precharge step, the first precharge step comprising applying a precharge voltage to the bit line for driving the unselected memory cells; Performing a first programming step, the first programming step comprising applying a first programming voltage to a word line among the word lines for driving the selected memory cell; performing a plurality of second precharge steps, each of the second precharge steps comprising applying the precharge voltage to the bit line for driving the unselected memory cells; as well as performing a plurality of second programming steps, each of the second programming steps comprising applying a second programming voltage to the word line for driving the selected memory cell among the word lines, Wherein, the first precharge step is performed before these second precharge steps, the first precharge step includes applying the precharge voltage to the bit line during a first precharge period, each of these second precharge steps includes applying the precharge voltage to the bit line during a second precharge period, the first precharge period is greater than the second precharge period; the second programming voltage is different from the first programming voltage. 6 . The programming method according to claim 5 , wherein the first programming step is performed before the second programming steps, and the first programming voltage is lower than the second programming voltage.

7. The programming method according to claim 6, wherein the first programming step includes applying the first programming voltage to the word line during a first programming period, and each of the second programming steps includes applying the second programming voltage to the word line during a second programming period, and the first programming period is greater than the second programming period.

8. The programming method according to claim 5, wherein the programming method further comprises: Performing a plurality of the first precharge steps, each of the plurality of the first precharge steps comprising applying the precharge voltage to the bit line for driving the unselected memory cells; performing a plurality of the first programming steps, each of the plurality of the first programming steps comprising applying the first programming voltage to the word line among the word lines for driving the selected memory cell, The plurality of first precharge steps and the plurality of first programming steps are performed before the second precharge steps and the second programming steps, and the number of the plurality of first precharge steps is less than the number of the second precharge steps.

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